JPH0621340A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0621340A JPH0621340A JP5061960A JP6196093A JPH0621340A JP H0621340 A JPH0621340 A JP H0621340A JP 5061960 A JP5061960 A JP 5061960A JP 6196093 A JP6196093 A JP 6196093A JP H0621340 A JPH0621340 A JP H0621340A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pattern
- forming
- poly
- side wall
- Prior art date
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Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高集積度の電気的信号
蓄積部を有する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a highly integrated electric signal storage section.
【０００２】[0002]
【従来の技術】従来、高集積メモリセルの構造として
は、文献「電子材料、１９８５年６月号、４１〜４６
頁」に記載されているように、トレンチ（溝掘り）型や
３次元積み上げ型があった。これらは、集積度向上に伴
うセル占有面積の減少によってキャパシタの容量が減少
することを避けるために、Ｓｉ基板に溝を掘り、等価的
に面積が増大したその溝の内面をキャパシタの容量部
（電気的信号蓄積層）として用いたり、段差の側壁、湾
曲による容量増大部を電気的信号蓄積層に利用するもの
である。2. Description of the Related Art Conventionally, as a structure of a highly integrated memory cell, reference has been made to "Electronic Materials, June 1985, 41-46.
As described in “Page”, there were a trench type and a three-dimensional stacked type. In order to avoid the reduction of the capacitance of the capacitor due to the reduction of the cell occupying area with the improvement of the integration degree, these trenches are formed in the Si substrate, and the inner surface of the trench whose equivalent area is increased is equivalent to the capacitor portion ( It is also used as an electrical signal storage layer, or the side wall of a step or a capacitance increasing portion due to bending is used as an electrical signal storage layer.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな従来の電気的信号蓄積部を有する半導体装置では、
再現性よく深い溝を掘ることは非常に難しく、トレンチ
型半導体装置においても溝内部は丸みを有し、深いとこ
ろでは細くなってしまう。また、積み上げ型半導体装置
においては、その容量増大は微々たるものである。この
ように、従来の技術は製造上難易度の高いプロセスを有
する、あるいは大幅な容量増大が期待できないという問
題があった。本発明の目的は、簡易なプロセスで高集
積、大容量の半導体装置を製造する方法を提供すること
にある。However, in the semiconductor device having such a conventional electric signal storage section,
It is very difficult to dig a deep groove with good reproducibility, and even in a trench type semiconductor device, the inside of the groove has a roundness and becomes thin at a deep place. In addition, in the stacked semiconductor device, the increase in capacity is insignificant. As described above, the conventional technology has a problem that it has a process that is difficult to manufacture or that a large capacity increase cannot be expected. An object of the present invention is to provide a method of manufacturing a highly integrated and large capacity semiconductor device by a simple process.
【０００４】[0004]
【課題を解決するための手段】本発明は、上記問題点を
解決するために、基板上に第１層の基礎パターンを形成
し、全面に半絶縁性または導電性の第２層を形成し、こ
の第２層を異方性エッチング法を用いて垂直エッチング
することにより、基礎パターンの側面に第２層の電極パ
ターン（側壁）を形成した後、基礎パターンを除去する
ことを特徴とする。すなわち、側壁による基板表面の凹
凸を、容量部面積の増大の手段とするものである。In order to solve the above problems, the present invention forms a basic pattern of a first layer on a substrate and forms a semi-insulating or conductive second layer on the entire surface. The second layer is vertically etched using an anisotropic etching method to form an electrode pattern (side wall) of the second layer on the side surface of the basic pattern, and then the basic pattern is removed. That is, the unevenness of the substrate surface due to the side wall is used as a means for increasing the area of the capacitance portion.
【０００５】[0005]
【作用】本発明によれば、以上のように側壁のパターニ
ングを行うことにより、微細なパターンが容易に得ら
れ、その凹凸を利用して容量の大きな半導体装置を得る
ことができる。According to the present invention, a fine pattern can be easily obtained by patterning the side wall as described above, and a semiconductor device having a large capacitance can be obtained by utilizing the unevenness.
【０００６】[0006]
【実施例】図１は本発明の第１の実施例の示す工程断面
図である。まず、図１（ａ）に示すように、Ｓｉ基板１
上に全面に化学気相成長法（ＣＶＤ法）等の手段を用い
て、シリコン酸化膜（ＳｉＯ2）を０．４μｍ程度の厚
さに積層する。そして、通常行われているホトリソグラ
フィおよびエッチングにより基礎パターンとしてのＳｉ
Ｏ2パターン２を形成する。その後、図１（ｂ）に示す
ように、ＣＶＤ法等の手段を用いて全面にｐｏｌｙ Ｓ
ｉ膜３を形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a process sectional view showing a first embodiment of the present invention. First, as shown in FIG. 1A, the Si substrate 1
A silicon oxide film (SiO 2 ) having a thickness of about 0.4 μm is laminated on the entire surface by means such as chemical vapor deposition (CVD). Then, Si as a basic pattern is formed by photolithography and etching which are usually performed.
O 2 pattern 2 is formed. After that, as shown in FIG. 1B, a poly S is formed on the entire surface by using a method such as a CVD method.
The i film 3 is formed.
【０００７】次に、図１（ｃ）に示すように、ｐｏｌｙ
Ｓｉ膜３の上面より、反応性イオンエッチング（ＲＩ
Ｅ）等の異方性エッチングを用いて、ｐｏｌｙ Ｓｉ膜
３をエッチングする。これにより、ＳｉＯ2パターン２
の側面にのみｐｏｌｙ Ｓｉ膜が残り、ｐｏｌｙ Ｓｉ
側壁３０が形成される。Next, as shown in FIG. 1 (c), poly
From the upper surface of the Si film 3, reactive ion etching (RI
The poly Si film 3 is etched using anisotropic etching such as E). As a result, the SiO 2 pattern 2
Of the poly Si film remains only on the side surface of the
The side wall 30 is formed.
【０００８】次に、図１（ｄ）に示すように、フッ酸
（ＨＦ）等を用いて基礎パターンであるＳｉＯ2パター
ン２を除去する。これにより、Ｓｉ基板１上に電極パタ
ーンであるｐｏｌｙ Ｓｉ側壁３０が形成される。この
ｐｏｌｙ Ｓｉ側壁３０とＳｉ基板１による凹凸を、電
気的信号蓄積部の表面積増大に用いるのである。Next, as shown in FIG. 1D, the SiO 2 pattern 2 which is the basic pattern is removed by using hydrofluoric acid (HF) or the like. As a result, the poly Si side wall 30 as the electrode pattern is formed on the Si substrate 1. The unevenness formed by the poly Si side wall 30 and the Si substrate 1 is used to increase the surface area of the electrical signal storage portion.
【０００９】次に、図１（ｅ）に示すように、Ｓｉ基板
１およびｐｏｌｙ Ｓｉ側壁３０の上に、全面にキャパ
シタの誘電体層６を形成する。誘電体層６は、例えば熱
酸化によるＳｉＯ２膜、ＣＶＤによるＳｉＯ2膜または
Ｓｉ3Ｎ4膜、あるいは、これらを組み合わせた積層膜で
もよい。また、誘電体となり得る材質で、所望の容量値
が得られるものであればよい。Next, as shown in FIG. 1E, a dielectric layer 6 of a capacitor is formed on the entire surface of the Si substrate 1 and the poly Si side wall 30. The dielectric layer 6 may be, for example, a SiO 2 film formed by thermal oxidation, a SiO 2 film or a Si 3 N 4 film formed by CVD, or a laminated film formed by combining these. Further, any material that can serve as a dielectric may be used as long as it can obtain a desired capacitance value.
【００１０】この誘電体層６の上にキャパシタの一方の
電極７を、例えば低抵抗のｎ+ｐｏｌｙ Ｓｉや金属等
で形成する。ここで、電極７に対するもう一方の電極と
しては、ｐｏｌｙ Ｓｉ側壁３０のみ用いる方法、ある
いはｐｏｌｙ Ｓｉ側壁３０とＳｉ基板１との両方を用
いる方法が考えられる。そして、それに応じてｐｏｌｙ
Ｓｉ側壁３０、Ｓｉ基板１を低抵抗化する必要があ
る。その方法としては、例えば、誘電体層６の形成前ま
たは形成後に、インプラや熱拡散等でＰ、Ａｓ等の不純
物を導入する。また、予め基板１に不純物を導入してお
き、この基板１上に不純物を含んだｐｏｌｙ Ｓｉ側壁
３０を形成するようにしてもよい。On the dielectric layer 6, one electrode 7 of the capacitor is formed of, for example, low resistance n + poly Si or metal. Here, as the other electrode with respect to the electrode 7, a method of using only the poly Si side wall 30 or a method of using both the poly Si side wall 30 and the Si substrate 1 can be considered. And poly accordingly
It is necessary to reduce the resistance of the Si side wall 30 and the Si substrate 1. As a method thereof, for example, before or after forming the dielectric layer 6, impurities such as P and As are introduced by implantation, thermal diffusion or the like. Alternatively, impurities may be introduced into the substrate 1 in advance, and the poly Si side wall 30 containing the impurities may be formed on the substrate 1.
【００１１】一方の電極としてＳｉ基板１、ｐｏｌｙ
Ｓｉ側壁３０を用いたが、これらを金属を含む基板の上
に金属を含む材質からなる側壁を形成する構造として
も、同様のプロセスが可能であり同様の効果が期待でき
る。また、以上述べた材料の種々の組み合わせでも同様
である。As one electrode, the Si substrate 1, poly
Although the Si side wall 30 is used, the same process can be performed and the same effect can be expected even if the side wall made of a material containing metal is formed on the substrate containing metal. The same applies to various combinations of the materials described above.
【００１２】図２は本発明の第２の実施例を示す工程断
面図である。第２の実施例の工程は、第１の実施例と途
中まで（図１（ａ）〜（ｃ））同じである。まず、第１
の実施例と同様に、図１（ａ）〜（ｃ）までの工程を経
て、Ｓｉ基板上にｐｏｌｙ Ｓｉ側壁３０を形成する。2A to 2D are process sectional views showing a second embodiment of the present invention. The process of the second embodiment is the same as that of the first embodiment (FIGS. 1A to 1C). First, the first
In the same manner as in Example 1, the poly Si side wall 30 is formed on the Si substrate through the steps of FIGS. 1A to 1C.
【００１３】次に、図２（ａ）に示すように、例えばＣ
ＶＤ法によりＳｉＯ2膜４を全面に形成する。その後、
図２（ｂ）に示すように、異方性エッチングによりＳｉ
Ｏ2膜４をエッチングして、ｐｏｌｙ Ｓｉ側壁３０の
側面にスペースパターンとしてのＳｉＯ２側壁４０を形
成する。Next, as shown in FIG. 2A, for example, C
The SiO 2 film 4 is formed on the entire surface by the VD method. afterwards,
As shown in FIG. 2 (b), Si is formed by anisotropic etching.
The O 2 film 4 is etched to form a SiO 2 side wall 40 as a space pattern on the side surface of the poly Si side wall 30.
【００１４】次に、図２（ｃ）に示すように、全面にｐ
ｏｌｙ Ｓｉ膜５を積層する。その後、図２（ｄ）に示
すように、異方性エッチングによりｐｏｌｙ Ｓｉ膜５
をエッチングして、ＳｉＯ2側壁４０の側面にｐｏｌｙ
Ｓｉ側壁５０を形成する。このようにして、所望の数
のｐｏｌｙ Ｓｉ側壁とＳｉＯ2側壁を形成する。Next, as shown in FIG. 2C, p is formed on the entire surface.
The poly Si film 5 is laminated. After that, as shown in FIG. 2D, the poly Si film 5 is anisotropically etched.
Is etched to form a poly on the side surface of the SiO 2 side wall 40.
The Si sidewall 50 is formed. In this way, a desired number of poly Si sidewalls and SiO 2 sidewalls are formed.
【００１５】次に、図２（ｅ）に示すように、フッ酸等
によりスペースパターンであるＳｉＯ2側壁４０を除去
する。これにより、Ｓｉ基板１上に電極パターンである
ｐｏｌｙ Ｓｉ側壁３０，５０が形成される。このｐｏ
ｌｙ Ｓｉ側壁３０，５０とＳｉ基板１による凹凸を、
電気的信号蓄積部の表面積増大に用いるのである。Next, as shown in FIG. 2 (e), the SiO 2 sidewall 40, which is a space pattern, is removed with hydrofluoric acid or the like. As a result, the poly Si side walls 30 and 50, which are electrode patterns, are formed on the Si substrate 1. This po
The unevenness formed by the ly Si side walls 30 and 50 and the Si substrate 1,
It is used to increase the surface area of the electrical signal storage section.
【００１６】次に、図２（ｆ）に示すように、Ｓｉ基板
１、ｐｏｌｙ Ｓｉ側壁３０，５０の上に全面にキャパ
シタの誘電体層６を形成する。この誘電体層６の上にキ
ャパシタの一方の電極７を、例えば低抵抗のｎ＋ｐｏｌ
ｙ Ｓｉや金属等で形成する。ここで、電極７に対する
もう一方の電極としては、ｐｏｌｙ Ｓｉ側壁３０，５
０のみ用いる方法、あるいはｐｏｌｙ Ｓｉ側壁３０，
５０とＳｉ基板１との両方を用いる方法が考えられる。
そして、それに応じてｐｏｌｙ Ｓｉ側壁３０，５０、
Ｓｉ基板１を低抵抗化する必要がある。Next, as shown in FIG. 2F, a dielectric layer 6 of a capacitor is formed on the entire surface of the Si substrate 1 and the poly Si sidewalls 30 and 50. One electrode 7 of the capacitor is formed on the dielectric layer 6, for example, n + pol having a low resistance.
It is formed of y Si or metal. Here, as the other electrode with respect to the electrode 7, the poly Si sidewalls 30 and 5 are used.
0 only, or the poly Si sidewall 30,
A method using both 50 and the Si substrate 1 can be considered.
Then, accordingly, the poly Si side walls 30, 50,
It is necessary to reduce the resistance of the Si substrate 1.
【００１７】図３は、第２の実施例において形成された
ｐｏｌｙ Ｓｉ側壁を示す斜視図である。図３のＡ−Ａ
に沿った断面が図２（ｅ）に相当する。図３において、
ｐｏｌｙ Ｓｉ側壁５−１，５−２が図２（ｅ）の側壁
５０に対応し、ｐｏｌｙ Ｓｉ側壁３−１が側壁３０に
対応する。FIG. 3 is a perspective view showing a poly Si side wall formed in the second embodiment. AA of FIG.
A cross section along the line corresponds to FIG. In FIG.
The poly Si side walls 5-1 and 5-2 correspond to the side wall 50 in FIG. 2E, and the poly Si side wall 3-1 corresponds to the side wall 30.
【００１８】以上のように、本発明の実施例によれば、
従来の技術的に難易度の高いトレンチ構造や、あまり容
量の増大が期待できない積み上げ方式によるメモリキャ
パシタの欠点を解決することができる。すなわち、側壁
によるパターニングを行うことにより、従来のホトリソ
手法では不可能な０．２μｍ幅程度の微細なパターンを
容易に得ることができる。これにより、その側壁による
凹凸を利用して、電気的信号蓄積部の容量を増大させる
ことができる。As described above, according to the embodiment of the present invention,
It is possible to solve the drawbacks of the conventional trench structure, which has a high degree of technical difficulty, and the stacked type memory capacitor, which is not expected to increase the capacitance so much. That is, by performing patterning on the side wall, it is possible to easily obtain a fine pattern having a width of about 0.2 μm, which is impossible by the conventional photolithography method. This makes it possible to increase the capacitance of the electrical signal storage unit by utilizing the unevenness formed by the side wall.
【００１９】例えば、キャパシタ（電気的信号蓄積部）
面内全域に本手法を用いて側壁による凹凸を作れば、側
壁の高さと幅を等しくしても表面積は約２倍になり、容
量も２倍になる。さらに高くすれば容量はより大きくな
る。実験では高さが０．４μｍで幅０．２５μｍが得ら
れており、この場合は約２．６倍の容量になる。側壁の
高さと幅の関係は成膜やエッチングの条件によるので、
これらの条件により、さらに容量の大きな電気的信号蓄
積部を得ることができる。For example, a capacitor (electrical signal storage unit)
If unevenness is formed by the side wall on the entire surface by using this method, even if the height and width of the side wall are made equal, the surface area is approximately doubled and the capacity is also doubled. The higher the capacity, the larger the capacity. In the experiment, the height is 0.4 μm and the width is 0.25 μm, and in this case, the capacity is about 2.6 times. The relationship between the height and width of the side wall depends on the conditions of film formation and etching.
Under these conditions, it is possible to obtain an electric signal storage unit having a larger capacity.
【００２０】[0020]
【発明の効果】以上説明したように、本発明によれば、
側壁によるパターニングを行うことにより、微細なパタ
ーンを容易に得ることができる。そして、その凹凸を利
用して電気的信号蓄積部を形成しているので、高集積度
で大容量の半導体装置を得ることができる。As described above, according to the present invention,
By patterning the side wall, a fine pattern can be easily obtained. Further, since the electrical signal storage portion is formed by utilizing the unevenness, a semiconductor device with high integration and large capacity can be obtained.
【図１】本発明の第１の実施例を示す工程断面図であ
る。FIG. 1 is a process sectional view showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す工程断面図であ
る。FIG. 2 is a process sectional view showing a second embodiment of the present invention.
【図３】第２に実施例で形成されたｐｏｌｙ Ｓｉ側壁
の斜視図である。FIG. 3 is a perspective view of a poly Si side wall formed in a second example.
１ Ｓｉ基板 ２ ＳｉＯ2パターン ３ ｐｏｌｙ Ｓｉ膜 ４ ＳｉＯ2膜 ５ ｐｏｌｙ Ｓｉ膜 ６ 誘電体層 ７ 電極 ３０ ｐｏｌｙ Ｓｉ側壁 ４０ ＳｉＯ2側壁 ５０ ｐｏｌｙ Ｓｉ側壁1 Si substrate 2 SiO 2 pattern 3 poly Si film 4 SiO 2 film 5 poly Si film 6 dielectric layer 7 electrode 30 poly Si side wall 40 SiO 2 side wall 50 poly Si side wall
Claims (2)
る工程と、 全面に半絶縁性または導電性の第２層を形成する工程
と、 前記第２層を異方性エッチング法を用いて垂直エッチン
グすることにより、前記基礎パターンの側面に前記第２
層の電極パターンを形成する工程と、 前記基礎パターンを除去する工程と、 全面にキャパシタの誘電体層を形成する工程と、 前記誘電体層上に前記キャパシタの一方の電極を形成す
る工程と を有することを特徴とする半導体装置の製造方法。1. A step of forming a basic pattern of a first layer on a substrate, a step of forming a semi-insulating or conductive second layer on the entire surface, and an anisotropic etching method for forming the second layer. Vertical etching is performed on the side surface of the basic pattern so that the second
A step of forming an electrode pattern of a layer, a step of removing the basic pattern, a step of forming a dielectric layer of a capacitor on the entire surface, and a step of forming one electrode of the capacitor on the dielectric layer. A method of manufacturing a semiconductor device, comprising:
る第１工程と、 全面に半絶縁性または導電性の第２層を形成する第２工
程と、 前記第２層を異方性エッチング法を用いて垂直エッチン
グすることにより、前記基礎パターンの側面に前記第２
層の電極パターンを形成する第３工程と、 前記基礎パターンを除去する第４工程と、 全面にスペースパターンを形成するための第３層を積層
する第５工程と、 前記第３層を異方性エッチング法を用いて垂直エッチン
グすることにより、前記電極パターンの両側面に前記第
３層のスペースパターンを形成する第６工程と、 全面に半絶縁性または導電性の第４層を積層する第７工
程と、 前記第４層を異方性エッチング法を用いて垂直エッチン
グすることにより、前記スペースパターンの側面に前記
第４層の電極パターンを形成する第８工程と、 前記スペースパターンを除去する第９工程と、 全面にキャパシタの誘電体層を形成する第１０工程と、 前記誘電体層上に前記キャパシタの一方の電極を形成す
る第１１工程とを有し、 前記第５工程から第８工程を１回またはそれ以上繰り返
すことを特徴とする半導体装置の製造方法。2. A first step of forming a basic pattern of a first layer on a substrate, a second step of forming a semi-insulating or conductive second layer on the entire surface, and anisotropy of the second layer. By performing vertical etching using an etching method, the second pattern is formed on the side surface of the basic pattern.
A third step of forming a layer electrode pattern, a fourth step of removing the basic pattern, a fifth step of laminating a third layer for forming a space pattern on the entire surface, and an anisotropic method of forming the third layer A sixth step of forming a space pattern of the third layer on both side surfaces of the electrode pattern by vertical etching using a conductive etching method; and a fourth step of laminating a semi-insulating or conductive fourth layer on the entire surface. 7 steps, 8th step of forming the electrode pattern of the 4th layer on the side surface of the space pattern by vertically etching the 4th layer using an anisotropic etching method, and removing the space pattern. A ninth step, a tenth step of forming a capacitor dielectric layer on the entire surface, and an eleventh step of forming one electrode of the capacitor on the dielectric layer; and the fifth step. The method of manufacturing a semiconductor device characterized by repeating et eighth step one or more times.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61288913A JPS63142665A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
| JP5061960A JP2500288B2 (en) | 1986-12-05 | 1993-03-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61288913A JPS63142665A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
| JP5061960A JP2500288B2 (en) | 1986-12-05 | 1993-03-22 | Method for manufacturing semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61288913A Division JPS63142665A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0621340A true JPH0621340A (en) | 1994-01-28 |
| JP2500288B2 JP2500288B2 (en) | 1996-05-29 |
Family
ID=26403042
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61288913A Granted JPS63142665A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
| JP5061960A Expired - Lifetime JP2500288B2 (en) | 1986-12-05 | 1993-03-22 | Method for manufacturing semiconductor device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61288913A Granted JPS63142665A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (2) | JPS63142665A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000065395A (en) * | 1999-04-02 | 2000-11-15 | 김영환 | Method for forming a single Electron Transistor |
| KR100412140B1 (en) * | 2001-12-28 | 2003-12-31 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| US6964899B2 (en) | 2003-04-07 | 2005-11-15 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP2010511306A (en) * | 2006-11-29 | 2010-04-08 | マイクロン テクノロジー， インク． | Method for reducing the critical dimension of a semiconductor device and semiconductor device having a reduced critical dimension that is partially fabricated |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63221659A (en) * | 1987-03-10 | 1988-09-14 | Nec Kyushu Ltd | Semiconductor memory device |
| JPS6474752A (en) * | 1987-09-17 | 1989-03-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5748237A (en) * | 1980-09-05 | 1982-03-19 | Nec Corp | Manufacture of 2n doubling pattern |
| JPS60245264A (en) * | 1984-05-21 | 1985-12-05 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-12-05 JP JP61288913A patent/JPS63142665A/en active Granted
-
1993
- 1993-03-22 JP JP5061960A patent/JP2500288B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5748237A (en) * | 1980-09-05 | 1982-03-19 | Nec Corp | Manufacture of 2n doubling pattern |
| JPS60245264A (en) * | 1984-05-21 | 1985-12-05 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000065395A (en) * | 1999-04-02 | 2000-11-15 | 김영환 | Method for forming a single Electron Transistor |
| KR100412140B1 (en) * | 2001-12-28 | 2003-12-31 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| US6964899B2 (en) | 2003-04-07 | 2005-11-15 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP2010511306A (en) * | 2006-11-29 | 2010-04-08 | マイクロン テクノロジー， インク． | Method for reducing the critical dimension of a semiconductor device and semiconductor device having a reduced critical dimension that is partially fabricated |
| US8338304B2 (en) | 2006-11-29 | 2012-12-25 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices |
| US8836083B2 (en) | 2006-11-29 | 2014-09-16 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63142665A (en) | 1988-06-15 |
| JPH0579181B2 (en) | 1993-11-01 |
| JP2500288B2 (en) | 1996-05-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |