EP0348046B1 - Method of producing a semiconductor device - Google Patents

Method of producing a semiconductor device Download PDF

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Publication number
EP0348046B1
EP0348046B1 EP89305353A EP89305353A EP0348046B1 EP 0348046 B1 EP0348046 B1 EP 0348046B1 EP 89305353 A EP89305353 A EP 89305353A EP 89305353 A EP89305353 A EP 89305353A EP 0348046 B1 EP0348046 B1 EP 0348046B1
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EP
European Patent Office
Prior art keywords
insulating layer
side wall
semiconductor pillar
film
pillar
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EP89305353A
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German (de)
French (fr)
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EP0348046A3 (en
EP0348046A2 (en
Inventor
Hiroshi Gotou
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Fujitsu Ltd
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Fujitsu Ltd
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Publication of EP0348046A3 publication Critical patent/EP0348046A3/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/40—ROM only having the source region and drain region on different levels, e.g. vertical channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/911—Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor memory device wherein a head portion of a semiconductor pillar having a conductive side wall is brought into contact with a conductive pattern.
  • Figures 1 and 2 respectively, show cross-sectional views of a pillar-shaped DRAM (Dynamic Random Access Memory) and a ROM (Read Only Memory) of a prior proposal.
  • DRAM Dynamic Random Access Memory
  • ROM Read Only Memory
  • a SiO 2 film 2 is formed on a silicon substrate 1, and a semiconductor pillar 3 is formed on the SiO 2 film 2 and consists of a first conductive layer (storage electrode) 4, p - type Si layer 5, channel doped layer 6, and a second conductive layer (drain) 7.
  • the DRAM of Fig. 1 further comprises a dielectric film 8, a gate insulating film (SiO 2 ) 9, a third conductive layer (electrode) 10, a polysilicon word line (gate) 11, an interlaminar insulating film such as a PSG film, etc., and an aluminum bit line 13.
  • the ROM comprises a silicon substrate 1 having an n + source region 19, a p channel region 6 and an n + drain region 7, dielectric film 2, a gate insulating film 9, a doped polysilicon gate electrode (word line), a PSG interlaminar insulating film 12, and an aluminum bit line 13.
  • the channel region 6 and the drain region 7 form a semiconductor pillar 3 on a portion of the source region 19.
  • a contact hole is formed in the interlaminar insulating film 12, by a photolithography process as shown in Figs 1 and 2.
  • the contact hole In the process of forming the contact holes, the contact hole must lie within the second conductive layer 7 or the drain region 7, and accordingly the whole head portion of the semiconductor pillar cannot be used for the contact; thus the diameter of the semiconductor pillar must be enlarged.
  • Figures 3A to 3G show cross-sectional step views of the production of another DRAM cell according to another prior proposal.
  • a SiO 2 film 2 having a thickness of 0.5 ⁇ m, an n + conductive layer 4, a p - silicon layer 5 having a thickness of 5 ⁇ m, a p channel doped layer 6, and an n + conductive layer 7 are formed on a silicon substrate 1.
  • a trench 15 is formed by etching the semiconductor layers (7, 6, 5 and 4) by an RIE process using an oxide film 14 as a mask.
  • Each semiconductor pillar 3 obtained by the etching has a top surface cross section of 0.7 ⁇ m by 0.7 ⁇ m and the gap (d1) between pillars in the X-direction is greater than that (d2) in the Y-direction, as shown in a top view of Fig. 3B(2).
  • a SiO 2 film 17 and n + poly Si film 18 are formed and the exposed SiO 2 film 17 is etched by hydrofluoric acid so that only a dielectric SiO 2 film remains.
  • a SiO 2 film 17B is formed by thermal oxidation and phospho-silicate-glass (PSG) or SiO 2 deposited over the entire surface of the substrate by a CVD process.
  • PSG thermal oxidation and phospho-silicate-glass
  • SiO 2 deposited over the entire surface of the substrate by a CVD process.
  • the deposited PSG or SiO 2 layer 21 is etched back until the top surface of the semiconductor pillar is exposed.
  • an aluminum film is deposited and patterned so that a bit line 22 is formed, the bit line 22 and the n + conductive layer 7 in the semiconductor pillar being connected by a self-alignment process.
  • the above descriptive is of a DRAM realized by a prior art process, and in the etching back process shown in Fig. 3F the end point of the etching, wherein the semiconductor pillar is exposed, is not easily found, and therefore, since overetching often occurs, the SiO 2 film at A in Fig. 3F is also etched, whereby a desired thickness of the SiO 2 film cannot be obtained and the breakdown voltage is lowered.
  • DRAM pillar array An example of a DRAM pillar array is provided by DE-A-3801525 (Mitsubishi) where polysilicon sidewall gates are applied and silicon oxide layers are deposited and etched to planarise the surface. No indication is given as to how to control the etch-back process.
  • EP-A-198590 pillars are likewise formed, with polysilicon gates on their walls shaped by anisotropic etching; here no planarisation takes place, the drain contacts being made through etched contact holes.
  • An object of the present invention is to provide a method of manufacturing a semiconductor device wherein a conductive pattern such as a bit line or like conductor is brought into contact with a semiconductor pillar formed on a semiconductor substrate, by a self-alignment process.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device, such as a DRAM cell structure, wherein the semiconductor pillar formed on a semiconductor substrate has a small diameter.
  • a method of producing a semiconductor device comprising the steps of: preparing a semiconductor substrate, forming a semiconductor pillar projecting from the semiconductor substrate so as to have a head portion surface and a circumferential surface, forming a first insulating layer on the head portion surface of the semiconductor pillar, forming a second insulating layer on the circumferential surface of the semiconductor pillar, forming a conductive side wall on the circumference of the semiconductor pillar on the second insulating layer, forming a third insulating layer, of a material different from that of the first insulating layer, on the surface of the conductive side wall, forming a fourth insulating layer, of a material different from that of the first insulating layer, on the entire exposed surface so that the semiconductor pillar and the conductive side wall are buried, removing the fourth insulating layer to the level of the first insulating layer on the head portion surface of the semiconductor pillar, selectively growing a layer of insulation on the upper portion of the conductive
  • Figures 4A to 4F show cross-sectional process views of an embodiment of the present invention.
  • silicon nitride (Si 3 N 4 ) film 24 having a thickness of about 0.15 ⁇ m is formed on a surface of a silicon substrate 1, by a usual CVD (chemical vapour deposition) process.
  • the Si 3 N 4 film 24 acts as an antioxidant film in an oxidizing process carried out at a later stage.
  • the upper portion of the silicon substrate 1 is etched to form a projecting pillar portion; for example, a resist pattern (not shown) is formed on a desiredportion of the surface of the Si 3 N 4 film 24, and, using the resist pattern as a mask, the Si 3 N 4 film 24 and the silicon substrate 1 respectively are selectively etched.
  • the pillar-shaped silicon thickness 25 is, for example, about 2.0 ⁇ m.
  • the exposed surface of the pillar-shaped silicon 25 is oxidized to form an oxide film 27 having a thickness of about 300 ⁇ , as shown in Fig. 4B.
  • a conductive side wall 28 is formed on the oxide film 27 of the pillar-shaped silicon 25.
  • the conductive side wall is formed by the steps of depositing a polysilicon on an entire exposed surface, implanting n type impurities (dopant) therein, and diffusing same, and carrying out an anisotropic etching using reactive ion etching so that the polysilicon remains on only the side wall of the pillar-shaped silicon, whereby the polysilicon side wall 28 is formed.
  • the surface of the polysilicon side wall 28 is oxidized to form an oxide film 29, and subsequently, a PSG or SiO 2 layer 30 is formed on the entire exposed surface as an interlaminar insulating film so that the semiconductor pillar 25 is buried as shown in Fig. 4C.
  • the PSG or SiO 2 layer 30 is etched back so that the surface of the Si 3 N 4 film 24 is exposed, with the result that the top surfaces of the pillar-shaped silicon 25 and the interlaminar insulating film 30 form a continuous flat surface.
  • a semiconductor element is apt to be faulty due to a low breakdown voltage between the aluminum wiring and the polysilicon side wall 28.
  • the low breakdown voltage exists because when the PSG film 30 is etched back to the PSG film 30 positioned at the top portion of the polysilicon side wall 28, and subsequently a part of oxide film 29, is etched whereby an insulating film having a thickness sufficient to withstand the breakdown voltage is no longer present.
  • an oxidizing treatment is additionally carried out since, during this oxidizing treatment, the Si 3 N 4 film 24 acts as an antioxidizing film, and thus the pillar-shaped silicon 25 is not oxidized.
  • the polysilicon side wall 28 is oxidized from the top portion thereof downward, and thus the top portion of the polysilicon side wall 28 is oxidized to a depth, e.g., about 0.2 ⁇ m, sufficient to withstand the breakdown voltage, and accordingly, an oxide portion 31 is obtained as shown in Fig. 4E.
  • an aluminum wiring or interconnection pattern 32 is formed on the pillar-shaped silicon 25 and the PSG film 30 as shown in Fig. 4F.
  • This formation of the aluminum wiring pattern 32 does not require a formation of a contact hole in the PSG film 30, and,as this technique does not require a mask alignment, the head surface portion of the pillar shaped silicon 25 can be narrowed, whereby the aluminum wiring 32 can be formed by a self alignment process. Further, a sufficient breakdown voltage property between the aluminum wiring 22 and the polysilicon side wall 28 is provided by the above-explained oxidizing treatment.
  • impurity doped regions are usually and optionally formed in the silicon substrate 1 and the pillar shaped silicon 3 during the process of the present invention;further, although in this example a breakdown voltage property is enhanced by oxidizing the polysilicon, it may be also enhanced by nitriding the polysilicon. In such a case, a film having an anti-nitriding property, such as an oxide film, must be formed on the surface of the pillar-shaped silicon.
  • Figures 5 and 6 show cross sectional views of respective examples of a DRAM and a ROM produced according to the present invention.
  • bit lines 13 are formed on a pillar shaped silicon 3 by a self-alignment process.
  • the upper portion of a gate insulating film (SiO 2 ) 9 obtained by the additional oxidizing process is thick.
  • the other structural elements are substantially the same as shown in Figs. 1 and 2.
  • wiring can be easily brought into contact with a surface of a semiconductor pillar formed or a substrate, by a self alignment process, without positioning, with the result that a miniaturization of a device can be realized and the costs reduced.

Description

  • The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor memory device wherein a head portion of a semiconductor pillar having a conductive side wall is brought into contact with a conductive pattern.
  • Figures 1 and 2, respectively, show cross-sectional views of a pillar-shaped DRAM (Dynamic Random Access Memory) and a ROM (Read Only Memory) of a prior proposal.
  • In Fig. 1 a SiO2 film 2 is formed on a silicon substrate 1, and a semiconductor pillar 3 is formed on the SiO2 film 2 and consists of a first conductive layer (storage electrode) 4, p- type Si layer 5, channel doped layer 6, and a second conductive layer (drain) 7. The DRAM of Fig. 1 further comprises a dielectric film 8, a gate insulating film (SiO2) 9, a third conductive layer (electrode) 10, a polysilicon word line (gate) 11, an interlaminar insulating film such as a PSG film, etc., and an aluminum bit line 13.
  • Further, as shown in Figure 2, the ROM comprises a silicon substrate 1 having an n+ source region 19, a p channel region 6 and an n+ drain region 7, dielectric film 2, a gate insulating film 9, a doped polysilicon gate electrode (word line), a PSG interlaminar insulating film 12, and an aluminum bit line 13. The channel region 6 and the drain region 7 form a semiconductor pillar 3 on a portion of the source region 19.
  • To bring the semiconductor pillar 3 into contact with the bit line 13, a contact hole is formed in the interlaminar insulating film 12, by a photolithography process as shown in Figs 1 and 2. In the process of forming the contact holes, the contact hole must lie within the second conductive layer 7 or the drain region 7, and accordingly the whole head portion of the semiconductor pillar cannot be used for the contact; thus the diameter of the semiconductor pillar must be enlarged.
  • Figures 3A to 3G show cross-sectional step views of the production of another DRAM cell according to another prior proposal.
  • First, as shown in Fig. 3A, a SiO2 film 2 having a thickness of 0.5 µm, an n+ conductive layer 4, a p- silicon layer 5 having a thickness of 5 µm, a p channel doped layer 6, and an n+ conductive layer 7 are formed on a silicon substrate 1.
  • Then, as shown in Figure 3B(1),a trench 15 is formed by etching the semiconductor layers (7, 6, 5 and 4) by an RIE process using an oxide film 14 as a mask. Each semiconductor pillar 3 obtained by the etching has a top surface cross section of 0.7 µm by 0.7 µm and the gap (d1) between pillars in the X-direction is greater than that (d2) in the Y-direction, as shown in a top view of Fig. 3B(2). Then, as shown in Fig. 3C, after removing the mask 14, a SiO2 film 17 and n+ poly Si film 18 are formed and the exposed SiO2 film 17 is etched by hydrofluoric acid so that only a dielectric SiO2 film remains.
  • Then, as shown in Fig. 3D(1), the substrate is thermally oxidized and a gate SiO2 film 17a having a thickness of 200 Å (200 Å = 20 nm) is formed. Further, after forming a poly Si film by a CVD process on the exposed surface of the substrate, the poly Si film is etched back by an RIE process so that a side wall poly Si film 20, which becomes a gate electrode,remains. Asexplained above, different gaps are set up between the pillars, i.e., dl is larger than d2 as shown in Fig. 3D(2).
  • Then, as shown in Fig. 3E, a SiO2 film 17B is formed by thermal oxidation and phospho-silicate-glass (PSG) or SiO2 deposited over the entire surface of the substrate by a CVD process.
  • Then, as shown in Fig. 3F, the deposited PSG or SiO2 layer 21 is etched back until the top surface of the semiconductor pillar is exposed.
  • Then an aluminum film is deposited and patterned so that a bit line 22 is formed, the bit line 22 and the n+ conductive layer 7 in the semiconductor pillar being connected by a self-alignment process. The above descriptive is of a DRAM realized by a prior art process, and in the etching back process shown in Fig. 3F the end point of the etching, wherein the semiconductor pillar is exposed, is not easily found, and therefore, since overetching often occurs, the SiO2 film at A in Fig. 3F is also etched, whereby a desired thickness of the SiO2 film cannot be obtained and the breakdown voltage is lowered.
  • An example of a DRAM pillar array is provided by DE-A-3801525 (Mitsubishi) where polysilicon sidewall gates are applied and silicon oxide layers are deposited and etched to planarise the surface. No indication is given as to how to control the etch-back process. In EP-A-198590 pillars are likewise formed, with polysilicon gates on their walls shaped by anisotropic etching; here no planarisation takes place, the drain contacts being made through etched contact holes.
  • An object of the present invention is to provide a method of manufacturing a semiconductor device wherein a conductive pattern such as a bit line or like conductor is brought into contact with a semiconductor pillar formed on a semiconductor substrate, by a self-alignment process.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device, such as a DRAM cell structure, wherein the semiconductor pillar formed on a semiconductor substrate has a small diameter.
  • Therefore, according to the present invention there is provided a method of producing a semiconductor device, comprising the steps of: preparing a semiconductor substrate, forming a semiconductor pillar projecting from the semiconductor substrate so as to have a head portion surface and a circumferential surface, forming a first insulating layer on the head portion surface of the semiconductor pillar, forming a second insulating layer on the circumferential surface of the semiconductor pillar, forming a conductive side wall on the circumference of the semiconductor pillar on the second insulating layer, forming a third insulating layer, of a material different from that of the first insulating layer, on the surface of the conductive side wall, forming a fourth insulating layer, of a material different from that of the first insulating layer, on the entire exposed surface so that the semiconductor pillar and the conductive side wall are buried, removing the fourth insulating layer to the level of the first insulating layer on the head portion surface of the semiconductor pillar, selectively growing a layer of insulation on the upper portion of the conductive side wall, without causing such growth on the semiconductor pillar, by using the first insulating layer as a mask, whereby the breakdown voltage between the conductive side wall and other elements is improved, removing at least one part of the first insulating layer formed on the head portion of the semiconductor pillar, and forming a conductive pattern on the head portion of the semiconductor pillar and the fourth insulating layer.
  • Reoxidation of the top part of an insulating sidewall on a polysilicon layer is known in itself; see for instance IBM TDB Vol 30 no. 5, pages 406-408. However, no advantage is taken here, as it is in the invention, of applying this technique to make a self-aligned contact to a pillar in a planarised construction.
    • BRIEF DESCRIPTION OF THE DRAWINGS
    • Figures 1 and 2 are, respectively, cross-sectional views of a pillar-shaped DRAM and a ROM of a prior proposal;
    • Figs. 3A to 3G are cross-sectional step views of the production of another DRAM cell according to another prior proposal;
    • Figs. 4A to 4F are cross sectional step views of the production of an example according to the present invention;
    • Figs. 5 and 6 are cross-sectional views of a DRAM and a ROM embodying the present invention.
  • An example of the present invention will now be explained with reference to Figures 4A to 4F.
  • Figures 4A to 4F show cross-sectional process views of an embodiment of the present invention.
  • First, as shown in Fig. 4A, silicon nitride (Si3N4) film 24 having a thickness of about 0.15 µm is formed on a surface of a silicon substrate 1, by a usual CVD (chemical vapour deposition) process. The Si3N4 film 24 acts as an antioxidant film in an oxidizing process carried out at a later stage.
  • Then, the upper portion of the silicon substrate 1 is etched to form a projecting pillar portion; for example,a resist pattern (not shown) is formed on a desiredportion of the surface of the Si3N4 film 24, and, using the resist pattern as a mask, the Si3N4 film 24 and the silicon substrate 1 respectively are selectively etched. The pillar-shaped silicon thickness 25 is, for example, about 2.0 µm. After forming the pillar-shaped silicon 25 with the Si3N4 film 24, the exposed surface of the pillar-shaped silicon 25 is oxidized to form an oxide film 27 having a thickness of about 300 Å, as shown in Fig. 4B.
  • Then a conductive side wall 28 is formed on the oxide film 27 of the pillar-shaped silicon 25. The conductive side wall is formed by the steps of depositing a polysilicon on an entire exposed surface, implanting n type impurities (dopant) therein, and diffusing same, and carrying out an anisotropic etching using reactive ion etching so that the polysilicon remains on only the side wall of the pillar-shaped silicon, whereby the polysilicon side wall 28 is formed. Then the surface of the polysilicon side wall 28 is oxidized to form an oxide film 29, and subsequently, a PSG or SiO2 layer 30 is formed on the entire exposed surface as an interlaminar insulating film so that the semiconductor pillar 25 is buried as shown in Fig. 4C.
  • Then, as shown in Fig. 4D, the PSG or SiO2 layer 30 is etched back so that the surface of the Si3N4 film 24 is exposed, with the result that the top surfaces of the pillar-shaped silicon 25 and the interlaminar insulating film 30 form a continuous flat surface.
  • If,after removing the Si3N4 film 24, an aluminum wiring is formed on the resulting surface of the silicon pillar 25, contact between the silicon pillar and the wiring can be realized by a self alignment process and without the need for mask alignment.
  • When the aluminum wiring is formed by such steps, however, a semiconductor element is apt to be faulty due to a low breakdown voltage between the aluminum wiring and the polysilicon side wall 28. The low breakdown voltage exists because when the PSG film 30 is etched back to the PSG film 30 positioned at the top portion of the polysilicon side wall 28, and subsequently a part of oxide film 29, is etched whereby an insulating film having a thickness sufficient to withstand the breakdown voltage is no longer present.
  • According to the present invention, after exposing the Si3N4 film 24, to prevent the above-mentioned overetching, an oxidizing treatment is additionally carried out since, during this oxidizing treatment, the Si3N4 film 24 acts as an antioxidizing film, and thus the pillar-shaped silicon 25 is not oxidized. Further, since the PSG film 30 and the oxide film 29 has been oxidized, the polysilicon side wall 28 is oxidized from the top portion thereof downward, and thus the top portion of the polysilicon side wall 28 is oxidized to a depth, e.g., about 0.2 µm, sufficient to withstand the breakdown voltage, and accordingly, an oxide portion 31 is obtained as shown in Fig. 4E.
  • After removing the Si3N4 film 24, an aluminum wiring or interconnection pattern 32 is formed on the pillar-shaped silicon 25 and the PSG film 30 as shown in Fig. 4F. This formation of the aluminum wiring pattern 32 does not require a formation of a contact hole in the PSG film 30, and,as this technique does not require a mask alignment, the head surface portion of the pillar shaped silicon 25 can be narrowed, whereby the aluminum wiring 32 can be formed by a self alignment process. Further, a sufficient breakdown voltage property between the aluminum wiring 22 and the polysilicon side wall 28 is provided by the above-explained oxidizing treatment.
  • In this example impurity doped regions are usually and optionally formed in the silicon substrate 1 and the pillar shaped silicon 3 during the process of the present invention;further, although in this example a breakdown voltage property is enhanced by oxidizing the polysilicon, it may be also enhanced by nitriding the polysilicon. In such a case, a film having an anti-nitriding property, such as an oxide film, must be formed on the surface of the pillar-shaped silicon.
  • Figures 5 and 6 show cross sectional views of respective examples of a DRAM and a ROM produced according to the present invention. In these two examples, bit lines 13 are formed on a pillar shaped silicon 3 by a self-alignment process. Further, the upper portion of a gate insulating film (SiO2) 9 obtained by the additional oxidizing process is thick. The other structural elements are substantially the same as shown in Figs. 1 and 2.
  • As explained above, according to the present invention, wiring can be easily brought into contact with a surface of a semiconductor pillar formed or a substrate, by a self alignment process, without positioning, with the result that a miniaturization of a device can be realized and the costs reduced.

Claims (5)

  1. A method of producing a semiconductor device, comprising the steps of:
    preparing a semiconductor substrate (1),
    forming a semiconductor pillar (3,25) projecting from the semiconductor substrate so as to have a head portion surface and a circumferential surface,
    forming a first insulating layer (24) on the head portion surface of the semiconductor pillar,
    forming a second insulating layer (9,27) on the circumferential surface of the semiconductor pillar,
    forming a conductive side wall (11,28) on the circumference of the semiconductor pillar (3,25) on the second insulating layer (9,27),
    forming a third insulating layer (29), of a material different from that of the first insulating layer, on the surface of the conductive side wall (11,28),
    forming a fourth insulating layer (12,30), of a material different from that of the first insulating layer (24), on the entire exposed surface so that the semiconductor pillar and the conductive side wall are buried,
    removing the fourth insulating layer (12,30) to the level of the first insulating layer (24) on the head portion surface of the semiconductor pillar,
    selectively growing a layer of insulation on the upper portion of the conductive side wall (11,28), without causing such growth on the semiconductor pillar, by using the first insulating layer (24) as a mask, whereby the breakdown voltage between the conductive side wall (11,28) and other elements is improved,
    removing at least one part of the first insulating layer (24) formed on the head portion of the semiconductor pillar, and
    forming a conductive pattern (13,32) on the head portion of the semiconductor pillar and the fourth insulating layer.
  2. A method according to claim 1, wherein the substrate is a silicon substrate.
  3. A method according to claim 1 or 2, wherein the semiconductor pillar (3,25) is made of silicon.
  4. A method according to any of claims 1 to 3, wherein the first insulating layer (24) is a silicon nitride layer and the insulator (31) obtained by selective growth on the upper portion of the conductive side wall (11,28) is of silicon oxide formed by oxidation of the side wall.
  5. A method according to any of claims 1 to 3, wherein the first insulating layer is a silicon oxide layer and the insulator obtained by selective growth on the upper portion of the conductive side wall is a nitride.
EP89305353A 1988-05-28 1989-05-26 Method of producing a semiconductor device Expired - Lifetime EP0348046B1 (en)

Applications Claiming Priority (2)

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JP129463/88 1988-05-28
JP63129463A JPH07105477B2 (en) 1988-05-28 1988-05-28 Semiconductor device and manufacturing method thereof

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EP0348046A2 EP0348046A2 (en) 1989-12-27
EP0348046A3 EP0348046A3 (en) 1991-09-11
EP0348046B1 true EP0348046B1 (en) 1996-08-28

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JP (1) JPH07105477B2 (en)
KR (1) KR930003277B1 (en)
DE (1) DE68927026D1 (en)

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DE68927026D1 (en) 1996-10-02
JPH07105477B2 (en) 1995-11-13
KR930003277B1 (en) 1993-04-24
US5372964A (en) 1994-12-13
US5057896A (en) 1991-10-15
KR900019215A (en) 1990-12-24
EP0348046A3 (en) 1991-09-11
JPH01300566A (en) 1989-12-05
EP0348046A2 (en) 1989-12-27

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