KR100368695B1 - Method for mounting semiconductor elements - Google Patents
Method for mounting semiconductor elements Download PDFInfo
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- KR100368695B1 KR100368695B1 KR10-2000-0021854A KR20000021854A KR100368695B1 KR 100368695 B1 KR100368695 B1 KR 100368695B1 KR 20000021854 A KR20000021854 A KR 20000021854A KR 100368695 B1 KR100368695 B1 KR 100368695B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Abstract
반도체소자와 배선기판의 접속에 있어서, 플럭스 잔류물에 의한 접속 신뢰성의 저하가 없는 반도체소자의 실장방법을 제공한다. 미리 반도체소자(1)와 배선기판(2)을 소정의 예열온도로 가열하고 반도체소자(1)와 배선기판(2)을 압착접합하는 것에 의해 미리 땜납 범프(3)의 산화막의 일부를 압착접합에 의해 부숴 놓을 수 있다. 더구나, 반도체소자와 배선기판 위의 땜납 범프를 땜납 용융점 이상으로 가열하여 땜납 범프를 용융한 상태에서 반도체소자(1)를 소정의 방향으로 율동시킴으로써, 땜납 범프(3)의 표면을 덮고 있는 산화막을 땜납 범프(3) 안으로 받아들일 수 있기 때문에, 플럭스를 사용하지 않고 본딩을 행할 수 있다. 더구나, 대기차단 박스(6) 내부의 불활성 가스(7) 등에 의해, 반도체소자(1) 및/또는 배선기판(2) 위에 형성된 땜납 범프(3)의 표면의 산화방지 또는 산화막의 환원을 행할 수 있기 때문에, 반도체소자(1)와 배선기판(2) 사이의 접합을 더욱 안정화시킬 수 있다.In the connection between a semiconductor device and a wiring board, there is provided a method for mounting a semiconductor device without deteriorating connection reliability due to flux residues. A portion of the oxide film of the solder bumps 3 is pressed in advance by heating the semiconductor element 1 and the wiring board 2 to a predetermined preheating temperature and pressing the semiconductor element 1 and the wiring board 2 in advance. Can be broken by Furthermore, the oxide film covering the surface of the solder bumps 3 is moved by heating the solder bumps on the semiconductor element and the wiring board above the solder melting point and moving the semiconductor elements 1 in a predetermined direction while the solder bumps are melted. Since it can be received in the solder bump 3, bonding can be performed without using a flux. In addition, the oxidation prevention or reduction of the oxide film on the surface of the solder bumps 3 formed on the semiconductor element 1 and / or the wiring board 2 can be performed by the inert gas 7 or the like inside the atmospheric blocking box 6. Therefore, the junction between the semiconductor element 1 and the wiring board 2 can be further stabilized.
Description
본 발명은, 반도체소자의 실장방법에 관한 것으로, 특히, 플립칩(flip chip) 실장을 사용하여 반도체소자와 배선기판을 접속하는 반도체소자의 실장방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device, and more particularly, to a method for mounting a semiconductor device that connects a semiconductor device to a wiring board using flip chip mounting.
반도체소자의 조립기술의 한가지로서 알려져 있는 플립칩 본딩방법은, 반도체소자의 하면에 설치된 전극 위의 땜납 범프와, 이에 대향하는 배선기판의 상면에 설치된 접속 패드 위의 땜납 범프를 접속하는 방법이다. 종래의 플립칩 본딩방법은, 플럭스(flux)를 사용하고 있기 때문에, 땜납 범프의 표면의 산화막을 제거하여 땜납에 의한 접속을 용이하게 하고 있었다. 그러나, 플럭스의 양의 최적화 또는 세정공정의 관리 등을 행하지 않으면, 세정공정 후에 플럭스가 잔류물로 되어 남게 되어 버리기 때문에, 이 플럭스의 잔류물이 나중의 공정에 있어서 봉지 수지의 주입을 방해하여 버린다고 하는 문제가 있었다. 더구나, 이 플럭스의 잔류물이 마이그레이션의 발생을 유발하여, 접속 신뢰성을 저하시킨다고 하는 품질 보증상의 문제가 있었다.The flip chip bonding method known as one of the assembling techniques of a semiconductor element is a method of connecting the solder bump on the electrode provided in the lower surface of a semiconductor element, and the solder bump on the connection pad provided in the upper surface of the wiring board which opposes. In the conventional flip chip bonding method, since a flux is used, the oxide film on the surface of the solder bumps is removed to facilitate connection by soldering. However, if the quantity of the flux is not optimized or the cleaning process is not managed, the flux remains as a residue after the cleaning process, and the residue of the flux prevents the injection of the encapsulating resin in a later process. There was a problem. In addition, there was a problem in quality assurance that the residue of the flux caused the migration to occur and lowered the connection reliability.
전술한 것과 같이, 종래의 플립칩 본딩방법은 플럭스를 사용하고 있기 때문에, 세정공정 후에 남는 플럭스 잔류물에 의한 접속 신뢰성의 저하라는 문제가 있었다.As described above, since the conventional flip chip bonding method uses flux, there is a problem that the connection reliability is lowered due to the flux residue remaining after the cleaning process.
따라서, 본 발명의 목적은, 상기한 문제를 해결하기 위해 이루어진 것으로, 반도체소자와 배선기판의 접속에 플럭스를 사용하지 않는 플립칩 본딩방법을 사용함으로써, 플럭스 잔류물에 의한 접속 신뢰성의 저하가 없는 반도체소자의 실장방법을 제공함에 있다.Accordingly, an object of the present invention is to solve the above problems, and by using a flip chip bonding method in which no flux is used to connect the semiconductor element and the wiring board, there is no deterioration in connection reliability due to the flux residue. The present invention provides a method for mounting a semiconductor device.
도 1은 본 발명의 실시예 1에 있어서의 반도체소자의 실장공정의 단면도이고,1 is a cross sectional view of a semiconductor device mounting process according to the first embodiment of the present invention;
도 2는 본 발명의 실시예 2에 있어서의 반도체소자의 실장공정의 단면도이다.Fig. 2 is a sectional view of the semiconductor device mounting step in the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1: 반도체소자 2: 배선기판1: semiconductor device 2: wiring board
3: 땜납 범프 4: 본딩 헤드3: solder bump 4: bonding head
5: 본딩 스테이지 6: 대기차단 박스5: Bonding Stage 6: Standby Block
7: 불활성 가스 또는 환원성 가스7: inert gas or reducing gas
본 발명의 반도체소자의 실장방법은, 반도체소자 또는 배선기판의 어느 하나의 위에 땜납 범프를 형성하는 땜납 범프 형성공정과, 상기 반도체소자와 상기 배선기판을 땜납 용융점보다 낮은 소정의 예열온도로 가열하는 가열공정과, 상기 반도체소자를 상기 땜납 범프를 통해 상기 배선기판 위에 압착접합하는 압착접합공정과, 상기 반도체소자와 상기 배선기판이 압착접합된 상태에서, 상기 반도체를 땜납 용융점 이상의 온도로 가열하여, 상기 반도체소자 또는 상기 배선기판 위에 형성된 땜납 범프를 용융시키는 공정과, 상기 반도체소자를 수평방향 또는 연직방향의 어느 한가지의 방향으로 주기적으로 율동시키는 율동공정과, 상기 반도체소자를 땜납 용융점보다 낮은 소정의 냉각온도로 냉각시키는 냉각공정을 구비한 것이다.A semiconductor device mounting method of the present invention includes a solder bump forming step of forming solder bumps on either a semiconductor device or a wiring board, and heating the semiconductor device and the wiring board to a predetermined preheating temperature lower than a solder melting point. A heating step, a press bonding step of pressing the semiconductor element onto the wiring board through the solder bumps, and heating the semiconductor to a temperature equal to or higher than the solder melting point in a state in which the semiconductor element and the wiring board are press-bonded, A process of melting the solder bumps formed on the semiconductor device or the wiring board, a swinging process of periodically moving the semiconductor device in any one of the horizontal direction and the vertical direction, and a predetermined lowering of the semiconductor element below the solder melting point It is equipped with the cooling process to cool to cooling temperature.
여기에서, 본 발명의 반도체소자의 실장방법에 있어서, 상기 압착접합공정과 상기 율동공정은, 상기 땜납 범프를 불활성 분위기 또는 환원성 분위기의 어느 한가지의 상태로 하여 행해질 수 있는 것이다.Here, in the method for mounting a semiconductor device of the present invention, the crimp bonding step and the swinging step can be carried out with the solder bumps in either an inert atmosphere or a reducing atmosphere.
이때, 본 발명의 반도체소자의 실장방법에 있어서, 상기 땜납 범프 형성공정은, 반도체소자 위 및 배선기판 위에 각각 땜납 범프를 형성할 수 있는 것이다.At this time, in the mounting method of the semiconductor element of the present invention, the solder bump forming step is to form solder bumps on the semiconductor element and the wiring substrate, respectively.
여기에서, 본 발명의 반도체소자의 실장방법에 있어서, 상기 율동공정은, 상기 반도체소자와 상기 배선기판이 압착접합된 상태에서, 상기 반도체를 땜납 용융점 이상의 온도로 가열하고, 상기 반도체소자 또는 상기 배선기판 위에 형성된 땜납 범프를 용융한 상태에서, 상기 반도체소자를 수평방향 및 연직방향으로 주기적으로 율동시킬 수 있는 것이다.Here, in the method of mounting a semiconductor device of the present invention, the moving step is performed by heating the semiconductor to a temperature equal to or higher than a solder melting point in a state in which the semiconductor device and the wiring board are crimped together, and the semiconductor device or the wiring In the state where the solder bumps formed on the substrate are melted, the semiconductor element can be periodically moved in the horizontal direction and the vertical direction.
이때, 본 발명의 반도체소자의 실장방법에 있어서, 상기 율동공정은, 상기 반도체소자와 상기 배선기판이 압착접합된 상태에서, 상기 배선기판을 땜납 용융점 이상의 온도로 가열하고, 상기 반도체소자 또는 상기 배선기판 위에 형성된 땜납 범프를 용융한 상태에서, 상기 반도체소자를 수평방향 및 연직방향으로 주기적으로 율동시킬 수 있는 것이다.At this time, in the method of mounting a semiconductor device of the present invention, the moving step is performed by heating the wiring board to a temperature higher than the solder melting point in a state where the semiconductor device and the wiring board are crimped together, and the semiconductor device or the wiring In the state where the solder bumps formed on the substrate are melted, the semiconductor element can be periodically moved in the horizontal direction and the vertical direction.
(실시예)(Example)
이하, 도면을 참조하여, 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
실시예 1:Example 1:
도 1a 내지 도 1d는, 본 발명의 실시예 1에 있어서 반도체소자의 실장공정의 단면도를 나타낸 것이다. 도 1에 있어서, 도면부호 1은 반도체소자, 2는 반도체소자(1)를 접속하고자 하는 배선기판, 3은 반도체소자(1) 또는 배선기판(2) 위에 형성된 땜납 범프, 4는 반도체소자(1)를 지지하는 본딩 헤드, 5는 배선기판(2)을 지지하는 본딩 스테이지이다.1A to 1D show cross-sectional views of the semiconductor device mounting process in Example 1 of the present invention. 1, reference numeral 1 denotes a semiconductor element, 2 denotes a wiring board to which the semiconductor element 1 is to be connected, 3 denotes a semiconductor element 1 or a solder bump formed on the wiring substrate 2, and 4 denotes a semiconductor element 1 Is a bonding stage for supporting the wiring board 2.
다음에, 본딩 헤드(4)와 본딩 스테이지(5)를 갖는 본딩장치에 대해 설명한다. 도 1에 나타낸 것과 같이, 반도체소자(1) 위와 배선기판(2) 위에는, 각각 땜납 범프(3)가 형성되어 있지만, 이 땜납 범프(3)에는 플럭스는 공급되고 있지 않다. 본딩 헤드(4)는 진공 흡인에 의해 반도체소자(1)를 흡착할 수 있으며, 실온으로부터 땜납 용융점(약 180℃) 이상인 약 400℃ 정도까지 가열할 수 있다. 본딩 스테이지(5)는 히터(미도시)를 내장하고 있으며, 미리 배선기판(2)을 땜납 용융점 근처의 예열온도로 가열해 놓을 수 있다.Next, a bonding apparatus having a bonding head 4 and a bonding stage 5 will be described. As shown in Fig. 1, the solder bumps 3 are formed on the semiconductor element 1 and the wiring board 2, respectively, but no flux is supplied to the solder bumps 3, respectively. The bonding head 4 can adsorb | suck the semiconductor element 1 by vacuum suction, and can heat from room temperature to about 400 degreeC which is more than a solder melting point (about 180 degreeC). The bonding stage 5 incorporates a heater (not shown), and the wiring board 2 can be heated to a preheating temperature near the solder melting point in advance.
전술한 본딩장치를 사용한 반도체소자의 실장방법을 설명한다. 도 1a에 나타낸 것과 같이, 배선기판(2)은 땜납의 용융점 근처의 온도로 과열된 본딩 스테이지(5)의 상면의 소정의 위치에 위치가 결정되어 놓여져 있다. 한편, 반도체소자(1)는 땜납 용융점보다 낮은 소정의 예열온도로 가열된 본딩 헤드(4)의 하면에 흡착되어 있다. 반도체소자(1)는, 본딩 헤드(4)의 수평방향으로의 이동에 의해, 소정의 위치로 위치가 결정(얼라인먼트)된 상태에서 배선기판(2)의 상측에 위치하고 있다.The mounting method of the semiconductor element using the above-mentioned bonding apparatus is demonstrated. As shown in Fig. 1A, the wiring board 2 is positioned at a predetermined position on the upper surface of the bonding stage 5 overheated at a temperature near the melting point of the solder. On the other hand, the semiconductor element 1 is adsorbed on the lower surface of the bonding head 4 heated to a predetermined preheating temperature lower than the solder melting point. The semiconductor element 1 is located above the wiring board 2 in a state where the bonding head 4 is positioned (aligned) to a predetermined position by the movement in the horizontal direction.
도 1b에 나타낸 것과 같이, 본딩 헤드(4)가 하강하면, 반도체소자(1)는 배선기판(2) 위의 소정의 위치에 놓인다. 반도체소자(1)는 본딩 헤드(4)의 하면에 부착되어 있기 때문에, 수평방향으로 위치가 결정된 상태에서, 연직방향으로 소정시간 압력이 가해져 배선기판(2) 위에 압착접합된다. 이 결과, 각 땜납 범프(3)의 접촉면적을 크게 잡을 수가 있으며, 더구나 미리 땜납 범프(3)의 산화막의 일부를 압착접합에 의해 부숴 놓을 수 있다.As shown in FIG. 1B, when the bonding head 4 is lowered, the semiconductor element 1 is placed at a predetermined position on the wiring board 2. Since the semiconductor element 1 is attached to the lower surface of the bonding head 4, in a state where the position is determined in the horizontal direction, pressure is applied for a predetermined time in the vertical direction to be crimped onto the wiring board 2. As a result, the contact area of each solder bump 3 can be made large, and a part of the oxide film of the solder bump 3 can be previously crushed by press bonding.
도 1c에 나타낸 것과 같이, 반도체소자(1) 위에 형성된 땜납 범프(3)와 배선기판(2) 위에 형성된 땜납 범프(3)가 접촉된 상태에서, 반도체소자를 땜납 용융점 이상으로 가열하고, 반도체소자 및 배선기판 위에 형성된 땜납 범프를 용융한 상태에서, 수평방향 X 또는 연직방향 Y 중에서 한가지의 방향으로 주기적으로 율동(스크러브(scrub))시킨다. 이 결과, 땜납 범프(3)의 표면을 덮고 있는 산화막이 땜납범프(3) 안으로 받아들어져, 플럭스를 사용하지 않고 본딩을 행할 수 있다.As shown in FIG. 1C, in a state where the solder bumps 3 formed on the semiconductor element 1 and the solder bumps 3 formed on the wiring board 2 are in contact with each other, the semiconductor element is heated above the solder melting point and the semiconductor element is heated. And the solder bumps formed on the wiring board are periodically moved (scrub) in one of the horizontal direction X or the vertical direction Y in the molten state. As a result, the oxide film covering the surface of the solder bump 3 is taken into the solder bump 3, and bonding can be performed without using flux.
도 1d에 나타낸 것과 같이, 본딩 헤드(4)를 땜납 용융점보다 낮은 온도로 냉각하면, 반도체소자(1)의 온도가 저하하여, 땜납 범프(3)가 고화한다. 본딩 헤드(4)에 의한 반도체소자(1)의 흡착을 해제하는 동시에, 본딩 헤드를 상승시켜 본딩을 종료시킨다.As shown in FIG. 1D, when the bonding head 4 is cooled to a temperature lower than the solder melting point, the temperature of the semiconductor element 1 decreases, and the solder bumps 3 solidify. The adsorption of the semiconductor element 1 by the bonding head 4 is released, and the bonding head is raised to terminate the bonding.
전술한 설명에서는, 반도체소자(1) 위 및 배선기판(2) 위에 땜납 범프(3)를 형성하였지만, 땜납 범프(3)는 반도체소자(1) 또는 배선기판(2) 위의 어느 하나의 위에 형성하여도 된다. 더구나, 전술한 설명에서는, 율동 방향은 수평방향 X 또는 연직방향 Y 중에서 어느 한가지의 방향이었지만, 수평방향 X 및 연직방향 Y의 양 방향으로 율동시키는 것도 가능하다.In the above description, the solder bumps 3 are formed on the semiconductor element 1 and on the wiring board 2, but the solder bumps 3 are placed on either the semiconductor element 1 or on the wiring board 2, respectively. You may form. Moreover, in the above description, although the movement direction was either of the horizontal direction X or the vertical direction Y, it is also possible to make the movement direction to both the horizontal direction X and the vertical direction Y.
본딩 헤드(4) 및 본딩 스테이지(5)의 예열온도는, 바람직하게는 약 150℃ 정도이다. 율동 중의 본딩 헤드(4)의 온도는 바람직하게는 약 260℃ 정도이다. 냉각시의 본딩 헤드(4)의 온도는 바람직하게는 약 180℃ 정도이다. 본딩 스테이지(5)의 온도는, 율동 중인 것도 포함하여 예열온도, 바람직하게는 약 150℃ 정도로 유지되어 있다.The preheating temperature of the bonding head 4 and the bonding stage 5 becomes like this. Preferably it is about 150 degreeC. The temperature of the bonding head 4 during the movement is preferably about 260 ° C. The temperature of the bonding head 4 at the time of cooling becomes like this. Preferably it is about 180 degreeC. The temperature of the bonding stage 5 is maintained at a preheating temperature, preferably about 150 ° C, including the one that is in motion.
이상으로부터, 실시예 1에 따르면, 미리 반도체소자(1)와 배선기판(2)을 소정의 예열온도로 가열하고, 반도체소자(1)와 배선기판(2)을 압착접합하는 것에 의해, 미리 땜납 범프(3)의 산화막의 일부를 압착접합에 의해 부숴 놓을 수 있다. 더구나, 반도체소자(1)를 소정의 방향으로 율동시킴으로써, 땜납 범프(3)의 표면을 덮고 있는 산화막을 땜납 범프(3) 안으로 받아들일 수 있기 때문에, 플럭스를 사용하지 않고 본딩을 행할 수 있다.As described above, according to the first embodiment, the semiconductor element 1 and the wiring board 2 are heated to a predetermined preheating temperature in advance, and the soldering of the semiconductor element 1 and the wiring board 2 is carried out in advance by soldering. A part of the oxide film of the bump 3 can be crushed by compression bonding. Moreover, since the oxide film covering the surface of the solder bump 3 can be taken into the solder bump 3 by moving the semiconductor element 1 in a predetermined direction, bonding can be performed without using a flux.
실시예 2:Example 2:
도 2는, 본 발명의 실시예 2에 있어서의 반도체소자의 실장공정의 단면도를 나타낸 것이다. 도 2에서 도 1과 동일한 부호를 붙인 것은 동일한 기능을 갖기 때문에 설명은 생략한다. 도 2에 있어서, 부호 6은 배선기판(2)을 대기로부터 차단하는 대기차단 박스, 7은 도시된 화살표 방향으로 유입되는 불활성 가스 또는 환원성 가스이다. 대기차단 박스(6)에는, 불활성 가스 또는 환원성 가스(7)의 공급원(미도시) 및 이들 가스(7)를 가열하는 가스 가열기(미도시)가 접속되어 있다. 대기차단 박스(6) 내부에는, 항상 땜납 용융점 근처의 온도까지 가열된 불활성 가스 또는 환원성 가스(7), 또는 이들의 혼합 가스가 채워져 있다.Fig. 2 is a sectional view of the semiconductor device mounting step in the second embodiment of the present invention. In FIG. 2, the same reference numerals as in FIG. 1 have the same functions, and thus descriptions thereof are omitted. In FIG. 2, reference numeral 6 denotes an air blocking box for blocking the wiring board 2 from the atmosphere, and 7 denotes an inert gas or a reducing gas flowing in the arrow direction shown. The atmospheric blocking box 6 is connected to a source of inert gas or reducing gas 7 (not shown) and a gas heater (not shown) for heating these gases 7. In the atmosphere blocking box 6, the inert gas or the reducing gas 7 heated up to the temperature near the solder melting point, or a mixed gas thereof is always filled.
전술한 대기차단 박스(6) 내부의 불활성 가스(7) 등에 의해, 반도체소자(1) 및/또는 배선기판(2) 위에 형성된 땜납 범프(3)의 표면의 산화방지 또는 산화막의 환원을 행할 수 있기 때문에, 반도체소자(1)와 배선기판(2) 사이의 접합을 더욱 안정화시킬 수 있다.By the inert gas 7 or the like in the above-described air blocking box 6, the oxidation prevention or the reduction of the oxide film on the surface of the solder bumps 3 formed on the semiconductor element 1 and / or the wiring board 2 can be performed. Therefore, the junction between the semiconductor element 1 and the wiring board 2 can be further stabilized.
본 실시예 2에 나타낸 반도체소자의 실장방법은, 땜납 범프(3)의 땜납재료에 무관하게 실장을 행할 수 있다. 더구나, 배선기판(2)은 세라믹 기판 또는 유기수지 기판이라도 실장을 행할 수 있다.The semiconductor element mounting method shown in the second embodiment can be mounted irrespective of the solder material of the solder bumps 3. In addition, the wiring board 2 can be mounted even on a ceramic substrate or an organic resin substrate.
이상으로부터, 실시예 2에 따르면, 대기차단 박스(6) 내부의 불활성 가스(7) 등에 의해, 반도체소자(1) 위 및/또는 배선기판(2) 위에 형성된 땜납 범프(3)의 표면의 산화방지 또는 산화막의 환원을 행할 수 있기 때문에, 반도체소자(1)와 배선기판(2) 사이의 접합을 더욱 안정화시킬 수 있다.As described above, according to the second embodiment, oxidation of the surface of the solder bumps 3 formed on the semiconductor element 1 and / or on the wiring board 2 by the inert gas 7 or the like inside the atmospheric blocking box 6 or the like. Since the prevention or reduction of the oxide film can be performed, the bonding between the semiconductor element 1 and the wiring board 2 can be further stabilized.
이상에서 설명한 것과 같이, 본 발명의 반도체소자의 실장방법에 따르면, 반도체소자와 배선기판의 접속에 플럭스를 사용하지 않는 플립칩 본딩방법을 사용하는 것에 의해, 플럭스 잔류물에 의한 접속 신뢰성의 저하가 없는 반도체소자의 실장방법을 제공할 수 있다.As described above, according to the method of mounting the semiconductor device of the present invention, the flip reliability bonding caused by the flux residue is reduced by using the flip chip bonding method in which the flux is not used to connect the semiconductor device and the wiring board. A method of mounting a semiconductor device can be provided.
Claims (5)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15418299A JP4275806B2 (en) | 1999-06-01 | 1999-06-01 | Mounting method of semiconductor element |
| JP11-154182 | 1999-06-01 |
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| Publication Number | Publication Date |
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| KR20010014820A KR20010014820A (en) | 2001-02-26 |
| KR100368695B1 true KR100368695B1 (en) | 2003-01-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0021854A KR100368695B1 (en) | 1999-06-01 | 2000-04-25 | Method for mounting semiconductor elements |
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| Country | Link |
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| US (1) | US6265244B1 (en) |
| JP (1) | JP4275806B2 (en) |
| KR (1) | KR100368695B1 (en) |
| TW (1) | TW459319B (en) |
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| US6461891B1 (en) | 1999-09-13 | 2002-10-08 | Intel Corporation | Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple |
| JP4456234B2 (en) * | 2000-07-04 | 2010-04-28 | パナソニック株式会社 | Bump formation method |
| DE10147789B4 (en) * | 2001-09-27 | 2004-04-15 | Infineon Technologies Ag | Device for soldering contacts on semiconductor chips |
| US6504242B1 (en) | 2001-11-15 | 2003-01-07 | Intel Corporation | Electronic assembly having a wetting layer on a thermally conductive heat spreader |
| JP2004265888A (en) * | 2003-01-16 | 2004-09-24 | Sony Corp | Semiconductor device and its manufacturing method |
| JP2005191460A (en) * | 2003-12-26 | 2005-07-14 | Fujitsu Ltd | Manufacturing method and manufacturing apparatus of semiconductor device |
| JP4534062B2 (en) | 2005-04-19 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP4736948B2 (en) * | 2006-05-22 | 2011-07-27 | 株式会社デンソー | Electronic component mounting method |
| JP4870584B2 (en) | 2007-01-19 | 2012-02-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP4998073B2 (en) | 2007-05-07 | 2012-08-15 | ソニー株式会社 | Semiconductor chip and manufacturing method thereof |
| US8143719B2 (en) | 2007-06-07 | 2012-03-27 | United Test And Assembly Center Ltd. | Vented die and package |
| JP5645592B2 (en) * | 2010-10-21 | 2014-12-24 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| TWI453845B (en) * | 2011-01-05 | 2014-09-21 | Toshiba Kk | Method for manufacturing semiconductor device |
| KR101214683B1 (en) | 2011-01-13 | 2012-12-21 | 가부시끼가이샤 도시바 | Method for manufacturing semiconductor device |
| US8802553B2 (en) | 2011-02-10 | 2014-08-12 | Infineon Technologies Ag | Method for mounting a semiconductor chip on a carrier |
| JP2012235055A (en) * | 2011-05-09 | 2012-11-29 | Daitron Technology Co Ltd | Joining method and joining device |
| JP2011211243A (en) * | 2011-07-27 | 2011-10-20 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| KR101330225B1 (en) * | 2012-05-25 | 2013-11-18 | 피에스케이 주식회사 | Method for bonding of substrate and substrate reflow treatment apparatus |
| EP2743972A1 (en) | 2012-12-17 | 2014-06-18 | Imec | Method for bonding semiconductor substrates and devices obtained thereby |
| JP6165127B2 (en) * | 2014-12-22 | 2017-07-19 | 三菱重工工作機械株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US9847313B2 (en) * | 2015-04-24 | 2017-12-19 | Kulicke And Soffa Industries, Inc. | Thermocompression bonders, methods of operating thermocompression bonders, and horizontal scrub motions in thermocompression bonding |
| KR102217812B1 (en) * | 2018-11-28 | 2021-02-22 | 주식회사 오럼머티리얼 | Producing device of mask integrated frame |
| CN110047766B (en) * | 2019-04-25 | 2020-10-20 | 广东工业大学 | Dual-mode hybrid control chip flip method |
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| DE3877438T2 (en) * | 1987-07-10 | 1993-06-03 | Hitachi Ltd | SEMICONDUCTOR REFRIGERATOR. |
| US4996589A (en) * | 1987-10-21 | 1991-02-26 | Hitachi, Ltd. | Semiconductor module and cooling device of the same |
| JP2507561B2 (en) * | 1988-10-19 | 1996-06-12 | 株式会社日立製作所 | Semiconductor cooling system |
| JPH0682710B2 (en) | 1989-03-31 | 1994-10-19 | アメリカン テレフォン アンド テレグラフ カムパニー | Device manufacturing method |
| JP3423727B2 (en) | 1992-01-16 | 2003-07-07 | 富士通株式会社 | Flip chip bonding method |
| JP3275396B2 (en) | 1992-10-12 | 2002-04-15 | カシオ計算機株式会社 | IC chip bonding method and bonding head |
| US5821627A (en) * | 1993-03-11 | 1998-10-13 | Kabushiki Kaisha Toshiba | Electronic circuit device |
| JPH08222846A (en) | 1995-02-15 | 1996-08-30 | Citizen Watch Co Ltd | Method for mounting semiconductor chip |
-
1999
- 1999-06-01 JP JP15418299A patent/JP4275806B2/en not_active Expired - Fee Related
- 1999-11-15 US US09/440,515 patent/US6265244B1/en not_active Expired - Lifetime
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2000
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| JP2000349123A (en) | 2000-12-15 |
| TW459319B (en) | 2001-10-11 |
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