KR100337461B1 - 반도체패키지 및 그 제조 방법 - Google Patents
반도체패키지 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100337461B1 KR100337461B1 KR1019980046574A KR19980046574A KR100337461B1 KR 100337461 B1 KR100337461 B1 KR 100337461B1 KR 1019980046574 A KR1019980046574 A KR 1019980046574A KR 19980046574 A KR19980046574 A KR 19980046574A KR 100337461 B1 KR100337461 B1 KR 100337461B1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit board
- board sheet
- semiconductor chip
- input
- sheet
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (2)
- 입출력패드가 형성되어 있는 반도체칩과;상기 반도체칩의 상부에 그 반도체칩의 넓이보다 더 넓게 접착제로 접착되어 있되, 상기 반도체칩의 입출력패드와 대응하는 위치에는 소정의 공간부가 형성된 회로기판시트와;상기 공간부 내측에서 회로기판시트와 반도체칩의 입출력패드를 연결하는 도전성와이어와;상기 도전성와이어 등을 외부의 환경으로부터 보호하기 위해 회로기판시트의 공간부에 충진된 봉지재와;상기 반도체칩의 외주연상에 위치된 회로기판시트의 하단부에 봉지되어 상기 회로기판시트의 둘레를 지지시켜주는 시트지지용 봉지재와;상기 회로기판시트의 상부에 융착됨으로써 차후 마더보드에 실장되는 솔더볼을 포함하여 이루어진 반도체패키지.
- 폴리이미드층상에 구리박막을 입히는 원시 회로기판시트 제조 단계와;상기 원시 회로기판시트 상에 통상의 포토마스킹 및 에칭 기술을 이용하여 본드핑거, 연결부, 솔더볼랜드 등의 회로패턴을 형성하고, 상기 본드핑거, 솔더볼랜드를 제외한 상면을 커버코오트로 코팅하는 회로기판시트 제조 단계와;상기 회로기판시트의 저면에 접착제를 붙이는 접착제 부착 단계와;차후 반도체칩의 입출력패드와 대응하는 회로기판시트 및 접착제의 소정 영역에 펀칭툴로 소정의 공간부를 형성하는 공간부 형성 단계와;상기 접착제가 부착된 회로기판시트에 웨이퍼에서 미리 절단된 양품의 반도체칩을 선별하여 그 상면에 접착시키되, 상기 공간부를 통해서 반도체칩의 입출력패드가 외부로 노출되도록 하는 회로기판시트 접착 단계와;상기 반도체칩의 입출력패드와 회로기판시트의 본드핑거를 도전성와이어로 본딩하는 와이어본딩 단계와;상기 회로기판시트의 공간부 내측에 봉지재를 충진하여 도전성와이어를 외부 환경으로부터 보호하는 1차 봉지 단계와;상기 회로기판시트의 하단부에서 반도체칩 측면까지 봉지재로 봉지하여 회로기판시트의 둘레가 반도체칩에 의해 지지되도록 하는 2차 봉지 단계와;상기 회로기판시트에 구비된 솔더볼랜드상에 고온의 환경에서 솔더볼을 융착하는 솔더볼 융착 단계를 포함하여 이루어진 반도체패키지의 제조 방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980046574A KR100337461B1 (ko) | 1998-10-31 | 1998-10-31 | 반도체패키지 및 그 제조 방법 |
JP11171708A JP2000138262A (ja) | 1998-10-31 | 1999-06-17 | チップスケ―ル半導体パッケ―ジ及びその製造方法 |
US09/422,027 US6462274B1 (en) | 1998-10-31 | 1999-10-20 | Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980046574A KR100337461B1 (ko) | 1998-10-31 | 1998-10-31 | 반도체패키지 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000028369A KR20000028369A (ko) | 2000-05-25 |
KR100337461B1 true KR100337461B1 (ko) | 2002-07-18 |
Family
ID=19556729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019980046574A KR100337461B1 (ko) | 1998-10-31 | 1998-10-31 | 반도체패키지 및 그 제조 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100337461B1 (ko) |
-
1998
- 1998-10-31 KR KR1019980046574A patent/KR100337461B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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KR20000028369A (ko) | 2000-05-25 |
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