KR100310492B1 - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture Download PDF

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Publication number
KR100310492B1
KR100310492B1 KR1019980035517A KR19980035517A KR100310492B1 KR 100310492 B1 KR100310492 B1 KR 100310492B1 KR 1019980035517 A KR1019980035517 A KR 1019980035517A KR 19980035517 A KR19980035517 A KR 19980035517A KR 100310492 B1 KR100310492 B1 KR 100310492B1
Authority
KR
South Korea
Prior art keywords
film
metal
sog
bonding
sio2
Prior art date
Application number
KR1019980035517A
Other languages
English (en)
Inventor
Tatsuya Usami
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Application granted granted Critical
Publication of KR100310492B1 publication Critical patent/KR100310492B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
KR1019980035517A 1997-09-02 1998-08-31 Semiconductor device and its manufacture KR100310492B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23738597A JP3226021B2 (ja) 1997-09-02 1997-09-02 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR100310492B1 true KR100310492B1 (en) 2002-02-19

Family

ID=17014614

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980035517A KR100310492B1 (en) 1997-09-02 1998-08-31 Semiconductor device and its manufacture

Country Status (5)

Country Link
US (1) US6133137A (ko)
JP (1) JP3226021B2 (ko)
KR (1) KR100310492B1 (ko)
CN (1) CN1135607C (ko)
GB (1) GB2329069B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038530B1 (ko) * 2007-05-23 2011-06-02 르네사스 일렉트로닉스 가부시키가이샤 장벽금속 및 피복막을 포함하는 반도체 장치 및 이를제조하기 위한 방법

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6157083A (en) * 1996-06-03 2000-12-05 Nec Corporation Fluorine doping concentrations in a multi-structure semiconductor device
JP3248492B2 (ja) * 1998-08-14 2002-01-21 日本電気株式会社 半導体装置及びその製造方法
US6165905A (en) * 1999-01-20 2000-12-26 Philips Electronics, North America Corp. Methods for making reliable via structures having hydrophobic inner wall surfaces
GB9904427D0 (en) 1999-02-26 1999-04-21 Trikon Holdings Ltd Method treating an insulating layer
JP2000294545A (ja) * 1999-04-09 2000-10-20 Nec Corp 半導体装置及びその製造方法
TW428230B (en) * 1999-09-27 2001-04-01 United Microelectronics Corp Post-treatment procedure for material with low dielectric constant
US7011868B2 (en) * 2000-03-20 2006-03-14 Axcelis Technologies, Inc. Fluorine-free plasma curing process for porous low-k materials
US6913796B2 (en) * 2000-03-20 2005-07-05 Axcelis Technologies, Inc. Plasma curing process for porous low-k materials
US7053005B2 (en) * 2000-05-02 2006-05-30 Samsung Electronics Co., Ltd. Method of forming a silicon oxide layer in a semiconductor manufacturing process
KR100362834B1 (ko) 2000-05-02 2002-11-29 삼성전자 주식회사 반도체 장치의 산화막 형성 방법 및 이에 의하여 제조된 반도체 장치
US7122900B2 (en) 2000-06-26 2006-10-17 Renesas Technology Corp. Semiconductor device and method manufacturing the same
DE60126906T2 (de) * 2000-06-30 2007-11-08 Tokyo Electron Ltd. Herstellungsverfahren für ein halbleiterbauelement
US6479405B2 (en) * 2000-10-12 2002-11-12 Samsung Electronics Co., Ltd. Method of forming silicon oxide layer in semiconductor manufacturing process using spin-on glass composition and isolation method using the same method
US6784095B1 (en) * 2001-02-14 2004-08-31 Advanced Micro Devices, Inc. Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing
SG102047A1 (en) * 2002-05-02 2004-02-27 Dso Nat Lab Ladder-like silicone polymers
US6914014B2 (en) * 2003-01-13 2005-07-05 Applied Materials, Inc. Method for curing low dielectric constant film using direct current bias
JP2004235548A (ja) 2003-01-31 2004-08-19 Nec Electronics Corp 半導体装置およびその製造方法
KR100464859B1 (ko) * 2003-02-26 2005-01-06 삼성전자주식회사 스핀온글래스 조성물을 이용한 캐패시터 형성 방법
US6921727B2 (en) 2003-03-11 2005-07-26 Applied Materials, Inc. Method for modifying dielectric characteristics of dielectric layers
JP5204370B2 (ja) * 2005-03-17 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
TWI389250B (zh) * 2006-01-18 2013-03-11 Az Electronic Mat Ip Japan Kk 矽石質膜之製法及附有由它製造的矽石質膜之基板
JP2009188411A (ja) * 2009-03-06 2009-08-20 Tokyo Electron Ltd シリル化処理方法、シリル化処理装置およびエッチング処理システム
CN102738076B (zh) * 2012-07-27 2014-10-22 上海华力微电子有限公司 通孔优先铜互连制作方法
CN105819393B (zh) * 2015-01-06 2017-04-05 中芯国际集成电路制造(上海)有限公司 改善惯性传感器中金属损失的方法
KR102395487B1 (ko) * 2019-08-21 2022-05-06 삼성에스디아이 주식회사 실리카 막 형성용 조성물 및 실리카 막

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056064A (ja) * 1996-05-31 1998-02-24 Texas Instr Inc <Ti> 金属間絶縁層形成法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2928409B2 (ja) * 1991-08-19 1999-08-03 松下電子工業株式会社 半導体装置の製造方法
JP2751820B2 (ja) * 1994-02-28 1998-05-18 日本電気株式会社 半導体装置の製造方法
KR0138853B1 (ko) * 1994-11-03 1998-06-01 양승택 플라즈마에 의한 SOG(Spin-On Glass) 경화(Curing) 방법
JP3281209B2 (ja) * 1995-01-30 2002-05-13 株式会社東芝 半導体装置の製造方法
JP2758847B2 (ja) * 1995-02-08 1998-05-28 日本電気株式会社 スピンオングラス膜の形成方法
JPH0964037A (ja) * 1995-08-23 1997-03-07 Mitsubishi Electric Corp 半導体装置の製造方法
JPH10214892A (ja) * 1997-01-30 1998-08-11 Sony Corp 半導体装置の製造方法
JPH10335458A (ja) * 1997-05-30 1998-12-18 Nec Corp 半導体装置及びその製造方法
TW375779B (en) * 1997-06-03 1999-12-01 United Microelectronics Corp Method for treating via side wall

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056064A (ja) * 1996-05-31 1998-02-24 Texas Instr Inc <Ti> 金属間絶縁層形成法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038530B1 (ko) * 2007-05-23 2011-06-02 르네사스 일렉트로닉스 가부시키가이샤 장벽금속 및 피복막을 포함하는 반도체 장치 및 이를제조하기 위한 방법

Also Published As

Publication number Publication date
CN1210361A (zh) 1999-03-10
GB9819141D0 (en) 1998-10-28
JP3226021B2 (ja) 2001-11-05
CN1135607C (zh) 2004-01-21
JPH1187332A (ja) 1999-03-30
US6133137A (en) 2000-10-17
GB2329069A (en) 1999-03-10
GB2329069B (en) 2002-02-13

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