KR100291180B1 - Method for forming gate-electrode in semiconductor device - Google Patents
Method for forming gate-electrode in semiconductor device Download PDFInfo
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- KR100291180B1 KR100291180B1 KR1019970075070A KR19970075070A KR100291180B1 KR 100291180 B1 KR100291180 B1 KR 100291180B1 KR 1019970075070 A KR1019970075070 A KR 1019970075070A KR 19970075070 A KR19970075070 A KR 19970075070A KR 100291180 B1 KR100291180 B1 KR 100291180B1
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- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims description 15
- 239000010936 titanium Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 230000007261 regionalization Effects 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 1
- 230000002776 aggregation Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000005054 agglomeration Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000004220 aggregation Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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Abstract
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치를 구성하는 가장 기본적인 소자(element)인 모스 트랜지스터의 게이트 전극 형성에 관한 것이며, 더 자세히는 실리사이드막을 적용한 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a gate electrode formation of a MOS transistor, which is the most basic element constituting a semiconductor device, and more particularly, to a gate electrode formation method using a silicide film.
일반적으로 실리사이드(Silicide) 게이트 공정은 소오스/드레인 영역 및 게이트 전극 상부를 동시에 실리사이드화하는 자기정렬(Self-aligned) 방식으로 진행되어 왔다. 그러나 최근 DRAM에서는 이러한 자기정렬 방식이 DRAM 설계 및 공정 상의 어려움을 수반하기 때문에 게이트 전극 상에만 실리사이드막을 형성시키는 기술 쪽으로 관심이 옮겨가고 있다.In general, the silicide gate process has been performed in a self-aligned manner in which silicides of the source / drain region and the gate electrode are simultaneously silicided. However, in recent years, since the self-alignment method is accompanied by difficulties in DRAM design and process, attention has shifted to a technology of forming a silicide film only on a gate electrode.
티타늄 실리사이드막(TiSi)을 예로 들어 그 공정을 간략히 살펴보면, 우선, 게이트 산화막 상부에 폴리실리콘막을 증착하고, 그 상부에 티타늄막을 증착한 다음, 열공정을 실시하여 티타늄 실리사이드막을 형성한다. 계속하여, 사진 및 식각 공정을 진행하여 티타늄 실리사이드막 및 폴리실리콘막을 차례로 선택 식각함으로써 게이트 전극 패턴을 형성한다.Taking a brief description of the process using a titanium silicide film (TiSi) as an example, first, a polysilicon film is deposited on the gate oxide film, a titanium film is deposited on the top thereof, and then a thermal process is performed to form a titanium silicide film. Subsequently, the gate electrode pattern is formed by sequentially etching the titanium silicide film and the polysilicon film by sequentially performing a photo and etching process.
이후, 게이트 전극 패턴 형성시의 식각에 의한 기판 및 게이트 산화막의 손상을 회복시키기 위한 재열산화 공정(re-oxidation)을 실시한다. 이러한 열산화 공정은 비교적 고온 공정으로 진행되므로 티타늄 실리사이드막 내에서 응집(agglomeration) 현상이 발생하거나, 티타늄 실리사이드막 내의 Ti의 이상산화현상이 발생하는 문제점이 있었다.Thereafter, a re-oxidation process is performed to recover damages to the substrate and the gate oxide film due to etching during the formation of the gate electrode pattern. Since the thermal oxidation process is performed at a relatively high temperature process, there is a problem in that an agglomeration phenomenon occurs in the titanium silicide film or an abnormal oxidation phenomenon of Ti in the titanium silicide film occurs.
이러한 문제점은 티타늄 실리사이드막 외에 텅스텐(W), 코발트(Co), 몰리브덴(Mo) 등의 리프렉토리(refractory) 금속을 사용한 실리사이드막을 적용한 게이트 전극 형성 공정에도 발생하는 것이다.This problem also occurs in a gate electrode forming process in which a silicide film using a refractory metal such as tungsten (W), cobalt (Co), molybdenum (Mo), etc. is used in addition to the titanium silicide film.
본 발명은 실리사이드막을 적용한 게이트 전극 형성시 열적 안정성을 확보할 수 있는 반도체 장치의 게이트 전극 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of securing thermal stability when forming a gate electrode to which a silicide film is applied.
도 1a 내지 도 1d는 본 발명의 일실시예에 따른 반도체 장치의 게이트 전극 형성 공정도.1A to 1D are diagrams illustrating a process of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : 게이트 산화막10
12 : 폴리실리콘막 13 : 산화막 스페이서12
14 : 층간 절연막 15 : 티타늄막14
16 : 티타늄 실리사이드막16: titanium silicide film
상기의 목적을 달성하기 위한 본 발명의 반도체 장치의 게이트 전극 형성방법은 반도체 기판 상에 게이트 절연막 및 폴리실리콘 게이트 전극 패턴을 형성하는 단계; 상기 폴리실리콘 게이트전극 패턴 형성으로 인한 상기 게이트절연막의 손상을 회복시키기 위한 재열산화 공정을 실시하는 단계; 상기 구조 전면에 층간절연막을 형성하는 단계; 상기 층간절연막을 에치백하여 상기 폴리실리콘 게이트 전극 패턴의 표면을 노출시키는 단계; 전체 구조 상부에 금속막을 형성하는 단계; 실리사이드반응을 위한 열처리를 실시하여 상기 폴리실리콘 게이트전극 패턴상에 실리사이드막을 형성하는 단계; 및 상기 실리사이드반응 후 잔류하는 상기 금속막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.A gate electrode forming method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a gate insulating film and a polysilicon gate electrode pattern on a semiconductor substrate; Performing a re-thermal oxidation process for recovering damage to the gate insulating layer due to the polysilicon gate electrode pattern formation; Forming an interlayer insulating film over the entire structure; Etching back the interlayer insulating film to expose a surface of the polysilicon gate electrode pattern; Forming a metal film on the entire structure; Performing a heat treatment for silicide reaction to form a silicide film on the polysilicon gate electrode pattern; And removing the metal film remaining after the silicide reaction.
즉, 본 발명은 게이트 전극 패턴 식각후 기판 및 게이트 산화막의 손상 회복을 위한 재열산화 공정 진행 후에 실리사이드 공정을 진행하는 게이트 전극 형성 공정을 제공하여 고온의 재열산화 공정시 발생하는 실리사이드막의 응집 현상 및 이상산화현상을 방지할 수 있다.That is, the present invention provides a gate electrode forming process for performing a silicide process after a rethermal oxidation process for recovering damage to a substrate and a gate oxide film after etching the gate electrode pattern, thereby causing a phenomenon of aggregation and abnormality of the silicide film generated during a high temperature rethermal oxidation process Oxidation can be prevented.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
첨부된 도면 도 1a 내지 도 1d는 본 발명의 일실시예에 따른 반도체 장치의게이트 전극 형성 공정을 도시한 것이다.1A to 1D illustrate a process of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
우선, 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 게이트 산화막(11)을 성장시키고, 그 상부에 게이트 전극용 폴리실리콘막(도시 생략)을 증착한 다음, 폴리실리콘막 및 게이트 산화막(11)을 선택 식각하여 게이트 전극(12)을 형성한다.First, as shown in FIG. 1A, a
다음으로, 도 1b에 도시된 바와 같이 상게 게이트전극(12) 식각으로 발생된 실리콘 기판(10) 및 게이트 산화막(11)의 손상을 회복시키기 위해 게이트산화막(11)의 재열산화 공정을 실시한다. 이어, 상기 게이트전극(12)을 포함한 전체구조 상부에 산화막을 증착한 후, 이를 전면 식각하여 게이트 전극(12)의 측벽에 접하는 산화막 스페이서(13)를 형성한 다음, 전체구조 상부에 게이트 전극(12)을 덮도록 충분한 두께로 층간절연막(14)을 증착한다. 이 때, 산화막 스페이서(13) 형성 이후에 게이트산화막(11)의 재열산화 공정을 실시할 수도 있다.Next, as shown in FIG. 1B, a rethermal oxidation process of the
계속하여, 도 1c에 도시된 바와 같이, 화학적기계적연마(Chemical Mechanical Polishing) 방식 또는 일반적인 전면성 에치백(Etchback) 방식을 사용하여 상기 층간절연막(14)을 부분적으로 제거하여 게이트 전극(12)의 표면을 노출시키고, 전체구조 상부에 통상 이용되는 RF(Radio Frequency) 스퍼터링법(Sputtering), DC스퍼터링법 또는 전자빔(Electron beam) 증착법을 이용하여 티타늄막(15)을 증착한다.Subsequently, as shown in FIG. 1C, the
이어서, 도 1d에 도시된 바와 같이 질소가스 분위기에서 열공정을 실시하여 티타늄막(15)을 열처리하면 티타늄막(15)과 게이트전극(12)을 이루는 폴리실리콘과의 실리사이드반응으로 인해 상기 게이트전극(12) 상에 준안정상태의 티타늄실리사이드막(16)이 형성되며, 층간절연막(14)상에 증착되어 실리사이드 반응에 참여하지 않은 티타늄막(15)은 습식 식각 방식을 사용하여 제거함으로써 티타늄실리사이드막(16)을 적용한 게이트 전극 형성 공정을 완료한다.Subsequently, when the
전술한 바와 같이, 게이트산화막 손상 회복을 위한 재열산화공정을 먼저 실시하고 실리사이드막을 형성하므로써, 고온 공정에 의한 실리사이드막의 응집현상 및 이상산화 현상을 방지할 수 있다.As described above, by performing a re-thermal oxidation process for recovering damage to the gate oxide film and forming a silicide film, it is possible to prevent aggregation and abnormal oxidation of the silicide film by the high temperature process.
본 발명의 다른 실시예는 상술한 일실시예에서 티타늄막 증착을 대신하여 코발트(Co)막, 몰리브덴(Mo)막 또는 텅스텐(W)막을 이용할 수 있다.According to another embodiment of the present invention, a cobalt (Co) film, a molybdenum (Mo) film, or a tungsten (W) film may be used instead of the titanium film deposition in the above-described embodiment.
특히, 선택적 텅스텐막(Selective-W)을 이용하는 경우, 게이트 전극 상부에서만 텅스텐막의 증착이 일어나기 때문에 후속 텅스텐 실리사이드막 형성후 잉여 텅스텐막이 남지 않도록 할 수 있어 텅스텐막 제거 공정을 필요로 하지 않는다. 물론 전면성 텅스텐막 증착 방식을 사용할 경우에는 상술한 제거 공정을 실시해야 한다.In particular, in the case of using the selective tungsten film (Selective-W), since the tungsten film is deposited only on the gate electrode, it is possible to prevent excess tungsten film from remaining after the formation of the subsequent tungsten silicide film, thus eliminating the need for a tungsten film removal process. Of course, when the full-tungsten film deposition method is used, the above-described removal process should be performed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
이상에서와 같이 본 발명은 게이트산화막 손상회복을 위한 재열산화공정을먼저 실시하므로써 재열산화 공정시의 고온에 의한 실리사이드막의 응집 현상 및 이상 산화 현상을 효과적으로 방지하여 반도체 장치의 특성 및 신뢰성을 향상시킬 수 있다.As described above, the present invention can improve the characteristics and reliability of the semiconductor device by effectively preventing the agglomeration and abnormal oxidation of the silicide film due to the high temperature during the re-oxidation process by performing the re-thermal oxidation process for the gate oxide film damage recovery first. have.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970075070A KR100291180B1 (en) | 1997-12-27 | 1997-12-27 | Method for forming gate-electrode in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970075070A KR100291180B1 (en) | 1997-12-27 | 1997-12-27 | Method for forming gate-electrode in semiconductor device |
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| Publication Number | Publication Date |
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| KR19990055158A KR19990055158A (en) | 1999-07-15 |
| KR100291180B1 true KR100291180B1 (en) | 2001-07-12 |
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