KR100263001B1 - 중재자 - Google Patents

중재자 Download PDF

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Publication number
KR100263001B1
KR100263001B1 KR1019920022802A KR920022802A KR100263001B1 KR 100263001 B1 KR100263001 B1 KR 100263001B1 KR 1019920022802 A KR1019920022802 A KR 1019920022802A KR 920022802 A KR920022802 A KR 920022802A KR 100263001 B1 KR100263001 B1 KR 100263001B1
Authority
KR
South Korea
Prior art keywords
input signals
groups
priority
input
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019920022802A
Other languages
English (en)
Korean (ko)
Other versions
KR930015431A (ko
Inventor
이. 다이크 챨스
Original Assignee
요트.게.아. 롤페즈
코닌클리케 필립스 일렉트로닉스 엔.브이.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 요트.게.아. 롤페즈, 코닌클리케 필립스 일렉트로닉스 엔.브이. filed Critical 요트.게.아. 롤페즈
Publication of KR930015431A publication Critical patent/KR930015431A/ko
Application granted granted Critical
Publication of KR100263001B1 publication Critical patent/KR100263001B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Logic Circuits (AREA)
KR1019920022802A 1991-12-04 1992-11-30 중재자 Expired - Fee Related KR100263001B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80426291A 1991-12-04 1991-12-04
US804,262 1991-12-04

Publications (2)

Publication Number Publication Date
KR930015431A KR930015431A (ko) 1993-07-24
KR100263001B1 true KR100263001B1 (ko) 2000-08-01

Family

ID=25188558

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920022802A Expired - Fee Related KR100263001B1 (ko) 1991-12-04 1992-11-30 중재자

Country Status (6)

Country Link
US (1) US5404540A (enExample)
EP (1) EP0545482B1 (enExample)
JP (1) JPH05257874A (enExample)
KR (1) KR100263001B1 (enExample)
DE (1) DE69226011T2 (enExample)
TW (1) TW208099B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5713025A (en) * 1993-10-21 1998-01-27 Sun Microsystems, Inc. Asynchronous arbiter using multiple arbiter elements to enhance speed
US5875339A (en) * 1993-10-21 1999-02-23 Sun Microsystems, Inc. Asynchronous arbiter using multiple arbiter elements to enhance speed
US6795365B2 (en) * 2002-08-23 2004-09-21 Micron Technology, Inc. DRAM power bus control
US7586927B1 (en) * 2003-11-04 2009-09-08 Force 10 Networks, Inc. Multistage cascade arbiter
US7949812B1 (en) * 2007-09-07 2011-05-24 Marvell International Ltd. Priority arbitration of coexisting wireless topologies
US20120089759A1 (en) * 2010-10-08 2012-04-12 Qualcomm Incorporated Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s)

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3964054A (en) * 1975-06-23 1976-06-15 International Business Machines Corporation Hierarchy response priority adjustment mechanism
US4035780A (en) * 1976-05-21 1977-07-12 Honeywell Information Systems, Inc. Priority interrupt logic circuits
BE887134A (fr) * 1979-12-14 1981-05-14 Gte Automatic Electric Lab Inc Circuit expanseur d'interruption
IT1128762B (it) * 1980-02-20 1986-06-04 Cselt Centro Studi Lab Telecom Circuito per diagnosi di reti di connessione pcm
US4395753A (en) * 1980-06-26 1983-07-26 Gte Automatic Electric Labs Inc. Allocation controller providing for access of multiple common resources by a plurality of central processing units
FR2494010B1 (fr) * 1980-11-07 1986-09-19 Thomson Csf Mat Tel Dispositif d'arbitration decentralisee de plusieurs unites de traitement d'un systeme multiprocesseur
JPS593614A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd 優先順位制御方式
US4627018A (en) * 1983-09-08 1986-12-02 Sperry Corporation Priority requestor accelerator
US4835672A (en) * 1984-04-02 1989-05-30 Unisys Corporation Access lock apparatus for use with a high performance storage unit of a digital data processing system
US4649475A (en) * 1984-04-02 1987-03-10 Sperry Corporation Multiple port memory with port decode error detector
US4633394A (en) * 1984-04-24 1986-12-30 International Business Machines Corp. Distributed arbitration for multiple processors
US4809164A (en) * 1986-03-26 1989-02-28 Tandem Computers Incorporated Processor controlled modifying of tabled input/output priority
EP0262608A1 (de) * 1986-09-30 1988-04-06 Siemens Aktiengesellschaft Anordnung zum Auswählen von Prioritäten bei einer Unterbrechungssteuerung
US4897833A (en) * 1987-10-16 1990-01-30 Digital Equipment Corporation Hierarchical arbitration system
JPH01126751A (ja) * 1987-11-11 1989-05-18 Fujitsu Ltd グルーピング装置
US4835422A (en) * 1988-03-14 1989-05-30 North American Philips Corporation Arbiter circuits with metastable free outputs
US4924380A (en) * 1988-06-20 1990-05-08 Modular Computer Systems, Inc. (Florida Corporation) Dual rotating priority arbitration method for a multiprocessor memory bus
JPH0831040B2 (ja) * 1989-01-12 1996-03-27 沖電気工業株式会社 多入力プライオリティエンコーダ
US4969120A (en) * 1989-02-13 1990-11-06 International Business Machines Corporation Data processing system for time shared access to a time slotted bus
US5280591A (en) * 1991-07-22 1994-01-18 International Business Machines, Corporation Centralized backplane bus arbiter for multiprocessor systems

Also Published As

Publication number Publication date
DE69226011T2 (de) 1999-02-04
TW208099B (enExample) 1993-06-21
EP0545482A1 (en) 1993-06-09
EP0545482B1 (en) 1998-06-24
DE69226011D1 (de) 1998-07-30
US5404540A (en) 1995-04-04
KR930015431A (ko) 1993-07-24
JPH05257874A (ja) 1993-10-08

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