KR100234198B1 - A circuit for verifying signal of selecting control board - Google Patents

Abstract

The present invention relates to a control board selection signal verification circuit, comprising: a control board selection signal verification circuit between an inspection board and an inspection board for verifying a board selection signal of a control board, the selection signal being received from the inspection board; An encoder that outputs a data signal and an enable signal, and is connected to the encoder to receive an address / data signal and an enable signal, and when the selection signal is applied to the output control signal from the test board, the enable signal is converted into a clock pulse. By operating during the rise time of the enable signal entering the clock pulse, the flip-flop for accurately reading the data of the signal, and the enable signal transmitted from the encoder to the flip-flop connected between the encoder and the flip-flop Delay the predetermined time to time difference between the signals applied to the flip-flop It is characterized by comprising an inverter for reducing.

Therefore, the board selection signal verification circuit of the control board of the present invention enables accurate inspection of the board selection signal in the control board and increases the board selection signal due to continuous operation or the board according to the expansion of the control board of the system. Even when the selection signal increases, it can be easily and accurately checked.

Description

Board selection signal verification circuit of control board

1 is a block diagram of a board selection signal verification circuit of a conventional CPU board.

2 is a timing diagram showing a delay time between the selection signal and the write signal of FIG.

3 is a block diagram of a board selection signal verification circuit of a CPU board according to the present invention.

4 is a timing diagram showing a delay time for each signal of the signal of FIG.

5A and 5B are a circuit diagram and an operation table of the latch means of FIG.

6A and 6B are a circuit diagram and an operation table of the flip-flop means of FIG.

7A and 7B are a circuit diagram and an operation table of the encoder of FIGS. 1 and 3;

The present invention relates to a board selection signal verification circuit, and more particularly, to a board selection signal verification circuit of a processor board using an encoder.

The conventional board selection signal verification circuit is shown in the block diagram of the board selection signal verification circuit of the conventional CPU board of FIG. 1 and in the timing diagram showing the delay time between the selection signal and the writing signal of FIG. If you want to write a signal from the side, when the board selection signal comes from the board under test to the encoder (2), the output is sent to the latch (1), and the write signal is sent to the enable terminal (C) of the latch through the inverter (3) ) Is delivered to the terminal.

At this time, the board selection signal has a 12-second delay from the CPU (not shown) to the encoder 2 (Fig. 2A), and the write signal is transmitted to the latch 1 from the CPU. There is an 8 ms delay before input (Fig. 2b).

Therefore, the board selection signal and the write signal have a time difference of about 4 ms from the central processing unit to the encoder 2 and the latch 1, which means that the write signal is passed through the inverter 3 to the latch. It is a result of adding to the delay time of the inverter 3 since it is output to (1).

In addition, when a test board wants to read a signal from the latch 1, a test select signal is generated to read a signal in the latch 1. At this time, the selection signal passing through the encoder 2 is delayed by about 11 ms (Fig. 2c), and the write signal passing through the inverter 3 is delayed by 7 ms (Fig. 2d). As a result, the selection signal and the write signal input from the CPU on the inspection board side are input to the input terminal D and the enable terminal C of the latch 1, and the time difference of 8 s is different. Is generated.

The board selection signal verification circuit of the conventional CPU board has a delay time between the selection signal and the writing signal on the board selection signal verification circuit, thereby reducing the effective range of the signal at the latch where the final readout occurs. Since there is not enough valid time (ｗ) to check for abnormality of the signal, it is difficult to continuously check if a signal corresponding to multiple channels is input or needs to be examined.

Accordingly, an object of the present invention is to provide a control board selection signal verification circuit having a wide selection range of valid signals by adjusting a time difference between a write signal and a selection signal in order to solve the above problems.

The control board selection signal verification circuit of the present invention for achieving the above object is a control board selection signal verification circuit between an inspection board and an inspection board for verifying a board selection signal of the control board, the selection signal in the inspection board An encoder that is applied to output an address / data signal and an enable signal, and is connected to the encoder to receive an address / data signal and an enable signal, and when the selection signal is applied to the output control signal from the test board, the enable signal is transmitted. A flip-flop for accurately reading data of the signal by operating as an enable signal entering the clock pulse as a clock pulse, and an link connected between the encoder and the flip-flop and transmitted from the encoder to the flip-flop. A signal applied to the flip-flop by delaying an enable signal for a predetermined time To a an inverter to reduce a time delay characterized by comprising.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a block diagram of a control board selection signal verification circuit according to the present invention.

Referring to FIG. 3, the control board selection signal verification circuit of the present invention is an encoder that receives a selection signal from an inspected board and outputs an address / data signal and an enable signal, and is connected to the encoder to generate an address / data signal. When the enable signal is received and the selection signal is applied to the output control signal from the inspection board, the enable signal is used as the clock pulse to operate at the rising time of the enable signal that enters the clock pulse to accurately read the data of the signal. A flip-flop for drawing, and an inverter connected between the encoder and the flip-flop to delay an enable signal transmitted from the encoder to the flip-flop for a predetermined time to reduce a time difference between signals applied to the flip-flop.

FIG. 4 is a timing diagram showing the delay time of the signal for each part of FIG.

Referring to FIG. 4, the operation of the present invention will be described with reference to FIG. 4. In the case where a signal is to be written on the inspected board, a selection signal is applied from the inspected board to the encoder, and the encoder is connected to an address / data signal as an output signal. Sends the enable signal to the flip-flop. At this time, the encoder inputs and outputs data to the input terminal (D) inside the encoder.

It takes about 11 ms until data is inputted to the input terminal D and the enable signal is output from the enable terminal EO until output to the terminal A is about 8 ms. . (Ⓕ)

Since the address / data signal of the encoder is transmitted 11 ㎱ to the flip-flop 11 as it is, it is applied to the input terminal IN of the flip-flop after about 22 후 after the selection signal is applied from the inspection board side. . (Ⓖ)

In addition, the enable signal EO output from the encoder is transmitted to the flip-flop as it is on the one hand and input to the clock pulse terminal CK of the flip-flop through the two inverters on the other hand while the two inverters pass through the inverter. Since a delay of about 10 ms occurs, the select signal is applied from the inspection board side and input to the clock pulse terminal CK of the flip-flop after about 18 ms.

On the other hand, when the test board side wants to read the signal of the flip flop, the test select signal is transmitted to read the signal on the flip flop.

5A and 5B refer to a circuit diagram and operation table of a latch used in a board selection signal verification circuit of a conventional control board, the latch is an LS573 with eight data input terminals 1D to 8D and an output terminal 1Q. 8Q), if the output control signal of the output control terminal OC is low and the enable signal of the enable terminal C is high, the input signal is output as it is.

6A and 6B are circuit diagrams and operation tables of the flip-flop means of FIG. 3, the latch and the flip-flop of the present invention are similar to the latches used in the conventional circuits, although the circuit and operation are the same as those of the latch of FIG. In comparison, the latch catches the incoming signal once and becomes valid by the latch enable signal, which makes it difficult to set the timing and consequently loses the data of the corresponding signal. By operating during the rise time, the data of the signal can be read accurately. Also, writing the enable signal, which is the output of the encoder, as the signal coming into the clock pulse of the flip-flop, which is the final reading side, operates only with the selection signal transmitted from the inspection board side, compared with the conventional selection and writing signals. Since the delay time difference can be reduced, the desired result can be obtained more precisely.

7A and 7B refer to the circuit diagrams and operation tables of the encoders of FIGS. 1 and 3, which detect the highest input among eight data (0 to 7) inputs and convert the value into a 3-bit binary code. And the enable input (EI) terminal and the output terminal for controlling the eight data inputs and outputs are data output terminals (A ₀ , A ₁ , A ₂ ), enable output terminals (EO), and the EI. Is low and any one of the eight inputs is configured as a strobe output terminal GS for outputting a low. The strobe output is also high when both inputs are high.

Therefore, the board selection signal verification circuit of the control board of the present invention increases the validity period of the signal that can be inspected, thereby enabling accurate inspection of the board selection signal on the control board and increasing the board selection signal by continuous operation. In this case, even if the board selection signal increases due to the expansion of the control board of the system, this can be easily and accurately checked.

Claims (1)

A control board selection signal verification circuit between an inspection board and an inspection board for verifying a board selection signal of a control board, comprising: an encoder receiving a selection signal from the inspection board and outputting an address / data signal and an enable signal; When the address / data signal and the enable signal are connected to the encoder, and a selection signal is applied from the test board as an output control signal, the rising time of the enable signal entering the clock pulse using the enable signal as the clock pulse. A flip-flop to read the data of the signal accurately by operating on; And an inverter connected between the encoder and the flip-flop to reduce a time difference between signals applied to the flip-flop by delaying an enable signal transmitted from the encoder to the flip-flop for a predetermined time. Selection signal verification circuit.