JPH05189517A - Simulation circuit - Google Patents

Abstract

PURPOSE:To produce a test pattern in consideration of the skews caused between the tester input and output signals and also to prevent the difference of operations caused between the testers. CONSTITUTION:The period longer than the data set-up time set to a clock signal when a logic tester used for a real device is viewed from the outside is referred to as a 1st period. Meanwhile the period longer than the data holding time set to the clock signal is defined as a 2nd period respectively. Then the total value of the 1st and 2nd periods is defined as a 3rd period. The delay of the 1st period is given to a simulation clock signal 101 by a delay element 14. Then unfixed level, is set to a simulation data signal 100 by an unfixed signal producing part 11 in the 3rd period after an edge emerged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation circuit used for circuit design of devices such as gate arrays and standard cells.

[0002]

2. Description of the Related Art When designing a device such as a gate array or a standard cell, it is necessary to simulate whether the logic circuit operates as designed. Therefore, conventionally, the simulation circuit shown in FIG. 3 is used to simulate the logic circuit.
In this circuit, the clock signal CK91 is led to the clock input of the flip-flop 93 through the Schmitt trigger 92, and the data signal D91 is led to the data input through the buffer 91, and appears at the output Q of the flip-flop 93. Based on the level change, we confirm whether the logic circuit operates properly.

[0003]

When the above simulation circuit is used, as shown in FIG.
Timing of rising edge at 91 and data signal
When a signal with the same edge appearance timing as D91 is introduced, the Schmitt trigger 92 delay time t91
Is longer than the delay time t92 of the buffer 91, the timing at which an edge appears in both the delayed clock signal CK91D and the data signal D91D is earlier than the timing at which an edge appears in the data signal D91D. Therefore, the difference time t93 satisfies the data setup time of the flip-flop 93, the H level of the data signal D91 is read into the flip-flop 93 at time T91, and the H level H91 appears at its output Q.

On the other hand, the above-mentioned two kinds of signals actually generated by the actual device include clock signals as shown in FIG.
A skew t94 may occur between CK91 and the data signal D91. Therefore, at this time, the input device (buffer 91 in FIG. 4) inside the tester for testing the actual device is
Time corresponding to the Schmidt trigger 92) and the rising edge of the delayed clock signal CK91D and the delayed data signal D91D change at time T9.
The time t95, which is different from 2, does not satisfy the data setup time of the flip-flop (corresponding to the flip-flop 93 in FIG. 4) in the tester.

On the other hand, the flip-flop does not guarantee its operation when both the data setup time and the data hold time are not satisfied. Therefore, when the above situation occurs, the flip-flop of the flip-flop used in the tester is Due to slight variations in characteristics,
The H level H92 is read by one tester, and the L level L91 which is the data before the H level H92 is read by another tester.
Occurs, and the result differs depending on the tester used, and it takes time to elucidate the cause, which causes a problem that the development time of the logic circuit becomes long.

The present invention was devised to solve the above problems, and an object thereof is to provide a simulation circuit capable of preventing a difference in operation between testers.

[0007]

In order to solve the above problems, the simulation circuit according to the present invention has a first period longer than the data setup time for a clock signal when a logic tester for testing an actual device is viewed from the outside.
, A period longer than the data hold time for the clock signal is a second period, and a total period of the first period and the second period is a third period. And a delay element for delaying the period of the simulation data signal is inserted in the signal path of the simulation data signal. When an edge appears in the simulation data signal, the level of the simulation data signal is changed in the third period after the edge appears. It is characterized by including an indefinite signal generating section which is indefinite.

[0008]

In the first period before the time when the edge appears in the simulation data signal, and in the second period after the time when the edge appears in the simulation data signal, the simulation clock signal is supplied with the data. When an edge instructing reading appears, the level of the simulation data signal read according to this edge becomes indefinite.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the electrical connection of one embodiment of the present invention.

In the figure, a simulation data signal (hereinafter simply referred to as a data signal) 100 is EXOR.
The output 211 of the delay element 21 is led to one input of the gate 22 and the input of the delay element 21, and the output 211 of the delay element 21 is led to the other input of the EXOR gate 22 and the input of the delay element 23.

The output 221 of the EXOR gate 22 is led to the output control terminals of the clocked inverters 24 to 26, and the output 231 of the delay element 23 is the clocked inverter.
Led to 24 inputs. Also clocked inverter 25
H level is given to the input of, and L level is introduced to the input of the clocked inverter 26.

The outputs of the clocked inverters 24-26 are connected to each other and led to the input of the inverter 27. The output 111 of the inverter 27 is a flip-flop.
It is connected to 15 data inputs and also to external logic.

A simulation clock signal (hereinafter simply referred to as a clock signal) 101 is led to an input of a delay element 14, and an output 141 of the delay element 14 is a flip-flop.
Connected to 15 clock inputs. The output 151 of the flip-flop 15 is sent to the outside.

The respective delay times of the delay elements 14, 21 and 23 in the above configuration are such that when the tester for testing the real device of the circuit simulated by this embodiment is viewed from the signal input side, the clock of this tester is measured. Since the two types of data setup time and data hold time for signals are both 10 ns, delay element 14
The first delay period, which is the delay time of, is set to 10 ns.

Further, the delay element 21 is an element that delays the total period of the first period and the second period, and
Is set as 10 ns of the data hold time of the tester, and the second period is set to 10 ns for the same reason as above. Therefore, the third delay period which is the delay time of the delay element 21 is 20 ns which is the total period of the first period and the second period.

Further, the delay element 14 is configured to give a delay of 10 ns, and the indefinite signal generating section 11 has two delay elements 2
1, 23, an EXOR gate 22, three clocked inverters 24 to 26, and an inverter 27.

The operation of all the elements such as the gate and the delay element in this embodiment is simulated by software including the delay time,
When the H level and the L level are simultaneously transmitted to one signal line, an uncertain signal indicating the indefinite level is transmitted to the signal line.

FIG. 2 is a timing chart showing the timing of the main signals of one embodiment of the present invention (this figure shows that the delay time of all gates is 0 for the sake of easy understanding of the explanation. The timing of various signals is shown).

The operation of one embodiment of the present invention will be described below with reference to FIG.

Both the data signal 100 and the clock signal 101 are timing signals that cause the test data to be different when the tester that tests the actual device is different, and both signals 100 at time T11. ,
A rising edge appears at 101.

An undelayed data signal 100 is supplied to one input of the EXOR gate 22, and a data signal 211 delayed by the delay element 21 for the period t13 is supplied to the other input of the EXOR gate 22. 22 outputs
At 221, the transmission of the H level H11 of 20 ns, which is the third period, is started at time T11.

Therefore, in the period indicated by t13, the output of the clocked inverter 24 becomes high impedance, and the clocked inverters 25 and 26 are in the output state. However, the output of the clocked inverter 25 is L level,
Since the output of the clocked inverter 26 becomes the H level, the H level and the L level are simultaneously introduced to the input of the inverter 27, and the input level becomes undefined. As a result, the output 111 of the inverter 27 has the period t13.
An indefinite signal indicating that the level is indefinite
31 appears.

On the other hand, since the clock signal 101 is guided to the delay element 14 via the Schmitt trigger 13, the delay element 14 is given a delay of 10 ns (shown by t11) which is the first period. Therefore, the clock signal 141 transmitted from the delay element 14 has a rising edge at time T12.

The flip-flop 15 has a clock signal 141.
When a rising edge appears at time T12, the data is read, so the data read to the flip-flop 15 is the undefined signal sent from the inverter 27.
31. Therefore, the output 151 of the flip-flop 15 is
It becomes indeterminate after time T12 (indicated by 32).

At time T13 when the third period ends, the output 221 of the EXOR gate 22 returns to the L level, the outputs of the clocked inverters 25 and 26 become high impedance, and the inverter 27 receives the clock signal. The output of the inverter 24 will be guided.

On the other hand, since the data signal 100 delayed by 30 ns is introduced to the input of the clocked inverter 24 through the two delay elements 21 and 23, at the time T13, the clocked inverter 24 is clocked. Since the H level of the period t14 equal to the delay period of the delay element 23 is sent to the output of the inverter 24, the output 111 of the inverter 27 changes from indefinite to L level at the time T13, and the time when the delay time ends. When it becomes T14, the H level H12 delayed by 30 ns of the H level of the data signal 100 appears.

The same is true when the falling edge appears in the data signal 100. When the falling edge E11 appears, the output 22 of the EXOR gate 22 after the time T15.
20ns H level appears in 1 and clocked inverter 24
Is in high impedance state, clocked inverter 25,
26 is output. Therefore, the uncertain signal 33 appears at the output of the inverter 27 in the period of 20 ns. Then, the L level L12 after the falling edge E11 in the data signal 100 is at time T16, which is delayed by 30 ns from time T15,
Appears at output 111 of inverter 27.

When the next rising edge appears in the clock signal 101 (time T17), there is no change in the level of the data signal 100 within 10 ns before and after that, so that the rising edge of the clock signal 101 appears in the flip-flop 15. At the appearing time T18, the L level L13 of the output 111 of the inverter 27 is read. Therefore, the output 151 of the flip-flop 15 changes from indefinite to L level at time T18.

As described above, when the edge appears in the data signal 100 within 10 ns before and after the time when the rising edge appears in the clock signal 101, the undefined signal 31 is read into the flip-flop 15. ..

Therefore, when comparing the simulation result of this embodiment with the simulation result when the indefinite signal generating section 11 and the delay element 14 are removed, if there is a difference in the results, the difference in the reading of the tester It is informed that it is designed with the timing of occurrence of.

As described above, since the data signal 100 guided to the clocked inverter 24 is delayed by the delay element 23 in addition to the delay by the delay element 21, the edge appearing in the data signal 100 is delayed. Will be sent as an edge to the output 111 of the inverter 27.
Even when the output 111 of the inverter 27 is connected to the external logic, it is possible to prevent the malfunction of the element operated by the edge.

The present invention is not limited to the above embodiment,
For the first period and the second period, both
Although the case where it was set to 10 ns was described, the difference in the delay time between the elements inside the tester, as well as satisfying the data setup time or data hold time of the tester,
The other period that satisfies the worst value of the total skew between the input signals can be set to, for example, 15 ns.

When the output 111 of the inverter 27 is not connected to the external logic, the delay element 23 is omitted.
Alternatively, the output of the buffer 12 may be connected to the input of the delay element 23.

[0035]

The simulation circuit according to the present invention is
The simulation clock signal is delayed for the first period, and the simulation data signal has an indefinite level during the third period after the edge appears. The simulation clock signal is instructed to read data during both the first period before the time when the edge appears in the data signal and the second period after the time when the edge appears in the simulation data signal. When an edge appears, the level of the simulation data signal read according to this edge becomes indefinite. Therefore, by designing so that this indefiniteness does not occur, it is possible to prevent the difference in operation between testers. Has the effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an electrical connection of an embodiment of the present invention.

FIG. 2 is a timing chart showing timings of main signals according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional electrical connection.

FIG. 4 is a timing chart showing the timing of main signals in the prior art.

FIG. 5 is a timing chart showing the timing of main signals in the prior art.

[Explanation of symbols]

 11 Undefined signal generator 14 Delay element 31 Undefined signal 100 Simulation data signal 101 Simulation clock signal

Claims (1)

[Claims] 1. A first period is a period longer than a data setup time for a clock signal when a logic tester for testing an actual device is viewed from the outside, and a second period is longer than a data hold time for the clock signal. And the total period of the first period and the second period is the third period, a delay element for delaying the simulation clock signal by the first period and a signal of the simulation data signal. When an edge appears in the simulation data signal after being inserted in the path, an indefinite signal generating section that makes the level of the simulation data signal indefinite during a third period after the edge appears is provided. And a simulation circuit.