JP2006349573A - Interface circuit and measurement method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a measurement method for securing setup, reducing measurement time, and improving precision. <P>SOLUTION: The semiconductor device comprises: an I/O buffer 36, having an output buffer 43 for outputting a clock signal from a terminal in an active state by a control signal 42 and setting output to a high-impedance state in the inactive state, and an inverted input buffer 44 where input is connected to the output of the output buffer; a delay circuit 38 for delaying the output of the input buffer; a flip flop 39 for sampling data signals according to the output of the delay circuit; and an output buffer 40 whose output is connected to a data output terminal while receiving the output of the flip flop. In a test mode, the output of the output buffer is set to a high-impedance state, and a clock signal is inputted from the terminal 37 and is supplied to the clock terminal of the flip flop 39 via the delay circuit 38. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a measuring method thereof, and more particularly to a circuit suitable for measuring AC characteristics of an interface unit of a semiconductor device and a measuring method thereof.

  A semiconductor device generally has an interface terminal with the outside, and a circuit is configured so as to satisfy a required AC characteristic (delay characteristic), and is configured so that it can be confirmed by measurement whether the characteristic can be satisfied. .

  Due to recent process miniaturization, device speedup, voltage reduction, wide IO (input / output) power supply range, etc., it has become difficult to satisfy the timing characteristics of the interface portion at a high-speed clock frequency.

  In addition, it has become difficult to accurately measure the AC characteristics of a device. For example, with respect to the measurement of AC characteristics, the AC characteristics are based on an internal clock signal generated inside the device (generated based on a clock signal input from the outside to the device and output from a specific output terminal). In general, the measurement is performed as follows.

  That is, with reference to an input clock signal (supplied from a tester) to a device under test (Device Under Test; DUT), measurement of an internal clock signal (specific output terminal) output from the device under test; After measuring the two AC characteristics of the terminal to be measured, it is necessary to calculate the difference.

JP-A-8-036438

  In order to satisfy high-speed interface specifications, high measurement accuracy requirements, and test cost reduction requirements, improvement of conventional methods is an issue. Hereinafter, the clock supply circuit disclosed in Patent Document 1 will be described as an example.

  FIG. 7 is a diagram illustrating a configuration of a clock supply circuit described in Patent Document 1. In FIG. Referring to FIG. 7, the input clock signal CKIN from the clock input terminal 10 is received by the input buffer 11 and is divided by the N divider 12 (the division ratio N is a predetermined integer of 2 or more). The divided clock signal is supplied to the output buffer 14 via the buffer 13, and the output buffer 14 outputs the divided clock signal from the output terminal 15 as the output clock signal CKOUT. A data input DIN from the data input terminal 16 is supplied to an input buffer 17, and an output of the input buffer 17 is supplied to a flip-flop circuit (abbreviated as “FF circuit”) 18. The FF circuit 18 latches the data input DIN using the clock signal CLK received by the buffer 21 from the output buffer 14 to the output terminal 15 as a sampling clock, and outputs it to the output terminal 20 through the output buffer 19.

  The output data DOUT is configured to be output at a timing based on the output clock signal CKOUT, and is basically output with a delay of the output buffer 19. In general, an output buffer that requires driving capability has a large delay. For this reason, the external interface has a circuit configuration that allows a sufficient hold time.

  FIG. 8 is a timing chart showing the operation of the circuit of FIG. Although not particularly limited, in the example shown in FIG. 8, the frequency of the output clock signal CKOUT is 25 MHz. In addition, the numerical value of the time of FIG. 8 is a reference value to the last. The output data signal DOUT is delayed by the output buffer 19 with respect to the reference output clock signal CKOUT. As shown in FIG. 8, the output data signal DOUT is delayed by the delay X of the output buffer 19 of FIG. 7 with respect to the output clock signal CKOUT. The delay of the output data signal DOUT is effective for securing the hold time, but the setup becomes severe. That is, in this case, the data signal is output from the terminal 20 after the delay X (= 10 ns) of the output buffer 19 from the rising edge of the output clock signal CKOUT, but the falling timing of the output clock signal CKOUT from the transition timing of the data signal. The period until this time (setup time) is 10 ns, while the period during which data is held from the falling timing of the output clock signal CKOUT (hold time) is 30 ns obtained by subtracting 10 ns from one cycle 40 ns.

  In general, an output buffer that requires driving capability has a large delay. This is because the external load can be seen, and outside the LSI, there are package capacity, load on the device board and board wiring, and input load on the connected device. Since all of these become external loads of the output buffer, the delay of the output buffer is much larger than the delay of the input buffer that can see the internal load of the LSI.

  Therefore, as shown in FIG. 8, the output data DOUT for the output clock signal CKOUT can be secured sufficiently as the hold time, but it is difficult to ensure the setup time.

  In particular, in the case of an interface having a high clock frequency, it is difficult to ensure setup. As an example, the clock frequency T of the output clock signal CKOUT is 40 nsec (25 MHz), and the delay of the output buffer 19 in FIG. 7 is X = 10 nsec.

  The setup time ST = X = 10 nsec, and the hold time is HT = T−ST = 30 nsec. The setup time is only 10 nsec.

  When the frequency of the output clock signal CKOUT is doubled, the setup time margin is halved.

  Thus, as the high-speed clock is used, the setup time margin decreases.

  Further, when measuring the AC characteristics of the output data DOUT with respect to the output clock signal CKOUT, it is usually necessary to perform two measurements of the clock (specific output terminal) generated from the inside of the device and the measurement target terminal with reference to the input clock CKIN. Yes, the result is obtained by outputting the difference by calculation. In this case, considering the tester accuracy, there is a problem that measurement becomes difficult.

  The present invention created in view of the above problems is roughly as follows.

  The semiconductor device according to the present invention is set to be switched between an active state and an inactive state based on a control signal. When the semiconductor device is in an active state, it receives and outputs a clock signal. An input / output buffer having an output buffer to be set; an input buffer having an input connected to the output of the output buffer; a delay circuit that receives and delays the output from the input buffer; and an output of the delay circuit And a first flip-flop for sampling and outputting the data signal.

  In the present invention, the input buffer comprises an inverter.

  In the present invention, the clock signal is an internal clock signal generated by inputting a first clock signal supplied from the outside.

  In the present invention, the first flip-flop may include an output buffer that samples an internal data signal, receives an output of the first flip-flop, and an output is connected to a data output terminal.

  In the present invention, the first flip-flop samples a data input signal supplied from the outside, and the clock signal is an internal clock signal generated by inputting the first clock signal supplied from the outside. Receiving the output of the first flip-flop directly or indirectly, receiving a second flip-flop that samples in response to the first clock signal, and the output of the second flip-flop, the output being a data connection The output buffer may be provided.

  In the present invention, in the test mode, the output of the output buffer is set to a high impedance state by the control signal, the second clock signal is input from the terminal, and the flip-flop is connected via the input / output buffer and the delay circuit. To the clock terminal.

  In the present invention, the output buffer includes an output terminal of the output buffer and an input terminal for the input buffer, and the output terminal and the input terminal are commonly connected to a common terminal of a package including a semiconductor device. It is good.

  In the measuring method according to the present invention, when testing the semiconductor device having the above configuration, the output of the output buffer of the input / output buffer is set to a high impedance state, and a clock signal is supplied from the tester to the input buffer of the input / output buffer Including at least a step.

  According to the present invention, the setup time can be secured by adopting a circuit configuration using an inverter and a delay circuit (delay element).

  According to the present invention, a circuit configuration that requires two measurements is added with a test mode that can be measured once. According to the present invention, since the number of measurements is halved, the measurement accuracy is doubled. According to the present invention, since the number of measurements is halved, the test time is halved.

The above-described present invention will be described below with reference to the accompanying drawings in order to explain in more detail.
With reference to FIG. 1 or FIG. 6, the interface circuit of the semiconductor device according to the present invention is controlled in an active state / inactive state by a control signal (42) (a TESTMODE signal in the embodiment), and is in an active state (output enable). State), a clock signal is output from the terminal, and in an inactive state (output disabled state), an output buffer (43) consisting of a tristate buffer whose output is set to a high impedance state, and an output of the output buffer An input / output buffer (36) having an input buffer (44) to which an input is connected, a delay circuit (38) for delaying an output of the input buffer (44), and an output of the delay circuit (38) A flip-flop (39) for sampling and outputting a data signal as a sampling clock is provided. During normal operation, the output buffer (43) is activated by the control signal (42). In the test mode, the output of the output buffer (43) is set to a high impedance state by the control signal (42), and the clock signal supplied from the tester to the common terminal (37) is input to the input buffer (44) and delayed. It is supplied to the clock terminal of the flip-flop (39) via the circuit (38). A description will be given below in connection with some examples.

  FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. Referring to FIG. 1, a clock signal MCLK (master clock) input from a terminal 31 is received by an input buffer 32 and is divided by an N divider circuit 33.

  The clock signal frequency-divided by the N frequency dividing circuit 33 passes through the logic circuit 34, the buffer 35, and the output buffer 43 and the input buffer (inversion buffer made up of an inverter) 44. The output buffer 43 is supplied to the output buffer 43, and outputs it as an output clock signal CLKOUT from a terminal 37 (also referred to as a common terminal for input and output, also referred to as “IO terminal”).

  At this time, the test mode signal (TESTMODE) 42 sets the normal mode, and the input / output buffer 36 outputs the input from the buffer 35 to the output terminal 37 through the output buffer 43.

  The clock signal CLKOUT output from the output buffer 43 to the terminal (I / O terminal) 37 is also input to the input terminal of the input buffer 44, inverted by the input buffer 44, and output. The clock signal obtained by delaying the output from the input buffer 44 by the delay circuit 38 is input to the clock terminal CLK of the FF circuit 39. The FF circuit 39 latches the internal data received at the data input terminal D, for example, at the rising edge of the clock signal input to the clock terminal CLK. The data signal from the data output terminal Q of the FF circuit 39 is supplied to the output buffer 40, and the output buffer 40 outputs the output data signal DATAOUT from the output terminal 41 to the outside.

  When the test mode signal (TESTMODE) 42 indicates the test mode, the input / output buffer 36 receives an input from the buffer 35, but the output of the output buffer 43 is in a high impedance state. An input signal is input from a terminal 37 (I / O terminal), and a signal obtained by inverting the input signal is transmitted to a delay circuit 38 through an input buffer (inverter) 44.

  The operation of the present embodiment will be described with reference to FIGS. FIG. 2 is a timing waveform diagram for explaining the operation of the embodiment of the present invention. 3 and 4 are diagrams for explaining the operation of the embodiment of the present invention. The circuit configuration is the same as in FIG. 1, but the clock signal path and the data path are indicated by thick solid lines. . FIG. 3 shows a signal path for normal mode operation (normal operation) in the configuration of FIG. The normal mode operation will be described with reference to FIG.

  A clock signal is input from the MCLK terminal 31, received by the input buffer 32, and divided by the N frequency dividing circuit 33. The divided clock signal output from the N divider circuit 33 is transmitted to the input / output buffer 36 via the logic circuit 34 and the buffer 35, and is output from the output terminal 37 as the output clock signal CLKOUT. This clock signal CLKOUT becomes a clock supplied to the external device.

  An output of the internal data signal generated by the semiconductor device to the outside is output from the output terminal 41 as an output data signal DATAOUT. In the input / output buffer 36, the connection portion of the terminal 37 (the connection portion of the output of the output buffer 43 and the input portion of the input buffer 44) is connected to the input buffer so that the output data signal is output with reference to the output clock signal CLKOUT. The clock signal CLKOUT is extracted via the (inverter) 44, supplied to the delay circuit 38, the delay is adjusted, and input to the clock terminal CLK of the FF circuit 39. The FF circuit 39 samples and outputs the internal data signal at the rising edge of the clock of the clock terminal CLK, for example, and the output from the data output terminal Q of the FF circuit 39 is output from the terminal 41 via the output buffer 40. Output as DATAOUT. That is, in one embodiment of the present invention, the output timing of the output data signal DATAOUT can be adjusted by the delay circuit 38.

  FIG. 2 is a diagram illustrating an example in which the N divider circuit 33 of FIG. 1 is divided by two (N = 2). The output of the CLKOUT terminal 37 in FIG. 2 is delayed by the delay of the output buffer 43 of the input / output buffer 36 in FIG.

  The output data signal DATAOUT from the terminal 41 of FIG. 1 outputs the output of the FF circuit 39 of FIG. The clock CLK of the FF circuit 39 in FIG. 1 is a signal obtained by passing the output clock CLKOUT of the terminal 37 in FIG. 1 through the inverter 44 and the delay circuit 38 in the input / output buffer 36 in FIG. When the output timing of the output data signal DATAOUT coincides with the output clock CLKOUT, the setup / hold can be most satisfied.

  In this embodiment, the delay circuit 38 is arranged on the clock line in this way, and the optimum value for the setup and hold can be set by adjusting the delay value of the delay circuit 38.

As an example,
The frequency of the clock CLKOUT is T = 40 nsec (25 MHz),
The delay value X of the delay circuit 38 in FIG.
When the delay value Y of the output buffer 40 is 10 nsec,
The setup time ST is ST = X + Y = 20 nsec,
Hold time HT is HT = T−ST = 20 nsec
Thus, the optimum value is set.

  Next, a method for measuring AC characteristics of a semiconductor device according to an embodiment of the present invention will be described.

  AC characteristics of the output delay of DATAOUT with respect to the output clock signal CLKOUT will be described. This is an AC standard for an external LSI to capture the data of the output data signal DATAOUT using the output clock signal CLKOUT from the semiconductor device.

  In the normal mode, as shown in FIG. 3, the input clock signal MCLK from the terminal 31 is used as a reference input, and the delay amount A is measured as the output clock signal CLKOUT from the terminal 37 (see arrow “A” in FIG. 3). . The delay amount A is a propagation delay time from a predetermined edge of the clock MCLK to the edge of the corresponding output CLKOUT.

  Next, using the input clock signal MCLK from the terminal 31 as a reference input, the delay amount B (see the arrow “B” in FIG. 3) to the output data signal DATAOUT from the terminal 41 is measured.

  The output delay C of the output data signal DATAOUT with respect to the output clock signal CLKOUT is obtained by calculating B−A (see white arrow “C = B−A” in FIG. 3).

  On the other hand, as shown in FIG. 4, when the test mode is enabled, the output buffer 43 in the input / output buffer 36 is set to output disable by the test mode signal 42, and its output is in a high impedance state. An input signal is input from 37. Using the clock from the terminal 37 as a reference input, the delay amount C of the output data signal DATAOUT from the terminal 41 is measured. This value is an output delay of the output data signal DATAOUT with respect to the output clock signal CLKOUT, and is obtained by one measurement in the test mode from two measurements in the normal mode.

  As described above, by allowing the input from the terminal 37, the AC characteristic of the output data signal DATAOUT from the terminal 41 can be measured as if the output clock from the terminal is measured as a reference. it can.

  The output clock signal CLKOUT from the terminal 37 in FIG. 1 is output with a delay of the output buffer 43 in the input / output buffer 36 in FIG. 3 with respect to the clock input MCLK in the terminal 31 in FIG.

  The output data signal DATAOUT from the terminal 41 in FIG. 1 is output with a delay of the delay time of the output buffer 40 with respect to the output timing of the FF circuit 39. At the clock input terminal of the FF circuit 39, CLKOUT from the terminal 37 is inverted by the inverter 44 and delayed by the delay circuit 38 to become a signal. When the timing of the output data signal DATAOUT coincides with the output clock signal CLKOUT, the setup / hold is most satisfactory. Since the delay circuit 38 is on the clock line, the timing of DATAOUT at the terminal 41 can be adjusted by adjusting this value. Therefore, it is possible to adjust the shortage of the setup time, which is a problem of the prior art, and it is possible to set the optimum value of setup and hold.

  With respect to the AC characteristic measurement method as well, by using the test mode in the circuit configuration of FIG. 1, a reference clock is directly input from the terminal 37 (supplied from a tester not shown), and output data from the terminal 41 is obtained. Therefore, the required AC characteristics can be measured with a single measurement.

  Also, according to the present embodiment, the delay of the clock signal at the clock terminal CLK of the FF circuit 39 can be adjusted by the delay circuit 38, so that the setup / hold time of the external interface can be satisfied even with a high-speed clock. it can.

  Furthermore, according to the present embodiment, the number of AC measurement tests is ½ that of the conventional method, so that the AC test time is also ½ that of the conventional method. That is, the test time is shortened.

  Furthermore, according to the present embodiment, the test accuracy (measurement margin) is doubled. A measurement error by a tester or the like causes a predetermined error for each measurement. This error is twice that of one measurement for two measurements. According to the present embodiment, as described above, the number of measurements is ½ compared to the conventional method, so that the measurement error can be halved and the test accuracy can be improved.

  According to this embodiment, the delay of the output with respect to the input can be directly confirmed, and the influence of the test board and the load is reduced, so that the debugging efficiency at the time of evaluation can be increased.

  In addition, according to the present embodiment, it is possible to reduce (relax) the requirement for high-precision test board design.

  Next, another embodiment of the present invention will be described. FIG. 5 is a diagram showing the configuration of the second embodiment of the present invention, and is intended to reduce the error of the delay value when the LSI configuration is considered. In FIG. 5, an LSI package 46 on which an LSI chip 45 is mounted is provided. In contrast to the embodiment shown in FIG. 1, the present embodiment shown in FIG.

  The input / output buffer 36 is not an input / output common terminal, but is divided into an output (Hi-Z output is possible) 48 and an input 49. The separated terminals are commonly connected to the terminals 50 of the LSI package 46.

  Whereas the input / output buffer 36 has the output point and the input point of the output clock signal CLKOUT, the output point and the input point of CLKOUT are formed in the LSI package 46 from the outside most.

  In the case of LSI, with this configuration, the adjustment value of the delay circuit 38 becomes more accurate, and the optimum value for setup and hold can be set more accurately. In addition, the measurement accuracy of AC characteristics can be improved.

  FIG. 6 is a diagram for explaining a third embodiment of the present invention. It is a figure which shows the example applied to the setup and hold characteristic of the input side when considering the AC characteristic of LSI. In FIG. 6, the configuration until the clock input MCLK from the terminal 31 is output to the terminal 37 as the output clock signal CLKOUT is the same as that in FIG.

  The input data DATAIN input to the data input terminal 60 is supplied to the data input terminal D of the FF circuit 39 via the input buffer 63. The clock signal input to the clock terminal CLK of the FF circuit 39 is the output of the delay circuit 38 (receives the output of the inverter 44), and the setup time and hold time of the terminal 60 are adjusted by adjusting the delay value in the delay circuit 38. The optimum value can be set.

  Whether or not the FF circuit 39 has correctly received data (output of the input buffer 63 that receives the data signal DATAIN of the terminal 60) (whether or not it has been sampled) depends on the input buffer 32 to which the terminal 31 (input MCLK) is connected. The output of the intermediate buffer 61 is based on the output signal from the data output terminal Q of the FF circuit 62 connected to the clock terminal CLK. This result (result of the suitability of the sample in the FF circuit 39) can be confirmed by the output signal (test output signal) TESTOUT output from the terminal 64 via the output buffer 40 that receives the output of the FF circuit 62.

  Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the configurations of the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

It is a figure which shows the structure of one Example of this invention. It is a timing diagram which shows operation | movement of one Example of this invention. It is a figure explaining an example of AC measurement operation | movement of one Example of this invention. It is a figure explaining the other example of AC measurement operation | movement of one Example of this invention. It is a figure which shows the structure of the 2nd Example of this invention. It is a figure which shows the structure of the 3rd Example of this invention. 10 is a diagram illustrating a configuration of a clock supply circuit disclosed in Patent Document 1. FIG. FIG. 8 is a timing chart showing the operation of the circuit of FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Clock input terminal 11 Input buffer 12 N frequency divider 13 Buffer 14 Output buffer 15 Clock output terminal 16 Data input terminal 17 Input buffer 18 FF circuit 19 Output buffer 20 Data output terminal 21 Buffer 31 Clock input terminal 32 Input buffer 33 N minutes Peripheral circuit 34 Logic circuit 35 Buffer 36 Input / output buffer 37 Terminal 39 FF circuit 38 Delay circuit 40 Output buffer 41 Data output terminal 42 Test mode signal 43 Output buffer 44 Inverter 45 LSI chip 46 LSI package 47 Clock terminal 48 Output terminal 49 Input Terminal 50 clock terminal 51 data output terminal 60 data input terminal 61 buffer 62 FF circuit 63 input buffer 64 terminal

Claims (11)

An output buffer that is controlled to switch between an active state and an inactive state based on a control signal, receives and outputs a clock signal in the active state, and outputs in a high impedance state in the inactive state;
An input buffer with an input connected to the output of the output buffer;
An input / output buffer having
A delay circuit that delays and outputs the output from the input buffer;
A first flip-flop that samples and outputs a data signal in response to the output of the delay circuit;
An interface circuit comprising:   2. The interface circuit according to claim 1, wherein the input buffer of the input / output buffer is composed of an inverter.   A semiconductor device comprising the interface circuit according to claim 1.   4. The semiconductor device according to claim 3, wherein the clock signal is an internal clock signal generated by inputting a first clock signal supplied from outside and generated inside the semiconductor device. The first flip-flop samples a data signal from an internal circuit of the semiconductor device;
4. The semiconductor device according to claim 3, further comprising an output buffer that receives an output of the first flip-flop and has an output connected to a data terminal. The first flip-flop samples a data input signal supplied from the outside,
The clock signal is an internal clock signal generated inside the semiconductor device by inputting a first clock signal supplied from the outside,
A second flip-flop that receives the output of the first flip-flop directly or indirectly via an internal circuit as a data signal, and samples and outputs the data signal in response to the first clock signal; When,
4. The semiconductor device according to claim 3, further comprising an output buffer that receives an output of the second flip-flop and has an output connected to a data terminal.   In the test mode, the output of the output buffer is set to a high impedance state by the control signal, and a second clock signal is input to the input / output buffer from a terminal to which the output of the output buffer and the input of the input buffer are connected. The semiconductor device according to claim 3, wherein the semiconductor device is supplied to the first flip-flop via the delay circuit.   In the normal mode, the output buffer is activated by the control signal to output a clock signal, and the clock signal output from the output buffer is input to the input / output buffer, and the first signal is output via the delay circuit. The semiconductor device according to claim 3, wherein the semiconductor device is supplied to one flip-flop.   The output buffer includes an output terminal of the output buffer and an input terminal of the input buffer, and the output terminal and the input terminal are commonly connected to a common terminal of a package on which the semiconductor device is mounted. The semiconductor device according to claim 3. Based on the control signal, it is controlled to be switched between an active state and an inactive state, and when it is in an active state, it receives and outputs a clock signal;
An input buffer with an input connected to the output of the output buffer;
An input / output buffer having
A delay circuit that delays and outputs the output from the input buffer;
A flip-flop that samples and outputs a data signal in response to the output of the delay circuit;
A method of measuring a semiconductor device comprising an output buffer that receives an output of the flip-flop and has an output connected to a data output terminal,
In the test, the output buffer of the input / output buffer is set to a high impedance state, and a clock signal is supplied from the tester to the input of the input / output buffer. Based on the control signal, it is controlled to be switched between an active state and an inactive state, and when in the active state, receives and outputs a clock signal, and when in an inactive state, an output buffer whose output is set to a high impedance state;
An input buffer with an input connected to the output of the output buffer;
An input / output buffer having
A delay circuit that delays and outputs the output from the input buffer;
A first flip-flop that samples and outputs an input data signal in response to an output of the delay circuit;
With
The clock signal is an internal clock signal generated by inputting a first clock signal supplied from the outside,
A second flip-flop that directly or indirectly receives the output of the first flip-flop, samples and outputs in response to the first clock signal;
A method of measuring a semiconductor device comprising an output buffer that receives an output of the second flip-flop and has an output connected to a data terminal,
In the test, the output buffer of the input / output buffer is set to a high impedance state, and a clock signal is supplied from the tester to the input buffer of the input / output buffer.

Images