KR100280418B1 - Phase comparating circuit - Google Patents

Abstract

The present invention compares the phase difference between the internal clock signal and the reference clock signal. As a result, when the internal clock signal is fast, the phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK is reduced. A phase comparator 41 for detecting the phase difference and outputting a delay control signal Y having a pulse width corresponding to the phase difference; A phase delay unit 42 reducing and outputting a phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK within a predetermined range according to the delay control signal Y output from the phase comparison unit 41; The phase delay unit 42 includes a phase compensator 43 for accurately synchronizing phases with each other by comparing an internal clock signal whose phase difference is adjusted with a reference signal.

Description

Phase comparison circuit {PHASE COMPARATING CIRCUIT}

The present invention relates to a technique for compensating a phase by comparing a phase of a reference clock signal and an internal clock signal. In particular, a phase comparison circuit detects a phase difference between a reference clock signal and an internal clock signal and minimizes the phase difference therebetween. It relates to a phase comparison circuit to be input to the compensation circuit.

1 is a block diagram of a phase comparison circuit according to the prior art, as shown therein, comparing the phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK to obtain a faster signal when the internal clock signal IN_CLK is faster. A phase comparator 11 for outputting FAST and outputting a slow signal SLOW when it is late; The phase compensator 12 is configured to compensate and output the phase of the internal clock signal IN_CLK based on the fast signal FAST and the slow signal SLOW input from the phase comparator 11. A description with reference to FIGS. 2 and 3A and 3B is as follows.

First, when the phase of the internal clock signal IN_CLK is earlier than the phase of the reference clock signal REF_CLK, "high" is output to the output node n2 of the RS latch flip-flop RS2 as shown in FIG. Since is enabled, the clocking data of the reference clock signal REF_CLK is output to the output node out.

On the contrary, when the phase of the internal clock signal IN_CLK is later than the phase of the reference clock signal REF_CLK, as shown in FIG. 3B, "high" is output to the output node n1 of the RS latch flip-flop RS1 to output the output path. Is disabled, so no clocking data is output.

As described above, in the prior art, the phase comparison circuit compares the phases of two clock signals to indicate only which clock signal has a faster or slower phase, and does not output information on how much phase difference there is. When compensating for phase in a circuit, there is a defect that the delay locking time becomes long, which consumes a lot of power.

Accordingly, a technical problem to be solved by the present invention is to provide a phase comparison circuit for detecting a phase difference between a reference clock signal and an internal clock signal in a phase comparison circuit, minimizing the phase difference in a phase delay unit, and then inputting the phase compensation circuit. have.

1 is a block diagram of a phase comparison circuit according to the prior art.

2 is a phase comparison circuit diagram according to the prior art.

3A and 3B are waveform diagrams of respective parts of FIG. 2.

Figure 4 is a block diagram showing an embodiment of a phase comparison circuit according to the present invention.

FIG. 5 is a phase difference detection circuit diagram in the phase comparison unit in FIG. 4; FIG.

6A and 6B are waveform diagrams of respective parts of FIG. 5.

FIG. 7 is a circuit diagram illustrating an embodiment of the phase delay unit in FIG. 4. FIG.

FIG. 8 is a block diagram illustrating an exemplary embodiment of the delay time setting unit in FIG. 7. FIG.

*** Description of the symbols for the main parts of the drawings ***

41: phase comparator 42: phase delay unit

43: phase compensator

FIG. 4 is a block diagram showing an embodiment of a phase comparison circuit for achieving an object of the present invention. As shown in FIG. 4, a phase difference is detected by detecting a phase difference between an internal clock signal IN_CLK and a reference clock signal REF_CLK. A phase comparison unit 41 for outputting a delay control signal Y having a pulse width corresponding to the phase comparison unit 41; A phase delay unit 42 reducing and outputting a phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK within a predetermined range according to the delay control signal Y output from the phase comparison unit 41; The phase delay unit 42 is composed of a phase compensator 43 for accurately synchronizing phases with each other by comparing an internal clock signal whose phase difference is adjusted again with a reference signal. FIG. A detailed description with reference to 5 to 8 is as follows.

The phase comparison unit 41 compares and detects a phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK using an internal phase difference detection circuit. FIG. 5 illustrates an embodiment of such a phase difference detection circuit. Will be shown.

That is, the internal clock signal IN_CLK is supplied to one input terminal of the NAND gate ND51 through two inverters I51 and I52 connected in series, and the reference clock signal REF_CLK is connected in series. The inverters I53 to I55 are continuously supplied to the other input terminal of the NAND gate ND51. Accordingly, the NAND gate ND51 outputs the NAND combination of two clock signals input through the path, which are inverted and output again through the inverter I56.

The reason for generating the delay control signal Y by processing the two clock signals IN_CLK and REF_CLK as described above is to improve accuracy in phase comparison.

FIG. 6A is a timing diagram illustrating a process of FIG. 5 and a process of the phase delay unit 42 of FIG. 7 when the phase of the internal clock signal IN_CLK is earlier than the phase of the reference clock signal REF_CLK. .

That is, when the phase of the internal clock signal IN_CLK is earlier than the phase of the reference clock signal REF_CLK, the enable signal EN becomes "low", so that the transfer gate TR71 is turned on while the transfer gate TR72 is turned off. do. Therefore, the internal clock signal IN_CLK is transmitted to the phase delay circuit 42B through the transfer gate TR71, where it is delayed by a time corresponding to the pulse width of the delay control signal Y.

For example, as shown in FIG. 8, when the phase of the internal clock signal IN_CLK is slightly faster than the phase of the reference clock signal REF_CLK, the delay control signal having the corresponding delay pulse width (for example, Y1) is converted into a morph transistor (eg, a transistor). Since it is supplied to the gate of M81, the internal clock signal IN_CLK is slightly delayed through the retarder 81 and then supplied to the internal clock signal of the phase compensator 43 through the NMOS M81.

However, when the phase of the internal clock signal IN_CLK is much faster than the phase of the reference clock signal REF_CLK, the delay control signal (eg, Y5) having the corresponding delay pulse width is supplied to the gate of the MOS transistor M85. Therefore, the internal clock signal IN_CLK is delayed a lot through the delay unit 85 and then supplied to the internal clock signal of the phase compensator 43 through the NMOS M85.

On the other hand, when the phase of the internal clock signal IN_CLK is slower than the phase of the reference clock signal REF_CLK, the enable signal EN becomes "high", whereas the transmission gate TR71 is turned off while the transmission gate TR71 is turned off. Gate TR72 is turned on. Therefore, at this time, the reference clock signal REF_CLK passes through the transfer gate TR72 and is supplied as an internal clock signal of the phase compensator 43 without being delayed as described above.

As a result, since the phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK is reduced and then supplied to the phase compensator 43, the delay locking time is reduced accordingly.

As described in detail above, the present invention detects the phase difference between the reference clock signal and the internal clock signal in the phase comparison circuit, minimizes the phase difference between them in the phase delay unit, and then compensates the phase by inputting the phase compensation circuit. Delay locking time is reduced by that, it can reduce the power consumption.

Claims (3)

A phase comparison unit 41 which detects a phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK and outputs a delay control signal Y having a pulse width corresponding to the phase difference; A phase delay unit 42 reducing and outputting a phase difference between the internal clock signal IN_CLK and the reference clock signal REF_CLK within a predetermined range according to the delay control signal Y output from the phase comparison unit 41; And a phase compensator (43) for accurately synchronizing phases with each other by comparing the internal clock signal having the phase difference adjusted by the phase delay unit (42) again with a reference signal. The phase comparison unit 41 connects the terminal of the internal clock signal IN_CLK to one input terminal of the NAND gate ND51 through the inverters I51 and I52 connected in series. Further, the terminals of the reference clock signal REF_CLK are sequentially connected to the other input terminal of the NAND gate ND51 through the serially connected inverters I53-I55, and then the output terminal of the NAND gate ND51 is connected. A phase comparison circuit comprising a phase difference detection circuit configured to be connected to a terminal of a delay control signal (Y) through an inverter (I56). The internal clock signal IN_CLK of claim 1, wherein the phase delay unit 42 has an internal clock signal IN_CLK when the phase of the internal clock signal IN_CLK is earlier than the phase of the reference clock signal REF_CLK based on the enable signal EN. Transmission gates TR71 and TR72 for selecting and outputting the reference signal and selecting and outputting the reference clock signal REF_CLK in the reverse case; When the internal clock signal IN_CLK is output through the transfer gate TR71, the delayed signal is delayed for a corresponding time according to the pulse width of the delay control signal Y, and the reference clock signal (through the transfer gate TR72) is output. A phase comparison circuit comprising a phase delay circuit 42B which is passed as it is when REF_CLK) is output.

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