KR940002700A - Board selection signal verification circuit on the control board - Google Patents

Board selection signal verification circuit on the control board Download PDF

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Publication number
KR940002700A
KR940002700A KR1019920012783A KR920012783A KR940002700A KR 940002700 A KR940002700 A KR 940002700A KR 1019920012783 A KR1019920012783 A KR 1019920012783A KR 920012783 A KR920012783 A KR 920012783A KR 940002700 A KR940002700 A KR 940002700A
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KR
South Korea
Prior art keywords
board
signal
selection signal
control board
flip
Prior art date
Application number
KR1019920012783A
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Korean (ko)
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KR100234198B1 (en
Inventor
한병준
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정용문
삼성전자 주식회사
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Priority to KR1019920012783A priority Critical patent/KR100234198B1/en
Publication of KR940002700A publication Critical patent/KR940002700A/en
Application granted granted Critical
Publication of KR100234198B1 publication Critical patent/KR100234198B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

본 발명은 제어보드 선택신호 검증회로에 관한 것으로, 제어보드의 보드선택신호를 검증하기 위한 검사보드와 피검사보드간의 제어보드 선택신호 검증회로에 있어서, 상기 피검사보드에서 선택신호를 인가받아 어드레스/데이타 신호와 인에이블신호를 출력하는 엔코더, 상기 엔코더와 연결되어 어드레스/데이타신호와 인에이블신호를 전송받고, 상기 검사보드로부터 출력제어신호로 선택신호가 인가되면 상기 인에이블신호를 클럭펄스로하여 상기 클럭펄스에 들어오는 인에이블 신호의 상승시간에 동작을 함으로써 정확하게 해당 신호의 데이타를 읽어들이기 위한 플립플롭, 및 상기 엔코더와 플립플롭사이에 연결되어 상기 엔코더로부터 플립플롭으로 전송되는 인에이블신호를 소정시간 지연시켜 상기 플립플롭으로 인가되는 신호들의 시간차를 감소시키기 위한 인버터를 구비하여 이루어지는 것을 특징으로 한다.The present invention relates to a control board selection signal verification circuit, comprising: a control board selection signal verification circuit between an inspection board and an inspection board for verifying a board selection signal of a control board, the selection signal being received from the inspection board; An encoder that outputs a data signal and an enable signal, and is connected to the encoder to receive an address / data signal and an enable signal, and when the selection signal is applied to the output control signal from the test board, the enable signal is converted into a clock pulse. By operating during the rise time of the enable signal entering the clock pulse, the flip-flop for accurately reading the data of the signal, and the enable signal transmitted from the encoder to the flip-flop connected between the encoder and the flip-flop Delay the predetermined time to time difference between the signals applied to the flip-flop It is characterized by comprising an inverter for reducing.

따라서 본 발명의 제어보드의 보드선택신호 검증회로는 제어보드에서의 보드선택신호에 대한 정확한 검사를 가능하게 하고 연속적인 동작에 의해 보드선택신호가 증가하는 경우나 시스템의 제어보드의 확장에 따른 보드선택신호가 증가하는 경우에도 이를 용이하고 정확하게 검사할 수 있다.Therefore, the board selection signal verification circuit of the control board of the present invention enables accurate inspection of the board selection signal in the control board and increases the board selection signal due to continuous operation or the board according to the expansion of the control board of the system. Even when the selection signal increases, it can be easily and accurately checked.

Description

제어보드의 보드선택신호 검증회로Board selection signal verification circuit of control board

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 CPU보드의 보드선택신호 검증회로의 블럭도.3 is a block diagram of a board selection signal verification circuit of a CPU board according to the present invention.

제4도는 제3도의 신호의 수단별 지연시간을 나타내는 타이밍도.4 is a timing diagram showing a delay time for each signal of the signal of FIG.

Claims (1)

제어보드의 보드선택신호를 검증하기 위한 검사보드와 피검사보드간의 제어보드 선택신호 검증회로에 있어서, 상기 피검사보드에서 선택신호를 인가받아 어드레스/데이타 신호와 인에이블신호를 출력하는 엔코더 ; 상기 엔코더와 연결되어 어드레스/데이타신호와 인에이블신호를 전송받고, 상기 검사보드로부터 출력제어신호로 선택신호가 인가되면 상기 인에이블신호를 클럭펄스로하여 상기 클럭펄스에 들어오는 인에이블 신호의 상승시간에 동작을 함으로써 정확하게 해당 신호의 데이타를 읽어들이기 위한 플립플롭 ; 및 상기 엔코더와 플립플롭사이에 연결되어 상기 엔코더로부터 플립플롭으로 전송되는 인에이블신호를 소정시간 지연시켜 상기 플립플롭으로 인가되는 신호들의 시간차를 감소시키기 위한 인버터를 구비하여 이루어지는 것을 특징으로 하는 제어보드 선택신호 검증회로.A control board selection signal verification circuit between an inspection board and an inspection board for verifying a board selection signal of a control board, comprising: an encoder receiving a selection signal from the inspection board and outputting an address / data signal and an enable signal; When the address / data signal and the enable signal are connected to the encoder, and a selection signal is applied from the test board as an output control signal, the rising time of the enable signal entering the clock pulse using the enable signal as the clock pulse. A flip-flop to read the data of the signal accurately by operating on; And an inverter connected between the encoder and the flip-flop to reduce a time difference between signals applied to the flip-flop by delaying an enable signal transmitted from the encoder to the flip-flop for a predetermined time. Selection signal verification circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920012783A 1992-07-16 1992-07-16 A circuit for verifying signal of selecting control board KR100234198B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920012783A KR100234198B1 (en) 1992-07-16 1992-07-16 A circuit for verifying signal of selecting control board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012783A KR100234198B1 (en) 1992-07-16 1992-07-16 A circuit for verifying signal of selecting control board

Publications (2)

Publication Number Publication Date
KR940002700A true KR940002700A (en) 1994-02-19
KR100234198B1 KR100234198B1 (en) 1999-12-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920012783A KR100234198B1 (en) 1992-07-16 1992-07-16 A circuit for verifying signal of selecting control board

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KR100234198B1 (en) 1999-12-15

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