KR970056603A - Dynamic RAM Refresh Method and Circuit - Google Patents

Dynamic RAM Refresh Method and Circuit Download PDF

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Publication number
KR970056603A
KR970056603A KR1019950061326A KR19950061326A KR970056603A KR 970056603 A KR970056603 A KR 970056603A KR 1019950061326 A KR1019950061326 A KR 1019950061326A KR 19950061326 A KR19950061326 A KR 19950061326A KR 970056603 A KR970056603 A KR 970056603A
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KR
South Korea
Prior art keywords
signal
reset signal
test mode
outputting
refresh
Prior art date
Application number
KR1019950061326A
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Korean (ko)
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KR0164517B1 (en
Inventor
강대운
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950061326A priority Critical patent/KR0164517B1/en
Publication of KR970056603A publication Critical patent/KR970056603A/en
Application granted granted Critical
Publication of KR0164517B1 publication Critical patent/KR0164517B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

본 발명은 다이나믹 램의 리프레쉬 방법 및 회로를 공개한다. 그 방법은 테스트 모드인지를 판단하는 테스트 모드 판단단계, 테스트 모드인 경우에는 외부 리셋신호를 출력시키는 제1리셋시니호 출력단계, 테스트 모드가 아닌 경우에는 내부 디지탈 프로세서로부터의 리프레쉬 싸이클보다 펄스폭이 짧은 리셋신호를 출력시키는 제2리셋신호 출력단계 및 제1리셋신호 또는 제2리셋신호를 리셋신호로 하여 리프레쉬 신호를 출력하는 리프레쉬 신호 출력단계를 포함하고, 그 회로는 외부 리셋신호 또는 내부 디지탈 프로세서로부터의 리셋신호 중에서 하나를 출력하는 다중신호선택기 및 다중신호선택기의 출력신호를 리셋신호로 하여 리프레쉬 신호를 출력하는 플립플롭으로 구성되어 있다. 따라서, 테스트시 사용되는 외부 리셋신호를 리프레쉬 회로의 리셋단에 직접 연결하여 사용하는 종래의 리스레쉬 회로에서 발생할 수 있는 다이나믹 램의 데이타 상실을 방지할 수 있는 장점이 있다.The present invention discloses a method and circuit for refreshing a dynamic RAM. The method includes a test mode determination step of determining whether the test mode is in a test mode, a first reset signal output step of outputting an external reset signal in the test mode, and a pulse width greater than a refresh cycle from the internal digital processor in the test mode. A second reset signal output step of outputting a short reset signal and a refresh signal output step of outputting a refresh signal using the first reset signal or the second reset signal as a reset signal, the circuit including an external reset signal or an internal digital processor; It consists of a multiple signal selector for outputting one of the reset signals from the output signal and a flip-flop for outputting a refresh signal using the output signal of the multiple signal selector as a reset signal. Therefore, there is an advantage in that data loss of the dynamic RAM, which may occur in a conventional refresh circuit which is directly connected to the reset terminal of the refresh circuit, is used.

Description

다이나믹 램의 리프레쉬 방법 및 회로Dynamic RAM Refresh Method and Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 다이나믹 램의 리프레쉬 회로의 블럭도를 나타낸 것이다.3 shows a block diagram of a refresh circuit of a dynamic RAM according to the present invention.

제4도는 본 발명에 따른 다이나믹 램의 리프레쉬 방법의 흐름도를 나타낸 것이다.4 is a flowchart illustrating a method of refreshing a dynamic RAM according to the present invention.

Claims (2)

테스트 모드인지를 판단하는 테스트 모드 판단단계; 상기 테스트 모드 판단단계에서 테스트 모드인 경우에는 외부 리셋신호를 출력시키는 제1리셋신호 출력단계; 상기 테스트 모드 판단단계에서 테스트 모드가 아닌 경우에는 내부 디지탈 프로세서로부터의 리프레쉬 싸이클보다 펄스폭이 짧은 리셋신호를 출력시키는 제2리셋신호 출력단계; 및 상기 제1리셋신호 또는 제2리셋신호에 의하여 다이나믹 램의 데이타를 유지하기 위한 리프레쉬 신호를 출력하는 리프레쉬 신호 출력단계를 포함한 것을 특징으로 하는 다이나믹 램의 리프레쉬 방법.A test mode determining step of determining whether the test mode; A first reset signal output step of outputting an external reset signal in a test mode in the test mode determination step; A second reset signal output step of outputting a reset signal having a shorter pulse width than a refresh cycle from an internal digital processor when the test mode is not in the test mode; And a refresh signal outputting step of outputting a refresh signal for holding data of the dynamic RAM according to the first reset signal or the second reset signal. 테스트 모드가 선택된 경우에는 외부 리셋신호를 출력하고 테스트 모드가 아닌 경우에는 내부 디지탈 프로세서로부터의 리프레쉬 싸이클보다 펄스폭이 짧은 리셋신호를 출력하는 다중신호선택기; 및 상기 다중신호선택기의 출력신호를 리셋신호로 하여 비동기 리프레쉬 신호를 클럭에 맞는 리프레쉬 신호로 출력하는 플립플롭을 구비한 것을 특징으로 하는 다이나믹 램의 리프레쉬 회로.A multiple signal selector for outputting an external reset signal when the test mode is selected, and outputting a reset signal having a shorter pulse width than a refresh cycle from the internal digital processor when the test mode is not selected; And a flip-flop for outputting an asynchronous refresh signal as a refresh signal suitable for a clock using the output signal of the multiple signal selector as a reset signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950061326A 1995-12-28 1995-12-28 Refresh method and circuit of dram KR0164517B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950061326A KR0164517B1 (en) 1995-12-28 1995-12-28 Refresh method and circuit of dram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950061326A KR0164517B1 (en) 1995-12-28 1995-12-28 Refresh method and circuit of dram

Publications (2)

Publication Number Publication Date
KR970056603A true KR970056603A (en) 1997-07-31
KR0164517B1 KR0164517B1 (en) 1999-02-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950061326A KR0164517B1 (en) 1995-12-28 1995-12-28 Refresh method and circuit of dram

Country Status (1)

Country Link
KR (1) KR0164517B1 (en)

Also Published As

Publication number Publication date
KR0164517B1 (en) 1999-02-01

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