KR980007175A - A data matching circuit of a time slot switch between a processor and a device - Google Patents

A data matching circuit of a time slot switch between a processor and a device Download PDF

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Publication number
KR980007175A
KR980007175A KR1019960024061A KR19960024061A KR980007175A KR 980007175 A KR980007175 A KR 980007175A KR 1019960024061 A KR1019960024061 A KR 1019960024061A KR 19960024061 A KR19960024061 A KR 19960024061A KR 980007175 A KR980007175 A KR 980007175A
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KR
South Korea
Prior art keywords
flip
output
inverters
data
flops
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KR1019960024061A
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Korean (ko)
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KR100210780B1 (en
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김주용
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유기범
대우통신 주식회사
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Priority to KR1019960024061A priority Critical patent/KR100210780B1/en
Publication of KR980007175A publication Critical patent/KR980007175A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 전전자 교환기에서 소정 시간 차를 두고 선택 신호(CSELO-CSEL15)를 각각 출력하고, 상기 선택 신호(SESLO-CSEL15)에 동기되어 데이터(RED0-RXD15)를 출력하는 디바이스들의 상기 데이터(RXD0-CSEL15)를 프로세서(2)에 송신하는 장치에 관한 것으로서, 선택 신호(CSEL0-CSEL15)를 소정 클럭(TCLK)에 동기되어 지연 출력하는 상기 디바이스들과 동일 개수의 D 플립플롭(D0-D15)들과, D 플립플롭(D1-D15)의 출력을 반전 출력하는 인버터(I0-I14)와; 인버터(I0-I13)들의 출력과 상기 D 플립플롭(D1-D15)들중 하나의 대응 D플립플롭(D1-D15)들중 어느 하나)의 출력을 조합하여 출력하는 오아게이트(OR0-OR14)들로 구성되며 상기 D 플립플롭(D0)의 출력을 버퍼 선택 신호(/SEL0)로, 상기 인버터(I0-I14)의 출력을 버퍼 선택 신호(/SEL1-SEL14)로 출력하며, 상기 디바이스들의 데이터(RXD0-RXD15)들을 각각 출력하는 정합부와; 버퍼 선택 신호(/SEL1-SEL14)를 반전 출력하는 인버터(I20-I35)와; 인버터(I20-I35)의 출력에 따라 상기 정합부(1)의 데이터(RSD0-RXD15)를 상기 프로세서(2)에 전송하는 버퍼(B0-B15)를 구비한다. 즉, 본 발명은 디바이스의 데이터들을 프로세서(2)에 송신하는 경우에 발생할 수 있는 데이터 중복을 우선권 할당에 의하여 방지할 수 있는 효과가 있다.The present invention is a method for outputting data (RXD0 (RXD0)) of devices that output selection signals (CSELO-CSEL15) with a predetermined time difference in the entire electronic exchanger and outputting data (RED0-RXD15) in synchronization with the selection signal And the same number of D flip-flops D0 to D15 as the devices for delaying and outputting the selection signals CSEL0 to CSEL15 in synchronization with a predetermined clock TCLK, Inverters I0-I14 for inverting the outputs of the D flip-flops D1-D15; (OR0-OR14) for outputting the combined outputs of the inverters I0-I13 and the corresponding D flip-flops D1-D15 of the D flip-flops D1-D15, And outputs the output of the inverter (I0-I14) to the buffer selection signal (/ SEL1-SEL14) by using the output of the D flip-flop D0 as the buffer selection signal / SEL0, (RXD0-RXD15); Inverters I20-I35 for inverting the buffer selection signals / SEL1-SEL14; And a buffer (B0-B15) for transmitting the data (RSD0-RXD15) of the matching section (1) to the processor (2) in accordance with the output of the inverters (I20-I35). That is, the present invention has an effect of preventing duplication of data, which may occur when data of a device is transmitted to the processor 2, by assigning priority.

Description

프로세서와 디바이스간의 타임 슬롯 스위치의 데이터 정합 회로A data matching circuit of a time slot switch between a processor and a device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 프로세서와 디바이스간의 카임 슬롯 스위치의 데이타 정합 정치의 블록도.FIG. 1 is a block diagram of a data match state of a car slot switch between a processor and a device in accordance with the present invention; FIG.

제2도는 본 발명에 따른 정합 장치의 주요 부분 파형도.FIG. 2 is a main part waveform diagram of a matching device according to the present invention; FIG.

제3도는 본 발명에 따른 정합부의 구체 회로도.FIG. 3 is a specific circuit diagram of a matching portion according to the present invention. FIG.

Claims (1)

소정 시간 차를 두고 선택 신호(CSEL0-CSEL15)를 각각 출력하고, 상기 선택 신호(CSEL0-CSEL15)에 동기되어 데이터(RXD0-RXD15)를 출력하는 디바이스들의 ㅅ아기 데이터(RXD0-RXD15)를 프로세서(2)에 송신하는 장치로서, 상기 선택 신호(CSEL0-CSEL15)를 소정 클럭(TCLK)에 동기되어 지연 출력하는 상기 디바이스들과 동일 개수의 D 플립플롭(D0-D15)들과; 상기 D 플립플롭(D1-D15)의 출력을 반전 출력하는 인버터(I0-I14)와; 상기 인버터(I0-I13)들중 상위 인버터(I0-I13)들의 출력과 상기 D 플립플롭(D1-D15)들중 하나의 대응 D 플립플롭(D1-D15들중 어느 하나)의 출력을 조합하여 출력하는 오아 게이트(OR0-OR14)들로 구성되며 상기 D플립플롭의 출력을 버퍼 선택 신호(/SEL0)로, 상기 인버터(I0-I14)의 출력을 버퍼 선택 신호(/SEL1-/SEL1-/SEL14)로 출력하며, 상기 디바이스들의 데이터(RXD0-RXD15)들을 각각 출력하는 정합부(1)와; 상기 버퍼 선택 신호(/SEL1-/SEL14)를 반전 출력하는 인버터(I20-I35)와; 상기 인버터(I20-I35)의 출력에 따라 상기 정합부(1)의 데이터(RXD0-RXD15)를 상기 프로세서(2)에 전송하는 버퍼(B0-B15)를 구비하는 프로세서와 디바이스간의 타임 슬롯 스위치의 데이터 정합 회로.RXD0 to RXD15 of devices for outputting selection signals CSEL0 to CSEL15 and outputting data RXD0 to RXD15 in synchronization with the selection signals CSEL0 to CSEL15 with a predetermined time difference, 2), wherein the number of D flip-flops (D0-D15) is equal to the number of the devices that delay output the selection signals (CSEL0-CSEL15) in synchronization with a predetermined clock (TCLK); An inverter (I0-I14) for inverting the output of the D flip-flop (D1-D15); The output of the upper inverters I0-I13 of the inverters I0-I13 and the output of one of the corresponding D flip-flops D1-D15 of the D flip-flops D1-D15 And outputs the output of the inverters I0-I14 to the buffer selection signal / SEL1- / SEL1- / SEL0. The output of the D flip- SEL14) and outputs the data (RXD0-RXD15) of the devices, respectively; Inverters I20-I35 inverting the buffer selection signals / SEL1- / SEL14; And a buffer (B0-B15) for transmitting data (RXD0-RXD15) of the matching section (1) to the processor (2) in accordance with an output of the inverter (I20-I35) Data matching circuit.
KR1019960024061A 1996-06-26 1996-06-26 Data matching circuit of time slot switch between processor and device KR100210780B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024061A KR100210780B1 (en) 1996-06-26 1996-06-26 Data matching circuit of time slot switch between processor and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024061A KR100210780B1 (en) 1996-06-26 1996-06-26 Data matching circuit of time slot switch between processor and device

Publications (2)

Publication Number Publication Date
KR980007175A true KR980007175A (en) 1998-03-30
KR100210780B1 KR100210780B1 (en) 1999-07-15

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