KR950010355A

KR950010355A - Synchronous control circuit

Info

Publication number: KR950010355A
Application number: KR1019930020250A
Authority: KR
Inventors: 권환우
Original assignee: 박성규; 대우통신 주식회사
Priority date: 1993-09-28
Filing date: 1993-09-28
Publication date: 1995-04-28

Abstract

본 발명은 신호 동기 제어 회로에 관한 것으로, 이를 위해 상호 배타적인 클럭(Clock) 신호를 사용하는 제1 및 제2 회로(210 및 247)간에 상호 제어 신호를 전달하거나 전달받는 경우, 상기 제1 및 제2 회로 (210 및 240)로의 제어신호를 일치시키기 위해 상기 제1 회로(210)와 제2회로(240) 사이에 제1 동기 회로(220)를 포함하는 동기 제어 회로에 있어서, 상기 제1 동기 회로(220)의 소자에 의해 발생되는 대기시간과 유지시간의 불일치로 인한 불안정한 동기 회로를 보다 안정하게 동기되도록 상기 제1 동기 회로(220)의 출력단과 상기 제2 회로(240)의 입력 단간에 제2 동기 회로(230)로 구성됨으로써 보다 안정된 동기 제어 신호를 제공할 수가 있다.The present invention relates to a signal synchronization control circuit, and when the first and second circuits 210 and 247 using mutually exclusive clock signals for this purpose, the first and second control signals are transmitted or received. In the synchronous control circuit comprising a first synchronous circuit 220 between the first circuit 210 and the second circuit 240 to match the control signal to the second circuit 210 and 240, the first Between the output terminal of the first synchronization circuit 220 and the input terminal of the second circuit 240 to more stably synchronize the unstable synchronization circuit due to the mismatch between the waiting time and the holding time generated by the device of the synchronization circuit 220 By the second synchronization circuit 230, a more stable synchronization control signal can be provided.

Description

Synchronous control circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 동기 제어 회로를 도시한 도면.2 shows a synchronous control circuit according to the invention;

Claims

When the mutual control signal is transmitted or received between the first and second circuits 210 and 240 using mutually exclusive clock signals, the control signals to the first and second circuits 210 and 240 match. In the synchronous control circuit including a first synchronous circuit 220 between the first circuit 210 and the second circuit 240, the waiting time generated by the element of the first synchronous circuit 220 And a second synchronization circuit 230 between the output terminal of the first synchronization circuit 220 and the attraction terminal of the second circuit 247 to more stably synchronize the unstable synchronization circuit due to the mismatch between the time and the holding time. Synchronous control circuit.

2. The apparatus of claim 1, wherein the second synchronization circuit (230) comprises: an inverter (232) for inverting an input clock signal; A clock input terminal CK for the inverted signal from the inverter 232, an input terminal D for inputting the output signal of the first synchronization circuit 220, and an output terminal Q for outputting a predetermined control signal. A synchronous control circuit comprising a D flip-flop consisting of.

※ Note: The disclosure is based on the initial application.