KR970051407A - Synchronous Semiconductor Memory Device - Google Patents

Synchronous Semiconductor Memory Device Download PDF

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Publication number
KR970051407A
KR970051407A KR1019950052591A KR19950052591A KR970051407A KR 970051407 A KR970051407 A KR 970051407A KR 1019950052591 A KR1019950052591 A KR 1019950052591A KR 19950052591 A KR19950052591 A KR 19950052591A KR 970051407 A KR970051407 A KR 970051407A
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South Korea
Prior art keywords
edge
memory device
semiconductor memory
generating means
response
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KR1019950052591A
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Korean (ko)
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KR100206724B1 (en
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장현순
이준희
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry

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  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

반도체 메모리 장치에 관한 것으로 특히 고속으로 메모리 어레이내의 데이타를 억세스하는 동기식 디램을 번-인 테스트시 싸이클 타임을 감축할 수 있는 동기식 반도체 메모리 장치의 클럭버퍼에 관한 것이다. 상기의 클러버퍼는, 칩 외보로부터 입력되는 시스템 클럭의 제1에지에 응답하여 소정의 듀레이션을 갖는 펄스를 출력하는 제1자동펄스 발생수단과, 번-인보드 인에이블 신호의 활성화에 인에이블되며, 상기 시스템 클럭의 제1에지 및 제2에지에 각각 응답하여 소정의 듀레이션을 갖는 펄스를 출력하는 제2자동펄스 발생수단과, 상기 제1, 제2자동펄스 발생수단의 출력노드와 상기 칩내부의 클럭입력노드의 사이에 접속되며, 상기 번-인모드 인에이블신호의 활성화 상태에 따라 상기 제1, 제2자동펄스 발생수단들로부터 각각 출력되는 펄스를 선택적으로 상기칩으로 전송하는 전송수단을 포함하여 구성된다.The present invention relates to a semiconductor memory device, and more particularly, to a clock buffer of a synchronous semiconductor memory device capable of reducing cycle time during a burn-in test of a synchronous DRAM that accesses data in a memory array at high speed. The clock buffer is enabled by the first automatic pulse generating means for outputting a pulse having a predetermined duration in response to the first edge of the system clock input from the chip output, and the activation of the burn-in board enable signal. Second automatic pulse generating means for outputting a pulse having a predetermined duration in response to the first and second edges of the system clock, an output node of the first and second automatic pulse generating means, and the chip inside A transmission means connected between the clock input nodes of the plurality of clock input nodes, and selectively transmitting pulses output from the first and second automatic pulse generating means to the chip according to the activation state of the burn-in mode enable signal. It is configured to include.

Description

동기식 반도체 메모리 장치Synchronous Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 동기식 디램의 클럭버퍼의 상세도를 나타낸 도면,4 is a diagram showing a detailed view of a clock buffer of a synchronous DRAM according to the present invention;

제5B도는 본 발명에 따른 클럭버퍼의 입출력 동작에 대한 시뮬레이션 파형도5B is a simulation waveform diagram of an input / output operation of a clock buffer according to the present invention.

Claims (6)

외부 시스템 클럭의 입력에 동기되어 칩 내부의 회로들을 동작시키는 동기식 반도체 메모리 장치에 있어서, 상기 시스템 클럭의 제1에지에 응답하여 소정의 듀레이션을 갖는 펄스를 출력하는 제1에지검출수단과, 상기 시스템 클럭의 제2에지에 응답하여 소정의 듀레이션을 갖는펄스를 출력하는 제2에지검출수단과, 전송인에이블신호에 응답하여 상기 제1및 제2에지검출 수단의 출력 노드로부터 출력되는 펄스를 상기 칩내부로 전송하는 전송수단으로 구비함을 특징으로 하는 동기식 반도체 메모리 장치.A synchronous semiconductor memory device operating circuits in a chip in synchronization with an input of an external system clock, comprising: first edge detection means for outputting a pulse having a predetermined duration in response to a first edge of the system clock; A second edge detecting means for outputting a pulse having a predetermined duration in response to a second edge of the clock, and a pulse output from an output node of the first and second edge detecting means in response to a transfer enable signal; A synchronous semiconductor memory device, characterized in that provided as a transmission means for transmitting inside. 제1항에 있어서, 상기 전송인에이블신호는 상기 동기식 반도체 메모리 장치가 번-인시 활성됨을 특징으로 하는 동기식 반도체 메모리 장치.The synchronous semiconductor memory device of claim 1, wherein the transfer enable signal is activated when the synchronous semiconductor memory device is burned-in. 외부 시스템 클럭의 입력에 동기되어 칩 내부의 회로들을 동작시키는 동기식 반도체 메모리 장치에 있어서, 상기 시스템 클럭의 제1에지에 응답하여 소정의 듀레이션을 갖는 펄스를 출력하는 제1자동펄스 발생수단과, 번-인모드 인에이블 신호의 활성화에 인에이블되며, 상기 시스템 클럭의 제1에지 및 제2에지에 각각 응답하여 소정의 듀레이션을 갖는 펄스를 출력하는 제2자동펄스 발생수단과, 상기 제1, 제2자동펄스 발생수단의 출력노드와 상기 칩내부의 클럭입력노드의 사이에 접속되며, 상기 번-인보드 인에이블 신호의 활성화 상태에 따라 상기 제1, 제2자동펄스 발생수단들로부터 각각 출력되는 펄스를 선택적으로 상기 칩으로 전송하는 전송수단으로 구성함을 특징으로 하는 동기식 반도체 메모리 장치.A synchronous semiconductor memory device which operates circuits inside a chip in synchronization with an input of an external system clock, comprising: first automatic pulse generating means for outputting a pulse having a predetermined duration in response to a first edge of the system clock; Second automatic pulse generating means enabled for activation of an in-mode enable signal and outputting a pulse having a predetermined duration in response to a first edge and a second edge of the system clock, respectively; A connection between an output node of a second automatic pulse generating means and a clock input node in the chip, and outputs from the first and second automatic pulse generating means, respectively, according to an activation state of the burn-in board enable signal; And a transmission means for selectively transmitting pulses to the chip. 제3항에 있어서, 상기 제2자동펄스 발생수단은 상기 시스템 클럭의 제1에지에 응답하여 소정의 듀레이션을 갖는 펄스를 출력하는 제1에지검출수단과, 상기 시스템 클럭의 제2에지에 응답하여 소정의 듀레이션을 갖는 펄스를 출력하는 제2에지검출수단으로 구성함을 특지으로 하는 동기식 반도체 메모리 장치.The method of claim 3, wherein the second automatic pulse generating means comprises: first edge detecting means for outputting a pulse having a predetermined duration in response to a first edge of the system clock, and in response to a second edge of the system clock; A synchronous semiconductor memory device, characterized in that it comprises a second edge detecting means for outputting a pulse having a predetermined duration. 제3항 또는 제4항에 있어서, 상기 제1에지와 제2에지는 시스템 클럭의 로우와 하이임을 특징으로 하는 동기식 반도체 메모리 장치.The synchronous semiconductor memory device of claim 3, wherein the first and second edges are low and high of a system clock. 제3항 또는 제4항에 있어서, 상기 전송수단은 상기 제1자동펄스 발생수단의 출력노드와 상기 칩의 클럭입력노드 사이에 접속된 제1전송게이트와, 상기 제2자동펄스 발생수단의 출력노드와 상기 칩의 클러입력노드 사이에 접속된 제2전송게이트로 구성되며, 상기 제1 및 제2전송게이트는 서로 배타적으로 스위칭됨을 특징으로 하는 동기식 반도체 메모리 장치5. The output device according to claim 3 or 4, wherein the transmission means comprises: a first transmission gate connected between an output node of the first automatic pulse generating means and a clock input node of the chip, and an output of the second automatic pulse generating means; And a second transfer gate connected between a node and a clock input node of the chip, wherein the first and second transfer gates are exclusively switched to each other. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052591A 1995-12-20 1995-12-20 Clock buffer of synchronous semiconductor memory device KR100206724B1 (en)

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KR100594206B1 (en) * 1999-11-05 2006-06-28 삼성전자주식회사 Memory test method of semiconductor device having a memory

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