KR100233277B1 - Ferro dielectronics ram fabrication method - Google Patents
Ferro dielectronics ram fabrication method Download PDFInfo
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- KR100233277B1 KR100233277B1 KR1019960026541A KR19960026541A KR100233277B1 KR 100233277 B1 KR100233277 B1 KR 100233277B1 KR 1019960026541 A KR1019960026541 A KR 1019960026541A KR 19960026541 A KR19960026541 A KR 19960026541A KR 100233277 B1 KR100233277 B1 KR 100233277B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
Abstract
본 발명은 강유전체 램의 캐패시터 제조시, 하부전극 증착 및 식각, 강유전체 증착, 상부전극 증착 및 식각으로 공정이 차례로 이루어져 좁은 면적에서도 캐패시터의 유효면적을 크게하고, O2및 강유전체 물질의 휘발성 물질의 확산에 의한 소자특성 저하를 방지하기 위해 캐패시터의 상·하부에 확산방지층인 실리콘 질화막을 형성하는 강유전체 램 제조 방법에 관한 것으로, 본 발명의 강유전체 램 제조 방법은 강유전체의 휘발성 물질 확산을 방지하여 모스트랜지스터의 파괴를 방지하고, 강유전체 캐패시터가 차지하는 면적을 줄이면서 같은 면적에서도 종래기술에 비해 유효 면적이 증대된 캐패시터를 갖는 효과가 있다.In the manufacturing of the capacitor of the ferroelectric ram, the process is sequentially performed by lower electrode deposition and etching, ferroelectric deposition, upper electrode deposition and etching to increase the effective area of the capacitor even in a small area, and diffusion of volatile materials of O 2 and ferroelectric materials The ferroelectric ram manufacturing method for forming a silicon nitride film as a diffusion barrier layer on the upper and lower portions of the capacitor to prevent the deterioration of the device characteristics by the method, the ferroelectric ram manufacturing method of the present invention prevents the diffusion of the volatile material of the ferroelectric There is an effect of preventing the breakdown and reducing the area occupied by the ferroelectric capacitor while having a capacitor having an effective area increased in comparison with the prior art in the same area.
Description
제1도는 종래의 강유전체 램의 단면도.1 is a cross-sectional view of a conventional ferroelectric ram.
제2(a)도 내지 제2(e)도는 본 발명의 일실시예에 따른 강유전체 램 제조 공정도.2 (a) to 2 (e) is a ferroelectric ram manufacturing process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 소자분리막21 silicon substrate 22 device isolation film
23 : 모스트랜지스터 24 : BPSG막23: MOS transistor 24: BPSG film
25,31 : 실리콘질화막 26 : 탄탈늄25, 31 silicon nitride film 26 tantalum
27,29 : 백금막 28 : 강유전체27,29: platinum film 28: ferroelectric
30 : 티타늄막 32 : PSG막30: titanium film 32: PSG film
본 발명은 불휘발성 메모리 장치인 강유전체 램 제조 방법에 관한 것으로, 특히 강유전체 캐패시터를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a ferroelectric RAM, which is a nonvolatile memory device, and more particularly, to a method of manufacturing a ferroelectric capacitor.
제1도는 종래의 강유전체 램의 단면도로서, 이를 통해 종래의 강유전체(Ferroelectric) 램(RAM) 제조 방법, 특히 캐패시터 제조 방법을 중점적으로 살펴본다.FIG. 1 is a cross-sectional view of a conventional ferroelectric ram, and focuses on a conventional method of manufacturing a ferroelectric ram (RAM), particularly a method of manufacturing a capacitor.
종래에는 소자분리막과 모스트랜지스터가 형성된 실리콘 기판 상에 평탄화 층간절연막인 BPSG막(1)이 형성된 다음, 강유전체 캐패시터가 형성되게 된다.Conventionally, a BPSG film 1, which is a planarization interlayer insulating film, is formed on a silicon substrate on which a device isolation film and a MOS transistor are formed, and then a ferroelectric capacitor is formed.
강유전체 캐패시터는 먼저, BPSG막(1)상에 장벽금속(Barrier Metal)인 티타늄(Ti)(2)과 캐패시터의 하부전극인 백금막(Pt)(3)을 차례로 형성하고, 강유전체(4)를 형성한 다음, O2및 강유전체의 휘발성 물질을 제거하여 결정화하기 위한 어닐링을 800℃의 온도에서 실시한다. 그리고, 캐패시터의 상부전극인 백금막(5)과 장벽금속인 티타늄(6)을 차례로 형성한다. 여기서, 강유전체 물질로는 PZT 또는 Y-1(SrBi2Ta2O8)을 사용한다.The ferroelectric capacitor first forms a titanium (Ti) 2, which is a barrier metal, and a platinum film (Pt, 3), which is a lower electrode of the capacitor, in order on the BPSG film 1, and then forms the ferroelectric 4. After formation, annealing for crystallization by removing volatiles of O 2 and ferroelectrics is carried out at a temperature of 800 ° C. Then, a platinum film 5, which is the upper electrode of the capacitor, and titanium 6, which is a barrier metal, are formed in this order. Here, PZT or Y-1 (SrBi 2 Ta 2 O 8 ) is used as the ferroelectric material.
이어서, 캐패시터 패턴을 형성하기 위한 마스크 및 식각 공정을 실시하게 되는데, 먼저 상부전극 마스크를 사용하여 티타늄(6)과 백금막(5) 및 강유전체(4)를 건식식각하고, 상부전극 마스크를 제거한 다음, 강유전체 리커버리 어닐을 O2분위기에서 실시하고, 하부전극 마스크를 사용하여 백금막(3)과 티타늄(2)을 식각한다. 여기서, 하부전극은 마스크 공정 및 식각 공정을 고려하여 상부전극에 비하여 상당히 커야한다.Subsequently, a mask and an etching process for forming a capacitor pattern are performed. First, the titanium 6, the platinum film 5, and the ferroelectric 4 are dry-etched using the upper electrode mask, and then the upper electrode mask is removed. The ferroelectric recovery annealing is performed in an O 2 atmosphere, and the platinum film 3 and the titanium 2 are etched using the lower electrode mask. Here, the lower electrode should be considerably larger than the upper electrode in consideration of the mask process and the etching process.
상기 설명한 바와 같이 캐패시터를 형성을 완료한 다음, 층간절연막인 PSG막(7)을 전체구조 상부에 형성하고, 금속콘택 식각 공정을 수행하고, 장벽금속막인 TiN/Ti와 금속막인 알루미늄(Al)을 형성하고, 금속 마스크 및 식각 공정을 실시하여 제1도와 같은 최종적인 강유전체 램을 완성한다.After completing the formation of the capacitor as described above, the PSG film 7, which is an interlayer insulating film, is formed on the entire structure, the metal contact etching process is performed, and the TiN / Ti, which is a barrier metal film, and aluminum, which is a metal film, is formed. ), A metal mask and an etching process are performed to complete the final ferroelectric ram as shown in FIG.
상기와 같이 이루어지는 종래의 강유전체 램 제조 방법은 다음과 같은 문제점을 가지게 된다.The conventional ferroelectric ram manufacturing method as described above has the following problems.
상술한 바와 같이 종래에는 강유전체 램의 캐패시터 패턴을 형성할 때, 상부전극과 강유전체 및 하부전극을 차례로 식각하는 순서로 제조되게 된다. 때문에, 하부전극은 마스크 및 식각 공정을 고려하여 상부전극에 비해 상당히 큰 크기를 가져야 하고, 이로 인해 강유전체 캐패시터의 전체면적이 단위 셀에서 많은 면적을 차지하여 소자의 집적도 향상에 장애가 되게 된다.As described above, when the capacitor pattern of the ferroelectric ram is conventionally formed, the upper electrode, the ferroelectric, and the lower electrode are sequentially manufactured by etching. Therefore, the lower electrode needs to have a considerably larger size than the upper electrode in consideration of a mask and an etching process, and thus, the entire area of the ferroelectric capacitor occupies a large area in the unit cell, which hinders the integration of the device.
또한, 통상적인 DRAM의 캐패시터 제조 방법과 같이 하부전극을 먼저 식각하고 유전체 및 상부전극을 형성한 다음, 상부전극을 식각하는 방법을 사용하여 강유전체 램의 캐패시터를 제조할 경우, 하부전극의 아래에 장벽금속막으로서 형성된 Ti가 식각되므로, 강유전체 결정화 어닐링시 O3및 강유전체 물질중의 휘발성 물질의 확산에 의한 모스트랜지스터 접합(소오스/드레인)의 특성에 변화 및 파괴를 가져오게 된다.Also, when a capacitor of a ferroelectric ram is manufactured using a method of etching a lower electrode first, forming a dielectric and an upper electrode, and then etching the upper electrode as in a conventional method of manufacturing a capacitor of DRAM, a barrier under the lower electrode Since Ti formed as a metal film is etched, the ferroelectric crystallization annealing causes changes and fractures in the characteristics of the MOS transistor junctions (source / drain) due to diffusion of volatile materials in O 3 and ferroelectric materials.
따라서, 본 발명은 O2및 강유전체의 휘발성 물질이 확산되는 것을 억제하여 모스트랜지스터의 파괴를 방지하고, 강유전체 캐패시터가 차지하는 면적을 줄이면서 같은 면적에서도 종래기술에 비해 유효 면적이 증대된 캐패시터를 갖는 강유전체 램 제조 방법을 제공함을 그 목적으로 한다.Accordingly, the present invention prevents the destruction of the MOS transistor by suppressing the diffusion of volatile materials of O 2 and the ferroelectric, and reduces the area occupied by the ferroelectric capacitor, while reducing the area occupied by the ferroelectric capacitor, the ferroelectric having a capacitor having an increased effective area compared to the prior art. It is an object of the present invention to provide a method for manufacturing a ram.
상기 목적을 달성하기 위한 본 발명은 모스트랜지스터 형성이 완료된 반도체 기판 전체구조 상부에 제1층간절연막을 형성하는 제1단계; 이후의 공정에서 O2와 강유전체의 휘발성 물질이 상기 제1층간절연막 하부로 확산되는 것을 방지하기 위하여, 상기 제1층간절연막 상에 제1확산방지층을 형성하는 제2단계; 상기 제1확산방지층 상에 제1전도막을 형성하고 선택식각하여 캐패시터의 하부전극 패턴을 형성하는 제3단계; 상기 제3단계가 완료된 전체 구조 상에 캐패시터의 강유전체막을 증착하고 결정화를 위한 어닐링을 실시하는 제4단계; 상기 강유전체막 상에 제2전도막을 형성하고, 상기 제2전도막 및 상기 강유전체막을 차례로 선택식각하여 캐패시터의 상부전극 패턴 및 강유전체막 패턴을 형성하는 제5단계; 강유전 특성 회복을 위한 어닐링을 실시하는 제6단계; O2및 강유전체의 휘발성 물질이 확산되는 것을 방지하기 위하여, 상기 제6단계가 완료된 전체 구조 상에 제2확산방지층을 형성하는 제7단계; 및 상기 제2확산방지층 상에 제2층간절연막 및 금속배선을 형성하는 제8단계를 포함하는 강유전체 램 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming a first interlayer insulating film on the entire semiconductor substrate structure of the MOS transistor formation; Forming a first anti-diffusion layer on the first interlayer insulating film to prevent the volatile material of O 2 and the ferroelectric from being diffused below the first interlayer insulating film in a subsequent process; A third step of forming a first conductive film on the first diffusion barrier layer and selectively etching to form a lower electrode pattern of a capacitor; A fourth step of depositing a ferroelectric film of a capacitor on the entire structure in which the third step is completed and performing annealing for crystallization; A fifth step of forming a second conductive film on the ferroelectric film, and selectively etching the second conductive film and the ferroelectric film to form an upper electrode pattern and a ferroelectric film pattern of a capacitor; A sixth step of performing annealing for restoring ferroelectric characteristics; A seventh step of forming a second diffusion barrier layer on the entire structure in which the sixth step is completed in order to prevent diffusion of the volatile material of O 2 and the ferroelectric material; And an eighth step of forming a second interlayer dielectric layer and a metal wiring on the second diffusion barrier layer.
이하, 첨부된 도면 제2(a)도 내지 제2(e)도를 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings (2) to 2 (e).
제2(a)도 내지 제2(e)도는 본 발명의 일실시예에 따른 강유전체 램 제조 공정도이다.2 (a) to 2 (e) is a manufacturing process diagram of a ferroelectric ram according to an embodiment of the present invention.
먼저, 제2(a)도와 같이 소자분리막(22)이 형성된 실리콘 기판(21)상에 모스트랜지스터(23)를 형성하고 전체구조 상부에 평탄화 층간절연막인 BPSG막(24)을 형성한다.First, a MOS transistor 23 is formed on the silicon substrate 21 on which the device isolation film 22 is formed, as shown in FIG. 2A, and a BPSG film 24, which is a planarization interlayer insulating film, is formed on the entire structure.
이어서, 제2(b)도와 같이, O2확산 장벽 역할을 하는 실리콘질화막(Si3N4)(25)을 BPSG막(24)상에 70Å 내지 500Å 두께 정도로 형성하고, 상기 실리콘질화막(25)과 백금막과의 접착력을 좋게하기 위하여 탄탈늄(Ta)(26)을 70Å 내지 300Å정도 증착한다. 이어 연속으로 캐패시터 하부전극인 백금막(27)을 500Å 내지 1000Å정도 증착한다.Subsequently, as shown in FIG. 2 (b), a silicon nitride film (Si 3 N 4 ) 25 serving as an O 2 diffusion barrier is formed on the BPSG film 24 to a thickness of about 70 kPa to about 500 kPa, and the silicon nitride film 25 Tantalum (Ta) 26 is deposited at about 70 kPa to about 300 kPa in order to improve adhesion to the platinum film. Subsequently, a platinum film 27, which is a capacitor lower electrode, is continuously deposited to about 500 mW to 1000 mW.
이어서, 제2(c)도와 같이, 하부전극 마스크를 사용하여 백금막(27) 및 탄탈늄막(26)을 식각한다.Next, as shown in FIG. 2C, the platinum film 27 and the tantalum film 26 are etched using the lower electrode mask.
이어서, 제2(d)도와 같이, 강유전체(28)를 1000Å 내지 1500Å 정도 증착하고, 결정화를 위한 어닐링을 실시한다. 이때, 하부전극 하부에 형성된 실리콘질화막(25)에 의해 강유전체 물질 중 휘발성 물질(PZT일 경우는 PbO, Y-1일 경우는 Bi2O3)이 내부로 확산되는 것을 방지하여 모스트랜지스터의 특성 파괴가 방지된다. 그리고, 계속해서 캐패시터 상부전극인 백금막(29)과 장벽금속인 티타늄막(30)을 연속적으로 형성한 다음 상부마스크를 사용하여 티타늄막(30), 백금막(29) 및 강유전체(28)를 차례로 식각하여 패턴화한다.Subsequently, as shown in FIG. 2 (d), the ferroelectric 28 is deposited at about 1000 GPa to 1500 GPa, and annealing for crystallization is performed. At this time, the silicon nitride film 25 formed under the lower electrode prevents the volatile materials (PbO in the case of PZT and Bi 2 O 3 in the case of Y-1) from being destroyed, thereby destroying the characteristics of the MOS transistor. Is prevented. Subsequently, the platinum film 29 as the capacitor upper electrode and the titanium film 30 as the barrier metal are successively formed, and then the titanium film 30, the platinum film 29 and the ferroelectric 28 are formed using the upper mask. Etch in turn to pattern.
이어서, O2분위기에서 강유전체 특성 회복을 위한 어닐(Ferroelectric Recovery Anneal)을 실시한다.Subsequently, an annealing is performed to recover the ferroelectric properties in an O 2 atmosphere.
이어서, 제2(e)도와 같이, O2및 강유전체 물질중의 휘발성분의 확산을 방지하기 위하여 실리콘질화막(31)을 50Å 내지 100Å 정도로 전체구조 상부에 형성한 다음, 층간절연막인 PSG(32)을 전체구조 상부에 형성하고, 장벽금속막(Ti/TiN)공정을 포함하는 금속배선 공정을 실시하여 최종적인 강유전체 램 구조를 완성한다.Subsequently, as shown in FIG. 2 (e), in order to prevent diffusion of volatile components in the O 2 and ferroelectric materials, a silicon nitride film 31 is formed on the entire structure at about 50 kPa to 100 kPa, and then the PSG 32 as an interlayer insulating film. Is formed on the whole structure, and a metal wiring process including a barrier metal film (Ti / TiN) process is performed to complete the final ferroelectric ram structure.
본 발명의 강유전체 램 제조 방법은 강유전체의 휘발성 물질 확산을 방지하여 모스트랜지스터의 파괴를 방지하고, 강유전체 캐패시터가 차지하는 면적을 줄이면서 같은 면적에서도 종래기술에 비해 유효 면적이 증대된 캐패시터를 갖는 효과가 있다.The method of manufacturing the ferroelectric ram of the present invention prevents the destruction of the MOS transistor by preventing the diffusion of the volatile material of the ferroelectric, and reduces the area occupied by the ferroelectric capacitor, and has the effect of having a capacitor having an increased effective area in the same area as compared with the prior art. .
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be clear to those who have
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