KR100652354B1 - Capacitor of a semiconductor device having low contact resistance between a lower electrode and a contact plug and method for fabricating the same - Google Patents

Abstract

Disclosed are a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug, and a method of manufacturing the same. The present invention provides a capacitor of a semiconductor device connected to a substrate with an interlayer insulating film interposed therebetween, wherein a contact hole is formed in the interlayer insulating film to expose the substrate, and the contact hole is a lower electrode of the capacitor. And a conductive plug connected to the at least one conductive plug, wherein at least an upper portion of the conductive plug is a metal silicide layer. Here, the metal silicide film is an oxidative cobalt or nickel silicide film and constitutes part or all of the lower electrode or the conductive plug.

Description

Capacitor of a semiconductor device having low contact resistance between a lower electrode and a contact plug and method for fabricating the same

1 is a cross-sectional view of a capacitor formed according to a method of manufacturing a capacitor of a semiconductor device according to the prior art.

2 to 5 are cross-sectional views of a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to the first to fourth embodiments of the present invention, respectively.

6 to 10 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to a first embodiment of the present invention.

11 is a cross-sectional view illustrating a step of forming a contact plug in a capacitor manufacturing method of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to a second embodiment of the present invention.

12 and 13 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to a third embodiment of the present invention.

14 and 15 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to a fourth embodiment of the present invention.

* Description of Signs of Major Parts of Drawings *

40: substrate. 42: interlayer insulation film.

44: Contact hole. 46, 80, 94: First to third conductive films.

48: metal film. 50: surface planarization film.

52, 66: First and second metal silicide plugs.

54, 68: 1st and 2nd adhesion film.

56, 70, 84: First to third diffusion barrier films.

58, 72, 86: First to third conductive metal oxide films.

60, 74, 88: First to third heat resistant metal films.

62, 76, 90, 98: first to fourth dielectric films.

64, 78, 92, 100: first to fourth upper electrodes.

46a, 46b: first and second conductive plugs.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a capacitor and a method for manufacturing the semiconductor device having a low contact resistance between a lower electrode and a contact plug.

As the degree of integration of semiconductor devices increases, the area in which semiconductor devices can be formed in a semiconductor substrate is narrowed. Increasing semiconductor device density not only narrows the spacing between devices, but also affects the operating characteristics of each device.

For example, in order to operate a semiconductor device normally, a semiconductor capacitor having an appropriate capacitance is necessary, and the capacitance of the capacitor is increased in proportion to the area of the electrode. However, when the electrode area of the capacitor is narrowed due to high integration of the semiconductor device, it is difficult to secure a desired capacitance and it is difficult to operate the semiconductor device normally. Accordingly, a method of using a ferroelectric film, such as a PZT film, has been proposed as an alternative to secure proper capacitance required for normal operation of a semiconductor device in a narrow electrode area.

Referring to FIG. 1, a conventional capacitor using a PZT film as a dielectric film is composed of the following components.

That is, the interlayer insulating film 12 is provided on the semiconductor substrate 10, and the contact hole 14 exposing the semiconductor substrate 10 is formed in the interlayer insulating film 12. The doped polysilicon layer 16 is filled in the contact hole 14. A titanium film (Ti) 18 is formed on the interlayer insulating film 12 to cover the doped polysilicon film 16, and a titanium nitride film (TiN) 20 is formed thereon. A platinum film (Pt) 22 used as a lower electrode, a PZT film 24 used as a dielectric film, an iridium oxide film (IrO ₂ ) 26 forming an upper electrode and an iridium film on the titanium nitride film 20 (Ir) 28 is formed sequentially.

The PZT film 24 is in an amorphous state immediately after formation. Since the leakage current rapidly increases in the amorphous state, the resultant product of the PZT film 24 is heat-treated at the crystallization temperature of the PZT film 24. That is, immediately after the PZT film 24 is formed, the resultant is heat-treated at a temperature of about 600 ° C to 800 ° C in an oxygen atmosphere.

In addition, after the capacitor is formed, the resultant is heat-treated in an oxygen atmosphere in the temperature range of 450 ℃ to 600 ℃ to recover the damage caused by the etching performed in the process of forming the capacitor and to stabilize the capacitor.

However, in this heat treatment process, oxygen (O ₂ ) diffuses through the grain boundary of the titanium nitride film 20 to the polysilicon plug 16 filling the contact hole 14 and reacts with silicon (Si). A silicon oxide film (SiO ₂ ) (not shown) is formed between the polysilicon plug 16 and the titanium nitride film 20 to rapidly increase the contact resistance of the polysilicon plug 16. As a result, the operation speed of the semiconductor device becomes slow. In addition, during the heat treatment, platinum and silicon are diffused through the titanium nitride film 20 to cause a silicide reaction. This reaction leads to deterioration of the properties of the PZT film. In order to solve this problem, a titanium silicide layer (TiSi ₂ ) or a tungsten silicide layer (WSi _x ) may be considered instead of the titanium nitride layer 20, but a dopant may be removed from the doped polysilicon layer 16 in the heat treatment process. There is a problem in that the resistance of the doped polysilicon layer 16 increases due to absorption. As another alternative, titanium silicide, tantalum silicide or three-component amorphous material films containing tungsten silicide and nitrogen (N) are of interest, but there is still a problem to be solved and satisfactory data applicable to the real process. Is not coming out.

In addition, an iridium oxide film (IrO ₂ ) or a ruthenium oxide film (RuO ₂ ) may be considered, but there is a problem in that phase formation is difficult during formation and surface roughness becomes worse during the heat treatment process.

In addition, there is an attempt to solve the problem by providing an iridium film (Ir) between the polysilicon plug 16 and the titanium nitride film 20, but still does not prevent the polysilicon plug 16 from being oxidized. I can't.

Therefore, the technical problem to be achieved by the present invention is to solve the problems of the prior art as described above, having a ferroelectric film, but can implement a low resistance between the lower electrode and the conductive plug in contact with the substrate and has an ohmic contact resistance The present invention provides a capacitor of a semiconductor device.

Another object of the present invention is to provide a method of manufacturing the capacitor.

In order to achieve the above technical problem, the present invention provides a lower electrode and a ferroelectric film on an interlayer insulating film including a substrate and a contact hole formed on the substrate, a conductive plug filling the contact hole, and the interlayer insulating film including the conductive plug. And a capacitor of the semiconductor device sequentially provided with an upper electrode,

The conductive plug provides a capacitor of a semiconductor device, wherein at least an upper portion thereof is provided with a metal silicide film having oxidation resistance.

According to the first embodiment of the present invention, the lower region of the conductive plug is a doped polysilicon layer, and the upper layer contacting the lower electrode is a cobalt silicide layer (CoSi ₂ ) or a nickel silicide layer (NiSi).

At this time, the thickness of the metal silicide film is about 50 kPa to 1,000 kPa, preferably about 300 kPa to 500 kPa.

The ferroelectric film is TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , SiO ₂ / SiN, BaTiO ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , Bi ₄ Ti ₃ O ₁₂ , PbTiO ₃ , PZT, (Pb, La) (Zr, Ti) O ₃ and SBT (SrBi ₂ Ta ₂ O ₉ ) is a crowd selected one.

The lower electrode is composed of a plurality of material films.

According to the first embodiment of the present invention, the lower electrode is composed of an adhesion film, a diffusion barrier film, a conductive metal oxide film, and a heat resistant metal film. These material films are provided sequentially from bottom to top in the order described.

Here, the adhesion film is a titanium film (Ti), the diffusion barrier film is an iridium film (Ir), the conductive metal oxide film is ruthenium oxide film (RuO ₂ ), iridium oxide film (IrO ₂ ), (Ca, Sr) RuO ₃ film Or LaSrCoO ₃ film. The heat resistant metal film is a platinum film Pt, an iridium film Ir, a ruthenium film Ru, a rhodium film Rh, an osmium film Os or a palladium film Pa.

According to a second embodiment of the present invention, the conductive plug is a cobalt silicide film having oxidation resistance.

Further, in order to achieve the above technical problem, the present invention provides a lower electrode on an interlayer insulating film including a substrate and a contact hole formed on the substrate, a conductive plug filling the contact hole and the conductive plug; A capacitor of a semiconductor device having a dielectric film and an upper electrode sequentially,

The lower electrode provides a capacitor of a semiconductor device, comprising a conductive film and a oxidizing metal silicide film sequentially stacked.

Here, the conductive film and the oxidizing metal silicide film are doped polysilicon film and cobalt silicide film, respectively. At this time, the thickness of the oxidizing metal silicide film is about 500 kPa to about 3,000 kPa.

According to another embodiment of the present invention, a diffusion barrier film, a conductive metal oxide film, and a heat resistant metal film are further sequentially stacked between the metal silicide film and the dielectric film. The thickness of the said metal silicide film at this time is about 50 kPa-about 1,000 kPa.

Further, in order to achieve the above technical problem, the present invention provides a lower electrode on an interlayer insulating film including a substrate and a contact hole formed on the substrate, a conductive plug filling the contact hole and the conductive plug; A capacitor of a semiconductor device having a dielectric film and an upper electrode sequentially,

The lower electrode provides a capacitor of a semiconductor device, wherein the oxidized metal silicide layer and the conductive layer are sequentially stacked.

Here, the oxidizing metal silicide film is a cobalt silicide film, and the conductive film is a diffusion preventing film, a conductive metal oxide film, and a heat resistant metal film sequentially formed on the oxidizing metal silicide film as a plurality of conductive material films.

In order to achieve the above another technical problem, the present invention (a) forming an interlayer insulating film on the substrate; (b) forming a contact hole in the interlayer insulating film; (c) filling a conductive plug in the contact hole; (d) converting the exposed portion of the conductive plug into an oxidized metal silicide film; (e) forming a lower electrode on the interlayer insulating layer to cover the metal silicide layer; And (f) sequentially forming a dielectric film and an upper electrode on the lower electrode.

In this case, the step (d) may include: (d1) forming a metal film covering the conductive plug on the interlayer insulating film, and forming a metal film having excellent downward diffusion toward the conductive plug in a subsequent heat treatment process; (d2) forming a surface planarization film on the metal film; (d3) heat-treating the resultant on which the surface planarization film is formed to form an oxidation resistant metal silicide film in a region in contact with the metal film of the conductive plug; (d4) removing the surface planarization film and the metal film; And (d5) stabilizing the resultant from which the surface planarization film and the metal film are removed.

According to an embodiment of the present invention, it is preferable that the metal film having excellent downward diffusion is formed of a cobalt film, and the surface planarization film is formed of a nitride-based material film, for example, a titanium nitride film (TiN). Do. At this time, the metal film is 130 Å, the surface planarization film is preferably formed to a thickness of about 100 각각 respectively.

The surface planarization film may be formed of a tungsten nitride film WN.

The metal film and the surface planarization film are preferably formed by sputtering, but may be formed by chemical vapor deposition (hereinafter, referred to as CVD).

The exposed surface of the conductive plug is cleaned with Radio Freqancy of 13.56 MHz before forming the metal film.

The cleaning process, the metal film and the surface planarization film forming process proceed in-situ.

It is preferable to heat-treat the resultant product on which the surface planarization film is formed by a rapid thermal processing method.

At this time, the heat treatment is carried out in a nitrogen atmosphere, it is preferably carried out at a temperature of about 400 ℃ to 1,000 ℃, preferably at 480 ℃ for about 90 seconds.

In the step (d5), the resultant is stabilized by heat treatment in a nitrogen atmosphere by the RTP method, it is preferably stabilized by heat treatment for 30 seconds at about 650 ℃.

According to another embodiment of the present invention, the entire conductive plug is converted into the oxidizing metal silicide layer during the heat treatment.

In addition, the metal silicide layer may be directly formed by CVD or sputtering.

The oxidizing metal silicide film is preferably formed of a cobalt silicide film (CoSi ₂ ).

At this time, the cobalt silicide film may be formed to a thickness of 50 kPa to 1,000 kPa, but preferably, it is formed to a thickness of about 300 kPa to 500 kPa.

The step (e) further includes the step of sequentially forming an adhesion film, a diffusion barrier film, a conductive metal oxide film, and a heat resistant metal film covering the metal silicide film on the interlayer insulating film.

In this case, the adhesion film is formed of a titanium film (Ti), and the diffusion barrier is formed of an iridium film (Ir) or ruthenium film (Ru).

The conductive metal oxide film is formed of a ruthenium oxide film (RuO ₂ ), an iridium oxide film (IrO ₂ ), a (Ca, Sr) RuO ₃ film, or a LaSrCoO ₃ film.

The heat resistant metal film is formed of a platinum film Pt, an iridium film Ir, a ruthenium film Ru, a rhodium film Rh, an osmium film Os or a palladium film Pa.

The dielectric layer is formed of a ferroelectric layer, but TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , SiO ₂ / SiN, BaTiO ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , Bi ₄ Ti ₃ O ₁₂ , PbTiO ₃ Form one selected from the group consisting of PZT, (Pb, La) (Zr, Ti) O ₃ and SBT.

In order to achieve the above another technical problem, the present invention (a) forming an interlayer insulating film on the substrate; (b) forming a contact hole in the interlayer insulating film; (c) forming a conductive film filling the contact hole on the interlayer insulating film; (d) converting the exposed portion of the conductive film into a metal silicide film; (e) forming a lower electrode on the metal silicide layer; And (f) sequentially forming a dielectric film and an upper electrode on the lower electrode.

In this process, step (c) includes: (c1) forming a first conductive film filling the contact hole on the interlayer insulating film; (c2) etching the entire surface of the first conductive layer until the interlayer insulating layer is exposed to form a conductive plug in the contact hole; And (c3) forming a second conductive film covering the conductive plug on the interlayer insulating film.

According to another embodiment of the present invention, the step (c) comprises the steps of (1) forming a conductive film filling the contact hole on the interlayer insulating film; And (2) planarizing the entire surface of the conductive film until it reaches a predetermined thickness within a range in which the interlayer insulating film is not exposed.

The forming of the lower electrode may further include sequentially forming a diffusion barrier layer, a conductive metal oxide layer, and a heat resistant metal layer on the metal silicide layer.

Step (d) comprises the steps of: (d1) forming a metal film on the second conductive film and forming a metal film having excellent downward diffusion toward the second conductive film in a subsequent heat treatment process; (d2) forming a surface planarization film on the metal film; (d3) forming a metal silicide film between the second conductive film and the metal film by heat-treating the resultant having the surface planarization film formed thereon; And (d4) removing the surface planarization film and the metal film.

Precleaning the entire surface of the second conductive film before forming the metal film; And cleaning the entire surface of the second conductive film by RF cleaning.

The RF cleaning process, the metal film formation and the surface planarization film formation process are performed in-situ.

In (d3), the resultant is heat treated by RTP method.

The first and second conductive films are formed of a polysilicon film.

The metal silicide film may be formed to a thickness of about 50 kPa to about 1,000 kPa, but may be formed to a thickness of about 300 kPa to about 500 kPa.

In addition, in order to achieve the above another technical problem, the present invention comprises the steps of (a) forming an interlayer insulating film on the substrate; (b) forming a contact hole in the interlayer insulating film; (c) forming a conductive film filling the contact hole on the interlayer insulating film; (d) forming an oxidizing metal silicide film on the conductive film; And (e) sequentially forming a dielectric film and an upper electrode on the metal silicide film.

In this process, step (c) includes: (c1) forming a third conductive film filling the contact hole on the interlayer insulating film; (c2) forming a conductive plug to fill the contact hole by etching the entire surface of the third conductive film until the interlayer insulating film is exposed; And (c3) forming a fourth conductive film covering the conductive plug on the interlayer insulating film.

According to another embodiment of the present invention, step (c) comprises the steps of (1) forming a conductive film filling the contact hole on the interlayer insulating film; And (c2) planarizing the entire surface of the conductive layer, but planarizing the layer in a range where the interlayer insulating layer is not exposed.

The oxidizing metal silicide film is a lower electrode, and is preferably formed of a cobalt silicide film. At this time, the oxidation-resistant metal silicide film is preferably formed to a thickness of about 500 kPa to 3,000 kPa.

(D) step (d1) forming a metal film on the fourth conductive film; (d2) forming a surface planarization film on the metal film; (d3) heat-treating the resultant on which the surface planarization film is formed to form an oxidizing metal silicide film between the fourth conductive film and the metal film; (d4) removing the surface planarization film and the metal film; And stabilizing the resultant material from which the surface planarization film and the metal film are removed.

Before forming the metal film, after planarizing the entire surface of the fourth conductive film, precleaning the entire surface of the fourth conductive film; And removing the oxide film from the entire surface of the fourth conductive film by RF cleaning.

The RF cleaning process, the metal film and the surface planarization film forming process are performed in-situ.

The third and fourth conductive films are preferably formed of a polysilicon film.

As such, a semiconductor having a ferroelectric film as a dielectric film is provided between the lower electrode of the capacitor and the conductive plug or between the lower electrode and the conductive film in contact with the conductive plug or by using the cobalt silicide film itself as the lower electrode. The contact resistance between the lower electrode of the device, such as a FRAM cell capacitor, and the conductive plug can be lowered, resulting in a higher operating speed of the capacitor.

Hereinafter, a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to an embodiment of the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

However, embodiments of the present invention can be modified in many different forms, the scope of the invention should not be construed as limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements.

2 to 5 are cross-sectional views of a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to the first to fourth embodiments of the present invention, respectively. 10 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to a first embodiment of the present invention, and FIG. 11 is a bottom view according to the second embodiment of the present invention. A cross-sectional view showing a step of forming a contact plug in a capacitor manufacturing method of a semiconductor device having a low contact resistance between an electrode and a contact plug. 12 and 13 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to a third embodiment of the present invention, and FIGS. 14 and 15 illustrate the present invention. 4 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a contact plug according to a fourth embodiment of the present invention.

First, a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a conductive plug according to the first to fourth embodiments of the present invention will be described.

<First Embodiment>

2, there is an interlayer insulating film 42 on the substrate 40. The substrate 40 is a semiconductor substrate, and the interlayer insulating film 42 includes at least a crowd selected of a nitride film (SiN), an oxide film (eg, a silicon oxide film (SiO ₂ )), a PSG film, a BPSG film, a TEOS film, and a USG film. Which one. A contact hole 44 is formed in the interlayer insulating layer 42 to expose a predetermined region of the substrate 40, for example, a source or drain region.

Although not illustrated, the interlayer insulating layer 42 may be a metal interlayer insulating layer. In this case, an area exposed through the contact hole 44 is a conductive pad layer in contact with the substrate 40, and the contact hole 44 serves as a via hole. The contact hole 44 is filled with conductive plugs 46a and 52, a part of the contact hole 44 is filled with a first conductive plug 46a, and the remaining part is an oxidized first metal silicide plug 52. Filled with) The first conductive plug 46a may be a doped polysilicon plug or other conductive material films such as tungsten film W, tantalum film Ta, ruthenium film Ru, iridium film Ir, and platinum film. (Pt), an osmium film (Os), a tungsten silicide film (WSi), and a tungsten nitride film (WN). The oxidizing first metal silicide plug 52 is an ohmic contact layer and is a cobalt silicide plug or a nickel silicide plug. At this time, the thickness of the first metal silicide plug 52 is about 50 kPa to about 1,000 kPa, but is preferably about 300 kPa to about 500 kPa.

A lower electrode 51 covering the oxidizing resistant first metal silicide plug 52 is formed on the interlayer insulating layer 42. The lower electrode 51 includes a first adhesion layer 54, a first diffusion barrier 56, a first conductive metal oxide layer 58, and a first heat resistant metal layer 60. The first adhesion layer 54 is a material layer for increasing adhesion between the first diffusion barrier layer 56 and a lower layer below it, in particular, the interlayer insulating layer 42.

For example, when the interlayer insulating layer 42 is a nitride layer (SiN) or a silicon oxide layer (SiO ₂ ), and the first diffusion barrier layer 56 is iridium (Ir), adhesion between the two material layers may be weakened. The first adhesion layer 54 serves to prevent this. The first adhesion film 54 is a titanium film (Ti). In this case, the thickness of the first adhesion layer 54 is preferably about 50 mm 3.

The first diffusion barrier 56 is a material layer for minimizing the reaction between the first conductive metal oxide layer 58 and its upper layer and the conductive material layers 46a and 52. An iridium film is preferred as the first diffusion barrier 56 for this purpose, but a ruthenium film Ru may be used. When the first diffusion barrier film 56 is an iridium film, the thickness thereof is suitably about 1,000 kPa. The first conductive metal oxide film 58 is a ruthenium oxide film (RuO ₂ ), an iridium oxide film (IrO ₂ ), a (Ca, Sr) RuO ₃ film, or a LaSrCoO ₃ film. The thickness of the first conductive metal oxide layer 58 may vary depending on the material of the constituent material. However, in the case of the iridium oxide layer IrO ₂ , the thickness of the first conductive metal oxide layer 58 is preferably about 500 GPa. The first heat resistant metal film 60 is preferably a platinum film (Pt), but may also be an iridium film (Ir), ruthenium film (Ru), rhodium film (Rh), osmium film (Os) or palladium film (Pa). Do. When the first heat resistant metal film 60 is a platinum film, the thickness thereof is preferably about 1,500 m 3, but when the other material film other than the platinum film is used, the thickness is different. The first dielectric layer 62 and the first upper electrode 64 are sequentially formed on the lower electrode 51. The first dielectric layer 62 may be a ferroelectric layer including TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , SiO ₂ / SiN, BaTiO ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , Bi ₄ Ti ₃ O ₁₂ , PbTiO ₃ , PZT, (Pb, La) (Zr, Ti) O _3, and (SrBi ₂ Ta ₂ O ₉ ) (SBT) are any one selected from a single film or a composite film. The first heat resistant metal layer 60 may be regarded as a lower electrode of the capacitor by itself, but the adhesion layer 54 to the first layer formed between the interlayer insulating layer 42 and the first dielectric layer 62. 1 It is preferable that all the heat resistant metal films 60 serve as a lower electrode.

As described above, in the capacitor in which the main material film constituting the lower electrode is a heat resistant metal film, and the dielectric film is a ferroelectric film, the upper electrode is preferably formed of the same heat resistant metal film as the lower electrode. Accordingly, the first upper electrode 64 may be regarded as the same material film as the first heat resistant metal film 60, and is preferably a platinum film.

In this way, a memory device having a ferroelectric film composed of the first adhesion film 54 to the first heat resistant metal film 60, the first dielectric film 62, and the first upper electrode 64, for example, a FRAM. The cell capacitor is configured.

Second Embodiment

Referring to FIG. 3, an interlayer insulating layer 42 is formed on the substrate 40, and a contact hole 44 is formed in the interlayer insulating layer 42. The contact hole 44 is filled with an oxidation resistant second metal silicide plug 66. The oxidizing second metal silicide plug 66 is a cobalt silicide plug or a nickel silicide plug. A lower electrode 67 is formed on the interlayer insulating layer 42 to cover the oxidized second metal silicide plug 66. The lower electrode 67 includes a second adhesion film 68, a second diffusion barrier film 70, a second conductive metal oxide film 72, and a second heat resistant metal film 74. The second dielectric layer 76 and the second upper electrode 78 are sequentially formed on the lower electrode 67. The role, thickness, or material of the second adhesion layer 68 to the second upper electrode 78 correspond to the first adhesion layer 54 to the first upper electrode 64 of the first embodiment, respectively.

Third Embodiment

Referring to FIG. 4, an interlayer insulating layer 42 is formed on a substrate 40, and a pad layer connected to the predetermined region of the substrate 40 or the substrate 40 is formed on the interlayer insulating layer 42. A contact hole 44 (or a via hole) through which the not shown portion is exposed is formed. The contact hole 44 is filled with a second conductive plug 46b. The second conductive plug 46b is a doped polysilicon plug. A lower electrode 79 including at least an oxidizing metal silicide layer covering the second conductive plug 46b is formed on the interlayer insulating layer 42. For example, the lower electrode 79 may include a second conductive layer 80, an oxidizing resistant first metal silicide layer 82, a third diffusion barrier layer 84, a third conductive metal oxide layer 86, and a second conductive layer 80. The heat resistant metal film 88 is comprised. The second conductive layer 80 is a doped polysilicon layer. The oxidation resistant first metal silicide film 82 is a cobalt silicide film (CoSi ₂ ) or a nickel silicide film (NiSi) having a preferred thickness of about 300 kPa to 500 kPa. The third dielectric layer 90 and the third upper electrode 92 are sequentially formed on the lower electrode 79. The third diffusion barrier layer 84 to the third upper electrode 92 are material layers corresponding to the first diffusion barrier layer 56 of FIG. 2 to the first upper electrode 64 of the first embodiment.

Fourth Example

Referring to FIG. 5, an interlayer insulating layer 42 is formed on a substrate 40, and a pad layer connected to a predetermined region of the substrate 40 or the substrate 40 is connected to the interlayer insulating layer 42. A contact hole 44 (or via hole) through which (not shown) is exposed is formed. The contact hole 44 is filled with a second conductive plug 46b. The second conductive plug 46b is a doped polysilicon plug. A third conductive film 94 covering the second conductive plug 46b, an oxidizing resistant second metal silicide film 96, a fourth dielectric film 98, and a fourth upper electrode 100 on the interlayer insulating film 42. ) Is formed. The third conductive layer 94 and the oxidizing resistant second metal silicide layer 96 constitute a lower electrode. The third conductive film 94 is the same material film as the second conductive film 80 of the third embodiment. The oxidizing resistant second metal silicide film 96 is a cobalt silicide film or a nickel silicide film, which is a substantially lower electrode and has a thickness of about 500 kPa to 3,000 kPa. The fourth dielectric film 98 is a ferroelectric film made of a material selected from a crowd selected material constituting the first dielectric film 62 of the first embodiment. In consideration of the fact that the fourth dielectric layer 98 is a ferroelectric layer, the fourth upper electrode 100 is a heat-resistant metal layer including platinum or the like similar to the first to third upper electrodes of the first to third embodiments. Or a composite film thereof, but in the case of the fourth embodiment, considering that the second metal silicide film 96 is used as the lower electrode, the fourth upper electrode 100 is the second metal silicide film 96. May be the same silicide film.

Fifth Embodiment

The capacitor according to the fifth embodiment is characterized by consisting of an oxide-resistant metal silicide film and a conductive film in which lower electrodes are sequentially stacked. At this time, the oxidizing metal silicide film is preferably a cobalt silicide film or a nickel silicide film as in the first to fourth embodiments, and has a thickness of about 50 kPa to 1,000 kPa. The conductive film is a plurality of conductive material films, which are a diffusion barrier film, a conductive metal oxide film, and a heat resistant metal film sequentially formed on the oxidizing metal silicide film. The diffusion barrier film, the conductive metal oxide film, and the heat resistant metal film are the same as mentioned in the first to fourth embodiments.

Next, a method of manufacturing a capacitor of a semiconductor device having a low contact resistance between a lower electrode and a conductive plug according to the first to fourth embodiments of the present invention described above will be described.

<First Embodiment>

Referring to FIG. 6, an interlayer insulating layer 42 is formed on the substrate 40. The substrate 40 may be a semiconductor substrate on which semiconductor elements are formed or an SOI substrate having an insulating layer therebetween. The interlayer insulating film 42 is preferably formed of at least one selected from the group consisting of a nitride film (SiN), an oxide film (eg, silicon oxide film (SiO ₂ )), a PSG film, a BPSG film, a TEOS film, and a USG film. A photo / etch process is applied to the interlayer insulating layer 42 to form a contact hole 44 exposing a predetermined region, for example, a source or drain region, of the substrate 40.

Prior to forming the interlayer insulating layer 42, a semiconductor device such as a cell transistor may be formed on the substrate 40. In addition, an insulating film may be further formed between the interlayer insulating film 42 and the substrate 40 and may include a conductive pad layer (not shown) in contact with the substrate 40 between the semiconductor devices. It may be. Accordingly, the contact hole 44 may be a contact hole penetrating the interlayer insulating layer 42 and the insulating layer to expose a predetermined region of the substrate 40. In addition, since the width of the contact hole decreases while the depth of the contact hole increases due to the high integration of the semiconductor device, the contact hole 44 may be a via hole exposing the conductive pad layer included in the insulating layer. .

A first conductive layer 46 is formed on the interlayer insulating layer 42 to fill the contact hole 44. The first conductive layer 46 may be formed of a doped polysilicon layer. However, the first conductive layer 46 may be formed of another conductive material layer such as tungsten layer (W), tantalum layer (Ta), ruthenium layer (Ru), iridium layer (Ir), platinum together with the doped polysilicon layer. The film Pt, the osmium film Os, the tungsten silicide film WSi, and the tungsten nitride film WN may be formed of at least one selected from the group. The entire surface of the first conductive layer 46 is planarized until the interlayer insulating layer 42 is exposed. The planarization is performed using chemical mechanical polishing (hereinafter referred to as CMP).

Referring to FIG. 7, as a result of the planarization, a first conductive plug 46a filling the contact hole 44 is formed. After the first conductive plug 46a is formed, the entire surface of the first conductive plug 46a is precleaned. When the first conductive plug 46a is formed of a polysilicon film, a natural oxide film (SiO ₂ ) is formed on the entire surface of the substrate 40 in the process of moving the substrate 40 or in the pre-cleaning process for the subsequent process. Therefore, the oxide film (not shown) formed on the first conductive plug 46a is removed before proceeding to the subsequent process.

Specifically, after the pre-cleaning, the dry result is cleaned using a specific frequency, for example, a radio frequency (RF) of 13.56 MHz. By doing so, the oxide film formed on the entire surface of the first conductive plug 46a is removed. The RF cleaning may be carried out in various ways, but it is preferable to use the sputtered ions such as argon ions (Ar ⁺ ) in the sputtering equipment. Subsequently, after the RF cleaning, a metal film 48 and a surface planarization film 50 covering the first conductive plug 46a are sequentially formed on the interlayer insulating film 42. The metal film 48 not only has excellent diffusion property toward the first conductive plug 46a, that is, downward diffusion property in the heat treatment process for subsequent silicide film formation, and also reacts with the first conductive plug 46a. After the formation of the metal silicide film used as the ohmic contact layer, a stable resistance property, for example, a stable sheet resistance property, can be exhibited even in a subsequent process, a capacitor stabilization process after the completion of the capacitor, or a heat treatment process for recovering damage during the process. It is preferable to form the metal film which can be used. The metal film 48 is preferably formed of a cobalt film Co, but may be formed of a nickel (Ni) film. The metal film 48 is formed by a sputtering method or a CVD method.

The metal film 48 is a source material film used to form a metal silicide film on the first conductive plug 46a. Therefore, when the metal film 48 is formed, the thickness thereof is preferably considered in consideration of the thickness of the metal silicide film to be formed in a subsequent step. In consideration of these matters, the metal film 48 is preferably formed to a thickness of about 130 kPa.

The surface planarization film 50 may reduce the surface roughness of the metal film 48 in a subsequent silicide process, and is a material film for preventing this. An auxiliary role of the surface planarization layer 50 is to prevent oxygen (O ₂ ) from passing through the metal film 48 and reacting with the first conductive plug 46a in the silicide process. The surface planarization layer 50 may be formed of a titanium nitride layer (TiN). At this time, the surface planarization film 50 is formed to a thickness of about 100Å. The RF cleaning process, the metal film 48 forming process, and the surface planarization film 50 forming process may be performed in-situ. Subsequently, the resultant on which the surface planarization film 50 is formed is heat-treated.

Specifically, the resultant formed with the surface planarization film 50 is preferably heat-treated by a rapid thermal processing (Rapid Thermal Processing) method. That is, it is preferable to perform rapid heat treatment in a nitrogen (N ₂ ) atmosphere term at a temperature of about 400 ° C. to 1,000 ° C., preferably at about 480 ° C. for about 90 seconds. The rapid heat treatment time may vary depending on the thickness of the metal silicide film to be formed. By such rapid heat treatment, the atoms constituting the metal film 50 (if the metal film 50 is a cobalt film, Co) is rapidly diffused into the first conductive plug 46a and its members (eg, silicon ( Si)) and react according to a predetermined ratio. The reaction continues until the rapid heat treatment ends. In the heat treatment process, an upper layer portion of the first conductive plug 46a filling the contact hole 44 is converted into an oxidized metal silicide film. Therefore, the contact hole 44 is filled with the first conductive plug 46a and the metal silicide layer. Thereafter, the surface planarization film 50 and the remaining film of the metal film 48 are wet etched using a mixture of phosphoric acid and nitric acid. And the resultant after the wet etching is rapidly heat treated at about 650 ℃ once again to stabilize the reaction. The rapid heat treatment is carried out in a nitrogen atmosphere, but for about 30 seconds.

Referring to FIG. 8, a first metal silicide plug 52 having oxidation resistance is formed on an upper layer of the first conductive plug 46a by the heat treatment and wet etching. The first metal silicide plug 52 is an ohmic contact layer and is a cobalt silicide (CoSi ₂ ) plug or a nickel silicide (NiSi) plug. In this case, the first metal silicide plug 52 may be formed within a range of 50 kPa to 1,000 kPa, but preferably has a thickness of about 300 kPa to 500 kPa.

9, a first adhesive layer 54 covering the first metal silicide plug 52 and the first conductive plug 46a and the first conductive plug 46a formed on the interlayer insulating layer 42. To form. Subsequently, the first diffusion barrier film 56 and the first conductive metal oxide film 58 are sequentially formed. The first diffusion barrier layer 56 may include the first conductive metal oxide layer 58, a material layer thereon, and the first metal silicide plug 52 formed under the first adhesion layer 54. The plugs 46a and 52 are used as material films to prevent the reactions during the subsequent process. Preferably, the first diffusion barrier 56 is formed of an iridium film Ir. At this time, it is preferable that the first diffusion barrier 56 is formed to a thickness of about 1,000 GPa. The first diffusion barrier 56 may be formed of a ruthenium film Ru.

What should be considered when forming the first diffusion barrier layer 56 is an adhesion characteristic between the first diffusion barrier layer 56 and a material film formed under the first diffusion barrier layer 56. However, when the first diffusion barrier film 56 is formed of an iridium film as described above and the interlayer insulating film 42 is formed of a nitride film or a silicon oxide film, the adhesion property between the iridium film and the nitride film or silicon oxide film is Degrades. Thus, the first adhesion film 54 is formed on the interlayer insulating film 42. The first adhesion layer 54 is preferably formed of a titanium (Ti) film. At this time, the first adhesion film 54 is preferably formed to a thickness of about 50 kPa. The first conductive metal oxide film 58 is preferably formed of an iridium oxide film (IrO ₂ ). At this time, the first conductive metal oxide film 58 is preferably formed to a thickness of about 500 kPa. Further, the iridium oxide film is initially formed in an amorphous state. Therefore, after the first conductive metal oxide film 58 is formed, the resultant is heat treated at about 600 ° C. to crystallize the first conductive metal oxide film 58. The formation thickness of the first conductive metal oxide film 58 may vary depending on the material film. For example, the first conductive metal oxide layer 58 may be formed of a ruthenium oxide layer (RuO ₂ ), a (Ca, Sr) RuO ₃ layer, or a LaSrCoO ₃ layer, in addition to the iridium oxide layer. In this case, the formation thickness or the heat treatment temperature for crystallization may vary depending on the material.

Referring to FIG. 10, a first heat resistant metal layer 60, a first dielectric layer 62, and a first upper electrode 64 are sequentially formed on the first conductive metal oxide layer 58. It is true that the first adhesion layer 54 to the first conductive metal oxide layer 58 together with the first heat resistant metal layer 60 form a lower electrode of the capacitor, but it is actually the lower electrode that acts as the lower electrode. 1 is a heat resistant metal film 60. The first heat resistant metal film 60 is preferably formed of a platinum film Pt, and the thickness thereof is preferably about 1,500 kPa. The first heat resistant metal film 60 may be formed of an iridium film Ir, a ruthenium film Ru, a rhodium film Rh, an osmium film Os or a palladium film Pa other than the platinum film Pt. However, the thickness formed according to the material film may vary. The first dielectric layer 62 may be formed of a conventional dielectric layer, but may be formed of a ferroelectric layer. For example, the first dielectric layer 62 may be formed of a PZT layer. At this time, the PZT film is formed in an amorphous state, and in this case, since leakage current is increased, immediately after the first dielectric film 62 is formed to prevent this, the resultant is in a temperature range of about 650 ° C to 800 ° C. Preferably heat treatment at 700 ℃. The first dielectric layer 62 is formed of TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , SiO ₂ / SiN, BaTiO ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , Bi ₄ Ti ₃ O _{12 in} addition to the PZT film. , PbTiO ₃ , (Pb, La) (Zr, Ti) O ₃ and SBT. At this time, the formation thickness or crystallization temperature may vary depending on the material.

The first heat resistant metal film 60 is a main material film constituting the lower electrode, and the first upper electrode 64 is a metal film or a conductive metal oxide film in a capacitor in which a ferroelectric film is used as the first dielectric film 62. It may be preferable to form the first heat resistant metal film 60 or a composite film thereof. For example, the first upper electrode 64 is formed of a platinum film.

As such, after the capacitor is formed, it is preferable to heat-treat the resultant at a temperature range of about 450 ° C. to 600 ° C., which can stabilize the capacitor and recover damage caused by etching after the capacitor is formed. You can. Heat treatment for this purpose is carried out in an oxygen atmosphere.

As described above, after forming the first conductive metal oxide film 58, the first dielectric film 62, and the like, for crystallization thereof, and after the formation of the capacitor, damage recovery and stabilization are performed at 600 ° C., respectively. A heat treatment process is performed between 700 ° C., wherein the first metal silicide plug 52, in particular cobalt silicide plug, exhibits sheet resistance that is thermally stable up to 900 ° C. FIG. Therefore, the resistance state of the first metal silicide plug 52 does not change due to the heat treatment performed in the capacitor manufacturing process. That is, the resistance does not increase.

Second Embodiment

The capacitor manufacturing method according to the second embodiment is characterized in that the entirety of the conductive plugs (46a and 52 of FIG. 10) is formed of a metal silicide plug in the first embodiment.

Specifically, as shown in FIG. 7, the process of forming the metal film 48 and the surface planarization film 50 covering the first conductive plug 46a on the interlayer insulating film 42 is performed according to the first embodiment. Proceed with the process. Subsequently, the first conductive plug 46a is completely reacted in the heat treatment process of the first embodiment for forming the silicide film. In other words, the entire first conductive plug 46a becomes a metal silicide film. Therefore, it is preferable that the metal film 48 be formed thicker than when formed in the first embodiment. In other words, it is preferable that the metal film 48 is formed to have a thickness of 130 GPa or more so that the metal film 48 remains after the heat treatment process is completed.

Subsequently, the process of removing the surface planarization film 50 and the metal film 48 is performed according to the first embodiment. As a result, as shown in FIG. 11, the contact hole 44 is filled with the second metal silicide plug 66. The second metal silicide plug 66 may be formed of a cobalt silicide plug or a nickel silicide plug.

Subsequently, as shown in FIG. 3, the second adhesion film 68, the second diffusion barrier film 70, and the second conductive metal covering the second metal silicide plug 66 on the interlayer insulating film 42. The oxide film 72, the second heat resistant metal film 74, the second dielectric film 76, and the second upper electrode 78 are sequentially formed. The second adhesion film 68 to the second upper electrode 78 are the same as when forming the first adhesion film 54 (FIG. 10) to the first upper electrode 64 (FIG. 10) of the first embodiment. Form by process.

Third Embodiment

The capacitor manufacturing method according to the third embodiment is characterized in that the silicide film is excluded from the conductive plug filling the contact hole, and the adhesion layer is formed of the same material film as the conductive plug filling the contact hole.

Specifically, referring to FIG. 12, the second conductive plug 46b is filled in the contact hole 44 according to the first embodiment.

Referring to FIG. 13, instead of converting an upper portion of the second conductive plug 46b into a metal silicide film as in the first embodiment, a second covering the second conductive plug 46b on the interlayer insulating film 44. The conductive film 80 is formed. The entire surface of the second conductive film 80 is planarized within the range in which the interlayer insulating film 42 is not exposed. The second conductive film 80 is preferably formed of a doped polysilicon film. At this time, an oxide film such as a natural oxide film may be formed on the surface thereof. The oxide film thus produced is subjected to RF cleaning after pre-cleaning the entire surface of the second conductive film 80 using a wet cleaning device, according to the first embodiment. Thereafter, a first metal silicide layer 82, a third diffusion barrier layer 84, and a third conductive metal oxide layer 86 are sequentially formed on the second conductive layer 80. The first metal silicide layer 80 is preferably formed of a cobalt silicide layer or a nickel silicide layer. The thickness of the first metal silicide layer 80 is about 50 kPa to about 1,000 kPa, and is preferably about 300 kPa to about 500 kPa.

Specifically, the first metal silicide layer 80 sequentially forms a metal layer and a surface planarization layer on the entire surface of the second conductive layer 80, heats the resultant material, and sequentially processes the surface planarization layer and the metal layer. It is formed by removing. The series of processes for forming the first metal silicide layer 80 follows the process of forming the first metal silicide plug 52 of the first embodiment.

The third diffusion barrier 84 and the third conductive metal oxide layer 86 respectively form the first diffusion barrier layer 56 (FIG. 2) and the first conductive metal oxide layer 58 (FIG. 2) of the first embodiment. It is preferable to form the same material film under the same process conditions as when used.

4, the third heat resistant metal film 88, the third dielectric film 90, and the third upper electrode 92 are sequentially formed on the third conductive metal oxide film 86. These films are preferably formed of the same material film under the same process conditions as those of the first heat resistant metal film (60 in FIG. 2) to the first upper electrode (64 in FIG. 2) of the first embodiment.

On the other hand, the second conductive plug 46b and the second conductive film 80 may be simultaneously formed as follows.

That is, by forming a conductive film (not shown) filling the contact hole 44 on the interlayer insulating film 42, and then planarizing the entire surface of the insulating film 42, the planarizing film is planarized within a range where the interlayer insulating film 42 is not exposed. A planarized conductive film having a predetermined thickness may be formed on the interlayer insulating layer 42 by filling the contact hole 44.

Fourth Example

As in the third embodiment, the silicide film is excluded from the conductive plug filling the contact hole, and the adhesion layer is formed of the same material film as the conductive plug filling the contact hole, and a metal silicide film is used instead of the heat resistant metal film as the substantially lower electrode. It is done.

Referring to FIG. 14, a third conductive film 94 covering the second conductive plug 46b is formed on the interlayer insulating film 42 according to the third embodiment. The entire surface of the third conductive film 94 is planarized within the range in which the interlayer insulating film 42 is not exposed. The second conductive plug 46b and the third conductive film 94 may be formed at the same time as mentioned in the third embodiment. The oxide film formed on the entire surface of the third conductive film 94 is removed according to the first embodiment or the third embodiment.

Referring to FIG. 15, a second metal silicide layer 96, a fourth dielectric layer 98, and a fourth upper electrode 100 are sequentially formed on the third conductive layer 94. The second metal silicide layer 96 is formed of a cobalt silicide layer or a nickel silicide layer. The second metal silicide film 96 is formed according to the method of forming the first metal silicide plug 52 of the first embodiment or the first metal silicide film (82 of FIG. 13) of the third embodiment. However, since the second metal silicide layer 96 is used as a substantially lower electrode, unlike the first metal silicide layer 82, the second metal silicide layer 96 may be formed to have a thickness in consideration of the capacitance of the capacitor. Therefore, it is preferable to form thicker than the first metal silicide layer 82. For example, the second metal silicide film 96 is preferably formed to a thickness of about 500 kPa to about 3,000 kPa. The fourth dielectric layer 98 is formed of a ferroelectric layer, but preferably formed of the same material layer as the first dielectric layer 62 of FIG. 2. Since the fourth dielectric layer 98 is formed of a ferroelectric layer, the fourth upper electrode 100 may be formed of a heat resistant metal layer including platinum, similar to the first to third upper electrodes of the first to third embodiments. In the case of the fourth exemplary embodiment, since the substantially lower electrode is formed of the second metal silicide layer 96, the fourth upper electrode 100 may be the same metal silicide as the second metal silicide layer 96. It can also be formed into a film.

Fifth Embodiment

The fifth embodiment is characterized in that in the capacitor manufacturing method according to the third embodiment, the second conductive film 80 is replaced with a metal silicide film. Accordingly, a single film formed of a metal silicide film is formed between the third diffusion barrier layer 84 and the interlayer insulating layer 42 including the second conductive plug 46b. At this time, the metal silicide film is not formed by a heat treatment method, but is formed directly by sputtering or CVD. In this case, the metal silicide film is formed to a thickness of about 50 kPa to 1,000 kPa. The subsequent process is according to the third embodiment. Therefore, in the fifth embodiment, the lower electrode is composed of a metal silicide film formed by a direct method, a diffusion barrier film, a conductive metal oxide film, and a heat resistant metal film sequentially formed thereon.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art to which the present invention pertains may form a heat treatment method in forming the first or second metal silicide plugs 52 and 66 or the first or second metal silicide films 82 and 96. Instead, the silicide film may be formed directly inside the contact hole or on the conductive film by CVD or sputtering using a source gas constituting the silicide film. In addition, the invention may be implemented in combination with the first to fourth embodiments of the present invention, and the technical idea including the matters described in the first to fourth embodiments is not a contact between the lower electrode and the conductive plug. Apparently, it is also applicable to other contacts, such as bit line contacts or contacts for interconnection between cells. In the capacitor manufacturing method according to the third and fourth embodiments, the second conductive film 80 or the third conductive film 94 may be formed at the same time as the first conductive plug 46a. That is, the conductive film filling the contact hole 44 is formed on the interlayer insulating film 42, and then the entire surface thereof is flattened, but planarized in a range where the interlayer insulating film 42 is not exposed. In this way, the second conductive film 80 or the third conductive film 94 covering the first conductive plug 46a together with the first conductive plug 46a filling the contact hole 44 is formed in the interlayer insulating film ( 42). As such, the scope of the present invention should not be defined by the above-described embodiments, but should be determined by the technical spirit described in the claims.

Referring to the first embodiment, a diffusion path of oxygen (O ₂ ) toward the conductive plug is formed by forming an oxidized metal silicide film such as a cobalt silicide film on the conductive plug in contact with the lower electrode of the capacitor. Is increased. Thus, in a subsequent process including the lower electrode, formation of a material film, such as SiO ₂ , which increases the contact resistance between the conductive plug and the lower electrode is prevented.

Referring to the second embodiment, the conductive plug itself is formed of a metal silicide film. Therefore, oxygen becomes difficult to diffuse downward by the height of the conductive plug. Therefore, the setting margin can be increased in setting the process conditions of the subsequent process, for example, the amount of oxygen gas injected into the chamber.

Referring to the third embodiment, since the adhesion film is replaced with a material film having the same material as the conductive plug forming material, it is possible to provide a lower electrode more stable in terms of contact resistance.

Referring to the fourth embodiment, the lower electrode is simplified compared to the first to third embodiments by providing a lower electrode more stable than the first and second embodiments and using the metal silicide film itself as the lower electrode. Provide a process.

Claims (20)

A capacitor of a semiconductor device connected to a substrate with an interlayer insulating film therebetween and having a ferroelectric film, A contact hole exposing the substrate is formed in the interlayer insulating film, The contact hole is filled with a conductive plug connected to the lower electrode of the capacitor, And at least an upper layer portion of the conductive plug is a metal silicide film. delete The capacitor of claim 1, wherein the conductive plug is entirely the metal silicide film. 4. The capacitor of claim 3, wherein the lower electrode comprises an adhesion film in contact with the metal silicide film, a diffusion barrier film sequentially formed on the adhesion film, a conductive metal oxide film, and a heat resistant metal film. The capacitor of claim 1, wherein the metal silicide film is a cobalt silicide film or a nickel silicide film. According to claim 1, wherein the ferroelectric film is TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , SiO ₂ / SiN, BaTiO ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , Bi ₄ Ti ₃ O ₁₂ , PbTiO ₃ And PZT, (Pb, La) (Zr, Ti) O ₃ and a crowd selected capacitor consisting of SBT. 5. The capacitor of claim 4, wherein the adhesion film and the diffusion barrier film are a titanium film (Ti) and an iridium film (Ir), respectively. 5. The capacitor of claim 4, wherein the conductive metal oxide film is a ruthenium oxide film (RuO ₂ ), an iridium oxide film (IrO ₂ ), a (Ca, Sr) RuO ₃ film, or a LaSrCoO ₃ film. The method of claim 4, wherein the heat-resistant metal film is a platinum film (Pt), iridium film (Ir), ruthenium film (Ru), rhodium film (Rh), osmium film (Os) or palladium film (Pa) Capacitors in semiconductor devices. A capacitor of a semiconductor device connected to a substrate with an interlayer insulating film therebetween and having a ferroelectric film, A contact hole through which the substrate is exposed is formed in the interlayer insulating layer, and the contact hole is filled with a conductive plug in contact with the lower electrode of the capacitor, The lower electrode is a capacitor of a semiconductor device, characterized in that consisting of a metal silicide film and a conductive film sequentially stacked. A capacitor of a semiconductor device connected to a substrate with an interlayer insulating film therebetween and having a ferroelectric film, And the lower electrode of the capacitor is a metal silicide layer. A semiconductor device comprising a substrate, an interlayer insulating film having a contact hole formed on the substrate, a conductive plug filling the contact hole, and a lower electrode, a ferroelectric film, and an upper electrode sequentially on the interlayer insulating film including the conductive plug. In the capacitor manufacturing method, And forming a part or all of at least one of the conductive plug and the lower electrode into an oxidizing metal silicide film. 13. The method of claim 12, further comprising converting the top or the entirety of the conductive plug into the oxidizing metal silicide film. The method of claim 13, wherein converting an upper portion of the conductive plug into the oxidizing metal silicide layer is performed. (a) forming a metal film covering the conductive plug on the interlayer insulating film and forming a metal film having excellent downward diffusion toward the conductive plug in a subsequent heat treatment process; (b) forming a surface planarization film on the metal film; (c) heat-treating the resultant on which the surface planarization film is formed to form an oxidation resistant metal silicide film in a region in contact with the metal film of the conductive plug; (d) removing the surface planarization film and the metal film; And (e) stabilizing a resultant from which the surface planarization film and the metal film have been removed. The method of claim 12, wherein the oxidizing metal silicide layer is formed of a cobalt silicide layer or a nickel silicide layer. The method of claim 12, further comprising forming the lower electrode as an oxidizing metal silicide layer. The method of claim 16, wherein the forming of the lower electrode as an oxidizing metal silicide layer comprises: Forming a conductive film covering the conductive plug on the interlayer insulating film; Forming a metal film on the conductive film covering the conductive film plug; Forming a surface planarization film on the metal film; Heat-treating the resultant on which the surface planarization film is formed to form an oxidized metal silicide film between the conductive film covering the conductive plug and the metal film; And And removing the surface planarization film and the metal film. 18. The method of claim 17, wherein before forming the metal film, Planarizing the entire surface of the conductive film covering the conductive plug, and then precleaning the entire surface of the conductive film; And And removing the oxide film from the entire surface of the conductive film covering the conductive plug by in-situ induction power (RF) cleaning. The ferroelectric film of claim 12, wherein the ferroelectric film is formed of TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , SiO ₂ / SiN, BaTiO ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , Bi ₄ Ti ₃ O ₁₂ , PbTiO ₃ And PZT, (Pb, La) (Zr, Ti) O ₃ and SBT. 13. The method of claim 12, further comprising forming the oxidized metal silicide film in contact with the conductive plug between the lower electrode and the interlayer insulating film.

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