KR19990018070A - Capacitor of semiconductor memory device and manufacturing method thereof - Google Patents
Capacitor of semiconductor memory device and manufacturing method thereof Download PDFInfo
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- KR19990018070A KR19990018070A KR1019970041163A KR19970041163A KR19990018070A KR 19990018070 A KR19990018070 A KR 19990018070A KR 1019970041163 A KR1019970041163 A KR 1019970041163A KR 19970041163 A KR19970041163 A KR 19970041163A KR 19990018070 A KR19990018070 A KR 19990018070A
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- interlayer insulating
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- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 34
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 229910008484 TiSi Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 5
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 5
- 229910052741 iridium Inorganic materials 0.000 claims description 5
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052707 ruthenium Inorganic materials 0.000 claims description 5
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 claims 2
- 239000010408 film Substances 0.000 description 120
- 238000010438 heat treatment Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- -1 tungsten nitride Chemical class 0.000 description 4
- 229910000457 iridium oxide Inorganic materials 0.000 description 3
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
고유전막을 이용하여 공정이 단순화된 반도체 메모리장치의 캐패시터 및 그 제조방법에 대해 개시되어 있다. 이 캐패시터는, 반도체기판과 접속된 하부전극과, 하부전극을 덮으며 탄탈륨 산화막과 같은 고유전막으로 이루어진 유전체막과, 유전체막 상에 형성되며 금속막으로 이루어진 상부전극, 및 상부전극이 형성된 결과물을 덮으며, 저온에서 열처리가 가능한 절연막으로 이루어진 층간절연막으로 구성된다.Disclosed are a capacitor of a semiconductor memory device and a method of manufacturing the same. The capacitor includes a lower electrode connected to the semiconductor substrate, a dielectric film covering the lower electrode and comprising a high dielectric film such as a tantalum oxide film, an upper electrode formed on the dielectric film and formed of a metal film, and a resultant on which the upper electrode is formed. And an interlayer insulating film made of an insulating film that can be heat treated at a low temperature.
Description
본 발명은 반도체 메모리장치 및 그 제조방법에 관한 것으로, 특히 고유전막을 이용한 캐패시터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a capacitor using a high dielectric film and a manufacturing method thereof.
최근, 메모리소자, 특히 디램(DRAM)의 집적화에 따라 단위 셀(cell) 당 차지하는 면적이 감소하고 메모리의 기본소자중 하나인 캐패시터가 차지할 수 있는 면적도 감소한다. 특히, 256M 디램(DRAM)과 같이 디자인 룰(design rule)이 0.25㎛ 이하이고 게이트라인의 피치 사이즈(pitch size)가 0.4㎛ 이하인 초고집적 소자의 경우, 단위 셀당 25fF 이상을 확보해야 하는 요구에 의해 부족한 캐패시턴스를 증가시킬 수 있는 방법을 필수적으로 개발하여야 한다. 그 일환으로, 캐패시터의 유전막을 기존의 산화막이나 질화막 대신에 유전율이 큰 탄탈륨산화막으로 대체하는 연구가 이루어지고 있다.Recently, with the integration of memory devices, particularly DRAM, the area occupied per unit cell is reduced and the area occupied by a capacitor, which is one of the basic elements of the memory, is also reduced. In particular, in the case of ultra-high density devices having a design rule of 0.25 μm or less and a gate line pitch size of 0.4 μm or less, such as 256M DRAM, the requirement to secure 25 fF or more per unit cell is required. It is essential to develop a way to increase the insufficient capacitance. As a part of this, research is being made to replace the dielectric film of the capacitor with a tantalum oxide film having a high dielectric constant instead of the existing oxide film or nitride film.
탄탈륨 산화막을 캐패시터의 유전막으로 사용할 경우 그 상부전극으로는 금속물질을 사용하여야 한다. 통상적인 DRAM에 있어서 캐패시터의 상부전극으로 폴리실리콘이 사용되는데, 탄탈륨산화막을 유전막으로 사용하고 상부전극물질로 폴리실리콘을 사용할 경우, 탄탈륨산화막과 폴리실리콘이 접촉하면 실리콘과 탄탈륨산화막 속의 산소(O2)가 반응하여 그 계면에 실리콘산화막(SiO2)이 형성된다. 이로 인해 전체적인 유효산화막의 두께가 증가되어 캐패시턴스가 감소하고, 탄탈륨산화막 내의 산소가 감소되어 누설전류가 증가된다. 따라서, 기존의 탄탈륨산화막을 유전막으로 하는 캐패시터에서는 티타늄 질화막(TiN)과 같은 금속막을 탄탈륨산화막과 접촉하도록 형성한다.When tantalum oxide is used as the dielectric film of the capacitor, a metal material should be used as the upper electrode. In conventional DRAM, polysilicon is used as the upper electrode of the capacitor. When a tantalum oxide film is used as the dielectric film and polysilicon is used as the upper electrode material, oxygen in the silicon and the tantalum oxide film (O 2) is in contact with the tantalum oxide film and the polysilicon. ) Reacts to form a silicon oxide film (SiO 2 ) at its interface. As a result, the thickness of the entire effective oxide film is increased to decrease the capacitance, and the oxygen in the tantalum oxide film is reduced to increase the leakage current. Therefore, in a capacitor having a conventional tantalum oxide film as a dielectric film, a metal film such as a titanium nitride film (TiN) is formed in contact with the tantalum oxide film.
도 1 내지 도 4를 참조하여 종래의 고유전막을 이용한 캐패시터의 제조방법을 설명한다.A method of manufacturing a capacitor using a conventional high dielectric film will be described with reference to FIGS. 1 to 4.
도 1을 참조하면, 트랜지스터(도시되지 않음) 등과 같은 하부 구조물이 형성된 반도체기판(10) 상에, 예를 들어 산화막과 같은 절연막을 이용하여 층간절연막(12)을 형성하고, 이 층간절연막(12)을 식각하여 반도체기판의 일부를 노출시키는 콘택홀을 형성한다. 결과물 상에, 예를 들어 도우프된 폴리실리콘막을 증착한 후, 이를 패터닝하여 캐패시터의 하부전극(14)을 형성한다.Referring to FIG. 1, an interlayer insulating film 12 is formed on a semiconductor substrate 10 on which a lower structure such as a transistor (not shown) is formed, for example, using an insulating film such as an oxide film, and the interlayer insulating film 12 is formed. ) Is etched to form a contact hole exposing a portion of the semiconductor substrate. On the resultant, for example, a doped polysilicon film is deposited and then patterned to form the lower electrode 14 of the capacitor.
도 2를 참조하면, 캐패시터의 하부전극(14)이 형성된 결과물의 전면에, 탄탈륨산화막(16)과 같은 고유전막을 증착하여 캐패시터의 유전막을 형성한다.Referring to FIG. 2, a dielectric film of a capacitor is formed by depositing a high-k dielectric film such as tantalum oxide film 16 on the entire surface of the resultant in which the lower electrode 14 of the capacitor is formed.
도 3을 참조하면, 탄탈륨산화막(16)이 형성된 결과물의 전면에, 예를 들어 티타늄 질화막(TiN)과 같은 금속막(18)을 형성한 다음, 불순물이 도우프된 폴리실리콘막(20)을 증착하여 이중 상부전극을 형성한다.Referring to FIG. 3, a metal film 18 such as, for example, titanium nitride (TiN) is formed on the entire surface of the resultant in which the tantalum oxide film 16 is formed, and then the polysilicon film 20 doped with impurities is formed. Deposition to form a double upper electrode.
도 4를 참조하면, 결과물상에 절연막을 증착하여 상기 캐패시터의 상부전극과 이후에 형성된 배선층을 절연시키기 위한 층간절연막(22)을 형성한 후 열처리를 실시한다.Referring to FIG. 4, an insulating film is deposited on the resultant to form an interlayer insulating film 22 to insulate the upper electrode of the capacitor and the wiring layer formed thereafter, followed by heat treatment.
상기한 이중 상부전극 대신에 TiN 등의 금속막만을 형성할 수도 있는데, 이럴 경우 층간절연막을 증착한 후 열처리하는 공정에 의해 금속전극의 열팽창으로 인한 스트레스가 발생하고, 이로 인해 유전막의 열화가 일어난다. 도 3에 도시된 것처럼 금속막과 폴리실리콘막의 이중막을 사용하면 탄탈륨산화막과의 반응도 억제하고, 폴리실리콘막의 완충작용으로 인해 열적 스트레스도 감소시킬 수 있다. 그러나, 금속막 증착공정이 추가되는 단점이 있다.Instead of the double upper electrode, only a metal film such as TiN may be formed. In this case, a stress due to thermal expansion of the metal electrode is generated by a process of depositing an interlayer insulating film and then performing a heat treatment, thereby causing deterioration of the dielectric film. As shown in FIG. 3, when the double film of the metal film and the polysilicon film is used, the reaction with the tantalum oxide film may be suppressed, and thermal stress may be reduced due to the buffering action of the polysilicon film. However, there is a disadvantage in that a metal film deposition process is added.
만일, 탄탈륨산화막 유전막을 형성하고 이후 층간절연막 증착 후 실시하는 열처리를 저온에서 진행하는 것이 가능하다면, 열적 스트레스의 요인이 감소하여 폴리실리콘막을 형성할 필요가 없어진다. 즉, 단일 금속막을 형성한 후 저온 열처리가 가능한 층간절연막을 형성할 경우 TiN과 같은 단일 금속막으로 상부전극을 형성할 수 있으므로, 공정을 단순화할 수 있다.If it is possible to form a tantalum oxide dielectric film and then perform a heat treatment performed after the interlayer dielectric film deposition at a low temperature, the factor of thermal stress is reduced, and there is no need to form a polysilicon film. That is, when the interlayer insulating film capable of low-temperature heat treatment after forming a single metal film is formed, the upper electrode can be formed of a single metal film such as TiN, thereby simplifying the process.
따라서, 본 발명이 이루고자 하는 기술적 과제는, 캐패시터 형성후 저온열처리가 가능한 층간절연막을 형성함으로써 단일 금속막으로 이루어진 상부전극을 구비하는 반도체 메모리장치의 캐패시터를 제공하는 것이다.Accordingly, an object of the present invention is to provide a capacitor of a semiconductor memory device having an upper electrode made of a single metal film by forming an interlayer insulating film capable of low-temperature heat treatment after forming the capacitor.
본 발명이 이루고자 하는 다른 기술적 과제는, 단일 금속막으로 이루어진 상부전극을 구비하는 캐패시터의 적합한 제조방법을 제공하는 것이다.Another technical problem to be solved by the present invention is to provide a suitable manufacturing method of a capacitor having an upper electrode made of a single metal film.
도 1 내지 도 4는 종래의 고유전막을 이용한 캐패시터의 제조방법을 나타내는 단면도들이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a capacitor using a conventional high dielectric film.
도 5 내지 도 7은 본 발명에 의한 고유전막을 이용한 캐패시터의 제조방법을 나타내는 단면도들이다.5 to 7 are cross-sectional views illustrating a method of manufacturing a capacitor using a high dielectric film according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10, 50....반도체기판 12, 22, 52, 60....층간절연막10, 50 ... semiconductor substrates 12, 22, 52, 60 ...
14, 54....하부전극 16, 56....유전체막14, 54 ... lower electrode 16, 56 ... dielectric film
18, 20, 58....상부전극18, 20, 58 .... Upper electrode
상기 과제를 이루기 위하여 본 발명에 의한 반도체 메모리장치의 캐패시터는, 반도체기판과 접속된 하부전극과, 상기 하부전극을 덮는 유전체막과, 상기 유전체막 상에, 금속막으로 이루어진 상부전극, 및 상기 상부전극이 형성된 결과물을 덮는 층간절연막을 구비하는 것을 특징으로 한다.In order to achieve the above object, a capacitor of a semiconductor memory device according to the present invention includes a lower electrode connected to a semiconductor substrate, a dielectric film covering the lower electrode, an upper electrode made of a metal film on the dielectric film, and the upper part. And an interlayer insulating film covering the resultant electrode formed thereon.
상기 하부전극은 폴리실리콘으로 이루어지고, 상기 유전체막은 탄탈륨 산화막으로 이루어진 것이 바람직하다.Preferably, the lower electrode is made of polysilicon, and the dielectric film is made of tantalum oxide film.
상기 상부전극은 티타늄(Ti), 티타늄 질화막(TiN), 티타늄 실리사이드(TiSix), 텅스텐(W), 텅스텐 질화막(WN), 텅스텐 실리사이드(WSix), 알루미늄(Al), 백금(Pt), 이리듐(Ir), 이리듐 산화막(IrO2), 루테늄(Ru), 루테늄 산화막(RuO2), 몰리브덴(Mo), 및 몰리브덴 질화막(MoN)으로 이루어진 그룹에서 선택된 어느 하나로 구성되고, 그 두께는 50Å∼5,000Å 정도이다.The upper electrode includes titanium (Ti), titanium nitride film (TiN), titanium silicide (TiSi x ), tungsten (W), tungsten nitride film (WN), tungsten silicide (WSi x ), aluminum (Al), platinum (Pt), It is composed of any one selected from the group consisting of iridium (Ir), iridium oxide film (IrO 2 ), ruthenium (Ru), ruthenium oxide film (RuO 2 ), molybdenum (Mo), and molybdenum nitride film (MoN). It is about 5,000Å.
상기 층간절연막은 저온에서 열처리가 가능한 물질로서, TEOS 산화막, 플라즈마 산화막 및 실리콘 질화막(SiN)으로 이루어진 그룹에서 선택된 어느 하나로 이루어지고, 그 두께는 100Å ∼ 10,000Å 정도이다.The interlayer insulating film is a material which can be heat-treated at a low temperature, and is made of any one selected from the group consisting of a TEOS oxide film, a plasma oxide film, and a silicon nitride film (SiN), and has a thickness of about 100 kPa to about 10,000 kPa.
상기 다른 과제를 이루기 위하여 본 발명에 의한 캐패시터의 제조방법은, 반도체기판 상에 형성된 층간절연막을 식각하여 상기 반도체기판의 일부를 노출시키는 콘택홀을 형성하는 단계와, 상기 층간절연막 상에, 상기 반도체기판과 접속된 하부전극을 형성하는 단계와, 하부전극이 형성된 결과물의 전면에 유전체막을 형성하는 단계와, 상기 유전체막 상에 금속막으로 이루어진 상부전극을 형성하는 단계; 및 상부전극이 형성된 결과물의 전면에 층간절연막을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor, the method including: forming a contact hole exposing a portion of the semiconductor substrate by etching an interlayer insulating layer formed on the semiconductor substrate; Forming a lower electrode connected to the substrate, forming a dielectric film on the entire surface of the resultant on which the lower electrode is formed, and forming an upper electrode formed of a metal film on the dielectric film; And forming an interlayer insulating film on the entire surface of the resultant product on which the upper electrode is formed.
상기 하부전극은 폴리실리콘으로 형성하고, 상기 유전체막은 탄탈륨 산화막으로 형성하는 것이 바람직하다.Preferably, the lower electrode is formed of polysilicon and the dielectric film is formed of a tantalum oxide film.
상기 상부전극은 티타늄(Ti), 티타늄 질화막(TiN), 티타늄 실리사이드(TiSix), 텅스텐(W), 텅스텐 질화막(WN), 텅스텐 실리사이드(WSix), 알루미늄(Al), 백금(Pt), 이리듐(Ir), 이리듐 산화막(IrO2), 루테늄(Ru), 루테늄 산화막(RuO2), 몰리브덴(Mo), 및 몰리브덴 질화막(MoN)으로 이루어진 그룹에서 선택된 어느 하나로 형성하며, 그 두께는 50Å∼5,000Å 정도로 형성한다.The upper electrode includes titanium (Ti), titanium nitride film (TiN), titanium silicide (TiSi x ), tungsten (W), tungsten nitride film (WN), tungsten silicide (WSi x ), aluminum (Al), platinum (Pt), It is formed of any one selected from the group consisting of iridium (Ir), iridium oxide film (IrO 2 ), ruthenium (Ru), ruthenium oxide film (RuO 2 ), molybdenum (Mo), and molybdenum nitride film (MoN). Form around 5,000Å.
상기 층간절연막은 저온에서 열처리가 가능한 물질로서, 예를 들어 TEOS 산화막, 플라즈마 산화막 및 실리콘 질화막(SiN)으로 이루어진 그룹에서 선택된 어느 하나로, 100Å∼10,000Å 정도의 두께로 형성하는 것이 바람직하다.The interlayer insulating film is a material that can be heat-treated at a low temperature, and is formed of, for example, one selected from the group consisting of a TEOS oxide film, a plasma oxide film, and a silicon nitride film (SiN).
그리고, 상기 층간절연막을 형성하는 단계후에 상기 층간절연막이 형성된 반도체기판을 400℃∼800℃ 정도의 저온에서 열처리하는 단계를 더 구비하는 것이 바람직하다.After the step of forming the interlayer dielectric layer, the semiconductor substrate on which the interlayer dielectric layer is formed is preferably further heat treated at a low temperature of about 400 ° C to 800 ° C.
본 발명에 따르면, 층간절연막으로 저온에서 열처리가 가능한 절연막을 형성함으로써 단일 금속막으로 상부전극을 형성할 수 있으므로, 공정을 단순화할 수 있으며, 유전체막이 열화되는 것을 방지할 수 있어서 소자의 신뢰성을 향상시킬 수 있다.According to the present invention, since the upper electrode can be formed of a single metal film by forming an insulating film that can be heat-treated at a low temperature as the interlayer insulating film, the process can be simplified and the dielectric film can be prevented from deteriorating, thereby improving the reliability of the device. You can.
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도 5 내지 도 7은 본 발명에 의한 캐패시터의 제조방법을 설명하기 위한 단면도들이다.5 to 7 are cross-sectional views illustrating a method of manufacturing a capacitor according to the present invention.
도 5를 참조하면, 트랜지스터(도시되지 않음) 등과 같은 하부 구조물이 형성된 반도체기판(50) 상에, 예를 들어 산화막과 같은 절연막을 이용하여 층간절연막(52)을 형성하고, 상기 층간절연막(52)을 식각하여 반도체기판의 일부를 노출시키는 콘택홀을 형성한다. 결과물 상에, 예를 들어 도우프된 폴리실리콘막을 증착한 후, 이를 패터닝하여 상기 반도체기판과 접속된 캐패시터의 하부전극(54)을 형성한다.Referring to FIG. 5, an interlayer insulating film 52 is formed on a semiconductor substrate 50 on which a lower structure such as a transistor (not shown) is formed, using an insulating film, for example, an oxide film, and the interlayer insulating film 52. ) Is etched to form a contact hole exposing a portion of the semiconductor substrate. For example, a doped polysilicon film is deposited on the resultant, and then patterned to form a lower electrode 54 of a capacitor connected to the semiconductor substrate.
도 6을 참조하면, 캐패시터의 하부전극(54)이 형성된 결과물의 전면에 탄탈륨산화막(56)과 같은 고유전막을 증착하여 캐패시터의 유전막을 형성한다.Referring to FIG. 6, a dielectric film of a capacitor is formed by depositing a high-k dielectric film such as a tantalum oxide film 56 on the entire surface of the result in which the lower electrode 54 of the capacitor is formed.
도 7을 참조하면, 탄탈륨산화막(56)이 형성된 결과물의 전면에 금속막을 50Å∼5,000Å 정도 증착하여 캐패시터의 상부전극(58)을 형성한다. 상기 캐패시터의 상부전극(58)을 형성하기 위한 금속막은 상기 유전막으로 사용되는 탄탈륨산화막(56)과 반응을 일으키지 않는 금속, 예를 들어 티타늄(Ti), 티타늄 질화막(TiN), 티타늄 실리사이드(TiSix), 텅스텐(W), 텅스텐 질화막(WN), 텅스텐 실리사이드(WSix), 알루미늄(Al), 백금(Pt), 이리듐(Ir), 이리듐 산화막(IrO2), 루테늄(Ru), 루테늄 산화막(RuO2), 몰리브덴(Mo), 및 몰리브덴 질화막(MoN)으로 이루어진 그룹에서 선택된 어느 하나로 형성한다.Referring to FIG. 7, the upper electrode 58 of the capacitor is formed by depositing a metal film on the entire surface of the resultant on which the tantalum oxide film 56 is formed. The metal film for forming the upper electrode 58 of the capacitor is a metal that does not react with the tantalum oxide film 56 used as the dielectric film, for example, titanium (Ti), titanium nitride (TiN), and titanium silicide (TiSi x ), Tungsten (W), tungsten nitride film (WN), tungsten silicide (WSi x ), aluminum (Al), platinum (Pt), iridium (Ir), iridium oxide film (IrO 2 ), ruthenium (Ru), ruthenium oxide film ( RuO 2 ), molybdenum (Mo), and molybdenum nitride film (MoN).
다음에, 상기 캐패시터의 상부전극(58)과 이후에 형성될 배선층과의 절연을 위하여 결과물상에 절연막을 증착하여 층간절연막(60)을 형성한 후, 열처리를 실시한다. 이 때, 상기 층간절연막(60)은 저온에서 열처리가 가능한 물질로서, 예를 들어 TEOS 산화막, 플라즈마 산화막 또는 실리콘 질화막(SiN) 등을 사용하여 100Å ∼10,000Å 정도의 두께로 형성한다. 그리고, 상기 층간절연막(60) 형성후 실시되는 열처리는 400℃∼800℃ 정도의 저온에서 이루어지는 것이 바람직하다.Next, to insulate the upper electrode 58 of the capacitor from the wiring layer to be formed later, an insulating film is deposited on the resultant to form an interlayer insulating film 60, and then heat treatment is performed. At this time, the interlayer insulating film 60 is a material which can be heat-treated at a low temperature, and is formed to a thickness of about 100 kPa to about 10,000 kPa using, for example, a TEOS oxide film, a plasma oxide film, or a silicon nitride film (SiN). The heat treatment performed after the interlayer insulating film 60 is preferably performed at a low temperature of about 400 ° C to 800 ° C.
이상 본 발명을 상세히 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며 본 발명이 속하는 기술적 사상내에서 당분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 물론이다.Although the present invention has been described in detail above, the present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.
상술한 본 발명에 의한 반도체 메모리장치의 캐패시터 및 그 제조방법에 따르면, 탄탈륨 산화막과 같은 고유전막을 유전체막으로 사용하는 캐패시터에 있어서 상부전극과 배선층의 절연을 위한 층간절연막으로 저온에서 열처리가 가능한 절연막을 형성함으로써 단일 금속막으로 상부전극을 형성할 수 있으므로, 공정을 단순화할 수 있다. 또한, 종래에 폴리실리콘막을 사용하던 방법에 비해 폴리실리콘과 유전체막의 반응에 의해 유전체막이 열화되는 것을 방지할 수 있어서, 소자의 신뢰성을 향상시킬 수 있다.According to the above-described capacitor of a semiconductor memory device according to the present invention and a method of manufacturing the same, an insulating film that can be heat-treated at a low temperature as an interlayer insulating film for insulating the upper electrode and the wiring layer in a capacitor using a high dielectric film such as a tantalum oxide film as a dielectric film. Since the upper electrode can be formed of a single metal film by forming a thin film, the process can be simplified. In addition, the dielectric film can be prevented from deteriorating due to the reaction between the polysilicon and the dielectric film, compared to the conventional method of using the polysilicon film, thereby improving the reliability of the device.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100451501B1 (en) * | 1998-12-30 | 2004-12-31 | 주식회사 하이닉스반도체 | Capacitor Formation Method of Semiconductor Memory Device |
| KR100480574B1 (en) * | 1997-11-27 | 2005-05-16 | 삼성전자주식회사 | Method for forming metal line interconnection in semiconductor device and method for forming apacitor using the same |
| KR100795683B1 (en) * | 2002-04-19 | 2008-01-21 | 매그나칩 반도체 유한회사 | Method of manufacturing a capacitor in semiconductor device |
| KR100801314B1 (en) * | 2002-06-29 | 2008-02-05 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
| KR100818768B1 (en) * | 2002-02-20 | 2008-04-01 | 주식회사 케이씨씨 | Distributor of fluidized bed reactor |
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| JPH0236559A (en) * | 1988-07-26 | 1990-02-06 | Nec Corp | Semiconductor device and its manufacture |
| KR970013343A (en) * | 1995-08-10 | 1997-03-29 | 김광호 | Capacitor of Semiconductor Device and Manufacturing Method Thereof |
| KR0155879B1 (en) * | 1995-09-13 | 1998-12-01 | 김광호 | Method of manufacturing ta2o5 dielectric film capacity |
| KR970024207A (en) * | 1995-10-16 | 1997-05-30 | 김광호 | Method for fabricating DRAM semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100480574B1 (en) * | 1997-11-27 | 2005-05-16 | 삼성전자주식회사 | Method for forming metal line interconnection in semiconductor device and method for forming apacitor using the same |
| KR100451501B1 (en) * | 1998-12-30 | 2004-12-31 | 주식회사 하이닉스반도체 | Capacitor Formation Method of Semiconductor Memory Device |
| KR100818768B1 (en) * | 2002-02-20 | 2008-04-01 | 주식회사 케이씨씨 | Distributor of fluidized bed reactor |
| KR100795683B1 (en) * | 2002-04-19 | 2008-01-21 | 매그나칩 반도체 유한회사 | Method of manufacturing a capacitor in semiconductor device |
| KR100801314B1 (en) * | 2002-06-29 | 2008-02-05 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
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