JPH0236559A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0236559A JPH0236559A JP18710388A JP18710388A JPH0236559A JP H0236559 A JPH0236559 A JP H0236559A JP 18710388 A JP18710388 A JP 18710388A JP 18710388 A JP18710388 A JP 18710388A JP H0236559 A JPH0236559 A JP H0236559A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- metal oxide
- capacitor
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 38
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 6
- -1 nitrogen- containing metal oxide Chemical class 0.000 claims abstract 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 52
- 229910052757 nitrogen Inorganic materials 0.000 claims description 25
- 239000012298 atmosphere Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 28
- 238000010438 heat treatment Methods 0.000 abstract description 10
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 abstract description 9
- 229910001936 tantalum oxide Inorganic materials 0.000 abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 abstract description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 8
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005546 reactive sputtering Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 240000001548 Camellia japonica Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 235000018597 common camellia Nutrition 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010985 leather Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000029305 taxis Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に金属酸化膜を用いた容
量部の構造及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure of a capacitive part using a metal oxide film and a method of manufacturing the same.
従来、高い誘電率をもつ金属酸化膜を容量絶縁膜に用い
た容量部には、シリコン基板やポリシリコン等の下部電
極(第1電極)とTaxes、Hf 02等の金属酸化
膜を用いた容量絶縁膜とポリシリフン、シリサイド等の
上部電極(第2電極)からなっている構造のものと、金
属酸化膜と上部電極す
との間に、バ椿ヤー膜を設けている構造のものがある。Conventionally, a capacitor part that uses a metal oxide film with a high dielectric constant as a capacitor insulating film has a lower electrode (first electrode) made of a silicon substrate or polysilicon, and a capacitor part that uses a metal oxide film such as Taxes or Hf 02. There are those with a structure consisting of an insulating film and an upper electrode (second electrode) such as polysilicon or silicide, and those with a structure where a camellia film is provided between the metal oxide film and the upper electrode.
このバ(ヤー膜として、窒化チタン等の金属窒化物やS
1 o、、 S i 3N4等の絶縁膜が用いられて
いる。As this barrier film, metal nitride such as titanium nitride or S
An insulating film such as Si3N4 is used.
上述した従来の容量構造では、金属酸化膜上に直接上部
電極を設ける場合、後熱処理工程で金属酸化膜と上部電
極との反応が起こり、容量絶縁膜のリーク電流が大幅に
増加するという問題点かあ1ノ
る。次に、バ啼ヤー膜を設ける場合、5if2やSi3
N4等の絶縁膜を用いると、金属酸化膜とバリヤー膜と
の2層絶縁膜になるので、バリヤー膜を用いることで容
量値が減少するという問題点がある。またバリヤー膜と
して窒化チタン等の窒化金属を用いると、窒化金属が導
電体であるためこのような容量値減少の問題点はないが
、窒化金属を反応性スパッタ等で形成するので、溝容量
、スタック容量等の凸凹のあるパターン上では窒化金属
の段差被覆性が悪く、リーク電流が流れやすくなったり
、ピンホール等の欠陥が発生しやすいという問題点があ
る。In the conventional capacitive structure described above, when the upper electrode is provided directly on the metal oxide film, a reaction occurs between the metal oxide film and the upper electrode in the post-heat treatment process, resulting in a significant increase in leakage current from the capacitor insulating film. Kaa1 noru. Next, when providing a barrier film, 5if2 or Si3
When an insulating film such as N4 is used, it becomes a two-layer insulating film consisting of a metal oxide film and a barrier film, so there is a problem in that the capacitance value decreases when a barrier film is used. Furthermore, when a metal nitride such as titanium nitride is used as a barrier film, there is no problem of such a decrease in capacitance because the metal nitride is a conductor. However, since the metal nitride is formed by reactive sputtering, the groove capacitance On an uneven pattern such as a stack capacitor, the metal nitride has poor step coverage, and there are problems in that leakage current is likely to flow and defects such as pinholes are likely to occur.
本発明の容量構造は、第1電極と金属酸化膜を含む誘電
体層と該金属酸化膜上に形成された窒素を含む金属酸化
膜と第2電極とを含んで構成されている。このような容
量構造の製造は第1電極を形成する工程と、金属酸化膜
を形成する工程と、窒素を含む金属酸化膜を形成する工
程と、第2電極を形成する工程とを少なくとも備えた製
造方法によって形成される。また、このうち、窒素を含
む金属酸化膜を形成する工程は、金属酸化膜をNH3雰
囲気、N2雰囲気、あるいはN HzとN2の混合雰囲
気中でのランプアニー麿で熱処理を行うことによって、
絶縁膜のピンホール等を防ぎながら、リーク電流を効果
的に防げる。The capacitor structure of the present invention includes a first electrode, a dielectric layer including a metal oxide film, a metal oxide film containing nitrogen formed on the metal oxide film, and a second electrode. Manufacturing such a capacitor structure includes at least the steps of forming a first electrode, a step of forming a metal oxide film, a step of forming a metal oxide film containing nitrogen, and a step of forming a second electrode. Formed by a manufacturing method. Furthermore, in the step of forming a metal oxide film containing nitrogen, the metal oxide film is heat-treated by lamp annealing in an NH3 atmosphere, a N2 atmosphere, or a mixed atmosphere of NHz and N2.
It can effectively prevent leakage current while preventing pinholes in the insulating film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は、本発明の一実施例の模式的断面図である。本
実施例の容量部構造は第1電極のポリシリコン電極31
と容量絶縁膜のTa2es膜51と窒素を含む酸化タン
タル52及び第2電極のポリシリコン電極61からなる
。FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention. The structure of the capacitive part in this embodiment is that the polysilicon electrode 31 of the first electrode
, a Ta2es film 51 as a capacitive insulating film, a tantalum oxide 52 containing nitrogen, and a polysilicon electrode 61 as a second electrode.
窒素を含む酸化タンタル52をT a 20 s膜51
とポリシリコン電極61との間に入れることにより、ポ
リシリコン電極61 (第2電極)形成後の後工程熱処
理によるT EL 20 s膜51とポリシリコン電極
61との反応を防ぎ、電気特性の劣化を防止できる。酸
化タンタル52中に含まれる窒素の濃度は、原子数で1
0〜70%程度でよい。A T a 20 s film 51 is made of tantalum oxide 52 containing nitrogen.
By placing it between the polysilicon electrode 61 and the polysilicon electrode 61, it is possible to prevent the reaction between the TEL 20s film 51 and the polysilicon electrode 61 due to post-process heat treatment after forming the polysilicon electrode 61 (second electrode), and to prevent deterioration of electrical characteristics. can be prevented. The concentration of nitrogen contained in tantalum oxide 52 is 1 in terms of the number of atoms.
It may be about 0 to 70%.
極)/Ta2es/ポリシリコン電極(第2電極)容量
構造に関して、第2電極形成後に窒素雰囲気中で900
℃熱処理1時間行った場合のリーク電流特性を第2図に
示す。第2電極形成後に熱処理を行う場合は、本実施例
も従来例もリーク電流特性はほぼ同じで、第2図中の破
線に示す。本実施例の場合は、熱処理によるリーク電流
の増加はないが、従来例では熱処理を行うと大幅にリー
ク電流が増加する。Regarding the capacitance structure of the Ta2es/polysilicon electrode (second electrode), after forming the second electrode, the capacitance structure was
Figure 2 shows the leakage current characteristics when heat treatment was performed for 1 hour at °C. When heat treatment is performed after forming the second electrode, the leakage current characteristics of this embodiment and the conventional example are almost the same, as shown by the broken line in FIG. 2. In the case of this embodiment, the leakage current does not increase due to the heat treatment, but in the conventional example, the leakage current increases significantly when the heat treatment is performed.
を
これは窒素8含む酸化タンタル52がポリシリコン電極
61とTa20s51との間に起こる。This occurs when the tantalum oxide 52 containing nitrogen 8 is between the polysilicon electrode 61 and the Ta20s51.
13S i+2Tazos−e4Tas iz+5s
iozのような反応を効果的に防止しているためである
。13S i+2Tazos-e4Tas iz+5s
This is because reactions such as those caused by Ioz are effectively prevented.
これにより、容量膜に生ずるピンホールやウィークスポ
ットの発生を抑制し、容量膜のリーク電流の増加や絶縁
耐圧劣化や信頼性の低下を抑制できる。Thereby, it is possible to suppress the occurrence of pinholes and weak spots in the capacitive film, and to suppress an increase in leakage current of the capacitive film, deterioration in dielectric strength, and reduction in reliability.
次に第1実施例の容量部構造の製造方法について、第3
図(a)〜(h)を参照して説明する。Next, regarding the manufacturing method of the capacitor structure of the first embodiment, the third
This will be explained with reference to FIGS. (a) to (h).
まず、シリコン基板1上に形成した5iO22上に、ポ
リシリコンを1000〜10000人気相成長法(略し
てCVD)等により形成する(第3 図(a))。次に
フォト・レジスト41を用いて、第1電極のバターニン
グを行う(第3図(b)。First, polysilicon is formed on 5iO22 formed on a silicon substrate 1 by a 1000-10000 phase growth method (abbreviated as CVD) or the like (FIG. 3(a)). Next, the first electrode is patterned using a photoresist 41 (FIG. 3(b)).
(C))。そして、ポリシリコン電極3上にCVD。(C)). Then, CVD is performed on the polysilicon electrode 3.
あるいは反応性スパッタ等でT a 20 s膜51を
50〜500人形成する(第3図(d))。さらにTa
205膜51を、N Hz雰囲気中でランブアニ−Vで
900〜1150℃の範囲で熱処理を数秒〜数百秒間行
って、表面から30〜100人程度、窒素を含む酸化タ
ンタル52を形成する(第3図(e))。そして、窒素
を含む酸化タンタル52上にポリシリコンロを2000
〜4000人形成し、フォト・レジスト42を用いて、
バターニングを行い、第2電極のポリシリコン電極を形
成する(第3図(f)〜(h))。Alternatively, 50 to 500 Ta 20 s films 51 are formed by reactive sputtering or the like (FIG. 3(d)). Furthermore, Ta
The 205 film 51 is heat-treated in the range of 900 to 1150° C. in an N Hz atmosphere using Lambanie-V for several seconds to several hundreds of seconds to form tantalum oxide 52 containing nitrogen in about 30 to 100 layers from the surface. Figure 3(e)). Then, 2000 ml of polysilicon was applied on the tantalum oxide 52 containing nitrogen.
Form ~4000 people and use photoresist 42,
Buttering is performed to form a polysilicon electrode as a second electrode (FIG. 3(f) to (h)).
第4図は本発明の他の実施例の模式的断面図である。本
実施例の容量は、第1電極のポリシリコン電極31と、
容量絶縁膜のSi、N4膜53及びHfO2膜54と、
窒素を含む酸化チタン56と、第2電極のポリシリコン
電極61とから構成される。FIG. 4 is a schematic cross-sectional view of another embodiment of the present invention. The capacitance of this example is that the polysilicon electrode 31 of the first electrode,
Si, N4 film 53 and HfO2 film 54 of the capacitive insulating film,
It is composed of titanium oxide 56 containing nitrogen and a polysilicon electrode 61 as a second electrode.
本実施例では容量絶縁膜をS i3N4/HfO2の2
層膜にすることにより、Hf O2膜単層より容量値は
小さくなるが、リーク電流の少ない容量を得ることがで
きる。また、第1〜3図の実施例と同様に、窒素を含む
酸化チタン56をHf O2膜54と第2電極のポリシ
リコン電極61との間にいれることにより、第2電極形
成後の後工程による容量膜の電気特性の劣化を防止でき
る。In this example, the capacitive insulating film is made of Si3N4/HfO2.
By forming a layered film, the capacitance value becomes smaller than that of a single layer of HfO2 film, but a capacitance with less leakage current can be obtained. Further, as in the embodiments shown in FIGS. 1 to 3, by inserting nitrogen-containing titanium oxide 56 between the HfO2 film 54 and the polysilicon electrode 61 of the second electrode, post-processing after forming the second electrode is possible. It is possible to prevent deterioration of the electrical characteristics of the capacitive film due to
なお、酸化チタン56中に含まれる窒素濃度は、第1実
施例と同様に原子数で10〜70%程度がよい。Note that the nitrogen concentration contained in the titanium oxide 56 is preferably about 10 to 70% in terms of the number of atoms, similar to the first embodiment.
次にこの実施例の容量部構造の製造方法について、第5
図(a)〜(j)を参照して説明する。Next, the method for manufacturing the capacitor structure of this example will be explained in the fifth section.
This will be explained with reference to FIGS. (a) to (j).
まず、シリコン基板1上に形成したSiO□2上に、ポ
リシリコン3を1000〜10000人CVD等により
形成する(第5図(a))。次にフォト・レジスト41
を用いて、第1電極のパターニングを行う(第5図(b
) 、 (c))。そして、ポリシリコン電極31上に
、CVD、直接熱窒化等で5isN453を20〜10
0人形成しく第5図(d))、さらにCVD、反応性ス
パッタ等でHf O2膜54を50〜500人形成する
。(第5図(e))。First, polysilicon 3 is formed on SiO□2 formed on silicon substrate 1 by CVD or the like for 1,000 to 10,000 times (FIG. 5(a)). Next, photo resist 41
The first electrode is patterned using
), (c)). Then, 20 to 10% of 5isN453 is applied on the polysilicon electrode 31 by CVD, direct thermal nitridation, etc.
Then, 50 to 500 people form the HfO2 film 54 by CVD, reactive sputtering, etc. (FIG. 5(d)). (Figure 5(e)).
次に、CVD、反応性スパッタ等でTiO2膜55を3
0〜100人形成しく第5図(r))、NH3雰」し
囲気中でランプアニー慶で熱処理を900〜1150℃
の範囲で数秒〜数百秒間行って、TiO2膜55を窒素
を含む酸化チタン56にする(第5図(g))。次に、
窒素を含む酸化チタン56上にCvD等によりポリシリ
コンロを2000〜4000人形成し、フォト・レジス
ト42を用いて、第2電極のパターニングを行い、ポリ
シリコン電極61を形成する(第5図(h)〜(j))
。Next, 3 layers of TiO2 film 55 are formed by CVD, reactive sputtering, etc.
0 to 100 people (Fig. 5 (r)), heat-treated at 900 to 1150°C in a lamp annealing in an NH3 atmosphere.
The TiO2 film 55 is converted into a titanium oxide 56 containing nitrogen by carrying out the process for several seconds to several hundred seconds (FIG. 5(g)). next,
2,000 to 4,000 polysilicon layers are formed on the nitrogen-containing titanium oxide 56 by CvD or the like, and a second electrode is patterned using a photoresist 42 to form a polysilicon electrode 61 (see FIG. 5). h) ~ (j))
.
本発明の各実施例では、金属酸化膜としてTazOs及
びTiO2について説明したが、Y 203. N b
20 s等の他の金属酸化膜、また金属酸化膜中に他
の金属が入っている膜にも適用できる。また、窒素を含
む金属酸化膜として、窒素を含む酸化タンタル、窒素を
含む酸化チタンを説明したが、他の窒素を含む金属酸化
膜でもよく、金属酸化膜と窒素を含む金属酸化物との組
み合せは自由である。In each embodiment of the present invention, TazOs and TiO2 have been described as metal oxide films, but Y203. Nb
The present invention can also be applied to other metal oxide films such as 20S, and films containing other metals in the metal oxide film. In addition, although tantalum oxide containing nitrogen and titanium oxide containing nitrogen have been described as metal oxide films containing nitrogen, other metal oxide films containing nitrogen may also be used, and combinations of metal oxide films and metal oxides containing nitrogen may also be used. is free.
また第4〜5図の実施例ではSi3N4上にHfO2を
形成した2層膜構造であったが、Sigh等の他の絶縁
膜上に金属酸化膜を形成した場合にも本発明は適用でき
る。Furthermore, although the embodiment shown in FIGS. 4 and 5 has a two-layer film structure in which HfO2 is formed on Si3N4, the present invention can also be applied to a case where a metal oxide film is formed on another insulating film such as Sigh.
また実施例では第1電極がポリシリコンの場合について
説明したが、シリコン基板、シリサイド、高融点金属等
の第1電極の場合、また第2電極がシリサイド、ポリサ
イド等の場合にも本発明を適用してもその効果は変わら
ない。Further, in the embodiment, the case where the first electrode is made of polysilicon has been explained, but the present invention is also applicable to the case where the first electrode is made of a silicon substrate, silicide, high melting point metal, etc., and the second electrode is made of silicide, polycide, etc. However, the effect remains the same.
また、金属酸化膜形成後に熱処理を行うのも自由である
。さらに窒素を含む金属酸化膜を形成する方法も、金属
を酸素を含む窒素雰囲気中でスパッタで形成したり、金
属酸化膜を拡散炉を用いて熱窒化したり、その方法は自
由である。Further, heat treatment can be freely performed after forming the metal oxide film. Furthermore, the method for forming the metal oxide film containing nitrogen is arbitrary, such as forming the metal by sputtering in a nitrogen atmosphere containing oxygen, or thermally nitriding the metal oxide film using a diffusion furnace.
以上説明したように、本発明は、金属酸化膜とポリシリ
コン、シリサイド等の電極との間に、窒素を含む金属酸
化膜をはさむことで、電極形成後の後工程の熱処理によ
る容量膜と電極との反応を抑制し、容量膜のリーク電流
の増加や絶縁耐圧の劣化がなく、容量値の大きい優れた
容量を得ることができ°るという効果がある。As explained above, in the present invention, by sandwiching a metal oxide film containing nitrogen between a metal oxide film and an electrode made of polysilicon, silicide, etc., a capacitive film and an electrode can be formed by heat treatment in a post-process after electrode formation. This has the effect of suppressing the reaction with the capacitor film, preventing an increase in leakage current of the capacitor film and deteriorating the dielectric breakdown voltage, and making it possible to obtain an excellent capacitance with a large capacitance value.
また、窒素を含む金属酸化膜をランプアニー慶で形成す
ることにより、本発明の半導体装置を量産性よく製造で
きる効果もある。Further, by forming the metal oxide film containing nitrogen by lamp annealing, the semiconductor device of the present invention can be manufactured with good mass productivity.
第1図は本発明の一実施例の模式的断面図、第2図は本
発明の一実施例及び従来技術例のリーク電流特性を示す
グラフで、縦軸がリーク電流の電流密度、横軸が容量膜
に印加されている電界強度である。第3図(a)〜(h
)は本発明の一実施例の製造方法を工程順に説明する断
面図である。第4図は本発明の他の実施例の模式的断面
図、第5図(a)〜(j)は本発明の他の実施例の製造
方法を工程順に説明する断面図である。
1・・・・・・シリコン基板、2・・・・・・S iO
z、3・・・・・・ポリシリコン、31・・・・・・第
り電極用のポリシリコン電極、41.42・・・・・・
フォトレジスト、51・・・・・・Ta205.52・
・・・・・窒素を含む酸化タンタル、53・・・・・・
Si3N4.54・・・・・・HfO2,55・・・・
・・TiO□、56・・・・・・窒素を含む酸化チタン
、6・・・・・・ポリシリコン、61・・・・・・第2
電極用のポリシリコン電極。
代理人 弁理士 内 原 晋
電昇g度ζM厳蟇2)
$ 2 回
茅
腑
(C)
cd)
革3
茅
回
(Z’J
(d+
$5
弗
茅
図FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention, and FIG. 2 is a graph showing leakage current characteristics of an embodiment of the present invention and a prior art example, where the vertical axis is the current density of the leakage current, and the horizontal axis is the current density of the leakage current. is the electric field strength applied to the capacitive membrane. Figure 3 (a) to (h)
) is a sectional view illustrating a manufacturing method according to an embodiment of the present invention in the order of steps. FIG. 4 is a schematic cross-sectional view of another embodiment of the present invention, and FIGS. 5(a) to (j) are cross-sectional views illustrating a manufacturing method of another embodiment of the present invention in the order of steps. 1... Silicon substrate, 2... SiO
z, 3... Polysilicon, 31... Polysilicon electrode for the second electrode, 41.42...
Photoresist, 51...Ta205.52.
...Tantalum oxide containing nitrogen, 53...
Si3N4.54...HfO2,55...
...TiO□, 56...Titanium oxide containing nitrogen, 6...Polysilicon, 61...2nd
Polysilicon electrode for electrode. Agent Patent Attorney Uchihara Shinden Shog Degree ζM Gansha 2) $ 2 Chika (C) CD) Leather 3 Chika (Z'J (d + $5 Fucha)
Claims (1)
化物を含む誘電体層及び該金属酸化膜を被覆する窒素を
含む金属酸化膜と該窒素を含む金属酸化膜上にシリサイ
ド、ポリサイド、もしくは多結晶シリコンのいずれかの
導電体層で形成される第2電極とを含んで構成される容
量部を備えていることを特徴とする半導体装置。 2、第1電極を形成する工程と、金属酸化膜を形成する
工程と、窒素を含む金属酸化膜を形成する工程と第2電
極を形成する工程とを少なくとも備えて容量部を形成す
る半導体装置の製造方法に於いて、前記窒素を含む金属
酸化膜を形成する工程は、金属酸化膜をNH_3雰囲気
、N_2雰囲気、あるいはNH_3とN_2の混合雰囲
気中でランプアニールで熱処理を行う工程を含んでいる
ことを特徴とする半導体装置の製造方法。[Claims] 1. A first electrode of a semiconductor substrate or a conductive film, a dielectric layer containing a metal oxide, a metal oxide film containing nitrogen covering the metal oxide film, and a metal oxide film containing nitrogen. 1. A semiconductor device comprising: a capacitor portion including a second electrode formed thereon by a conductive layer of silicide, polycide, or polycrystalline silicon. 2. A semiconductor device that forms a capacitive part by at least the steps of forming a first electrode, forming a metal oxide film, forming a metal oxide film containing nitrogen, and forming a second electrode. In the manufacturing method, the step of forming the metal oxide film containing nitrogen includes a step of heat-treating the metal oxide film by lamp annealing in an NH_3 atmosphere, an N_2 atmosphere, or a mixed atmosphere of NH_3 and N_2. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18710388A JPH0236559A (en) | 1988-07-26 | 1988-07-26 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18710388A JPH0236559A (en) | 1988-07-26 | 1988-07-26 | Semiconductor device and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0236559A true JPH0236559A (en) | 1990-02-06 |
Family
ID=16200159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18710388A Pending JPH0236559A (en) | 1988-07-26 | 1988-07-26 | Semiconductor device and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0236559A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06502967A (en) * | 1991-10-15 | 1994-03-31 | モトローラ・インコーポレイテッド | Voltage variable capacitor with amorphous dielectric film |
JPH06244364A (en) * | 1993-02-17 | 1994-09-02 | Nec Corp | Manufacture of semiconductor device |
KR19990055204A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Capacitor Formation Method of Semiconductor Device |
KR100231604B1 (en) * | 1996-12-20 | 1999-11-15 | 김영환 | Manufacturing method of capacitor of semiconductor device |
KR100234702B1 (en) * | 1996-12-05 | 1999-12-15 | 김영환 | Method for manufacturing capacitor with a dielectric film of ta2o5 |
US6096619A (en) * | 1994-03-01 | 2000-08-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device comprising a capacitor with an intrinsic polysilicon electrode |
GB2355113A (en) * | 1999-06-25 | 2001-04-11 | Hyundai Electronics Ind | Tantalum oxynitride capacitor dielectric |
KR100450657B1 (en) * | 1997-08-26 | 2004-12-17 | 삼성전자주식회사 | A capacitor of semiconductor memory device and method for fabricating the same |
KR100480914B1 (en) * | 2002-08-05 | 2005-04-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
JP2005537652A (en) * | 2002-09-02 | 2005-12-08 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Semiconductor device having field effect transistor and passive capacitor with reduced leakage current and improved capacitance per unit area |
-
1988
- 1988-07-26 JP JP18710388A patent/JPH0236559A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06502967A (en) * | 1991-10-15 | 1994-03-31 | モトローラ・インコーポレイテッド | Voltage variable capacitor with amorphous dielectric film |
JPH06244364A (en) * | 1993-02-17 | 1994-09-02 | Nec Corp | Manufacture of semiconductor device |
US6096619A (en) * | 1994-03-01 | 2000-08-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device comprising a capacitor with an intrinsic polysilicon electrode |
KR100234702B1 (en) * | 1996-12-05 | 1999-12-15 | 김영환 | Method for manufacturing capacitor with a dielectric film of ta2o5 |
KR100231604B1 (en) * | 1996-12-20 | 1999-11-15 | 김영환 | Manufacturing method of capacitor of semiconductor device |
KR100450657B1 (en) * | 1997-08-26 | 2004-12-17 | 삼성전자주식회사 | A capacitor of semiconductor memory device and method for fabricating the same |
KR19990055204A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Capacitor Formation Method of Semiconductor Device |
GB2355113A (en) * | 1999-06-25 | 2001-04-11 | Hyundai Electronics Ind | Tantalum oxynitride capacitor dielectric |
GB2355113B (en) * | 1999-06-25 | 2004-05-26 | Hyundai Electronics Ind | Method of manufacturing capacitor for semiconductor memory device |
KR100480914B1 (en) * | 2002-08-05 | 2005-04-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
JP2005537652A (en) * | 2002-09-02 | 2005-12-08 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Semiconductor device having field effect transistor and passive capacitor with reduced leakage current and improved capacitance per unit area |
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