KR980006290A - Ferroelectric RAM Manufacturing Method - Google Patents

Ferroelectric RAM Manufacturing Method Download PDF

Info

Publication number
KR980006290A
KR980006290A KR1019960026541A KR19960026541A KR980006290A KR 980006290 A KR980006290 A KR 980006290A KR 1019960026541 A KR1019960026541 A KR 1019960026541A KR 19960026541 A KR19960026541 A KR 19960026541A KR 980006290 A KR980006290 A KR 980006290A
Authority
KR
South Korea
Prior art keywords
ferroelectric
forming
film
capacitor
conductive film
Prior art date
Application number
KR1019960026541A
Other languages
Korean (ko)
Other versions
KR100233277B1 (en
Inventor
송태식
이창구
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960026541A priority Critical patent/KR100233277B1/en
Publication of KR980006290A publication Critical patent/KR980006290A/en
Application granted granted Critical
Publication of KR100233277B1 publication Critical patent/KR100233277B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 강유전체 램의 캐패시터 제조시, 하부전극 증착 및 식각, 강유전체 증착, 상부전극 증착 및 식각으로 공정이 차례로 이루어져 좁은 면적에서도 캐패시터의 유효면적을 크게하고및 강유전체 물질의 휘발성 물질의 확산에 의한 소자특성 저하를 벙자하기 위해 캐패시터의 상·하 부에 확산방지층인 실리콘 질화막을 형성하는 강유전체 램 제조방법에 관한 것으로, 본 발명의 강유전체 램 제조방법은 강유전체의 휘발성 물질 확산을 방지하여 모스트랜지스터의 파괴를 방지하고, 강유전체 캐패시터가 차지하는 면적을 줄이면서 같은 면적에서도 종래기술에 비해 유효 면적이 증대된 캐패시터를 갖는 효과가 있다.In the fabrication of the capacitor of the ferroelectric RAM, the process is sequentially performed by the lower electrode deposition and etching, the ferroelectric deposition, the upper electrode deposition, and the etching, thereby increasing the effective area of the capacitor even in a narrow area The present invention relates to a ferroelectric RAM fabrication method for forming a silicon nitride film as a diffusion preventing layer on upper and lower portions of a capacitor in order to exhibit degradation of device characteristics due to diffusion of a volatile material of a ferroelectric material. There is an effect of preventing the breakdown of the MOS transistor by preventing the diffusion of the volatile substance, reducing the area occupied by the ferroelectric capacitor, and increasing the effective area of the capacitor even in the same area.

Description

강유전체 램 제조 방법Ferroelectric RAM Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 2A도 내지 제 2E도는 본 발명의 일실시예에 따른 강유전체 램 제조공정도FIGS. 2A to 2E are views illustrating a process of manufacturing a ferroelectric RAM according to an embodiment of the present invention

Claims (5)

모스트랜지스터가 형성된 반도체 기판 전체구조 상부에 제1층간절연막을 형성하는 단계; 상기 제1층간절연막 상에 이후의 공정에 의해와 강유전체의 휘발성 물질이 상기 제1층간절연막 하부로 확산되는 것을 방지하는 제1확산 방지층을 형성하는 단계; 캐패시터의 하부전극용 제1전도막을 형성하고 선택식각하여 패턴화하는 단게; 캐패시터의 강유전체를 증착하고 결정화를 위한 어닐링을 실시하는 단계; 상기 강유전체상에 상부전극용 제2전도막을 형성하고 상기 제2전도막 및 상기 강유전체를 차례로 선택 식각하여 패턴화하는 단계; 강유전체 리커버리 어니링을 실시하느 단계; 전체구조 상부에및 강유전체의 휘발성 물질이 캐패시터 상부층으로 확산되는 것을 방지하는 제2확산방지층을 형성하는 단계; 상기 제2확산방지층 상에 제2층간절연막 및 금속배선을 형성하는 단계를 포함하여 이루어진 강유전체 램 제조방법Forming a first interlayer insulating film on the entire structure of the semiconductor substrate on which the MOS transistor is formed; On the first interlayer insulating film, Forming a first diffusion preventing layer for preventing a ferroelectric volatile material from diffusing to a lower portion of the first interlayer insulating film; Forming a first conductive film for the lower electrode of the capacitor and patterning the same by selective etching; Depositing a ferroelectric of the capacitor and performing annealing for crystallization; Forming a second conductive film for an upper electrode on the ferroelectric body, sequentially etching and patterning the second conductive film and the ferroelectric body; Performing ferroelectric recovery annealing; On top of the whole structure And forming a second diffusion barrier layer that prevents ferroelectric volatiles from diffusing into a capacitor upper layer; And forming a second interlayer insulating film and a metal interconnection on the second diffusion preventing layer 제1항에 있어서, 상기 제1전도막 및 제2전도막은 백금인 것을 특징으로 하는 강유전체램 제조방법The ferroelectric RAM according to claim 1, wherein the first conductive film and the second conductive film are platinum 제1항 또는 제2항에 있어서, 상기 제1확산방지층 및 제2확산방지층은 실리콘질화막인 것을 특징으로 하는 강유전체 램 제조방법The ferroelectric RAM fabrication method according to claim 1 or 2, wherein the first diffusion preventing layer and the second diffusion preventing layer are silicon nitride films 제3항에 있어서, 상기 실리콘질화막과 상기 백금과의 계면에 상기 두막의 접착력을 향상시키는 탄탈늄막을 형성하는 단계와, 상기 제1전도막 식각 단계에서 상기 탄탈늄막을 동일한 패턴으로 선택식각하는 단계를 더 포함하는 것을 특징으로 하는 강유전체 램 제조방법.The method of claim 3, further comprising: forming a tantalum film for enhancing the adhesion between the silicon nitride film and the platinum to enhance adhesion between the two films; and selectively etching the tantalum film in the same pattern in the first conductive film etching step And forming a ferroelectric layer on the ferroelectric layer. 제1항 또는 제2항에 있어서, 상기 제2전도막과 상기 제2층간절연막 계면에 티타늄막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 강유전체 램 제조방법.The method of claim 1 or 2, further comprising forming a titanium film on the interface between the second conductive film and the second interlayer insulating film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960026541A 1996-06-29 1996-06-29 Ferro dielectronics ram fabrication method KR100233277B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960026541A KR100233277B1 (en) 1996-06-29 1996-06-29 Ferro dielectronics ram fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960026541A KR100233277B1 (en) 1996-06-29 1996-06-29 Ferro dielectronics ram fabrication method

Publications (2)

Publication Number Publication Date
KR980006290A true KR980006290A (en) 1998-03-30
KR100233277B1 KR100233277B1 (en) 1999-12-01

Family

ID=19465207

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960026541A KR100233277B1 (en) 1996-06-29 1996-06-29 Ferro dielectronics ram fabrication method

Country Status (1)

Country Link
KR (1) KR100233277B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000042450A (en) * 1998-12-24 2000-07-15 김영환 Method for fabricating capacitor which can prevent characteristics deterioration of bottom electrode
KR100335398B1 (en) * 1998-10-13 2002-07-18 박종섭 Manufacturing method for capacitor of ferroelectric RAM

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714993A (en) * 1993-06-18 1995-01-17 Mitsubishi Electric Corp Semiconductor device and manufacturing thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100335398B1 (en) * 1998-10-13 2002-07-18 박종섭 Manufacturing method for capacitor of ferroelectric RAM
KR20000042450A (en) * 1998-12-24 2000-07-15 김영환 Method for fabricating capacitor which can prevent characteristics deterioration of bottom electrode

Also Published As

Publication number Publication date
KR100233277B1 (en) 1999-12-01

Similar Documents

Publication Publication Date Title
KR960004089B1 (en) Forming method of low resistance contact for semiconductor device
KR970063577A (en) Metal wiring structure and formation method
KR950021526A (en) Semiconductor device and manufacturing method thereof
KR930020561A (en) Manufacturing method of semiconductor integrated circuit device
KR950012601A (en) Contact formation method of semiconductor device
KR980006290A (en) Ferroelectric RAM Manufacturing Method
KR930011279A (en) Conductive layer connection structure of semiconductor device and manufacturing method thereof
KR960039434A (en) Transistor having metal gate electrode and manufacturing method thereof
KR19980070983A (en) Semiconductor device and manufacturing method
KR860009497A (en) Semiconductor devices
KR970054048A (en) Capacitor Manufacturing Method of Semiconductor Device
KR950009933A (en) Metal wiring formation method of semiconductor device
KR970077199A (en) Method for forming wiring layer of semiconductor device
KR980005512A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR970024215A (en) Method of forming tantalum pentoxide capacitor by vacuum annealing
KR980005596A (en) Method for forming a metal contact of a semiconductor device
KR940001279A (en) Metal wiring formation method of semiconductor
KR950004548A (en) Semiconductor device manufacturing method
KR960032601A (en) Method of contact between polyside and polyside
KR970063500A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR960002576A (en) Metal wiring formation method of semiconductor device
KR900010931A (en) Impurity diffusion prevention method of contact area
EP0933783A3 (en) Nonvolatile semiconductor storage device using ferroelectric films and its fabricating method.
KR960032602A (en) Contact window between polyside and polyside and forming method
KR970053084A (en) Method for manufacturing a semiconductor device having a multilayer gate

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070827

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee