KR0185976B1 - Integrated cmos circuit - Google Patents

Integrated cmos circuit Download PDF

Info

Publication number
KR0185976B1
KR0185976B1 KR1019900016859A KR900016859A KR0185976B1 KR 0185976 B1 KR0185976 B1 KR 0185976B1 KR 1019900016859 A KR1019900016859 A KR 1019900016859A KR 900016859 A KR900016859 A KR 900016859A KR 0185976 B1 KR0185976 B1 KR 0185976B1
Authority
KR
South Korea
Prior art keywords
transistors
subrows
narrow
cmos circuit
subrow
Prior art date
Application number
KR1019900016859A
Other languages
English (en)
Other versions
KR910008818A (ko
Inventor
Hendrikus Josephius Veendrick
Den Elshout Andreas Antoni Van
Dirk Willem Harberts
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of KR910008818A publication Critical patent/KR910008818A/ko
Application granted granted Critical
Publication of KR0185976B1 publication Critical patent/KR0185976B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Logic Circuits (AREA)
KR1019900016859A 1989-10-24 1990-10-22 Integrated cmos circuit KR0185976B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8902629A NL8902629A (nl) 1989-10-24 1989-10-24 Geintegreerde cmos-schakeling.
NL8902629 1989-10-24

Publications (2)

Publication Number Publication Date
KR910008818A KR910008818A (ko) 1991-05-31
KR0185976B1 true KR0185976B1 (en) 1999-04-15

Family

ID=19855506

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900016859A KR0185976B1 (en) 1989-10-24 1990-10-22 Integrated cmos circuit

Country Status (8)

Country Link
EP (1) EP0425032B1 (ko)
JP (1) JP3060235B2 (ko)
KR (1) KR0185976B1 (ko)
AT (1) ATE147543T1 (ko)
DE (1) DE69029642T2 (ko)
NL (1) NL8902629A (ko)
RU (1) RU2025829C1 (ko)
UA (1) UA27693C2 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391943A (en) * 1994-01-10 1995-02-21 Mahant-Shetti; Shivaling S. Gate array cell with predefined connection patterns

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130140A (ja) * 1983-12-17 1985-07-11 Toshiba Corp 半導体集積回路装置
JPH0695570B2 (ja) * 1985-02-07 1994-11-24 三菱電機株式会社 半導体集積回路装置

Also Published As

Publication number Publication date
JP3060235B2 (ja) 2000-07-10
JPH03152970A (ja) 1991-06-28
RU2025829C1 (ru) 1994-12-30
DE69029642D1 (de) 1997-02-20
EP0425032A1 (en) 1991-05-02
DE69029642T2 (de) 1997-07-10
KR910008818A (ko) 1991-05-31
UA27693C2 (uk) 2000-10-16
NL8902629A (nl) 1991-05-16
ATE147543T1 (de) 1997-01-15
EP0425032B1 (en) 1997-01-08

Similar Documents

Publication Publication Date Title
US5055716B1 (ko)
FR2571178B1 (fr) Structure de circuit integre comportant des transistors cmos a tenue en tension elevee, et son procede de fabrication
EP0258653A3 (en) Dynamic programmable logic arrays with nor-nor structure implemented in c-mos technology
GB2071910B (en) Fabrication of complementary bipolar transistors with cmos devices with polysilicon gates
DE3585669D1 (de) Verbesserte programmierbare logische netzvorrichtung mit verwendung der cmos-eprom-floating-gate-technologie.
EP0161734A3 (en) Integrated circuit architecture and fabrication method therefor
GB8927594D0 (en) Cmos input level shifting circuit with temperature-compensating n-channel field effect transistor structure
KR850000797A (ko) 마스터슬라이스형 반도체 장치
DE3576612D1 (de) Halbleiteranordnung mit mos-transistoren.
IT1137495B (it) Complesso circuitale utilizzante la logica ad emettitori accoppiati e la logica integrata ad iniezione
KR0185976B1 (en) Integrated cmos circuit
KR940010175A (ko) 개선된 배치 패턴을 갖는 반도체 회로
JPS6467795A (en) Reading amplifier
FR2568723B1 (fr) Circuit integre notamment de type mos et son procede de fabrication
DE3583674D1 (de) Programmierbare logische anordnung mit verhaeltnislosen feldeffekttransistoren.
EP0130363A3 (en) Differential logic circuit implemented in complementary transistor technology
FI861408A0 (fi) I cmos-teknik utfoert element.
JPS5470736A (en) Decoder circuit
JPS564932A (en) Tristate circuit
DE3887703D1 (de) MOS-Gatearray-Schaltung.
JPS5749253A (en) Semiconductor integrated circuit
KR890004465B1 (en) Delay circuit for gate array
JPS6418250A (en) Semiconductor integrated circuit
ES2088032T3 (es) Conjunto incorporado de camaras de mezcla para instalaciones de la tecnologia de los fluidos.
JPS5441027A (en) Memory output circuit

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021203

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee