KR0154355B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

Depositing an interlayer insulating film on a silicon substrate having a diffusion layer formed on a surface thereof, and forming a contact hole reaching the diffusion layer in the interlayer insulating film; and forming a titanium film and a first titanium nitride film on the interlayer insulating film surface including the contact hole surface. A step of sequentially depositing, a step of performing nitrogen treatment, a step of depositing a second titanium nitride film on the surface of the first titanium nitride film in a vacuum chamber, and at least silicon on the surface of the second titanium nitride film in the vacuum chamber Depositing an aluminum alloy film, fluidizing the aluminum alloy film by high temperature heating, and embedding the contact hole in the aluminum alloy film; and the aluminum alloy film, the second titanium nitride film, and the first titanium nitride film. And forming a wiring by sequentially patterning the titanium film. .

Description

Semiconductor device manufacturing method

1A and 1B are cross-sectional views showing main processes in the manufacture of a semiconductor device according to one of the prior art embodiments.

2 is a cross-sectional view showing main processes in semiconductor device fabrication in accordance with another conventional embodiment.

3A to 3D are cross-sectional views showing processes in manufacturing a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 diffusion layer

3: interlayer insulating film 4: contact hole

5: Ti film 6, 6a, 7: TiN film

8a, 8b, 8c, 8d, 8e: A1 alloy film 9: barrier metal film

10: void 11, 11a: spike

18: wiring

[Background of invention]

[Field of Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for electrically connecting a wiring provided on an interlayer insulating film to a diffusion layer through a folding hole.

[Prior art]

BACKGROUND ART In semiconductor devices in which high integration and multilayering proceed, demands for miniaturization and planarization of devices are increasing. Connecting the wiring to the diffusion layer under the interlayer insulating film via the contact hole also makes it difficult to satisfy the required performance with the existing technology. To cope with this, a reflow sputtering technique of A1 as reported in the Proceedings of 1991 VMIC Conference, pages 326-328, as a contact hole embedding method for the purpose of flattening the wiring on the contact holes. This was developed. In this method, the A1 film is deposited at room temperature in a vacuum chamber, and then heated at a high temperature in the same vacuum chamber to fluidize the A1 film.

Referring to FIGS. 1A and 1B, which are cross-sectional views of a main manufacturing process of a conventional semiconductor device, the reported manufacturing method (formerly first manufacturing method) is as follows. First, the interlayer insulating film 3 is formed on the surface of the silicon substrate 1 on which the diffusion layer 2 is formed. Subsequently, contact holes 4 are formed in the interlayer insulating film 3 so as to reach the diffusion layer 2. An A1 alloy film 8a made of A1-Si-Cu covering the surface of the interlayer insulating film 3 (including the contact hole 4) is formed by sputtering at room temperature in a vacuum chamber (FIG. 1a). Next, in the same vacuum chamber, it is heated to the melting point ambient temperature (400 ° C to 550 ° C) of A1, and the A1 alloy film 8a is reflowed to obtain the A1 alloy film 8b (see also the first b).

In addition, an example of another method of embedding contact holes by increasing the reflowability of an A1 alloy film is reported, for example, in Procedures of 1992 VMIC Conference, pages 219-225.

Referring to FIG. 2, which is a cross-sectional view of a main manufacturing process of a semiconductor device according to another prior art, the reported manufacturing method (previous second manufacturing method) is as follows. First, the process until the contact hole 4 is formed in the interlayer insulating film 3 made of, for example, a PSG film is performed in the same manner as in the conventional first manufacturing method. Next, the surface of the interlayer insulating film 3 (including the contact hole 4) is covered by the barrier metal film 9 deposited by sputtering in the vacuum chamber. Next, an A1 alloy made of A1-Si is sputtered in the same vacuum chamber heated to about 500 ° C, and the barrier metal film 9 surface is covered by the A1 alloy film 8c (made of A1-Si). According to this method, since the wettability of the A1 alloy film 8c with respect to the barrier metal film 9 is high, this method is superior to the said 1st manufacturing method regarding the embedding of the contact hole 4. .

According to this report, a Ti film, a TiN film or a TiON film was tested as the barrier metal film 9, but there was voiding in the TiON film. This is because the wettability to the A1 alloy film 8c is low. As for the wettability, the Ti film is the best. Since the oxygen of the interlayer insulating film reacts with the Ti film and the Ti film surface is oxidized, when the aspect ratio of the contact hole 4 is 1.3 or more, voids are generated in the contact hole 4. In this report, in order to avoid this, a spacer (not shown) made of a silicon nitride film is provided on the sidewall of the contact hole 4.

Referring to FIGS. 1A and 1B, the conventional first manufacturing method has the following problems. Although void formation depends also on the aspect ratio of the contact hole 4, the void 10 is formed in the contact hole 4 in the deposition step of the Al alloy film 8a (see also FIG. 1a). When the A1 alloy film 8b is reflowed by high temperature heating to form the A1 alloy film 8b, even if the void 10 is extinguished, the abnormality to the diffusion layer 2 of the A1 alloy film 8b, for example. The spike 11 is formed by (abnormal) diffusion (see also FIG. 1b). The presence of the void 10 causes an increase in contact resistance, and the presence of the spike 11 causes a junction leak.

On the other hand, in the said conventional 2nd manufacturing method, generation | occurrence | production of a void is suppressed. However, referring to FIG. 2, which is a cross-sectional view of the main manufacturing process of the semiconductor device, the following problem remains in the conventional second manufacturing method. Even if the barrier metal film 9 is any one of a Ti film, a TiN film, and a laminated film of Ti and TiN, an alloying reaction of Si in the A1 alloy film 8c at about 500 ° C. and Ti in the barrier metal film 9 is performed. Remarkable As a result, the barrier metal film 9 does not function as a barrier, and as in the conventional first manufacturing method, it is impossible to suppress the occurrence of the spike 11a, and it is difficult to avoid the junction leakage.

That is, by applying the said conventional 2nd manufacturing method to the said 1st conventional manufacturing method, even if it forms the barrier metal film containing Ti after forming the contact hole 4, a spike will generate | occur | produce.

[Overview of invention]

This invention is made | formed in view of said situation, The objective is the manufacturing method of the semiconductor device for electrically connecting the wiring provided on the interlayer insulation film via a contact hole to a diffusion layer, suppressing the raise of a contact resistance, It is to provide a method for manufacturing a semiconductor device that avoids the occurrence of junction leaks.

In order to achieve the above object, according to a main feature of the present invention, a step of depositing an interlayer insulating film on a silicon substrate having a diffusion layer formed on the surface and forming a contact hole reaching the diffusion layer in the interlayer insulating film, and the contact hole surface Depositing a titanium film and a first titanium nitride film on a surface of the interlayer insulating film including a step; performing a nitrogen treatment; depositing a second titanium nitride film on a surface of the first titanium nitride film in a vacuum chamber; Depositing an aluminum alloy film containing at least silicon on the surface of the second titanium nitride film in the vacuum chamber, fluidizing the aluminum alloy film by high temperature heating, and embedding the contact hole in the aluminum alloy film; An aluminum alloy film, the second titanium nitride film, the first titanium nitride film, and the titanium film are sequentially lost. There is provided a semiconductor manufacturing method comprising a step of turning to form a wiring.

In the semiconductor device manufacturing method according to one aspect of the present invention, deposition of the second titanium nitride film, deposition of the aluminum alloy film, and fluidization of the aluminum alloy film are continuously performed in the same vacuum chamber.

In addition, the thickness of the said second titanium nitride film is 0.02 micrometer-0.1 micrometer normally.

In general, the nitrogen treatment is performed by lamp annealing in a nitrogen atmosphere of 400 ° C. to 1000 ° C., furnace annealing in a nitrogen atmosphere of 400 ° C. to 600 ° C., or nitrogen at 400 ° C. to 800 ° C. Plasma treatment.

According to the semiconductor device manufacturing method of the present invention, in the semiconductor device manufacturing method for electrically connecting a wiring made of an A1 alloy film containing at least Si and placed on an interlayer insulating film to a diffusion layer via a contact hole, voids are formed in the contact hole. Contact holes may be buried by reflowing the Al alloy film without generating or generating spikes in the diffusion layer. Therefore, it is easy to suppress the increase in contact resistance and to avoid the occurrence of junction leaks.

These and other various advantages, features, and other objects of the present invention will become apparent to those skilled in the art upon reference to the following detailed description and accompanying drawings, in which preferred structural embodiments in which the principles of the invention are implemented are illustrated.

Next, the present invention will be described with reference to the drawings (FIGS. 3A to 3D).

Referring to FIGS. 3A to 3D which are sectional views of the manufacturing process of a semiconductor device, an embodiment of the present invention is as follows. First, an interlayer insulating film 3 having a film thickness of about 1.0 μm is formed on the silicon substrate 1 on which the diffusion layer 2 is formed on the surface. By known lithography techniques and dry etching techniques, contact holes 4 that reach the diffusion layer 2 are formed in the interlayer insulating film 3 (see also FIG. 3A).

Subsequently, the Ti film 5 having a film thickness of about 0.03 μm and the first Tin film 6 having a thickness of about 0.1 μm are sequentially deposited on the entire surface, for example, by sputtering (see also FIG. 3b). That is, the film formation method of Ti (5) and TiN film 6 is not limited to sputtering, For example, you may use CVD method.

In the film forming step, the nitrogen content of the first TiN film 6 is too stoichiometrically insufficient, and oxygen is adsorbed on the surface of the TiN film 6 to be easily oxidized. Therefore, in particular, nitrogen treatment is performed to improve the barrier properties of the TiN film 6 (and to stabilize the contact resistance of the Ti film 5). By this nitrogen treatment, the first TiN film 6 is nitrided, and the nitrogen content of the TiN film 6 is close to the stoichiometric amount, and the TiN film 6 becomes the TiN film 6a. Also by this treatment; The contact between the Ti film 5 and the diffusion layer 2 is also stable. However, even with this nitrogen treatment, it is difficult to separate the oxygen oxidizing the surface of the TiN film 6 from the TiN film 6a. By this nitrogen treatment, the progress of oxidation on the surface of the TiN film 6a is stopped.

As this nitrogen treatment, there is a lamp annealing in a nitrogen atmosphere as an example. In this case, the lamp annealing is suitably performed at a temperature range of 400 ° C to 1000 ° C. When the nitrogen treatment is performed at a temperature lower than 400 ° C, the nitride of the TiN film formed by sputtering or the like is incomplete, and it is difficult to secure the barrier properties of the wiring and the diffusion layer 2 made of an A1 alloy film, and the diffusion layer 2 and the silicon substrate ( The junction leak between 1) increases. In addition, in the case of lamp annealing, if it is performed at a temperature higher than 1000 ° C, redispersion and redistribution of impurities (for example, interlayer insulating film components such as Si, Ti or oxygen) occur, and the contact resistance becomes unstable, A change in the electrical characteristics of the semiconductor device is brought about. Another method as the nitrogen treatment includes a nitrogen plasma treatment at 400 ° C to 600 ° C. The lower limit of the temperature range in these other nitrogenous treatments is determined from the conditions for ensuring complete barrier properties. In addition, the upper limit of the temperature range of these other nitrogen treatments is determined in the same manner as in the lamp annealing described above, in terms of re-diffusion and redistribution of impurities, respectively.

Next, in the same vacuum chamber, the second TiN film 7 having a thickness of about 0.05 μm and the A1 alloy 8d having a thickness of about 0.5 μm made of, for example, A1-1% Si-0.5% Cu are sputtered. It is in turn deposited on the entire surface (see also 3c).

The thickness of the second TiN film 7 is 0.02 m or more in order to completely cover the surface of the TiN film 6a having the oxidized surface, and the A1 alloy film 8a is reflowed without deteriorating the contact shape. In order not to affect the burying properties at the time, it needs to be 0.1 micrometer or less.

Next, for example, heating is performed for about 180 seconds at a temperature of about 450 DEG C in the same vacuum room in which the TiN film 7 and the A1 alloy film 8d are formed. The main reason for carrying out this treatment in the same vacuum chamber is economical. By this treatment, the A1 alloy film 8d is reflowed to become the A1 alloy film 8e, and the contact hole 4 is buried by the A1 alloy film 8e without voids or spikes. After taking out from the vacuum chamber, the A1 alloy film 8e, the TiN film 7, the TiN film 6a, and the Ti film 5 were sequentially patterned by a known lithography technique and a dry etching technique, and the Ti film 5 ), A wiring 18 in which the TiN film 6a, the TiN film 7 and the A1 alloy film 8e are laminated is formed (see also 3d).

The reason why the second TiN film 7 is interposed between the A1 alloy film 8d and the TiN film 6a will be described. The TiN film 7 is provided to ensure wettability with the A1 alloy film 8d in the reflow. When the TiN film 7 is not interposed, the A1 film 8d comes in direct contact with the TiN film 6a having the oxidized surface, making it difficult to secure wettability in the reflow process. The TiN film 7 and the A1 alloy film 8d are formed in the same vacuum chamber in order to prevent the wettability of the A1 film 8d from deteriorating due to oxidation on the surface of the TiN film 7. Instead of the TiN film 7, it is not preferable to use a Ti film having excellent wettability with the A1 alloy film. This is because if the Ti film is not oxidized by oxygen on the surface of the TiN film 6a, the wettability is extremely reduced, the barrier property is difficult to be secured, and spikes are likely to occur.

Claims (13)

Depositing an interlayer insulating film on a silicon substrate having a diffusion layer formed on the surface, and forming a contact hole reaching the diffusion layer in the interlayer insulating film; and forming a titanium film and a first titanium nitride film on the interlayer insulating film surface including the contact hole surface. A step of sequentially depositing, a step of performing nitrogen treatment, a step of depositing a second titanium nitride film on the surface of the first titanium nitride film in a vacuum chamber, and aluminum containing at least silicon on the surface of the second titanium nitride film in a vacuum chamber Depositing an alloy film, fluidizing the aluminum alloy film by high temperature heating, embedding a contact hole in the aluminum alloy film, and then the aluminum alloy film, the second titanium nitride film, the first titanium nitride film, and the titanium film. A method of manufacturing a semiconductor device, comprising the step of forming a wiring by patterning. The semiconductor device manufacturing method according to claim 1, wherein the deposition of the second titanium nitride film, the deposition of the aluminum alloy film, and the fluidization of the aluminum alloy film are continuously performed in the vacuum chamber. The method of manufacturing a semiconductor device according to claim 1, wherein the second titanium nitride film has a thickness of 0.02 µm to 0.1 µm. The method of claim 2, wherein the second titanium nitride film has a thickness of 0.02 μm to 0.1 μm. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen treatment is lamp annealing in a nitrogen atmosphere at 400 占 폚 to 1000 占 폚. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen treatment is furnace annealing in a nitrogen atmosphere at 400 ° C to 600 ° C. The semiconductor device manufacturing method according to claim 1, wherein the nitrogen treatment is a nitrogen plasma treatment at 400 占 폚 to 800 占 폚. The semiconductor device manufacturing method according to claim 2, wherein the nitrogen treatment is lamp annealing in a nitrogen atmosphere at 400 占 폚 to 1000 占 폚. 3. The semiconductor device manufacturing method according to claim 2, wherein the nitrogen treatment is furnace annealing in a nitrogen atmosphere at 400 deg. C to 600 deg. The method of manufacturing a semiconductor device according to claim 2, wherein the nitrogen treatment is a nitrogen plasma treatment at 400 占 폚 to 800 占 폚. The method of manufacturing a semiconductor device according to claim 3, wherein the nitrogen treatment is lamp annealing in a nitrogen atmosphere at 400 占 폚 to 1000 占 폚. 4. The semiconductor device manufacturing method according to claim 3, wherein the nitrogen treatment is furnace annealing in a nitrogen atmosphere at 400 deg. C to 600 deg. The method of manufacturing a semiconductor device according to claim 3, wherein the nitrogen treatment is a nitrogen plasma treatment at 400 占 폚 to 800 占 폚.