KR0143037B1 - Method of forming metal connection - Google Patents
Method of forming metal connectionInfo
- Publication number
- KR0143037B1 KR0143037B1 KR1019940013493A KR19940013493A KR0143037B1 KR 0143037 B1 KR0143037 B1 KR 0143037B1 KR 1019940013493 A KR1019940013493 A KR 1019940013493A KR 19940013493 A KR19940013493 A KR 19940013493A KR 0143037 B1 KR0143037 B1 KR 0143037B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal
- metal wiring
- forming
- semiconductor device
- trench
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 금속배선(Metal Pattern)이 형성될 부분의 절연층을 소정깊이 및 넓이로 식각하여 트렌치(trench)를 형성한 후 그 상부에 금속배선을 형성시키므로써 이루 열처리 공정시 사이드 힐록(side hillock)현상의 발생으로 인한 금속배선간의 단락(short)을 방지할 수 있도록 한 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein a trench is formed by etching an insulating layer of a portion where a metal pattern is to be formed to a predetermined depth and width, and then a metal wiring is formed thereon. The present invention relates to a method for forming metal wirings in a semiconductor device to prevent short circuits between metal wirings due to side hillock phenomenon during heat treatment.
Description
제 1a 및 제 1b도는 종래 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device.
제2a 내지 제 2c 도는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:실리콘 기판 2:소자 형성층1: Silicon substrate 2: Element formation layer
3:절연층 4 및 4A:금속배선3: insulation layer 4 and 4A: metallization
5:감광막 6:트랜치5: photoresist 6: trench
7:요홈7: recess
본 발명의 반도체 소자의 금속배선 형성 방법에 관한 것으로, 특히 금속배선(Metal Pattern)이 형성될 부분의 절연층을 소정깊이 및 넓이로 식각하여 트렌치(trench)를 형성한 후 그 상부에 금속배선을 형성시키므로써 이루 열처리 공정시 사이드 힐록(side hillock)현상의 발생으로 인한 금속배선간의 단락(short)을 방지할 수 있도록 한 반도체 소자의 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and particularly, to form a trench by etching an insulating layer of a portion where a metal pattern is to be formed to a predetermined depth and width, and then forming a metal wiring thereon. The present invention relates to a method for forming metal wirings in a semiconductor device to prevent shorting between metal wirings due to side hillock phenomenon during heat treatment.
일반적으로 반도체 소자의 제조공정에서 금속배선의 폭은 목적에 따라 달리 선택하여 형성하는데, 주변회로상에서는 넓은 금속배선을 많이 사용한다. 이러한 넓은 폭의 금속배선에는 형성이후의 열처리 공정중 고온에 의해 금속배선 바깥쪽으로 성장하는 사이드 힐록 현상이 발생되고, 이 사이드 힐록이 지나치게 클 경우 인접하는 금속배선과 전기저으로 단락(short)되어 소자의 동작에 치명적인 영향을 미치게 된다. 그러면 종래 반도체 소자의 금속배선 형성방법을 제 1a 및 제 1b 도를 통해 설명하면 다음과 같다.In general, the width of the metal wiring in the manufacturing process of the semiconductor device is selected and formed according to the purpose, a wide metal wiring is often used on the peripheral circuit. In this wide metal wiring, a side heel lock phenomenon that grows to the outside of the metal wiring occurs due to the high temperature during the heat treatment process after formation. It will have a fatal effect on the operation of. A method of forming metal wirings of a conventional semiconductor device will now be described with reference to FIGS. 1A and 1B.
종래 반도체 소자의 금속배선 형성방법을 제 1a 도에 도시된 바와 같이 소정의 공정에 의해 소자 형성층(2)이 형성된 실리콘 기판(1)상에 절연층(3)을 형성시키고 소정의 금속을 증착(Deposition)하여 금속층을 형성시킨 상태에서 금속배선 형성용 마스크를 사용하여 사진 및 식각공정에 의해 금속배선(4)이 형성되는데, 이후 열처리 공정을 진행하게 되면 제 1b 도에 도시된 바와 같이 금속이 바깥쪽으로 성장되는 사이드 힐록 현상이 발생되어 인접하는 금속배선과 사이드 힐록 부위(A)가 서로 접촉된다.As shown in FIG. 1A, a method of forming a metal wiring of a conventional semiconductor device is formed by forming an insulating layer 3 on a silicon substrate 1 on which an element forming layer 2 is formed by a predetermined process and depositing a predetermined metal. In the state where the metal layer is formed to form a metal layer, the metal wiring 4 is formed by a photolithography and etching process using a mask for forming a metal wiring. After the heat treatment is performed, the metal is outside as shown in FIG. The side hillock phenomenon that grows toward the side is generated so that the adjacent metal wiring and the side hillock portion A come into contact with each other.
따라서 본 발명은 금속배선(Metal Pattern)이 형성될 부분의 절연층을 소정깊이 및 넓이로 식각하여 트렌치(trench)를 형성한 후 그 상부에 금속배선을 형성시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention can solve the above-mentioned disadvantages by forming a trench by etching the insulating layer of the portion where the metal pattern is to be formed to a predetermined depth and width and forming a trench. It is an object of the present invention to provide a method for forming metal wirings in a semiconductor device.
상술한 목적을 달성하기 위한 본 발명은 실리콘 기판에 반도체 소자를 구성하는 여러 요소를 형성한 후 전체구조상에 절연층을 형성하는 단계와, 금속배선이 형성될 상기 절연층의 선택된 부분을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 포함한 상기 절연층상에 금속을 증착한 후 패터닝하여 상기 트렌치를 따라 금속배선이 형성되는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to form an insulating layer on the entire structure after forming a number of elements constituting a semiconductor device on a silicon substrate, and by etching a selected portion of the insulating layer to be formed of metal wiring trench And forming a metal wiring along the trench by patterning and depositing a metal on the insulating layer including the trench.
이하, 첨부된 도면을 참조하여 본 발명은 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 2a 내지 제 2c 도는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도로서, 제 2a 도는 실리콘 기판(1)에 반도체 소자를 구성하는 여러 요소가 형성된 소자 형성층(2)을 형성한 후 전체 구조상에 절연층(3)을 형성하고, 절연층(3) 상에 감광막(5)을 형성시킨 후 소정의 마스크를 사용하여 사진 및 식각공정에 의해 상기 감광막(5)을 패턴화하고, 상기 패턴화된 감광막을 이용한 식각공정으로 금속배선이 형성될 부분의 절연층(3)을 소정 깊이 및 넓이로 식각하여 트렌치(6)를 형성시킨 상태의 단면도인데, 상기 트렌치(6)는 금속배선과 같은 방향으로 형성시키며 금속 배선폭보다 좁게 형성된다.2A to 2C are cross-sectional views of a device for explaining a method of forming metal wirings of a semiconductor device according to the present invention. FIG. 2A is a view illustrating a device formation layer 2 having various elements constituting a semiconductor device on a silicon substrate 1. After the formation, the insulating layer 3 is formed on the entire structure, the photosensitive film 5 is formed on the insulating layer 3, and then the photosensitive film 5 is patterned by a photographic and etching process using a predetermined mask. In the etching process using the patterned photoresist, the insulating layer 3 of the portion where the metal wiring is to be formed is etched to a predetermined depth and width to form a trench 6. It is formed in the same direction as the metal wiring and is formed narrower than the metal wiring width.
제 2b 도는 상기 패턴화된 감광막(5)을 제거한 후 소정의 금속(Metal)을 증착하여 금속층을 형성시키고 패터닝하여 금속배선(4A)이 형성된 상태의 단면도인데, 상기 절연층(3)의 트렌치(6) 상부 즉, 상기 금속배선(4A)의 중앙부위에는 요홈(7)이 형성된다. 이 상태에서 열처리 공정이 진행되면 상기 금속은 제 2c 도에 도시된 바와 같이 상기 금속배선의 요홈(7)부분 즉, 내측으로 성장이 유도되기 때문에 인접하는 다른 금속배선과 접촉되는 것이 방지된다.FIG. 2B is a cross-sectional view of a metal layer 4A formed by forming and patterning a metal layer by depositing a predetermined metal after removing the patterned photosensitive film 5, wherein the trenches of the insulating layer 3 6) A recess 7 is formed in an upper portion, that is, a central portion of the metal wiring 4A. In this state, when the heat treatment process is performed, the metal is prevented from coming into contact with other adjacent metal wires because growth is induced in the recess 7 of the metal wire, that is, as shown in FIG. 2C.
상술한 바와 같이 본 발명에 의하여 금속배선(Metal Patten)이 형성될 부분의 절연층을 소정 깊이 및 넓이로 식각하여 트렌치(Trench)를 형성한 후 그 상부에 금속배선을 형성시키므로써, 열처리 공정시 금속의 성장이 금속배선 내측으로 유도되어 금속배선 간의 단락이 방지되며, 이로 인해 소자의 신뢰성을 향상시킬 수 있는 탁월한 효과가 있다.As described above, after forming the trench by etching the insulating layer of the portion where the metal wiring is to be formed to a predetermined depth and width, the metal wiring is formed on the upper part, thereby The growth of the metal is induced inside the metal wiring to prevent a short circuit between the metal wiring, which has an excellent effect of improving the reliability of the device.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940013493A KR0143037B1 (en) | 1994-06-15 | 1994-06-15 | Method of forming metal connection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940013493A KR0143037B1 (en) | 1994-06-15 | 1994-06-15 | Method of forming metal connection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960002485A KR960002485A (en) | 1996-01-26 |
| KR0143037B1 true KR0143037B1 (en) | 1998-08-17 |
Family
ID=19385338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940013493A KR0143037B1 (en) | 1994-06-15 | 1994-06-15 | Method of forming metal connection |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0143037B1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990062214A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
| KR101303777B1 (en) * | 2007-10-15 | 2013-09-04 | 포산 내션스타 옵토일렉트로닉스 코., 엘티디 | A heat dissipation substrate for power led and a power led device manufactured by it |
| US10128279B2 (en) | 2015-04-30 | 2018-11-13 | Samsung Display Co., Ltd. | Display apparatus having a stepped part |
| US11075231B2 (en) | 2015-04-30 | 2021-07-27 | Samsung Display Co., Ltd. | Display apparatus having a stepped part |
-
1994
- 1994-06-15 KR KR1019940013493A patent/KR0143037B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990062214A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
| KR101303777B1 (en) * | 2007-10-15 | 2013-09-04 | 포산 내션스타 옵토일렉트로닉스 코., 엘티디 | A heat dissipation substrate for power led and a power led device manufactured by it |
| US10128279B2 (en) | 2015-04-30 | 2018-11-13 | Samsung Display Co., Ltd. | Display apparatus having a stepped part |
| US11075231B2 (en) | 2015-04-30 | 2021-07-27 | Samsung Display Co., Ltd. | Display apparatus having a stepped part |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960002485A (en) | 1996-01-26 |
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