KR0124631B1 - Method of semiconductor device wiring - Google Patents
Method of semiconductor device wiringInfo
- Publication number
- KR0124631B1 KR0124631B1 KR1019940004592A KR19940004592A KR0124631B1 KR 0124631 B1 KR0124631 B1 KR 0124631B1 KR 1019940004592 A KR1019940004592 A KR 1019940004592A KR 19940004592 A KR19940004592 A KR 19940004592A KR 0124631 B1 KR0124631 B1 KR 0124631B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal
- insulating film
- contact hole
- plug
- wiring
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 종래의 반도체 장치 배선공정 단면도.1 is a cross-sectional view of a conventional semiconductor device wiring process.
제2도는 제1도에 따른 문제점을 나타낸 레이아웃도 및 단면도.2 is a layout and cross-sectional view showing a problem according to FIG.
제3도는 본 발명의 반도체 장치 배선공정 단면도.3 is a cross-sectional view of a semiconductor device wiring process of the present invention.
제4도는 제3도에 따른 작용, 효과를 나타낸 레이아웃도 및 단면도.4 is a layout and cross-sectional view showing the action, effect according to FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 필드 산화막 2 : 게이트1: field oxide film 2: gate
3 : 층간 절연막 4, 8 : 텅스텐3: interlayer insulating film 4, 8: tungsten
5 : 제1메탈 6, 6a : 감광막5: 1st metal 6, 6a: photosensitive film
7, 10 : 제1, 제2절연막 9 : 제2메탈7, 10: 1st, 2nd insulating film 9: 2nd metal
본 발명은 반도체 장치의 다충배선 형성공정에 관한 것으로, 특히 제1메탈과 비아 콘택(Via Contact) 공정의 마진(Margin)을 증대시키기 위한 반도체 장치의 배선방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a process for forming a multi-level interconnection of a semiconductor device, and more particularly, to a method of wiring a semiconductor device to increase a margin of a first metal and via contact process.
종래의 반도체 장치 배선공정을 첨부된 도면을 참조하여 설명하면 다음과 같다.A conventional semiconductor device wiring process will now be described with reference to the accompanying drawings.
제1도는 종래의 반도체 장치 배선공정 단면도로써, 제1도(a)와 같이 반도체 기판에 활성영역과 필드영역을 정의하면 필드영역에 필드 산화막(1)을 형성하고, 통상적인 방법으로 게이트(2)와 소오스 및 드레인영역을 구비한 트랜지스터를 형성한 후, 전면에 층간 절연막(3)을 증착하고 층간 절연막(3)을 선택적으로 제거하여 제1메탈 콘택 홀(Contact Hole)을 형성한 다음, 블랭키트 텅스텐(4)을 상기 제1메탈 콘택홀이 채워지도록 증착하고 에치 백(Etch Back)하여 텅스텐 (4) 플러그를 형성한다. 그리고 텅스텐(4) 플러그에 연결되도록 제1메탈(5)을 증착하고 감광막(6)을 이용한 포토에치 공정으로 제1메탈(5)을 패터닝하여 제1메탈 배선을 형성한다.FIG. 1 is a cross-sectional view of a conventional semiconductor device wiring process. When an active region and a field region are defined in a semiconductor substrate as shown in FIG. ) And a transistor having a source and a drain region, and then depositing an interlayer insulating film 3 on the front surface and selectively removing the interlayer insulating film 3 to form a first metal contact hole. Rankit tungsten (4) is deposited so as to fill the first metal contact hole and etch back to form a tungsten (4) plug. The first metal 5 is deposited to be connected to the tungsten 4 plug, and the first metal 5 is patterned by a photoetch process using the photosensitive film 6 to form a first metal wire.
계속해서, 제1도(b)와 같이 금속층간 제1절연막(7)을 전면에 증착하고 제1메탈배선과 제2메탈배선을 연결할 제2메탈 콘택 홀을 감광막(6a)을 이용하여 형성한다.Subsequently, as shown in FIG. 1 (b), the first insulating film 7 between the metal layers is deposited on the entire surface, and a second metal contact hole for connecting the first metal wiring and the second metal wiring is formed using the photosensitive film 6a. .
그리고, 제1도(c)와 같이 상기 제2메탈 콘택 홀내에 블랭키드 텅스텐(8)을 증착하고 패터닝하여 텅스텐(8) 플러그를 형성한다.As illustrated in FIG. 1C, a blank tungsten 8 is deposited and patterned in the second metal contact hole to form a tungsten 8 plug.
전면에 상기 텅스텐(8) 플러그가 연결되도록 제2메탈을 증착하고 패터닝하여 제2메탈 배선(9)을 형성한다.The second metal is deposited and patterned so that the tungsten (8) plug is connected to the front surface to form the second metal wiring (9).
그러나, 이와 같은 종래의 배선방법에 있어서는 다음과 같은 문제점이 있었다. 즉, 제2도는 종래의 배선방법에 따른 문제점을 설명하기 위한 레이아웃도 및 단면도로써, 제2도(a)와 같이 제1메탈(5)위에 비아 콘택을 형성하기 위해서 얼라인먼트 마진(Alignment margin) x, y을 0.2μ이상(64M DRAM인 경우) 확보하는 것이 통상적인 디자인 틀(Design Rule)이므로 그만큼 제1메탈의 폭을 갖추어야 하기 때문에 집적화에 불리하다.However, such a conventional wiring method has the following problems. That is, FIG. 2 is a layout diagram and a cross-sectional view for explaining a problem according to a conventional wiring method. As shown in FIG. 2 (a), an alignment margin x is formed to form a via contact on the first metal 5. For example, since it is a common design rule to secure y of 0.2 mu or more (in case of 64M DRAM), it is disadvantageous for integration because the first metal must have a width of the first metal.
또한 제2도(b)와 같이 미스-얼라인(Mis-align)이 생겼을 경우 비아 콘택 에치시에 비아(Via)가 형성되어 제2도(c)와 같이 다른 전도체와의 쇼트(Short) 내지는 누설전류의 발생 원인이 되어 소자의 신뢰성이 저하된다.In addition, when mis-alignment occurs as shown in FIG. 2 (b), vias are formed at the time of via contact etch, and thus short or short with other conductors as shown in FIG. It causes the leakage current and reduces the reliability of the device.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로써, 세미-셀프 얼라인(Semi-Self Align) 콘택 홀을 형성하여 콘택 마진을 증대시키면서 칩 사이즈를 감소시키는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has an object of reducing chip size while increasing a contact margin by forming a semi-self align contact hole.
이와 같은 목적을 달성하기 위한 본 발명을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
제3도는 본 발명은 반도체 장치 배선공정 단면도로써, 반도체 기판에 활성영역과 필드영역을 정의하여 필드영역에 선택적으로 필드 산화막(1)을 형성하고 활성영역에 게이트(2), 소오스 및 드레인 등의 반도체 소자를 형성한다.3 is a cross-sectional view of a semiconductor device wiring process, in which an active region and a field region are defined in a semiconductor substrate to selectively form a field oxide film 1 in the field region, and a gate 2, a source, a drain, etc. in the active region. A semiconductor device is formed.
이와 같이 반도체 소자가 형성된 기판 전면에 층간 절연막(3)을 형성하고 포토에치공정으로 층간 절연막(3)을 선택적으로 제거하여 제1메탈 콘택 홀을 형성한다. 그리고 콘택 홀 내부에 텅스텐(4) 플러그를 형성하고 텅스텐(4) 플러그에 연결되도록 전면에 제1메탈(5)을 증착한 후, 제1메탈(5)위에 금속층간 제1절연막(7)을 형성한다.Thus, the interlayer insulating film 3 is formed on the entire surface of the substrate on which the semiconductor element is formed, and the interlayer insulating film 3 is selectively removed by the photoetch process to form the first metal contact hole. After forming a tungsten (4) plug in the contact hole and depositing a first metal (5) on the front surface to be connected to the tungsten (4) plug, a first insulating film (7) between the metal layers is deposited on the first metal (5). Form.
계속해서, 감광막(6)을 이용한 포토에치 공정으로 금속층간 제1절연막(7)을 선택적으로 제거하여 제2메탈 콘택 홀을 형성한다.Subsequently, the first interlayer metal insulating film 7 is selectively removed by a photoetch process using the photosensitive film 6 to form a second metal contact hole.
제3도(b)와 같이 제2메탈 콘택 홀내에 텅스텐(8) 플러그를 형성하고 감광막(6a)을 이용한 제1메탈 배선을 노광한 후 제3도(c)와 같이 금속층간 제1절연막(7)과 제1메탈(5)을 식각하여 제1메탈 배선을 패터닝한다.As shown in FIG. 3 (b), a tungsten (8) plug is formed in the second metal contact hole and the first metal wiring using the photosensitive film 6a is exposed, and then as shown in FIG. 7) and the first metal 5 are etched to pattern the first metal wiring.
제3도(d)와 같이 제3도(c)에서 금속층간 제1절연막(7)과 제1메탈(5)이 제거된 부위에 금속층간 제2절연막(10)을 형성하고, 상기 텅스텐(8) 플러그에 연결되도록 전면에 제2메탈(9)을 증착하고 포토에치 공정으로 제2메탈(9)을 패터닝하여 제2메탈 배선을 형성한다.As shown in FIG. 3 (d), the second interlayer metal insulating film 10 is formed on a portion where the first interlayer metal insulating film 7 and the first metal 5 are removed in FIG. 8) The second metal 9 is deposited on the front surface so as to be connected to the plug, and the second metal 9 is patterned by a photoetch process to form a second metal wiring.
이와 같은 본 발명의 반도체 장치 배선방법에 있어서는 다음과 같은 효과가 있다.Such a semiconductor device wiring method of the present invention has the following effects.
제4도는 본 발명에 의한 작용, 효과를 설명하기 위한 레이아웃도 및 단면도로써, 제4도(a)와 같이 제1메탈(5)을 증착하고 제1메탈 배선을 패터닝하지 않는 상태에서 제1메탈 콘택을 위한 텅스텐(8) 플러그를 형성한 뒤 제1메탈(5)을 패터닝하여 제1메탈(5) 배선을 형성하므로써, 얼라인먼트 마진을 확보하기 위한 x, y값이 종래보다 작으므로 칩 사이즈(Chip Size)를 줄일 수 있다. 뿐만 아니라 제4도(b)와 같이 미스-얼라인 된다해도 제1메탈(5)을 제1메탈(5) 배선으로 패터닝할 시에 제4도(c)와 같이 미스 얼라인된 부분을 식각하여 제1메탈 배선을 형성할 수 있으므로 다른 전도층과 쇼트될 가능성과 누설전류 발생가능성을 줄여 소자의 신뢰성을 향상시킬 수 있다.FIG. 4 is a layout and cross-sectional view for explaining the operation and effect of the present invention. As shown in FIG. 4 (a), the first metal 5 is deposited and the first metal wiring is not patterned. By forming the tungsten (8) plug for the contact and then patterning the first metal (5) to form the first metal (5) wiring, the x and y values for securing alignment margins are smaller than in the prior art. Chip Size can be reduced. In addition, even when misaligned as shown in FIG. 4 (b), when the first metal 5 is patterned with the first metal 5 wiring, the misaligned portion as shown in FIG. 4 (c) is etched. Therefore, since the first metal wiring can be formed, the reliability of the device can be improved by reducing the possibility of short circuit with other conductive layers and the occurrence of leakage current.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940004592A KR0124631B1 (en) | 1994-03-09 | 1994-03-09 | Method of semiconductor device wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940004592A KR0124631B1 (en) | 1994-03-09 | 1994-03-09 | Method of semiconductor device wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950027949A KR950027949A (en) | 1995-10-18 |
| KR0124631B1 true KR0124631B1 (en) | 1997-12-10 |
Family
ID=19378592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940004592A KR0124631B1 (en) | 1994-03-09 | 1994-03-09 | Method of semiconductor device wiring |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0124631B1 (en) |
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1994
- 1994-03-09 KR KR1019940004592A patent/KR0124631B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950027949A (en) | 1995-10-18 |
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