KR100533983B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100533983B1 KR100533983B1 KR1020040050184A KR20040050184A KR100533983B1 KR 100533983 B1 KR100533983 B1 KR 100533983B1 KR 1020040050184 A KR1020040050184 A KR 1020040050184A KR 20040050184 A KR20040050184 A KR 20040050184A KR 100533983 B1 KR100533983 B1 KR 100533983B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
본 발명의 목적은 디램 소자에서 제조비용 상승을 최소화하면서 N형 접합영역 자체의 저항을 낮춰 비트라인과의 콘택 저항을 감소시킴으로써 우수한 동작 속도를 확보하는 것이다.An object of the present invention is to ensure an excellent operating speed by reducing the contact resistance with the bit line by lowering the resistance of the N-type junction region itself while minimizing the increase in manufacturing cost in the DRAM device.
본 발명의 목적은 제 1 도전형 제 1 접합영역과 제 2 도전형 제 2 접합영역이 형성된 반도체 기판 상에 층간절연막을 형성하는 단계; 층간절연막을 패터닝하여 제 1 접합영역을 노출시키는 제 1 콘택홀을 형성하는 단계; 층간절연막을 마스크로하여 노출된 제 1 접합영역으로 제 1 도전형 불순물을 이온주입하여 제 1 접합영역에 제 1 불순물층을 형성하는 단계; 층간절연막을 패터닝하여 제 2 접합영역을 노출시키는 제 1 콘택홀을 형성하는 단계; 층간절연막 상에 제 2 접합영역만을 노출시키는 마스크 패턴을 형성하는 단계; 노출된 제 2 접합영역으로 제 2 도전형 불순물을 이온주입하여 제 2 접합영역에 제 2 불순물층을 형성하는 단계; 및 마스크 패턴을 제거하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다. An object of the present invention is to form an interlayer insulating film on a semiconductor substrate on which a first conductive type first junction region and a second conductive type second junction region are formed; Patterning the interlayer insulating film to form a first contact hole exposing the first junction region; Forming a first impurity layer in the first junction region by ion implanting a first conductivity type impurity into the exposed first junction region using the interlayer insulating film as a mask; Patterning the interlayer insulating film to form a first contact hole exposing the second junction region; Forming a mask pattern exposing only the second junction region on the interlayer insulating film; Implanting a second conductivity type impurity into the exposed second junction region to form a second impurity layer in the second junction region; And it may be achieved by a method for manufacturing a semiconductor device comprising the step of removing the mask pattern.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 디램 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a DRAM device.
일반적으로, 디램(Dynamic Random Access Memory; DRAM)과 같은 메모리 소자에서 비트라인과 같은 배선과 실리콘 기판의 P형 또는 N형 접합영역을 전기적으로 연결할 때, 콘택 저항은 계면의 저항뿐만 아니라 접합영역 자체의 저항에도 영향을 받는데, 실리콘은 불순물 주입량이 증가할수록 저항이 낮아지는 효과가 있다. 따라서, 실리콘 자체의 저항을 낮추기 위해, 예컨대 P형 접합영역의 경우에는 보론(Boron; B) 등의 불순물을 적절하게 주입하고, N형 접합영역의 경우에는 인(Phosphorous; P) 또는 아세닉(Arsenic; As) 등의 불순물을 적절하게 주입하여야 한다.In general, when electrically connecting a wiring such as a bit line and a P-type or N-type junction region of a silicon substrate in a memory device such as DRAM (Dynamic Random Access Memory (DRAM)), the contact resistance is not only the resistance of the interface but also the junction region itself. It is also affected by the resistance of silicon, silicon has the effect of lowering the resistance as the amount of impurity injection increases. Therefore, in order to lower the resistance of the silicon itself, impurities such as boron (B) are appropriately implanted in the case of the P-type junction region, and phosphorus (P) or arsenic (in the case of the N-type junction region). Impurities such as Arsenic; As) should be appropriately injected.
그런데, 통상적으로 비트라인과 N형 접합영역 사이의 콘택 저항에 비해 비트라인과 P형 접합영역 사이의 콘택 저항이 더 높고 중요하기 때문에, 종래에는 도 1과 같이 P형 접합영역(11)에만 P형 접합영역(11)보다 깊은 깊이로 P형 불순물층(13)을 더 형성하여 P형 접합영역(11)의 불순물 주입량을 증가시켜 비트라인(미도시)과 P형 접합영역(11) 사이의 콘택 저항을 감소시키고 있다. 도 1에서, 미설명 도면부호 10은 반도체 기판, 12는 N형 접합영역, 14는 층간절연막, 15 및 16은 비트라인용 콘택홀을 각각 나타낸다.However, in general, since the contact resistance between the bit line and the P-type junction region is higher and important than the contact resistance between the bit line and the N-type junction region, conventionally, only the P-type junction region 11 as shown in FIG. The P-type impurity layer 13 is formed deeper than the type junction region 11 to increase the amount of impurity implanted in the P-type junction region 11, thereby forming a gap between the bit line (not shown) and the P-type junction region 11. Reducing contact resistance. In FIG. 1, reference numeral 10 denotes a semiconductor substrate, 12 an N-type junction region, 14 an interlayer insulating film, and 15 and 16 a contact hole for a bit line, respectively.
한편, 최근에는 디램 소자의 개발 동향이 동작 속도 향상 위주로 변해가면서 속도와 관련된 비트라인과 N형 접합영역 사이의 콘택 저항이 점차 중요해지고 있으나, 도 2와 같이, 고집적화로 인해 콘택 CD(Critical Dimension)가 작아지면서 콘택 저항은 점점 더 증가하고 있다. On the other hand, as the development trend of DRAM devices has shifted to the improvement of operation speed, the contact resistance between the bit line and the N-type junction region related to speed is becoming increasingly important. However, as shown in FIG. 2, due to high integration, a contact CD (critical dimension) As contact becomes smaller, contact resistance is increasing.
따라서, 콘택 저항을 낮추기 위해 티타늄실리사이드(TiSi2)층 형성을 조절하거나 N형 접합영역 자체의 저항을 낮추려는 노력이 이루어지고 있으나, 전자의 경우 그 한계가 분명하고 후자의 경우 별도의 마스크 공정 및 이온주입 공정이 더 요구되므로 제조비용이 상승하는 문제가 있다.Therefore, efforts have been made to control the formation of the titanium silicide (TiSi 2 ) layer or to lower the resistance of the N-type junction region itself in order to lower the contact resistance. However, in the former case, the limit is clear and in the latter case, a separate mask process and Since the ion implantation process is required more, there is a problem that the manufacturing cost increases.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 디램 소자에서 제조비용 상승을 최소화하면서 N형 접합영역 자체의 저항을 낮춰 비트라인과의 콘택 저항을 감소시킴으로써 우수한 동작 속도를 확보하는데 그 목적이 있다. The present invention has been proposed to solve the problems of the prior art as described above, while reducing the resistance of the N-type junction region itself while minimizing the increase in manufacturing cost in the DRAM device to secure excellent operating speed by reducing the contact resistance with the bit line Its purpose is to.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 제 1 도전형 제 1 접합영역과 제 2 도전형 제 2 접합영역이 형성된 반도체 기판 상에 층간절연막을 형성하는 단계; 층간절연막을 패터닝하여 제 1 접합영역을 노출시키는 제 1 콘택홀을 형성하는 단계; 층간절연막을 마스크로하여 노출된 제 1 접합영역으로 제 1 도전형 불순물을 이온주입하여 제 1 접합영역에 제 1 불순물층을 형성하는 단계; 층간절연막을 패터닝하여 제 2 접합영역을 노출시키는 제 1 콘택홀을 형성하는 단계; 층간절연막 상에 제 2 접합영역만을 노출시키는 마스크 패턴을 형성하는 단계; 노출된 제 2 접합영역으로 제 2 도전형 불순물을 이온주입하여 제 2 접합영역에 제 2 불순물층을 형성하는 단계; 및 마스크 패턴을 제거하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is to form an interlayer insulating film on a semiconductor substrate on which a first conductive type first junction region and a second conductive type second junction region are formed. Doing; Patterning the interlayer insulating film to form a first contact hole exposing the first junction region; Forming a first impurity layer in the first junction region by ion implanting a first conductivity type impurity into the exposed first junction region using the interlayer insulating film as a mask; Patterning the interlayer insulating film to form a first contact hole exposing the second junction region; Forming a mask pattern exposing only the second junction region on the interlayer insulating film; Implanting a second conductivity type impurity into the exposed second junction region to form a second impurity layer in the second junction region; And it may be achieved by a method for manufacturing a semiconductor device comprising the step of removing the mask pattern.
여기서, 제 1 및 제 2 불순물층은 각각 상기 제 1 및 제 2 접합영역보다 깊은 깊이를 가진다.Here, the first and second impurity layers have a depth deeper than the first and second junction regions, respectively.
또한, 제 1 도전형은 N형이고 제 2 도전형은 P형이며, 제 1 도전형 불순물로 As 또는 PH3를 사용하며, 이때 제 1 도전형 불순물의 이온주입은 1.0E14 내지 1.0E16의 주입량과 5 내지 50KeV의 에너지로 수행하는 것이 바람직하다.In addition, the first conductivity type is N type, the second conductivity type is P type, and As or PH 3 is used as the first conductivity type impurity, and the ion implantation of the first conductivity type impurity is 1.0E14 to 1.0E16 And energy of 5 to 50 KeV.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 3a 내지 도 3e를 참조하여 본 발명의 실시예에 따른 디램 소자의 제조방법을 설명한다.A method of manufacturing a DRAM device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 3E.
도 3a에 도시된 바와 같이, 상부에는 게이트 절연막(미도시)과 게이트(미도시)가 형성되고, 내부에는 P형 접합영역(21)과 N형 접합영역(22)이 서로 이격된 반도체 기판(20)을 준비한다.As shown in FIG. 3A, a gate insulating layer (not shown) and a gate (not shown) are formed on an upper portion thereof, and a semiconductor substrate having a P-type junction region 21 and an N-type junction region 22 spaced apart from each other ( 20) Prepare.
도 3b에 도시된 바와 같이, 반도체 기판(20) 상에 층간절연막(23)을 형성하고, 마스크 공정 및 식각공정에 의해 층간절연막(23)을 패터닝하여 N형 접합영역(22)을 노출시키는 비트라인용 제 1 콘택홀(24)을 형성한다. As shown in FIG. 3B, a bit for forming an interlayer insulating film 23 on the semiconductor substrate 20 and patterning the interlayer insulating film 23 by a mask process and an etching process to expose the N-type junction region 22. A first contact hole 24 for a line is formed.
그 다음, 층간절연막(23)을 마스크로하여 노출된 N형 접합영역(22)으로 N형 불순물(25), 바람직하게 As 또는 PH3를 1.0E14 내지 1.0E16의 주입량과 5 내지 50KeV의 에너지로 이온주입하여, 도 3c에 도시된 바와 같이, N형 접합영역(22)에 N형 접합영역(22)보다 깊은 깊이로 N형 불순물층(25a)을 형성한다. 즉, 비트라인용 제 1 콘택홀(24) 형성 후 이온주입을 수행하기 때문에 별도의 마스크 공정이 요구되지 않아 제조 비용 상승이 발생되지 않는다.Next, the N-type impurity 25, preferably As or PH 3 , is injected into the N-type junction region 22 exposed using the interlayer insulating film 23 as a mask with an energy of 1.0E14 to 1.0E16 and energy of 5 to 50KV. By ion implantation, as shown in FIG. 3C, the N-type impurity layer 25a is formed in the N-type junction region 22 to a depth deeper than the N-type junction region 22. That is, since ion implantation is performed after the formation of the first contact hole 24 for the bit line, a separate mask process is not required, and thus an increase in manufacturing cost does not occur.
도 3d에 도시된 바와 같이, 제 1 콘택홀(24)을 매립하도록 층간절연막(23) 상에 포토레지스트막을 도포하고 노광 및 현상하여 N형 접합영역(22)은 보호하고 P형 접합영역(21) 상의 층간절연막(23)만을 노출시키는 마스크 패턴(27)을 형성한다. 그 다음, 마스크 공정 및 식각공정에 의해 층간절연막(23)을 패터닝하여 P형 접합영역(21)을 노출시키는 비트라인용 제 2 콘택홀(26)을 형성한다. 이때, 도시되지는 않았지만, 게이트를 노출시키는 제 3 콘택홀도 동시에 형성된다. As shown in FIG. 3D, a photoresist film is coated on the interlayer insulating film 23 so as to fill the first contact hole 24, and is exposed and developed to protect the N-type junction region 22 and to protect the P-type junction region 21. The mask pattern 27 exposing only the interlayer insulating film 23 on the () is formed. Next, the interlayer insulating film 23 is patterned by a mask process and an etching process to form a second contact hole 26 for bit lines exposing the P-type junction region 21. At this time, although not shown, a third contact hole exposing the gate is also formed at the same time.
그 후, 제 1 및 제 2 콘택홀(24, 26)과 제 3 콘택홀을 매립하도록 층간절연막(23) 상에 포토레지스트막을 도포하고 노광 및 현상하여, N형 접합영역(22)은 보호하면서 P형 접합영역(21)만을 노출시키는 마스크 패턴(27)을 형성한다. Thereafter, a photoresist film is applied, exposed and developed on the interlayer insulating film 23 so as to fill the first and second contact holes 24 and 26 and the third contact hole, thereby protecting the N-type junction region 22. A mask pattern 27 exposing only the P-type junction region 21 is formed.
그 다음, 노출된 P형 접합영역(21)으로 P형 불순물(28)을 이온주입하여, 도 3e에 도시된 바와 같이, P형 접합영역(21)에 P형 접합영역(21) 보다 깊은 P형 불순물층(28a)을 형성한다. 그 후, 공지된 방법에 의해 마스크 패턴(27)을 제거한 후, 도시되지는 않았지만 비트라인 콘택공정 및 비트라인 공정 등의 후속 공정을 수행한다.P-type impurities 28 are then ion implanted into the exposed P-type junction region 21, so that P is deeper in the P-type junction region 21 than the P-type junction region 21, as shown in FIG. 3E. A type impurity layer 28a is formed. Thereafter, after removing the mask pattern 27 by a known method, subsequent steps such as a bit line contact process and a bit line process are performed, although not shown.
상기 실시예에 의하면, N형 접합영역을 노출시키는 콘택홀만을 먼저 형성하고 별도의 마스크 공정을 부가하는 것 없이 층간절연막을 마스크로하여 노출된 N형 접합영역에만 N형 불순물을 더 형성한다.According to the above embodiment, N-type impurities are further formed only in the exposed N-type junction region using the interlayer insulating film as a mask without first forming only a contact hole exposing the N-type junction region and adding a separate mask process.
이에 따라, 제조 비용 상승은 최소화하면서 비트라인과 N형 접합영역 사이의 콘택 저항을 낮출 수 있으므로, 디램 소자의 동작 속도를 향상시킬 수 있다.Accordingly, the contact resistance between the bit line and the N-type junction region can be lowered while minimizing the increase in manufacturing cost, thereby improving the operating speed of the DRAM device.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 제조비용 상승을 최소화하면서 N형 접합영역 자체의 저항을 낮춰 비트라인과의 콘택 저항을 감소시킬 수 있으므로, 우수한 동작 속도의 디램 소자를 구현할 수 있다.The present invention described above can reduce the resistance of the N-type junction region itself while minimizing the increase in manufacturing cost, thereby reducing the contact resistance with the bit line, thereby realizing a DRAM device having excellent operating speed.
도 1은 종래 디램 소자를 나타낸 단면도.1 is a cross-sectional view showing a conventional DRAM device.
도 2는 콘택 CD에 따른 콘택저항 변화를 나타낸 도면.2 is a view illustrating a change in contact resistance according to a contact CD.
도 3a 내지 도 3e는 본 발명의 실시예에 따른 디램 소자의 제조방법을 설명하기 위한 단면도.3A to 3E are cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
20 : 반도체 기판 21 : P형 접합영역20 semiconductor substrate 21 P-type junction region
22 : N형 접합영역 23 : 층간절연막22: N-type junction region 23: interlayer insulating film
24, 26 : 콘택홀 25 : N형 불순물24, 26: contact hole 25: N-type impurities
25a : N형 불순물층 27 : 마스크 패턴25a: N-type impurity layer 27: mask pattern
28 : P형 불순물 28a : P형 불순물층28: P type impurity 28a: P type impurity layer
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