KR0135674B1 - BiCMOS 반도체 메모리 장치 - Google Patents

BiCMOS 반도체 메모리 장치

Info

Publication number
KR0135674B1
KR0135674B1 KR1019940024809A KR19940024809A KR0135674B1 KR 0135674 B1 KR0135674 B1 KR 0135674B1 KR 1019940024809 A KR1019940024809 A KR 1019940024809A KR 19940024809 A KR19940024809 A KR 19940024809A KR 0135674 B1 KR0135674 B1 KR 0135674B1
Authority
KR
South Korea
Prior art keywords
signal
transistor
node
potential
circuit
Prior art date
Application number
KR1019940024809A
Other languages
English (en)
Korean (ko)
Other versions
KR950009728A (ko
Inventor
아쭈시 오바
아쭈시 가노시따
히로또시 사또
아끼라 호소가네
후또시 가따다
다까시 하야사까
Original Assignee
기다오까 다까시
미스비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 기다오까 다까시, 미스비시 뎅끼 가부시끼가이샤 filed Critical 기다오까 다까시
Publication of KR950009728A publication Critical patent/KR950009728A/ko
Application granted granted Critical
Publication of KR0135674B1 publication Critical patent/KR0135674B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017527—Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1019940024809A 1993-09-29 1994-09-29 BiCMOS 반도체 메모리 장치 KR0135674B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5243266A JPH0798983A (ja) 1993-09-29 1993-09-29 半導体回路、基準電圧発生回路、アドレスデコード回路、および半導体記憶装置
JP93-243266 1993-09-29

Publications (2)

Publication Number Publication Date
KR950009728A KR950009728A (ko) 1995-04-24
KR0135674B1 true KR0135674B1 (ko) 1998-04-24

Family

ID=17101316

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940024809A KR0135674B1 (ko) 1993-09-29 1994-09-29 BiCMOS 반도체 메모리 장치

Country Status (3)

Country Link
JP (1) JPH0798983A (de)
KR (1) KR0135674B1 (de)
DE (1) DE4434117C2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0765038A3 (de) * 1995-07-27 1998-01-07 Texas Instruments Incorporated Verbesserungen in CMOS Inverterkonzepten
JP3866451B2 (ja) * 1999-06-24 2007-01-10 Ｎｅｃエレクトロニクス株式会社 冗長プログラム回路及びこれを内蔵した半導体記憶装置
JP2004048377A (ja) * 2002-07-11 2004-02-12 Renesas Technology Corp レベルシフタ回路
JP4830504B2 (ja) * 2006-01-18 2011-12-07 ソニー株式会社 レベル変換回路および表示装置
JP4289410B2 (ja) 2007-03-12 2009-07-01 セイコーエプソン株式会社 レベルシフト回路、電気光学装置、およびレベルシフト方法
JP4986727B2 (ja) * 2007-06-15 2012-07-25 新日本無線株式会社 増幅回路
JP6755652B2 (ja) * 2015-11-20 2020-09-16 ラピスセミコンダクタ株式会社 表示ドライバ
KR102392661B1 (ko) * 2017-07-18 2022-04-29 삼성전자주식회사 비휘발성 메모리 장치의 전압 생성기, 비휘발성 메모리 장치 및 비휘발성 메모리 장치의 동작 방법
CN110752843B (zh) * 2019-11-26 2023-09-19 上海华力微电子有限公司 电平转换电路

Also Published As

Publication number Publication date
DE4434117A1 (de) 1995-03-30
JPH0798983A (ja) 1995-04-11
KR950009728A (ko) 1995-04-24
DE4434117C2 (de) 1997-06-19

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A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee