KR0135674B1 - Bicmos semiconductor memory device - Google Patents

Abstract

The level converting circuit comprises a MOS transistor Q3 that receives an input signal at its gate, a MOS transistor Q1 conducting according to a reference voltage (Vref) and an input signal, and a MOS transistor that constitutes a current mirror in which the current from the transistor Q1 functions as a current mirror current source. Q2 and Q4 and capacitive elements Cs and the like which transfer the input signal to the gates of the current mirror transistors Q2 and Q4 by capacitive coupling.

Transistor Q3 charges output node NB to the level of power supply potential Vcc, and transistor Q4 discharges output node NB to the level of second power source potential Vee.

When the input signal is at a high level, the gate potentials of the transistors Q2 and Q4 rise rapidly by capacitive coupling.

By reducing the amount of current supplied by the transistors Q1 and Q2, a level conversion circuit that operates at high speed with little consumption current can be realized.

When this level conversion circuit is applied to a semiconductor memory device, it is possible to obtain a semiconductor memory device which operates at a high speed while having a low current consumption.

The semiconductor memory device also includes a bit line load circuit, a redundant repairing circuit, and an internal power supply voltage conversion circuit for realizing low power consumption.

Description

BiCMOS semiconductor memory device

1 is a schematic view showing an overall structure of a semiconductor memory device according to the present invention.

2 is a view showing a specific structure of a level conversion circuit according to the present invention.

3 is a cross-sectional view of the main part of the level conversion circuit shown in FIG.

4 is a planar layout of the main part of the level conversion circuit shown in FIG.

5 shows the effect of the layout shown in FIGS. 3 and 4;

6 is another example of a level conversion circuit.

7 shows a third specific structure of the level conversion circuit.

8 shows a fourth specific structure of the level conversion circuit.

9 shows a fifth specific structure of the level conversion circuit.

10 shows a sixth specific structure of the level conversion circuit.

FIG. 11 is a cross-sectional structural view of the main part of the level conversion circuit shown in FIG.

12 is a planar layout of the main part of the level conversion circuit shown in FIG.

13A and 13B show a plan layout and a cross-sectional structure of a modification of the main part of the level conversion circuit shown in FIG.

14 shows the seventh specific structure.

15 shows an eighth specific structure of the level conversion circuit.

16 is a view showing a specific structure of a reference voltage generation circuit for level conversion

17A and 17B show a relationship between currents flowing in a level conversion circuit.

18 is a view showing a more specific structure of the reference voltage generating circuit shown in FIG.

19 is a view showing another specific structure of the reference voltage generation circuit for level conversion.

20 is a view showing another specific structure of the reference voltage generating circuit for level conversion.

21 is a view showing a specific structure of a reference voltage generation circuit.

22 is a view showing another specific structure of the reference voltage generating circuit.

FIG. 23 is a diagram showing a specific structure of one row of memory cells and a peripheral circuit of the semiconductor memory device; FIG.

24 is a signal waveform diagram showing operation in reading data in the structure shown in FIG.

FIG. 25 is a signal waveform diagram showing an operation during data recording in the structure shown in FIG.

26 is a view showing a transfer path of an internal address signal, internal write data, and an internal write enable signal.

27 is a signal waveform diagram showing a generation method of a read / write control signal used in FIG.

FIG. 28 is a signal waveform diagram showing another generation method of the read / write control signal shown in FIG.

29 is a diagram showing the structure of implementing the signal waveform in FIG.

30 is a signal waveform diagram showing operation of the circuit structure shown in FIG. 29. FIG.

31 is a view showing in detail the structure of the bit line pull up device and the bit line load circuit used in the present invention.

32 is a view showing a modification of the bit line pull-up element shown in FIG.

33 is a diagram showing a logic structure of a spare decode circuit and a normal decode circuit.

34 is a diagram showing the structure of a predecode signal.

35 shows a specific structure of a normal decode circuit.

36A and 36B show the specific structure of the preliminary decode circuit shown in FIG.

FIG. 37 shows another specific structure of the preliminary decode circuit of FIG.

38 is a view showing a specific structure of the preliminary activation circuit shown in FIG.

39 is a schematic view showing the structure of a memory block.

40A and 40B show the concept of operation of a shift redundancy circuit.

41 shows a specific structure of a shift redundancy circuit.

42 shows schematically the structure of the read / write gate located at the boundary of the I0 block and its connection to the internal data bus.

43 shows the specific structure of the bit line load circuit and the write gate of the bit line pair located at the boundary of the IO block shown in FIG. 42;

44 is a view showing a modification of the bit line load circuit shown in FIG. 43;

45 shows an example of an activation control circuit constructed in accordance with the present invention.

46 shows another application of the activation control circuit used in the present invention.

47 is a view showing a specific structure of the activation control circuit shown in FIGS. 45 and 46. FIG.

48 is a diagram showing the specific structure of the activation control circuit shown in FIGS. 45 and 46;

49 is a view showing a specific structure of an address input buffer.

50 is a view showing a specific structure of a V address input signal buffer.

51 is a view showing a modification of the V address input signal buffer shown in FIG. 50;

52 is a view showing a specific structure of the Cs buffer shown in FIG.

53 is a view showing a specific structure of the X predecoder shown in FIG.

FIG. 54 is a diagram for explaining the concatenation OR predecode operation shown in FIG. 53; FIG.

Fig. 55 is a diagram showing the logical state of the combination of the signals on the predecode line of Fig. 53 and the signals of the selector;

56 is a view showing the structure of the WE buffer shown in FIG.

57 is a diagram showing the schematic structure of the mode detection circuit shown in FIG.

58 is a diagram showing the specific structure of the first and second detection circuits shown in FIG. 57;

59 is a diagram showing the specific structure of an operation mode designating signal generating circuit shown in FIGS.

60 is a view showing a specific structure of the memory cell potential supply circuit shown in FIG.

61 is a view showing the specific structure of the mode detection circuit and the step-down circuit shown in FIG.

62 is a view showing the specific structure of the voltage switching circuit shown in FIG.

63 is a view showing another specific structure of the mode detection circuit shown in FIG.

64 is a view showing the specific structure of an operation mode designating signal generating circuit when the mode detecting circuit of FIG. 63 is used;

The present invention relates to a semiconductor memory device, in particular a BiCMOS semiconductor memory device using a bipolar transistor and an MOS (insulated gate type field effect) transistor.

More specifically, the present invention relates to BiCMOS SRAMs, and more particularly to ECL RAM having an ECL interface.

Bipolar ICs (Integrated Circuit Devices) have the advantages of precise processing of analog signals and high current driving capability, enabling high-frequency signal processing and high-speed operation, while having low input impedance and high power consumption.

In contrast, MOS ICs have the advantages of high integration, high input impedance, and low power consumption, while being inadequate for analog signal processing.

Therefore, a "BiCMOS" circuit configuration method has been proposed to realize a semiconductor memory device having the advantages of a bipolar IC's MOS IC.

The "BiCMOS" technique is a type of circuit configuration in which bipolar elements and MOS elements exist on the same chip.

SRAM (static random access memory) exists in a semiconductor integrated circuit device using the "BiCMOS" technique.

BiCMOS SRAMs have been widely used in high-speed data processing systems because they have the advantage of low power consumption and fast operation (a few nanoseconds of access time).

In the SRAM cell, a transistor constituting a flip-flop, an access transistor for connecting a latch node (storage node) of the flip-flop to a bit line, and a latch node of the flip-flop are pulled to a power supply potential level. High resistance elements (high resistance loads or thin film transistors) for raising are required.

Therefore, the SRAM cell occupies a larger area than a DRAM (Dynamip Random Access Memory) cell having one access transistor and one capacitor.

Recently, with the development of high integration technology, various types of SRAMs having a large storage capacity and high integration have been proposed and realized, but there is still room for improvement in operation speed and integration power consumption of the conventional SRAM.

Therefore, the main object of the present invention is to provide an SRAM that operates at high speed with low power consumption.

A plurality of chips is used in the data processing system.

This is because the size of the circuit that can be integrated on one chip is limited and it is often advantageous to implement different functions using different technologies.

As an interface between chips in the system, a signal level different from the signal level in the chip is used.

CMOS interface level, TTL interface level, ECL interface level, etc. are representative examples of the interface level.

At the CMOS level, one power supply potential Vcc is used at the high level, and the other power supply potential Vee is used at the low level.

Since the potential amplitude is large, the MOS transistor is reliably turned off to interrupt the current path, thereby reducing current consumption.

At the ttl level, the high level of the input signal is 2.2V and the low level is 0.8V.

The TTL interface level is employed in a variety of systems because TTL logic has long been used in standard parts of data processing systems.

At the ECL level, the high level is typically -0.9V and the low level is typically -1.7V.

Since the signal of the ECL level has a small logic amplitude, it can be transmitted at high speed.

Therefore, in a system requiring high speed operation, an ECL level signal is used as a signal transmitted between devices in the system.

The ECL level and the CMOS level have different magnitudes of potential value and logic amplitude.

Therefore, a semiconductor integrated circuit device having an ECL interface needs a level conversion function that converts a signal of one logic level into a signal of another logic level so that an external signal and an internal signal are matched with each other.

In the ECL / SRAM, a level converting circuit for converting an input signal of the ECL level into an internal signal of the CMOS level is used in various parts.

Such level conversion circuit is constructed using a current mirror circuit.

In the current mirror type level conversion circuit, when the input signal is at the level E3CL or high, current flows from the input node to the second power source potential Vee through the current path of the current mirror circuit.

The output node is discharged to the level of the second power supply voltage Vee by the mirror current of the current.

When the input signal is at the ECL low level, no current flows in the current path of the current mirror circuit, and the output node is charged to the level of the first power supply voltage Vcc by a separate charging transistor.

In the current mirror type level conversion circuit, current flows in the current path of the current mirror circuit when the output node is discharged.

In order to reduce the current consumption, the current flowing through the current path of the current mirror circuit must be reduced.

However, when the current in the current path decreases, the charging / discharging speed of the gate potential of the transistor that generates the mirror current becomes slow, so that a longer time is required for switching the transistor that generates the mirror current to discharge the output node. Causes the problem to slow down.

Therefore, one of the specific objects of the present invention is to provide a level conversion circuit that operates at a high speed with a small current consumption.

In the SRAM, a load circuit for raising the potential of the bit line to the first power source potential Vcc is provided to speed up the data read rate.

This bit line load circuit increases the data read speed by reducing the amplitude of the bit line potential during data read.

Unlike DRAM, there is no RAS precharge period in SRAM.

Therefore, data read and write operations can be performed by continuously accessing memory cells of different rows without intermediate intervals.

During data writing, the potential of one of the selected bit line pairs is discharged from the precharge level Vcc to the second power source potential Vee by a write driver.

After the write operation is completed, the potential of the bit line discharged to the second power supply voltage Vee is charged to the level of the first power supply voltage Vcc again by the bit line load circuit.

If a word line is selected before the bit line potential is fully recovered when the data read operation is performed immediately after the data write operation, data in the selected memory cell may be read incorrectly or the data read time may be delayed (bit The time required for the line potential to change to the potential corresponding to the read data becomes longer).

Therefore, to reduce the access time, it is necessary to raise the bit line potential at high speed after data writing is completed.

An example of the proposed configuration for solving the write recovery, that is, the recovery of the bit line potential after the completion of the write operation is disclosed in Japanese Patent Publication No. 3-29189.

Japanese Patent Publication No. In the example disclosed in No. 3-29189, the output from the write driver is set to " H " after completion of the data write operation, and the write driver remains connected to the bit line for a period of time after the write is completed.

Charging of the bitline is performed using both the bitline load circuit and the write driver.

However, since the bit line potential is raised to the level of the first power source potential Vcc, it takes time to make the bit line potentials the same, and thus it is difficult to say that effective post-record recovery is realized.

In Japanese Patent Laid-Open No. 63-211190, the bit line charging operation by the bit line load circuit is prohibited while the sense amplifier is operating for data reading, and the bit line for charging the bit line after completion of the sense amplifier operation is disclosed. The structure in which the bit line charging operation of the load circuit is started is shown.

However, this prior art only deals with the filling of the bitline during data readout and no consideration of the post-write recovery problem is seen.

Therefore, another specific object of the present invention is to provide a structure that provides sufficient margin for recovery after recording.

In ECL and SRAM, the logic level (high / low level) of the input signal is determined, a constant current is supplied to the bipolar differential amplifying circuit, the ECL level signal is converted into a CMOS level signal, and the like. A reference voltage is needed for the purpose.

For correct operation, this reference voltage must be kept constant and not affected by the power supply voltage.

In general, since the transistor size and circuit configuration of the portion generating the reference voltage and the portion using the reference voltage are different, the dependence of the reference voltage on temperature is different from the dependence on the temperature of the operating characteristics of the transistors in the portion using the reference voltage. There are many cases.

Therefore, the operating characteristics of the portion using the reference voltage change as the operating temperature changes, and as a result, accurate operation cannot be guaranteed.

Therefore, another specific object of the present invention is to provide a reference voltage generating circuit which can accurately generate the required reference voltage without being influenced by the power supply voltage.

Another specific object of the present invention is to provide a reference voltage generation circuit that can adjust the reference voltage according to the operation characteristics of the portion using the reference voltage.

In a semiconductor memory device, when a defective memory cell exists, the defective memory cell is replaced with a spare memory cell, thereby increasing the yield of the semiconductor memory device.

A decoded circuit (a defective decode circuit) for selecting a defective memory cell is replaced by a spare decode circuit.

Various structures have been proposed for the spare decode circuit.

One of these proposals has the same logical structure as the spare and ordinary decode circuits.

As the two decode circuits have the same structure, the operation speed when the spare decode circuit is selected is the same each time the ordinary decode circuit is selected.

The decode circuit includes one NAND gate and one NOR gate.

When the logic circuit is composed of a NAND gate and a NOR gate, in order to provide the same driving capability as an inverter, the transistors in the NOR gate and the NAND gate must be larger in size (a part in which a plurality of transistors are connected in series). Therefore, it is necessary to compensate for the current loss in the transistor connected in series.

When a large transistor is used, the output load of a circuit of a front end such as a predecoder becomes large (as the gate capacitance increases as the size of the MOS transistor increases).

As a result, the rise of the output signal of the preceding circuit is delayed and the access time becomes long.

In addition, since a large output load must be driven (for charging / discharging), a problem arises in that the current consumption increases.

It is therefore a further object of the present invention to provide a decode circuit capable of operating at high speed with low current consumption.

As one of the methods of repairing a defective memory cell, a so-called "shift redundancy type relief circuit" in which a connection of a decoder output node is switched and moved sideways is known.

In general, a block division configuration in which only a selected block is driven is adopted in the semiconductor memory device in view of power consumption.

One block includes a plurality of I0 blocks respectively corresponding to the plurality of data input / output pins.

In view of yield and high integration of SRAM, it is required to effectively repair defective memory cells.

When one preliminary column (bit line pair) is provided in one memory block and a defective bit line pair is repaired by the shift redundancy method, the following problem occurs.

Consider I0 blocks # 1 and # 2 corresponding to I0 pins # 1 and # 2.

If a defective memory cell does not exist, the bit line pair of the first column of I0 block # 2 is connected to the data bus connected to I0 pm # 2.

If a defective memory cell exists in block # 1, the connection of the output node of the column decoder is switched so that the bit line pair of the first column of I0 block # 2 is connected to the data bus connected to I0 pm # 1.

A load circuit is provided for the SRAM bit line pair.

Therefore, it is necessary to drive the load circuit of I0 block # 2 by two column select signals.

As a result, the load circuit of the bit line pair of the first column of I0 block # 2 has a more complicated structure than the load circuits of the other bit line pairs.

Therefore, another specific object of the present invention is to provide a bit line load circuit capable of implementing a shift redundancy method without degrading operation characteristics with a simple circuit structure.

Accurate reference voltage generation is required in a reference voltage generation circuit such as an SRAM.

In DRAM, a structure in which the reference voltage is trimmed to “laser-blowing” resistors arranged in parallel is used (see Japanese Patent Publication No. 4-102300).

However, when trimming by the reference voltage "laser blowing", it is impossible to readjust the reference voltage.

In addition, when an optimal transistor element in a plurality of transistor elements is selected as the reference voltage generation source, it is necessary to select a transistor having an optimum operating characteristic beforehand, and after selection, it is impossible to replace another transistor.

Therefore, a circuit having optimum operating characteristics cannot be easily formed.

Therefore, another detailed object of the present invention is to provide a structure that can easily implement a circuit having an optimal operating characteristics.

In a semiconductor memory device, it is necessary to find out whether the device operates normally.

For this purpose, the semiconductor memory device should be able to be set to the test mode by an external signal.

The test mode includes a life test under accelerated test conditions (high voltage and high temperature), a burn in mode for screening out initial defects, a hold test mode for inspecting a data holding device of a memory cell, and the like. There is a kind.

In addition, a circuit capable of setting the plurality of test modes without increasing the number of pins should be implemented without affecting the operation of other circuits in normal operation.

The above applies to setting not only the test mode but also the special operation mode of the semiconductor memory device.

Therefore, another detailed object of the present invention is to provide a special mode setting circuit which does not affect the operation of other circuits while reliably setting the special mode with a simple circuit structure.

One of the objects of the present invention is to provide a BiCMOS semiconductor memory device having a structure which achieves each of the objects described above.

It is another object of the present invention to provide an improved BiCMOS SRAM and to provide its components for obtaining improved performance.

According to an embodiment of the present invention, a semiconductor memory device may include a plurality of bit lines connected to memory cells of each column, a column decoder configured to generate a column selection signal for selecting one column of a memory cell according to a column address signal; And a potential conversion circuit for driving the potential level of the bit line pair corresponding to the column selected by the column selection signal to a second potential level lower at the given potential level during the data write operation.

Since data proxy data is written in the state where the bit line potential is low, the potential difference between the bit lines of the selected bit line pair is reduced, and the bit line potential can be made the same at high speed after the data writing is completed, thus recovering problems after writing. Can be improved.

Each component for achieving the above described specific purpose is also included in the features of the invention.

Since the present invention includes these components, it is possible to obtain a semiconductor memory device having low current consumption and high reliability by operating stably at high speed.

The above, the features, aspects and advantages of the present invention will become more apparent when the following description is taken in conjunction with the accompanying drawings.

1 is a block diagram schematically showing the overall structure of a semiconductor memory device according to one embodiment of the present invention.

Referring to FIG. 1, this semiconductor memory device includes a memory plane 1.

The memory plane 1 includes a plurality of memory blocks 10.

In FIG. 1, only one memory block 10 is shown as a representative.

The memory block 10 includes a memory array 2 including memory cells MC arranged in a matrix form.

The memory array 2 includes a word line WL connected to one row of memory cells MC and a bit line pair BLP connected to one column of memory cells MC.

In FIG. 1, one memory line MC disposed at the intersection of one word line WL, one bit line pair BLP, a bit line pair BLP and a word line WL is shown as a representative example.

As described later, memory array 2 includes a plurality of I0 blocks.

Each I0 block corresponds to a different data input / output pin.

In operation, one memory block is selected in memory plane 1, and one bit memory cell is selected in each I0 block in memory array 2.

Memory block 10 that is not selected remains in the standby state.

Memory block 10 also includes bit line load circuit 3, which includes circuits for equalizing and adjusting the amplitude of each bit line potential of bit line pair BLP, and decoding the column address signal to select the corresponding bit line pair of memory array 2. The Y decoder 6 generating the column select signal, the shift redundancy circuit 5 for delivering the output from the Y decoder 6, and the corresponding bit line pair according to the column select signal transmitted from the shift redundancy circuit 5 are stored in the internal local data bus 8. And a read / write control circuit 7 for controlling the opening / closing state of the write / read gate 4 and read / write gate 4 connected to and 9 and adjusting the potential of the bit line pair after completion of data writing.

The shift redundancy circuit 5 includes a plurality of switching gates for selectively delivering a column select signal from the Y decoder 6 to one of the two bit line pairs, to thereby repair the defective bit line pair.

The read / write control circuit 7 is activated in accordance with the block select signal.

The semiconductor memory device further includes a Cs buffer 12 receiving the external chip select signal / Cs and an address buffer 14 receiving the address signals A0 to An of a plurality of bits for generating the internal address signal.

Internal address signals from the address buffer 14 are applied to the Y predecoder 15, the Z predecoder 16, the V predecoder 17, the X predecoder 18, and the like.

The Y predecoder 15 predecodes the column address signal from the address buffer 14, and generates a predecode signal specifying one bit line pair in each memory block.

The output from Y predecoder 15 is applied to Y decoder 6.

The Z predecoder 16 predecodes an address signal for designating one block in the address buffer 14.

A predecoder signal for selecting the memory block designated by the block address signal in the memory plane 1 is generated in the Z predecoder 16 and applied to the Z decoder 25.

The Z decoder 25 predecodes the predecoder signal from the Z predecoder 16 to generate a block select signal for activating the peripheral circuits (Y decoder, read / write control circuit 7, etc.) of the selected memory block.

The X predecoder 18 generates a predecode signal for selecting a main word line that is commonly installed in a plurality of memory blocks of the memory plane 1.

The predecode signal output from the X predecoder 18 is applied to the X decoder 24.

X decoder 24 decodes the predecode signal from X predecoder 18 and selects one main word line.

Each memory block is connected to a plurality of dependent word line main word lines.

The V predecoder 17 generates a predecode signal for selecting one of a plurality of word lines connected to the main word line.

The predecode signal from the V predecoder 17 is applied to the VZ decoder 26.

VZ decoder 26 decodes the predecode signal from Z predecoder 16 and the predecode signal from V predecoder 17 to generate a decode signal that specifies a memory block and one of a plurality of dependent word lines.

The output of VZ decoder 26 and the output of X decoder 24 are applied to the local X decoder 27.

According to the readout signal from the VZ decoder 27 and the readout signal from the X decoder 24, the local X decoder 27 generates a signal for bringing the dependent word lines of the corresponding memory block 10 into the selected state.

To the X predecoder 18, an internal control signal (Cs word line cut mode designation signal: to be described later) is applied from the Cs buffer 12.

As a result, the output from X predecoder 18 is selectively activated / deactivated.

The address buffer 14 performs a buffer operation on an external address signal and generates the internal address signal.

This is to speed up the operation speed of the address buffer.

In Fig. 1, the control signal from the Cs buffer 12 is to be applied only to the X predecoder 18.

Internal control signals from the CS buffer 12 can also be applied to the Y predecoder 15, the Z predecoder 16 and the V predecoder 17.

The semiconductor memory device also receives a WE buffer 28 that receives an external write enable signal / WE for generating an internal writeable signal, an external write data Q received from the Din buffer 29 and internal read data by receiving the external input data D. It additionally includes a Dout buffer 30 and the like.

Data recording is specified when both the internal writeable signal from the WE buffer 28 and the external control signal / Cs go low.

When the external control signal / Cs is at the low level and the writeable signal / WE is at the high level, the data reading operation is specified.

The chip select signal / Cs for data writing / reading is applied via a path separate from the Cs buffer 12 shown in FIG.

The semiconductor memory device is activated in response to an internal write enable signal (more precisely with the chip select signal Cs) from the WE buffer 28, and receives the internal write data from the Din buffer 29 and writes the write data to each memory block. It is activated in response to the global write driver 31 to transmit, the internal write enable signal from the WE buffer 28, and the block select signal from the Z decoder 25, and receives the internal write data from the global write driver 31 to receive the local data of the memory block. A local write driver 33 that delivers recorded data to bus 8, a local sense amplifier 34 that is activated in response to the block select signal from Z decoder 25 and amplifies the read data on internal read data bus 9; To transfer the data obtained as a result of amplifying the internal readout from the local sense amplifier 34 to the Dout buffer 30. And a reverse sense amplifier 32.

Global write driver 31 and global sense amplifier 32 are commonly provided for each memory I0 in memory plane 1.

Local write driver 33 and local sense amplifier 34 are provided in one memory block I0 of memory plane 1.

This is to drive only the memory blocks selected for reducing power consumption.

In order to set a special mode of the semiconductor memory device, the semiconductor memory device sets a mode detecting circuit 35 that detects designation of a predetermined special mode according to an external control signal, and a designated operation mode according to the output of the mode detecting circuit 35. And a memory cell potential supply circuit 35 for changing a potential supplied to the memory cell MC in accordance with a control signal from the operation mode designation signal generating circuit 36. do.

The output of the operation mode designation signal generating circuit 36 is also applied to the Cs buffer 12.

The Cs buffer 12 limits the activation / deactivation of the X predecoder 128 according to the signal from the operation mode designation signal generating circuit 36.

The special mode set in this manner will be described later in detail.

The semiconductor memory device further includes a reference voltage generating circuit 38 for generating reference voltages Vref and Vcs for driving a constant current source used in a bipolar differential amplifier circuit and for determining the level of an input signal.

The structure of each part is described in detail below.

[Level conversion circuit]

When an ECL level signal is to be input to the BiCMOS SRAM, the ECL level signal must be converted to the CMOS level in order to surely turn off the internal CMOS transistor.

The level conversion circuit will be described below.

2 shows a first embodiment of the level conversion circuit according to the present invention.

Referring to FIG. 2, this level conversion circuit is conducted in response to a signal applied to the input node NA to refer to the p-channel MOS transistor Q3, which charges the output node NB to the first power supply potential level Vcc, and to the gate. A p-channel MOS transistor Q1 selectively conducting in response to the level of the signal In applied to the input node NA upon receiving the voltage Vref, and an n-channel MOS transistor Q2 discharging the current from the transistor Q1 to the second power supply potential level Vee. In order to discharge the output node NB to the level of the second power source potential Vee, n-channel MOS transistor Q4 connected to the transistor Q2 and the current mirror type, and capacitor Cs provided between the input node NA and the internal node NC, and the like.

The internal node NC is connected to the gates of transistors Q2 and Q4.

The signal In applied to the input node NA is an ECL level signal having a high level of about -0.8V and a low level of about -2.0V.

The reference voltage Vref applied to the gate of transistor Q1 is in the range of about -2.5 to about -2.9V, although depending on the threshold voltage of transistor Q1.

For example, the gate width of transistor Q3 is set to about 40 mu m, the gate width of transistors Q1 and Q4 is set to about 20 mu m, and the gate width of transistor Q2 is set to 5 mu m.

Capacitor Cs has a capacitance of 0.3 pF.

The gate widths of the transistors Q1 and Q2 are made small enough to reduce the current flowing through the transistors Q1 and Q2 to reduce the current consumption.

Capacitor Cs transfers the signal applied to the input node NA to the gate of transistor Q4 by capacitive coupling, thereby changing the potential of the node NC (gate of transistor Q4) to high speed, thereby enabling fast switching of transistor Q4. .

This operation is described below.

When the signal In applied to the input node NA is at the ECL low level, the transistor Q3 is turned on and the output node NB is charged to the level of the first power source potential Vcc.

When the input signal In is at the ECL low level, since the difference between the input signal In and the reference voltage Vref is smaller than the absolute value of the threshold voltage of the transistor Q1, the transistor Q1 is turned off and the transistors Q2 and Q4 are turned off.

When the input signal In applied to the input node NA is at the ECL high level, the transistor Q3 is turned off.

On the other hand, transistor Q1 is turned on, so that the potential of node NC rises and transistors Q2 and Q4 turn on.

Since the gate widths of the transistors Q1 and Q2 are made small, the current flowing from the input node NA to the second potential potential Vee can be made sufficiently small.

The potential at the node NC (gates of transistors Q2 and Q4) rises relatively slowly by the charging current through transistor Q1.

At this time, since the potential rise of the input node NA is transferred to the internal node NC by the capacitive coupling of the capacitor Cs, the transistor Q4 is turned on at a high speed.

Therefore, the potential of the output node NB can be discharged at high speed to the level of the second power source potential Vee at high speed.

As described above, since the current from the input node NA to the second power potential becomes small, the through current from the first power potential supply node of the front end circuit to the second power potential Vee supply node of the level conversion circuit is It can be reduced, so that a low current consumption is realized.

The provision of the capacitor Cs compensates for the decrease in the gate potential rising speed of the transistor Q4 as the current decreases, so that the gate potential of the transistor Q4 rises at high speed when the potential of the node NA rises.

When the signal In of the input node NA falls to the low level, the potential of the node NC, that is, the gate of the transistor Q4, drops at a high speed due to the capacitive coupling of the capacitor Cs, so that the transistor Q4 is turned off at a high speed.

By using the level converting circuit of FIG. 2, a level converting circuit capable of switching at high speed with little current consumption is implemented.

FIG. 3 shows the structure of capacitor Cs shown in FIG.

Referring to FIG. 3, the capacitor Cs includes an electrode layer 52 formed of a first polysilicon layer on a semiconductor oxide film 51 on a semiconductor body (substrate or well region), and an interlayer. A polysilicon electrode layer 54 formed on the electrode layer 52 with an insulating film interposed therebetween, and an electrode layer 53 formed with a first aluminum interconnection layer on the electrode layer 54 with an interlayer insulating film interposed therebetween.

The electrode layers 52 and 53 are connected to the input node NA to form one electrode of the capacitor Cs.

The electrode layer 54 is connected to the internal node NC.

Capacitor Cs is composed of capacitance C2 formed between electrode layers 52 and 54 and capacitance C1 formed between electrode layers 54 and 53.

Capacitances C1 and C2 are connected in parallel.

The internal node NC is connected to the gates of transistors Q1 and Q2.

In Fig. 3, a brief structure of transistor Q2 is shown.

The transistor Q2 is composed of impurity regions 55 and 56 formed on the surface of the semiconductor body 50 and a gate electrode 57 formed on the channel region between the impurity regions 55 and 56 with the gate insulating film underneath.

The impurity region 55 is connected to the node NC, and the impurity region 56 is connected to receive the second power source potential Vee.

The gate electrode layer 57 and the electrode layer 52 are formed in the same wiring process.

4 is a plan layout of capacitor Cs.

4, the electrode layers 52, 54, 53 are formed in the order listed above in the manufacturing process.

The electrode layers 52 and 54 are connected to the input node NA at the contact hole 55.

The protrusion of the electrode layer 54 is connected to the node NC.

By placing the electrode layer 54 between the electrode layers 52 and 53, it is possible to increase the capacitance value of the capacitor while reducing the parasitic capacitance of the node NC.

5 shows an equivalent circuit of capacitor Cs.

Capacitor Cs is formed by the parallel connection of capacitances C1 and C2.

The capacitance value of capacitor Cs is given by C1 + C2.

Node NC has parasitic capacitance Cp.

Parasitic capacitance Cp is generated in the signal line connecting the nodes of transistors Q1 and Q2 to the gates of transistors Q2 and Q4.

The area of this signal line is sandwiched by electrode layers 52 and 53.

Since the electrode layer 54 is shielded from other signal lines, the parasitic capacitance Cp accompanying the signal lines can be sufficiently reduced.

Accordingly, when the potential of the node NA rises, the potential of the node NC can be made sufficiently high.

The potential change of the node NC is when the potential change of the node NA is V (NA).

CsV (NA) / (Cs + Cp)

Is given by

Therefore, when the parasitic capacitance Cp decreases, the potential change of the node NC can be large enough.

This enables high speed switching of transistor Q4.

6 shows a second specific configuration example of the level conversion circuit.

The level converting circuit of FIG. 6 conducts in response to the capacitor Cs provided between the input node NA and the allocation node NC and the low level of the signal In at the input node NA to charge the node NB to the level of the first power potential Vcc. P-channel MOS transistors Q3 and n-channel MOS transistors Q2 and Q4 constituting a current mirror circuit for discharging the node NB to the level of the second power source potential Vee according to the potential of the node NC.

The structures of the transistors Q2 to Q4 and the capacitor Cs are as shown in FIG.

The level converting circuit of FIG. 6 supplies an npn biplane transistor Q6 for clamping the node NC to a predetermined potential level, an inverter IV for inverting the potential of the node NB, and a node NB in response to an output from the inverter IV. And further includes an n-channel MOS transistor Q5 which discharges at the level of the potential Vee.

The output signal Out is output from the inverter IV to the node ND.

A constant reference voltage VCL is applied to the base of the transistor Q6.

Transistor Q6 clamps the potential of the node NC to the potential of VCL-VBE.

VBE represents the forward voltage drop between the base emitter of transistor Q6.

The clamp potential VCL-VBE of transistor Q6 is approximately set at the potential level of Vee + VtH.

Here, Vth represents threshold voltages of the transistors Q2 and Q4.

The operation is explained.

When the input signal In is at the ECL low level, the transistor Q3 is turned on to charge the node NB to the level of the first power source potential Vcc.

The potential rise of the node NB is inverted by the inverter IV and transferred to the output node ND to output the signal low at the CMOS low level.

At this time, transistors Q4 and A2 are turned off, while the potential of the node NC is at the clamp potential of transistor Q6.

When the input signal In is at the ECL high level, the potential of the node NC rises above the clamp potential by the capacitive coupling of the capacitor Cs, and the transistors Q2 and Q4 are turned on.

By the transistor Q4, the node NB is discharged to the level of the second power source potential Vee.

Since the gate width of the transistor Q2 is made small, the potential of the node NC gradually discharges.

During this period, the transistor Q6 is turned off because the emitter potential is raised.

During the period in which the potential of the node NC is discharged by the transistor Q2, the node NB is discharged through the transistor Q4.

When the potential of the node NB becomes lower than the input logic threshold voltage of the inverter IV, the output of the inverter IV rises to a high level, the transistor Q5 is turned on, and the node NB discharges the potential to the level of the second power supply potential.

As a result, the potential of the node NB is discharged at high speed, and the low potential of the node NB is latched by the IV and the transistor Q5.

Therefore, the CMOS high level produces the output signal Out.

When the input signal In falls from the high level to the low level, the potential of the node NC also drops.

At this time, since the potential of the node NC is clamped by the transistor Q6, no undershoot occurs in the node NC, so that the transistors Q2 and Q4 can be reliably turned off at high speed.

In the structure of FIG. 6, since there is no direct current path between the input node NA and the node supplying the second power source potential Vee, the current consumption can be greatly reduced.

7 shows a third embodiment of the level conversion circuit.

In addition to the structure of the level converting circuit shown in FIG. 6, the level converting circuit shown in FIG. 7 includes a capacitor Cc provided between the input NA and the transistor Q6, and a resistor R for transmitting the reference voltage VCL to the base of the transistor Q6. It includes.

The resistor R is provided as a separate resistor so that the potential change of the base of the transistor Q6 does not affect the circuit supplying the reference voltage VCL.

The operation is described below.

When the signal In of the input node NA rises from the low level of the ECL to the high level of the ECL, the potential of the node NC increases due to the capacitive coupling of the capacitor Cs, the transistors Q2 and Q4 become conductive, and the potential of the node NB decreases.

The lowered potential of the node NB is latched by the inverter IV and the transistor Q5 to output the high level output signal Out.

At this time, with the capacitor Cc, the base potential of the transistor Q6 also rises, and the clamp potential of the transistor Q6 rises.

If capacitors Cs and Cc have approximately the same capacitance value, the potential rise of node NC becomes approximately equal to the potential rise of base potential of transistor Q6, and transistor Q6 remains off.

Therefore, an operation similar to the level converting circuit shown in FIG. 6 can be implemented.

When signal In of input node NA falls from ECL high level to ECL low level, transistor Q3 is turned on to charge node NB.

At this time, the potential of the node NC is lowered by the capacity defect of the capacitor CS.

At this time, the base potential of the transistor Q6 is also lowered due to the capacitance defect of the capacitor Cc.

Therefore, the clamp potential of transistor Q6 is lowered and transistor Q6 is turned off.

The base potential of transistor Q6 is clamped to reference voltage level VCL by resistor R.

Therefore, fluctuation such as undershoot does not occur in the base potential of the transistor Q6.

When there is a possibility of an undershoot in the node NC, transistor Q6 is turned on to reliably prevent the undershoot.

In the level converting circuit of FIG. 7, when the input signal In falls to the low level, the base potential of the transistor Q6 goes down while the potential of the node NC goes down, so that the clamp potential falls.

Therefore, the output load of the transistor Q6 is reduced, and thus current consumption can be reduced.

8 shows a fourth concrete configuration example of the level conversion circuit.

Referring to FIG. 8, this level conversion circuit includes a P-channel MOS transistor QA for charging the node NB to the first power supply potential Vcc, and an n-channel MOS transistor OB for discharging the node NB to the level of the second power supply potential Vee. A capacitor CA which transfers the input signal In applied to the input node NA to the base of the transistor QA by capacitive coupling, and a capacitor CB and node NB which transfers the input signal n applied to the input node NA to the gate of the transistor OB by capacitive coupling. It consists of inverters I∀A, I∀B, etc., for latching the signal potential of.

The level conversion circuit further includes a resistor RA for clamping the gate of the transistor QA to the specified potential Vee-Vthp, and a resistor RB for clamping the gate potential of the transistor QB to the specified potential Vee + Vthn.

Here, Vthp and Vthn are threshold voltages of transistors QA and QB.

The clamp potential applied to the resistors RA and RB can be easily generated by connecting transistors having threshold voltages such as transistors QA and QB in the form of diodes.

The operation is briefly explained.

When the input signal In applied to the input node NA falls from the ECL high level to the ECL low level, the gate potential of the transistor QA drops by the capacitive coupling of the capacitor CA, and the transistor QA is turned on.

Thus, transistor QA remains on for a period of time.

By the transistor QA, the node NB is charged and its potential rises.

When the potential of the node NB exceeds the input logic threshold voltage of the inverter IVA, the output of the inverter IVA drops.

Inverter IVA has an amplifier function.

Therefore, the potential change of the node NB is amplified and inverted and transferred to the inverter IVB.

As a result, the potential of the node NB is latched at high speed by the inverters IVA and IVB to reach the CMOS high level, and the signal Out of the output node ND becomes the CMOS low level.

After the specified period has elapsed, the gate potential of the transistor QA returns to the original clamp potential by the resistor RA.

Transistor QA is turned off.

When the input signal In applied to the input node NA rises from the ECL low level to the ECL high level, the potentials of the transistors QA and QB rise by the capacitive coupling of the capacitors CA and CB.

Thus, the gate potential of transistor QA rises above the clamp potential level so that transistor QA is turned on while transistor QB is turned off.

As a result, the node NB is discharged to the level of the second power supply potential by the transistor QB, and the potential is lowered.

The potential drop of the node NB is amplified by the inverters IVA and IVB so that the potential of the node NB becomes the CMOS low level at high speed, and the output signal Out of the output node ND becomes the CMOS high level.

After the specified period has elapsed, the gate potentials of the transistors QA and QB return to their original clamp potentials.

In the structure of the level converting circuit shown in FIG. 8, there is no current path through which a direct current flows from the input node NA to the node supplying the second power source potential Vee.

Therefore, the current consumption can be greatly reduced.

The periods in which the transistors QA and QB are on are only a very short period from when the change of the input signal In occurs (since the gate potentials of the transistors QA and QB are clamped by the resistors RA and RB).

Therefore, the flow through transistors QA and QB is very small.

When the inverters IVA and IVB are composed of CMOS transistors, their through current can be greatly reduced.

Therefore, a level conversion circuit with very low current consumption can be implemented.

Since the reference voltage is not used to determine the level of the input signal, the threshold voltages of the transistors QA and QB can be set to any desired value, making circuit design easier.

9 shows a fifth example of the level conversion circuit.

The level converting circuit shown in Fig. 9 generates one output signal Out from the complementary input signals IN and / IN.

Referring to FIG. 9, the level conversion circuit includes a p-channel MOS transistor MQ1 that receives an input signal IN applied to an input node NA1 to a gate, and a p-channel MOS transistor MQ3 that receives a complementary input signal / IN applied to an input node NA2 to a gate. N-channel MOS transistor MQ2 supplied with current from transistor MQ1, n-channel MOS transistor MQ4 and the like.

Transistors MQ2 and MQ4 form a current mirror circuit in which transistor MQ1 acts as a current supply path.

The level converting circuit of FIG. 9 further includes a capacitor Cs provided between the input node NA2 and the internal node NC (gate electrodes of transistors MQ2 and MQ4).

The output signal Out is provided at the node between transistors MQ3 and MQ4.

The current driving capability of transistors MQ1 and MQ2 is made small.

The operation is explained.

When the input signal IN rises from the ECL low level to the ECL high level, the transistor MQ1 is turned off and the transistor MQ3 is turned on.

The complementary input signal / IN applied to the input node NA2 is transferred to the transistors MQ2 and MQ4 by the capacitance defect of the capacitor Cs, and the transistors MQ2 and MQ4 are turned off because the gate potentials of the transistors MQ2 and MQ4 are dropped at high speed.

Accordingly, the node NB is charged by the transistor MQ3 to provide an output signal Out of CMOS high level.

When the input signal IN falls from the ECL high level to the ECL low level, transistor MQ1 is turned on and transistor MQ3 is turned off.

Since the input signal / IN rises to a high level, the potential of the node NC rises due to the capacitive coupling of the capacitor Cs, and as a result, the transistors MQ2 and MQ4 are turned on.

Therefore, the output node NB is discharged to the level of the second power supply potential Vee through the transistor MQ4 to obtain the CMOS low level.

When transistor MQ1 is turned on in the level converting circuit of FIG. 9, transistor MQ2 is also turned on.

Therefore, the through current flows from the first power source potential Vcc to the second power source potential Vee.

However, by making the gate widths of the transistors MQ1 and MQ2 sufficiently small, this through current can be minimized.

In this case, the potential of the node NC rises at high speed by the capacitive coupling of the capacitor Cs.

Therefore, transistor MQ4 can be switched quickly while consuming a small current.

In particular, when the gate width of transistor MQ4 is made wider than the gate width of transistor MQ2, the ratio of the current flowing through transistor MQ2 to the current flowing through transistor MQ4 is given by the ratio of the gate widths of transistors MQ2 and MQ4, so that the output node NB Can be discharged at high speed.

10 shows a sixth example of the level conversion circuit.

The level converting circuit of FIG. 10 also has a function of performing AND operation of signals IN1 and IN2 which are ECL level signals.

Referring to FIG. 10, this level converting circuit receives p-channel MOS transistors PQ1 and PQ2 for receiving the input signals In1 and IN2 at the ECL level, respectively, and complementary input signals / IN1 and / IN2 at the ECL level, respectively. p-channel transistors PQ3 and PQ4.

When the transistors PQ1 and PQ2 are placed in parallel, the transistors PQ3 and PQ4 are placed in series between the first power supply potential supply node and the output node NB.

The level conversion circuit further includes n-channel MOS transistors Q2 and Q4 constituting a current mirror circuit in which transistors PQ1 and PQ2 operate as their current sources, and diodes D1 and D2 receiving complementary input signals / IN1 and / IN2, respectively. .

The outputs of diodes D1 and D2 are connected in a connected OR (wired-OR) form.

This level conversion circuit further includes a capacitor Cs provided between the output portions (node E) of the diodes D1 and D2 and the note NC.

The gate widths of the transistors PQ1, PQ2, and Q2 are made small, and the current driving capability becomes small.

The operation is explained.

When at least one of the input signals IN1 and In2 is at the ECL low level, at least one of the transistors PQ1 and PQ2 is turned on to supply current from the first power supply supply node to the transistor Q2.

In this case, since at least one of the complementary input signals / IN1 and / IN2 is at the high level, the potential of the node NE rises through the diodes D1 and / or D2, and the potential of the node NC is caused by the capacitive coupling of the capacitor Cs. To rise.

Thus, transistor Q4 is turned on at high speed.

One or more of transistors PQ3 and PQ4 are turned off.

Therefore, output node NB is discharged at high speed through transistor Q4 to provide an output signal Out of CMOS low level.

When the input signals IN and IN2 are both at the ECL high level, both the transistors PQ1 and PQ2 are turned off, and both the transistors PQ3 and PQ4 are turned on.

In this case, the potential of the node NC is discharged through the transistor Q2, so that the transistors Q2 and Q4 are turned off. The output node NB is charged through the transistors PQ3 and PQ4, and the output signal Out of the CMOS high level is output.

In the level conversion circuit shown in FIG. 10, no current flows between the node for supplying the second power source potential Vee from the signal input node, so that current consumption can be significantly reduced.

At this time, since the driving capability of each transistor PQ1, PQ2, Q2 can be made small, the through-current flowing from the node supplying the first power supply potential Vcc to the node supplying the second power supply potential Vee can be made sufficiently small.

FIG. 11 shows a schematic cross-sectional structure of the capacitor and diode shown in FIG.

Referring to FIG. 11, the capacitor Cs is composed of an electrode layer 65 formed of a first polysilicon layer on a semiconductor body (substrate or well) 60 and an electrode 64 formed of a first aluminum band layer on the electrode 65 with an interlayer insulating film therebetween. do.

The electrode layer 64 is connected to the node NE shown in FIG. 10 and the electrode layer 65 is connected to the node NC.

The diode D1 is composed of a P-type impurity region 61 formed on the surface of the semiconductor body 60 and an n-type impurity region 63 formed on the surface of the semiconductor body 60.

The diode D2 is composed of a p-type impurity region 62 and an n-type impurity region 63 formed on the surface of the semiconductor body 60.

In this example, it is assumed that diodes D1 and D2 are formed on the n-type semiconductor body 60.

Diodes D1 and D2 may also be formed in the n-type well region formed on the surface of the semiconductor body 60.

FIG. 12 is a planar layout of the capacitor and diode shown in FIG.

In FIG. 12, p-type impurity regions 61 and 62 and n-type impurity regions 63 (not clearly shown) are formed next to one side of the capacitor Cs.

The electrode layer 64 is connected to the n-type impurity region 63 through the contact hole (indicated by the node NE) at the protruding portion.

The electrode layer 65 is connected to the node NC at the protrusion (12th left part).

In the structure of the capacitor shown in FIGS. 11 and 12, the wiring layer connected to the node NC can be shielded by the electrode layer 64 made of the first aluminum wiring layer.

Therefore, the parasitic capacity accompanying the node NC can be changed at high speed by the capacity defect.

13A and 13B show another arrangement of a capacitor and a diode. FIG. 13A shows a planar layout and FIG. 13B shows a cross-sectional structure of a diode portion.

13A and 13B, the n-type impurity region 63 forming the cathodes of the diodes D1 and D2 is between the p-type impurity regions 61 and 62 forming the anodes of the diodes D1 and D2. Is formed.

The n-type impurity region 63 is connected to the electrode layer 64.

In the arrangement shown in FIGS. 13A and 13B, the distance D1 between the p-type impurity region 61 and the n-type impurity region can be made equal to the distance D2 between the p-type impurity region 62 and the n-type impurity region 63.

Thus, diodes D1 and D2 have similar operating characteristics.

14 shows a seventh example of the level conversion circuit.

Referring to FIG. 14, this level converting circuit comprises a p-channel MOS transistor PQ5 receiving an ECL level input signal IN1 at a gate, a p-channel MOS transistor PQ6 receiving an ECL level input signal IN2 at a gate, and an input signal IN1. And a diode D3 receiving the wood and a diode D4 receiving the input signal IN2.

Transistors PQ5 and PQ6 are connected in series between the node supplying the first power supply potential Vcc and the output node NB.

The cathodes of diodes D3 and D4 are connected to each other to form a connecting OR logic gate.

This level conversion circuit is connected to a p-channel MOS transistor Q1 in which a gate is connected to receive a reference voltage Vref, and one conducting terminal is connected to the node NF (the cathodes of the diodes D3 and D4) and the other conducting terminal is connected to the node NC. Capacitor Cs provided between the node NF and the NC, and one channel and the gate are connected to the node NC and the other channel is connected to the node supplying the second power supply potential Vee. A p-channel MOS transistor Q4 and the like, wherein the conducting terminal is connected to the output node NB, the gate is connected to the node NC, and the other conducting terminal is connected to the node supplying the second power supply potential Vee.

Transistors Q2 and Q4 form a current mirror circuit.

The operation is explained.

When at least one of the input signals In1 and IN2 is at a high level, at least one of the transistors PQ5 and PQ6 is turned off to interrupt the current path between the node supplying the first power supply potential Vcc and the output node NB.

Since one of the diodes D3 and D4 is conducted, the potential of the node NF rises to a high level, and the transistor Q1 is turned on to supply current to the transistor Q2.

At this time, the potential of the node NC rises at high speed due to the capacitance defect of the capacitor Cs, and the transistors Q2 and Q4 are turned on.

The output node NB is discharged by the transistor Q4, and the signal Out of the CMOS low level is output.

When both input signals In1 and IN2 are at low level, transistors PQt and PQ6 are turned on, while diodes D3 and D4 shift input signals IN1 and IN2 to the node NF, so transistor Q1 is turned off and in response Transistors Q2 and Q4 are turned off.

As a result, the signal High at the CMOS high level is output from the output node NB by the transistors PQ5 and PQ6.

In the level converting circuit shown in FIG. 14, the potential level of the node NF has the same value when (a) the input signals IN1 and IN2 are both at high level and (b) when one of the input signals IN1 and IN2 is at the high level. Has

Therefore, since transistor Q1 supplies the same current in the case of (a) and (b), transistor Q4 can be turned on at the same speed in case of (a) and (b).

Therefore, occurrence of skew of the output signal depending on the combination of logic states of the input signal can be prevented.

Transistor Q4 can be switched at high speed by capacitor Cs.

15 shows an eighth example of the level conversion circuit.

The level converting circuit shown in FIG. 15 has the same structure as the level converting circuit shown in FIG. 14 except that no capacitor Cs is provided.

In the level converting circuit shown in Fig. 15, the connection OR logic is constituted by diodes D3 and D4.

Therefore, regardless of the combination of the logic states of the input signals IN1 and IN2, the current flowing through the transistor Q1 can be made constant, so that the switching speed of the transistor Q4 can be made constant regardless of the logical combination of the input signals IN1 and IN2. have.

Accordingly, skewing of the output signal Out can be prevented.

The current driving capability of the transistor Q1 of the level converting circuit shown in FIG. 15 is made larger than the transistor Q1 of the level converting circuit shown in FIG.

This enables high speed switching of transistor Q4.

Current consumption is slightly increased, but skewing of the output signal Out can be reliably prevented.

The structure of the level converter circuit shown in FIG. 14 and FIG. 15 is also applicable to a level converter circuit having a function of logic processing complementary input signals.

For example, a level converting circuit which completely prevents skew generation and has a function of processing a complementary input signal replaces transistors PQ1 and PQ2 of the level converting circuit shown in FIG. It can be realized by applying the output of to the transistor Q1 receiving the reference voltage.

[Reference voltage generation circuit for level conversion circuit]

16 shows a specific example of the reference voltage generation circuit for the level conversion circuit.

Referring to FIG. 16, the level conversion circuit 65 has a structure similar to that of the level conversion circuit shown in FIG.

The reference voltage generation circuit 70 includes a p-channel MOS transistor MP1 provided in correspondence with the transistor Q1 and a p-channel MOS transistor MP2 provided in correspondence with the transistor Q2.

Transistors MP1 and MP2 have similar magnitudes (or ratios of the same magnitude) as transistors Q1 and Q2, respectively, and supply the same currents (or currents with the same current ratio) as currents I1 and I3 supplied by transistors Q1 and Q2, respectively. do.

Transistor MP1 receives the reference voltage Vref at its gate, and receives the high level potential of the input signal In applied to the level conversion circuit 65 to one of the conducting terminals. Transistor MP2 receives the low level potential of input signal In at its gate.

In general, the high level potential VH is 0.8 beta lower than the power supply potential Vcc, and the low level potential VL is set to 1.2 be low (that is, Vcc-2.0 beta).

These potentials are equal to the potentials of the input signal IN applied to the level converting circuit 65 as the output of the emitter follower.

The reference voltage generating circuit 70 is generated by a resistor R1 for converting the current I1 supplied by the transistor MP1 into a voltage signal, a resistor R2 for converting the current I3 supplied by the transistor MP2 into a voltage signal and a resistor R2 at the positive input terminal. It further includes a differential amplifier circuit OP that receives the voltage applied.

The reference voltage Vref is generated by the differential amplifier circuit OP.

The reference voltage Vref from the differential amplifier circuit OP is applied to the gate of the transistor Q1 of the level converter circuit 65 and the gate of the transistor MP1.

The operation is explained.

First, the amount of current flowing in the level converting circuit will be described with reference to the seventeenth.

When the input signal is at the high level, transistors Q2 are turned off and transistors Q1, Q3 and Q4 are turned on.

For simplicity, the capacitor Cs is not considered.

In this state, as shown in FIG. 17A, current I1 flows through transistor Q1.

The current I2 flowing from the output node through the transistor Q4 to the second power source potential Vee is the mirror current of the current I1 and is determined by the ratio β of the transistors Q3 and Q4.

Inversely, when μη denotes the mobility of electrons, Cox denotes the capacitance by the gate oxide film, W denotes the gate width, and L denotes the gate length, β denotes μη˙Cox˙W / L. Is given by

More specifically, the currents I1 and I2 have a relationship of I2 = I1˙β (Q4) / β (Q3), and β (Q3) and β (Q4) represent β values of the transistors Q3 and Q4, respectively.

When the input signal applied to the level converting circuit is at the low level (Low), the output node is charged through transistor Q2, as shown in FIG. 17B.

The current I3 is given by I3 = β [(Vg-Vt) Vd-Vd 2/2], where Vg represents the gate-source voltage of transistor Q2 and Vt represents the absolute value of transistor Q2 in the unsaturated region. , Vd represents the potential difference between the first power source potential Vcc and the output node.

In the saturation region, the following current flows:

I3 = β (Vg-Vt) 2/2 mfos

Current I1 through transistor Q1 changes in a similar manner to current I3 when the gate potentials of transistors Q3 and Q4 rise.

More specifically, the current I1 flowing through the transistor Q1 is also determined by the β of the transistor Q1, the threshold voltage, the potential level of the input signal and the reference voltage Vref applied to the gate.

It is preferable that the rise time and fall time of the output node potential be the same.

For this purpose, the reference voltage Vref is set such that the currents I2 and I3 are equal.

In practice, when the transistor Q4 is turned on, the rise of the gate potential becomes slower than the rise of the gate potential of the transistor Q2 because of the resistance component and the capacitance component of the transistors Q1 and Q3.

Therefore, the reference voltage Vref is set so that the current I2 is slightly larger than the current I3.

The reference voltage generation circuit 70 shown in FIG. 16 adjusts the ratio of the charge / discharge currents I3 and I2 to be constant at the output node of the level conversion circuit 65.

The operation of the reference voltage generating circuit 70 will be described again with reference to the sixteenth.

The transistors MP1 and MP2 have the same β as the transistors Q1 and Q2 of the level converter circuit 65, respectively.

Therefore, current I1 flows through transistor MP1, and current flowing through transistor MP2 is given by I3.

The voltage ∀ (R1) = I1 전압 R1 + Vee, which is determined by the resistance value of the current I1 and the resistor R1, is applied to the positive input terminal of the differential amplifier circuit OP, and the resistance of the current I3 and the resistor R2 is applied to the negative input terminal. The voltage I3˙R1 + Vee = V (R2) determined by the value is applied.

If V (R1) > V (R2), the reference voltage Vref output from the differential amplifier circuit OP rises, so that the gate potential of the transistor MP1 rises.

As a result, the conductivity of the transistor MP1 becomes small, the current I1 becomes small, and the voltage V (R1) becomes low.

In contrast, when V (R1) < V (R20), the reference voltage Vref output from the differential amplifier circuit OP is lowered, the conductivity of the transistor MP1 is increased, and the current I1 is increased.

As a result, the voltage V (R1) rises.

Therefore, the reference voltage Vref from the differential amplifier circuit OP adjusts the gate potential of the transistor MP1 such that V (R1) = V (R2).

The currents I1 and I3 flowing through the transistors MP1 and MP2 are the same as the currents flowing through the transistors Q1 and Q2 of the level conversion circuit 65.

Therefore, the following three equations

I1˙R1 = I3˙R2 I2 = I1˙β (Q4) / β (Q3) I2 = I3

Depending on the resistance of the resistors R1 and R2

R1 / R2 = β (Q4) / β (Q3)

Should be set to satisfy.

When capacitor Cs is not provided, in practice, current I2 is set slightly larger than current I3, so the resistance values of resistors R1 and R2 are

R1 / R2 ≥β (Q4) / β (Q3)

Is set to satisfy.

When capacitor Cs for high speed operation is provided, the current I2 flowing through transistor Q4 can be determined to be large enough.

Therefore, in this case,

R1 / R2 <β (Q4) / β (Q3)

Even if is satisfied, the rise time and fall time of the output signal Out can be made equal.

In other words, the reference voltage Vref is set so that the current I2 is smaller than the current I3 in terms of the DC current.

In any case, the reference voltage Vref is controlled so that the ratio of the current I2 and the current I3 is constant.

Accordingly, even if the temperature characteristic of the transistor of the level conversion circuit 65 is different from the temperature characteristic of the reference voltage generator circuit 70, the reference voltage Vref from the reference voltage generator circuit 70 can adjust the output information source currents I2 and I3 to the predetermined values. In this way, a level conversion circuit that can stably operate can be realized.

The transistors MP1 and MP2 are formed through the same process as the transistors Q1 and Q2, that is, the same mask step.

If the level converting circuit 65 and the reference voltage generating circuit 70 are made close to each other, the transistors MP1 and MP2 having the same parameters as the transistors Q1 and Q2 are the parameters of the transistor due to some cause in manufacturing such as inaccuracy of mask alignment. Even if the fluctuations can be made.

FIG. 18 shows an example of a specific configuration of the reference voltage generating circuit shown in FIG.

Referring to FIG. 18, the reference voltage generating circuit 70 includes a high voltage generating circuit 72 for generating a high level voltage VH, a low voltage generating circuit 74 for generating a low level voltage VL, a differential amplifier stage 76 and an output terminal 77. .

The differential amplifier stage 76 and the output stage 77 constitute a differential amplifier circuit OP.

The high voltage generator circuit 72 is an npn bipolar transistor 102 in which a collector is connected to receive a first power supply potential Vcc, a base is connected to receive a first power supply potential Vcc through a resistor 101, and the emitter generates a high voltage VH, and a transistor. An n-channel MOS transistor 103 or the like provided between the node 102 and the node supplying the second power source potential Vee, receiving the reference voltage VCS at the gate, and operating as a constant current source.

In the high voltage generator circuit 72, the transistor 103 operates as a constant current source and the bipolar transistor 102 operates in the same way as the emitter follower.

The first power source potential Vcc is applied to the base of the bipolar transistor 102 through the resistor 101, and the high level potential VH becomes Vcc-VBE.

The low voltage generator circuit 74 is connected to a node at which the collector supplies the first power supply potential Vcc, and a base is connected to a node supplying the first power supply potential Vcc through a resistor 104 so that the emitter generates a low level voltage VL. The npn bipolar transistor 105, an n-channel MOS transistor 106 provided between the emitter of the bipolar transistor 105 and the node supplying the second power supply potential Vee and receiving a reference voltage VCS to the gate, supplies a resistor 104 and a second power supply potential Vee. N-channel MOS transistors 107 and the like, which are connected in series between the nodes and receive a reference voltage Vcs at their gates.

Transistors 106 and 107 act as constant current sources.

In this case, the base potential of the transistor 105 is lower than the first power source potential Vcc by the current flowing through the resistor 104.

If the current supplied from the constant current source transistor 107 is represented by I and the resistance value of the resistor 104 is represented by R 104, the low-level potential VL can be represented by VL-Vcc-I˙R 104 -VBE.

In general, a voltage drop of about 1.2 ∀ occurs in the resistor 104.

The base-emitter forward drop VBE of a bipolar transistor is about 0.8V.

Transistor MP1, which receives high level voltage VH, receives the reference voltage Vref at its gate and applies the output voltage as an input to differential amplifier stage 76.

The output of transistor MP1 is provided to an n-channel MVS transistor R1 that is resistor connected through an npn bipolar transistor 110 having a collector and a base connected to each other.

The base and collector of the bipolar transistor 110 are connected to one input of the differential amplifier stage 76.

The bipolar transistor 110 is provided for setting the operating point of the differential amplifier stage 76 to the optimum point by shifting the input potential of the differential amplifier stage 76.

Transistor MP2 supplies current to n-channel MOS transistor R2 that is resistance-connected through npn bipolar 111 where base and collector are connected to each other.

Transistor 11 is also provided to bring the operating point of the differential amplifier stage 76 to its optimum point and provides a potential level shift of the same magnitude as transistor 110.

One output terminal of the transistor MP2, that is, the base and the collector of the bipolar transistor 111, is connected to the other input terminal of the differential amplifier stage 76.

Since the resistors R1 and R2 are constituted by resistance-connected MOS transistors, it is possible to accurately create a resistor having the same β ratio as the transistors Q3 and Q4 constituting the current mirror circuit of the level conversion circuit.

The differential amplifier stage 76 has an n-channel MOS transistor 113 whose gate is connected to the base of the bipolar transistor 110 and forms one of the inputs of 76, and the n channel whose gate is connected to the base of the bipolar transistor 111 and forms the other input of 76. A MOS transistor 114, an n-channel MOS transistor 112 which receives a reference voltage VCS at its gate and serves as a constant current source for transistors 113 and 114, and a p-channel MOS transistor for supplying current from the first power supply potential Vcc to transistors 113 and 114 Includes 115 and 116.

Transistors 115 and 116 form a current mirror circuit.

Transistor 115 is resistor connected.

The differential amplifier stage 76 further includes a capacitor 118 provided between the gate of the transistor 114 and the output node NG, and a capacitor 117 provided between the output node NG and one of the conductive terminals of the transistor 113.

Capacitor 118 is provided to stabilize the output signal.

Capacitor 117 is provided to feed back the potential of output node NG to the gates of transistors 116 and 115.

By attaching capacitors 117 and 118, a sudden change in the potential of the output node NG can be prevented.

More specifically, when the potential of the output node NG rises sharply, the gate potential of the transistor 114 rises by the capacitor 118, thereby lowering the potential of the output node NG.

The sudden rise of the output node NG is transferred to the gates of the transistors 115 and 116 by the capacitor 117, thereby reducing the amount of current flowing through the transistor 116.

Even when transistor 113 is suddenly turned on / off, abrupt potential change of output node NG is prevented by capacitors 117 and 118.

Therefore, the voltage generated by the resistors R1 and R2 is stably differentially amplified without the influence of noise, for example, to generate a reference voltage.

The output stage 77 is provided between the npn bipolar transistor 120 which receives the voltage from the output node NG of the differential amplifier stage 76 at the base, and the node supplying the emitter of the bipolar transistor 120 and the second power supply potential Vee, and the reference voltage VCS at the gate. Is provided between the n-channel MOS transistor 121 receiving the n-channel MOS transistor 121, the npn bipolar transistor 122 receiving the voltage from the output node NG of the differential amplifier stage at the base, and the node supplying the emitter of the npn bipolar transistor 122 and the second power supply potential Vee. An n-channel MOS transistor 126 or the like that receives a reference voltage VCS at its gate.

Transistors 121 and 126 operate as constant current sources, and bipolar transistors 120 and 122 operate in the manner of emitter followers to generate a reference voltage Vref.

The reference voltage Vref generated at the emitter of the bipolar transistor 120 is applied to the gate of the transistor MP1.

The output stage 77 further includes a p-channel MOS transistor 123 connected in resistance, an npn bipolar transistor 124 receiving an output from the transistor 123 at the base, a resistor 125 connected between the emitter of the transistor 124 and the emitter of the transistor 122, and the like. .

Transistor 123, bipolar transistor 124, and resistor 125 constitute a clamp circuit that prevents the reference voltage Vref from dropping excessively. The clamping potential is generally provided in the following manner.

The base current of the bipolar transistor 124 flows through the diode-connected MOS transistor 123, which is 1 / hfe times the current flowing through the constant current source 126.

The voltage at which the MOS transistor 123 is almost turned on, Vcc- | Vthp |, is output and applied to the base of the MOS transistor 124.

The bipolar transistor 124 operates in an emitter follower manner and, at its emitter, outputs a potential Vcc-| Vthp |-V BE.

The voltage drop V (R125) determined by the resistance value of the resistor 125 and the current value of the constant current source is generated, and the reference voltage Vref is clamped and maintained higher than Vcc-| Vthp | -V BE-V (R125).

19 shows another structure of the reference voltage generation circuit for the level conversion circuit.

The reference voltage generating circuit shown in the 19th includes transistors DQ1 to DQ4 provided correspondingly to the transistor elements Q1 to Q4 of the sixteenth level conversion circuit.

The transistor DQ1 is connected to one of the gate and the conductive terminal to function as one resistor.

The transistor DQ1 receives the high level potential VH at the other conductive terminal.

Transistor DQ3 is provided in series with transistor DQ.

The gate of transistor DQ3 is connected to the gate of transistor DQ4.

The gate of the transistor DQ4 is connected to one of the conducting terminals.

Transistor DQ2, which receives the low level potential VL at its gate, supplies current to transistor DQ4 from a node supplying the first power supply potential.

Therefore, the current I3 flowing in the transistor DQ2 is the same as the current I2 flowing in the transistor DQ4.

When the β value of the transistors DQ1 to DQ4 is made equal to the β values of the transistors Q1 to Q4 of the level converting circuit, a reference voltage Vref is generated which makes the current I3 and the current If2 of the level converting circuit equal to each other.

In order to stabilize the reference voltage Vref output from the reference voltage generating circuit, it is desirable to make the output impedance small.

For this purpose, the sizes of transistors DQ1 and DQ3 are increased to increase these transistors β values, while the sizes of transistors DQ2 and DQ4 are reduced.

To clarify, these values

β (DQ2) / β (DQ4) = β (Q2) / β (Q4) and

It is set to satisfy the relationship of β (DQ2) / β (DQ3) = β (Q1) / β (Q3).

This enables stable generation of the reference voltage Vref for level conversion.

If the reference voltage generating transistors DQ1 to DQ4 are formed through the same manufacturing process as the transistors Q1 to Q4 constituting the level converting circuit, the variation of the process parameters of the transistor for the level converting circuit will be the same as in the reference voltage generating transistor, Even when process parameters change, a reference voltage Vref can be generated that implements the desired level shift function.

20 shows another configuration of the reference voltage generator circuit for the level conversion shown.

As the reference voltage generating circuit shown in FIG. 20, one of the conducting terminals of the transistor DQ1 receives the first power supply voltage Vcc instead of the high level voltage VH.

As can be seen in FIG. 18, the high level voltage VH becomes Vcc-VBE.

The gate of the transistor DQ1 and the other conductive terminal are connected to the base of the npn bipolar transistor BP1.

The bipolar transistor BP1 is connected to the node at which the collector supplies the first power supply potential Vcc, and the emitter is connected to one of the conducting terminals of the n-channel MOS transistor MN1.

The gate of the transistor MN1 is connected to the gates of the transistors DQ3 and DQ4, and the other conductive terminal is connected to a node supplying the second power source potential Vcc.

Transistor MN1 operates in the form of a cutrun mirror with transistor DQ4.

In the structure shown in FIG. 20, it operates in a bipolar transistor BP1 emitter follower manner and generates a reference voltage Vref.

The voltage output from transistor DQ1 is higher by VBE (= Vcc-VH) than the output in the structure of FIG.

Therefore, the reference voltage Vref generated by emitter follower transistor BP1 is equal to the reference voltage Vref generated by reference voltage generating circuit 1 shown in FIG.

Since a bipolar transistor is used at the output stage and the bipolar transistor operates in an emitter follower manner, the output impedance of the reference voltage generating circuit can be reduced, and a stable reference voltage Vref can be generated.

[Reference voltage generation circuit]

In the BiCMOS circuit, a plurality of different reference voltage generation circuits are used.

The input circuit and the logic gate circuit that constitute the peripheral circuit include a current switch circuit including a differential transistor pair as a basic component.

The logic threshold voltage of the logic gate circuit is set by the reference potential supplied to the base (or gate) of one of the differential transistor pairs.

In the input circuit, a constant current source is connected to supply the operating current of the differential transistor.

A reference potential is used to control the constant current source transistor.

Reference potential is also used in the ECL-CMOS level shift section.

Below, the structure of the circuit which generate | occur | produces these reference electric potentials is demonstrated.

21 shows the configuration of the reference voltage generation circuit 1 according to the present invention.

Referring to FIG. 21, the reference voltage generator circuit includes a constant voltage generator 80 for generating constant reference voltages VCS and VREF1, and a reference voltage generator 82 for generating the reference voltage VCS1 according to the constant voltage Vcs from the constant voltage generator 80. It consists of.

The constant voltage generator circuit 80 has a resistor RR1 connected at one terminal to a node supplying the first power supply potential Vcc, a collector connected to the other terminal of the resistor RR1, an emitter connected to a node supplying a second power supply potential Vee, and a base. Is connected to npn bipolar transistor RQ1 through resistor RR2 to second power supply potential Vee, the collector is connected to receive first power supply potential Vcc through resistor RR20, the base is connected to the remaining terminals of resistor RR1 and the emitter is connected to resistor RR4. Npn bipolar transistor RQ2 connected to one terminal, the npn bipolar transistor RQ3 connected to the other terminal of resistor RR4, the collector connected to the second power supply potential Vee through resistor RR5, and the base connected to one end of downstream RR7; The collector is connected to receive a first supply potential Vcc, the base is connected to the other end of resistor RR1, and the emitter is connected to one end of output node ND1 and resistor RR6. The npn bipolar transistor RQ4 to be connected and the npn bipolar transistor RQ5 to which the collector and base are both connected to the other end of the resistor RR6 and the other end of the resistor RR7 are connected to receive the second power supply potential Vee.

Reference voltage VCS is generated at the emitter of bipolar transistor RQ4.

The constant voltage generator 80 is a P-channel MOS transistor MP4 having one conducting terminal connected to receive a first power supply potential Vcc, a gate connected to receive a second power supply potential Vee, and another conducting terminal connected to one end of a resistor RR21. And an npn bipolar transistor RQ10 whose collector is connected to receive a first power supply potential Vcc, whose base is connected to the other end of resistor RR21 and the collector of transistor RQ2 and whose emitter is connected to a second output node, and the collector is transistor RQ10. Npn bipolar transistor RQ11 connected to the emitter of transistor QR4 and the emitter connected to the other end of transistor RR22, and the node supplying the emitter of transistor RQ11 and the second power supply potential Vee. It further includes the resistor RR22 etc. provided to the.

The other end of resistor RR21 is connected to the other end of resistor RR20 too.

Reference voltage VREF1 is generated at the emitter of transistor RQ10.

The constant current generator 80 is called a band gap reference circuit.

The reference voltage generator 82 has an npn bipolar transistor RQ6 receiving a constant voltage VCS from the constant voltage generator 80 at its base, a resistor RR10 provided between the emitter of the bipolar transistor RQ6 and a node supplying the second power supply potential Vee, and the bipolar transistor. Supply the p-channel MOS transistor RP2 provided between the collector of RQ6 and the node supplying the first power supply potential Vcc, and the output node and the second power supply potential Vee of the p-channel MOS transistor RP1 connected in a emitter follower manner with the transistor RP2. The gate of the n-channel MOS transistor RP2 provided between the nodes is connected to the gate of the transistor RP1 and the collector of the bipolar transistor RQ6.

The reference voltage generator 82 further includes a p-channel MOS transistor MP3 provided in parallel with the transistor RP2.

The second power source potential Vee is applied to the gate of the transistor MP3.

Transistor RN1 delivers reference voltage VCS1 to the gate of current source transistor CQ.

In this case, the transistor RN1 and the constant current source transistor CQ constitute a current mirror circuit.

The operation will be described next.

First, the constant voltage generation circuit 80 describes the operation.

Let the currents flowing through the resistors RR1, RR4, RR5, and RR6 be I11, I12, I13 and I14, respectively, and the base-emitter forward voltage drops of the bipolar transistors RQ1 to RQ5 be VBE1 to VBE5, respectively.

The current amplification factor of the bipolar transistors RQ1 to RQ5 is sufficiently large and the base current can be ignored.

The voltage VCS at the output node ND1 (voltage for the second power supply potential Vee) is

Vcs = VBE5 + RR6˙I14 ˙˙˙˙˙˙˙ (1)

It is represented by

The resistance values of the resistors RR1 to RR6 are denoted by the same reference numerals RR1 to RR6, respectively.

On the other hand, the potential difference between the first power source potential Vcc and the second power source potential Vee is the voltage applied to the resistor RR1, the base-emitter voltage drop of the bipolar transistor RQ2, the voltage applied to the resistor RR4, and the voltage of the bipolar transistor RQ1. It is given by the sum of the base-emitter drop, VBE1, etc. therefore,

Vcc-Vee = I11˙RR1 + VBE2

+ I12 ˙RR4 + VBE1 ˙˙˙˙˙˙˙ (2)

The potential difference between the first power source potential Vcc and the second power source potential Vee is also equal to the potential difference in the path passing through the resistor RR1, the bipolar transistor RQ4, the resistor RR6 and the bipolar transistor RQ5.

therefore,

Vcc-Vee = I11˙RR1 + VBE4

+ I14 ˙RR6 + VBE5 ˙˙˙˙˙˙˙ (3)

Is derived.

The following equation (4) is obtained from the above equations (2) and (3).

I14˙RR6 = VBE1 + VBE2-VBE4

-VBE5 + I12 ˙RR4 ˙˙˙˙˙˙˙ (4)

Substituting equation (4) into above equation (1) yields the following equation.

Vcs = VBE1 + VBE2-VBE4

+ I12 ˙RR4 ˙˙˙˙˙˙˙ (5)

In addition, the voltage applied to the resistor RR2 is equal to the base-emitter voltage drop VBE1 of the bipolar transistor RQ1.

Therefore, the following holds true.

VBE1 = I15 ˙RR2

Since the base current of a bipolar transistor can be neglected by a sufficiently large current gain, the base current can be neglected by a sufficiently large current gain.

The following equation holds.

I12 = I13 + I15 = I13 + (VBE1 / RR2) ˙˙˙˙˙˙˙ (7)

Substituting equation (7) into (5), the following equation is obtained.

Vcs = VBE1 + VBE2-VBE4

+ RR4-(I13 + (VBE1 / RR2)) ˙˙˙˙˙˙˙ (8)

Since the base-emitter voltage drop of the bipolar transistor RQ5 is the sum of the base-emitter voltage drop VBE3 of the bipolar transistor RQ3 and the voltage drop of the resistor RR5, the following is true.

VBE5 = VBE3 + I13˙RR5 ˙˙˙˙˙˙˙ (9)

By modifying this equation (9)

I13 = (VBE5-VBE3) / RR5 ˙˙˙˙˙˙˙ (10)

Get

By substituting equation (10) into equation (8), the following equation is obtained.

Vcs = VBE1 + VBE2-VBE4

+ (VBE5-VBE3) / RR5 ˙˙˙˙˙˙˙ (11)

As can be seen from equation (11), Vcs appearing at the output node ND1 is determined by the voltage drop and the resistance value.

When the supply voltages Vcc and Vee change, the current also changes.

However, the change in base-emitter voltage drop caused by the current variation is very small and can be ignored. Therefore, according to equation (11), a constant voltage Vcs is output from the output node ND1 regardless of the variation of the first power supply voltage Vcc.

The resistance value of the transistor MP4 changes with the variation of the gate potential Vcc and has a function of adjusting the potential of the output node ND2 in inverse proportion to the change of this resistance.

Since the potential of the output node ND1 is a constant voltage Vcs, the base potential of the bipolar transistor RQ2 becomes Vcs + VBE4.

Therefore, the base potential of the bipolar transistor RQ2 remains constant without changing with the variation of the second power source potential Vee, so that the current flowing through the resistor RR20 is constant. As a result, a constant voltage appears at the second output node ND1, and the bipolar transistor RQ10 operates in an emitter follower manner to deduce the reference voltage VREF1.

Bipolar transistor RQ11 and resistor RR22 serve as current sources for bipolar transistor RQ10.

Normal operation of the constant voltage generator 80 is as follows.

When the current I11 increases, the base potentials of the bipolar transistors RQ2 and RR4 go down, and the currents I12 and I14 decrease.

Accordingly, the current I15 also decreases, and the base potential of the bipolar transistor RQ1 drops by the resistor RR2, causing I11 to decrease.

As a result, the base potentials of the bipolar transistors RQ2 and RQ4 rise.

That is, the resistor RR2 has a function of keeping the potential of the bipolar transistor RQ1 always at the base-emitter voltage drop VBE1 and keeping the current I11 flowing through the resistor RR1 constant.

Since constant currents I12 and I14 flow, a constant voltage appears at the output node ND1.

The resistor RR7 functions to prevent variations in the base potential of the bipolar transistor RQ5, that is, variations in the operating characteristics of the bipolar transistor RQ3 caused by the change in the collector potential transferred to the base of the bipolar transistor RQ3.

The operation of the reference voltage generator 82 will be described.

Resistor RR10 forms the emitter resistance of current source bipolar transistor RQ6.

The emitter potential of the bipolar transistor RQ6 is given by Vcs-VBE6.

Where VBE6 represents the base-emitter voltage of bipolar transistor RQ6.

Emitter current IE of bipolar transistor RQ6

IE = (Vcs-VBE6-Vee) / RR10

It is represented by

Assuming that the base current of bipolar transistor RQ6 can be ignored, the collector current IC of bipolar transistor RQ6 is approximately equal to emitter current IE.

Transistors RP1 and RP2 constitute a current reamer circuit.

When the collector current IC of the bipolar transistor RQ6 increases, the current flowing through the transistor RP1 increases,

The level of the reference voltage Vcs1 appearing at the output node ND3 is increased. When the emitter current IE decreases, the reference voltage VCS1 drops.

Since a constant voltage Vcs is applied to the base of the bipolar transistor RQ6, the current IC and IE can be made constant, and thus a reference voltage VCS1 can be generated.

Current I flowing through transistor RP1 is I = IC˙B (RP1) / B (RP2)

It can be represented as.

Here, B (RO1) and B (RP2) represent B values of the transistors RP1 and RP2.

Since the gate and the drain of the transistor RN1 are connected to each other, they operate in the saturation region.

Current I (RN1) supplied by transistor RN1 is

I (RN1) = B (Vgs-Vth) ² / 2

Is given by

Here, Vgs represents the gate-source voltage of transistor RN1, and Vth represents the threshold voltage of transistor RN1.

The output transistor RN1 and the current source transistor CQ form a current mirror circuit, and the mirror current of the current I (RN1) flows through the current source transistor CQ.

The current IE can be kept constant regardless of the value of the second power supply potential Vee (Vcs-Vee is constant).

However, although transistor RN1 operates in the falling region, the current I (RN1) supplied by this transistor changes in accordance with the source potential, that is, the second power source potential Vee.

In this case, even if the gate length of the transistor RN1 is increased and the gate width is increased to increase the current driving capability (assuming B is constant), the saturation current of the transistor RN1 inevitably changes slightly depending on the gate-source voltage of the transistor RN1. do.

In view of this, the transistor MP3 is provided in parallel with the transistor RP2.

The current supply capability of the transistor MP3 is set to a sufficiently small value, for example, about 1/10 of the transistor RP2.

Receives at the gate and functions as a resistor usually in the on state.

When the second power source potential Vee rises with respect to the first power source potential Vcc, the resistance value becomes large.

On the other hand, when the second power source potential Vee falls relatively, the resistance value becomes small, resulting in the potential rise of the node ND4.

As a result, the gate potentials of the transistors RP2 and RP1 rise, which reduces the current I.

In transistor RN1, when source-drain current Ids flowing from the output node ND3 to the second power source potential Vee increases and the gate-source voltage Vgs of transistor RN1 increases relatively, the transistor RP1 supplies The smaller the current I is compensated for the relative change in the second power source potential Vee.

On the other hand, when the second power source potential Vee rises, the resistance of the transistor MP3 increases, so that the potential of the node ND4 falls, so that the current I flowing through the transistor RP1 increases.

As a result, even if the second power source potential Vee rises, the current I increases and the gate-source voltage Vgs of the transistor RN1 decreases.

Therefore, the current Ids flowing through the transistor RN1 can be kept constant.

Even if the power source potential Vee changes by the source voltage line, the reference voltage Vcsl corresponding to the change can be generated, and therefore, the current supplied by the current source transistor CQ can be kept constant.

As described above, since the potential of the node ND4 is adjusted in inverse proportion to the second power source potential Vee, the dependence of the current flowing through the transistor RN1 on the second power source potential Vee can be reliably eliminated, and the constant reference voltage VCS1 (second On the basis of the power supply potential Vee) can be applied to the current source transistor CQ, so that the current supplied by the energy saving transistor CQ is always kept constant.

In the reference voltage generator 80, the transistor MP4 and the resistor RR21 have the same function as the transistor MP3.

The node ND2 potential depends on the second power source potential Vee.

Therefore, by adjusting the potential of the node ND2 in a similar manner to the transistor MP3 by the transistor MP4 and the resistor RR21, the current flowing in the resistor RR20 can be kept constant and the reference voltage VREF1 output from the bipolar transistor RQ10 can be kept constant. .

Here, the current flowing through the transistor MP4 and the resistor RR21 is set to be smaller than the current flowing through the resistor RR20.

Resistor RR21 ensures that the size of transistor MP4 does not have to be excessively reduced and forms a series resistor with transistor MP4.

In this manner, by adjusting the potential of the node ND2 in inverse proportion to the change of the second power source potential Vee, a constant reference voltage VREF1 can be generated.

22 shows another structure of the reference voltage generating circuit 1.

In the reference voltage generator 82 of the reference voltage generator 1 of FIG. 22, the transistor RN2 is provided in parallel with the transistor RN1.

Transistor RN2 receives the first power supply potential Vcc at its gate.

The gate width of transistor RN2 is made to be sufficiently small compared to the gate width of transistor RN1.

When the second power supply voltage Vee drops (the difference between Vcc and Vee increases), the resistance value of the transistor RN2 decreases (because the gate-to-small voltage of the transistor RN2 increases).

As a result, the reference voltage VCS1 from the output node ND3 falls.

The gate voltage (gate-source voltage) of the transistor RN1 drops, so that the current flowing through the transistor RN1 is suppressed.

In this way, the dependency on the drain voltage (drain-source voltage) of the current supplied by the transistor RN1 can be canceled out.

By regulating the current flowing through RN1 of the output transistor in response to the change of the second power supply potential Vee, a constant reference voltage can be generated regardless of the change in the power supply potential, so that the current flowing through the current source transistor receiving the reference voltage is constant. Can be maintained.

Therefore, the reference voltage can certainly be generated even in the following structure.

In more detail, the reference voltage generator 82 is provided in a plurality of parts on the body and is disposed near the current source transistor CQ.

A constant voltage VCS of one electrostatic voltage generator 80 is applied to the plurality of reference voltage generators 82.

In this case, even if the power supply potential Vee applied to each reference voltage generator 82 changes in accordance with the resistance of the power supply wiring, the current flowing through the output transistor of each reference voltage generator is dependent on the magnitude of the power supply potential Vee (or Vcc and Vee). According to the size of the car).

Therefore, the constant reference voltage VCS1 can be reliably generated at any part on the chip.

[Memory Array Structure]

23 shows the structure of the memory array unit.

FIG. 23 shows the memory cells 153a and 153b arranged in two rows and one column in one memory block together with the peripheral circuit.

Memory cells 153a and 153b are disposed at intersections of word lines 154a and 154b and bit line pairs 155a and 155b, respectively.

Memory cells 153a include n-channel MOS transistors 181a and 181b conducting in response to the signal potential of wordline 154a, n-channel MOS transistors 183a and 183b that cross-couple gates and drains to form flip-flops; High resistance loads 182a, 182b, etc. for lifting the memory node up to the level of the first power supply potential Vcc.

Word lines 154a and 154b are provided with word line driver circuits 151a and 151b for driving corresponding word lines in response to the output of the local X decoder shown in FIG.

The word line driver circuits 151a and 151b are both composed of CMOS inverter circuits.

The word line driver circuits 151a and 151b may be included in the local X decoder 27 shown in FIG.

For the bit line pairs 155a and 155b, the bit line equalization transistor 159 conducting in response to the signal ФW from the read / write detection circuit 170 and the output signal Φ from the read / write detection circuit 170. Signal from the bit line load circuit 157 and the read / write detection circuit 170 in response to There is additionally provided a write gate 151, etc., which is connected in response to and connects the bit lines 155a and 155b to the internal write data lines 163a and 163b.

The bit line equalization transistor 159 is formed using a P-channel MOS transistor to equalize the potentials of the bit lines 155a and 155b and reduce the potential difference between the bit lines 155a and 155b through the on-state resistance when reading data.

The bit line load circuit 157 includes a P-channel MOS transistor 185a for precharging the bit line 155a to the first power supply potential Vcc, and a P-channel MOS transistor 185b for precharging the bit line 155b to the first power supply potential Vcc.

The bit line load circuit 157 serves to reduce the potential amplitude of the bit lines 155a and 155b through their on-state resistance when reading data.

The data write gate 151 includes an N-channel MOS transistor 186a for connecting the bit line 155a to the internal write data line 163a, and an n-channel MOS transistor 186b for connecting the bit line 155b to the internal write data line 163b.

The read / write detection circuit 170 sends a signal Ф in response to the column selection signal from the column select signal generation circuit 172 and the data write / read designation signal ФRW. Create

The column select signal generator 172 corresponds to the Y decoder shown in FIG. 1, and decodes the column address signal to generate a column select signal for selecting a bit line pair.

The column select signal from the column select signal generation circuit 172 goes low when activated.

Read / write detection circuit 170 is signal ФR Level selection signal Ф on the selected bit line pair Add.

During data writing, the load circuit 157 and the bit line equalization transistor 159 are turned off and off to prevent the generation of through current flowing from the load circuit 157 to the internal data lines 163a or 163b.

As the peripheral circuit, the read gate 152 which is conducted in response to the column select signal from the column select signal generator 172 and connects the bit lines 155a and 155-b to the internal data read lines 164a and 164b to the internal data read lines 164a and 164b. And precharges the potentials of the internal data reading lines 164a and 164b to the level of the first power source potential Vcc when the block selection signal from the block selection signal generation circuit 167 indicates a non-selection state. A data bus line load circuit 160 and a sense amplification circuit 171 for amplifying the potentials of the read data lines 164a and 164b and generating read data are provided.

The read gate 152 consists of a P-channel MOS transistor 187a for connecting the bit line 155a to the read data line 164a and a P-channel MOS transistor 187b for connecting the bit line 155b to the read data line 164b.

The data line load circuit 160 is composed of a P-channel MOS transistor 180a that charges the read data line 164a to the level of the first power supply potential Vcc and a P-channel MOS transistor 180b that charges the read data line 164b to the level of the first power supply potential Vcc. .

The sense amplifier circuit 171 corresponds to the local sense amplifier 34 shown in FIG. 1 and is provided to each IO block of one memory block.

The block select signal generator 167 corresponds to the Z decoder 25 shown in FIG. 1, and deactivates the data line load circuit 160 of the selected memory block.

Write / read designation signal ФR is provided on the data lines 164a and 164b. And precharge circuits 162a and 162b for charging data read lines 164a and 164b in accordance with the potentials of the write data lines 163a and 163b.

Precharge circuit 162a indicates write / read designation signal ФR P-channel MOS transistor 188a conducting in response to the P-channel MOS transistor 188b conducting in response to the potential of the write data line 163a.

The precharge circuit 162a delivers the first power supply potential Vcc to the read data line 164a when both transistors 188a and 188b are turned on.

Precharge circuit 162b writes and reads the specified signal ФR P-channel MOS transistor 189a conducting in response to the P-channel MOS transistor 188b conducting in response to the potential of the write data line 163b.

The precharge circuit 162b charges the read data line 164b to the level of the first power supply potential Vcc when both the transistors 189a and 189b are turned on.

The operation will be described next.

First, with reference to FIG. 24, the data reading operation will be described.

When an external address signal is applied, this address signal is decoded to perform a word line and bit line pair selection operation.

Assume that memory cell 153a is selected.

In this case, the potential of the word line 154a becomes high level, so that the transistors 181a and 181b are turned on, and the information stored in the memory cell 153a is transferred to the bit lines 155a and 155b.

The block select signal generation circuit 167 applies a block select signal to the data line load circuit 160 to deactivate the load circuit 160.

The column select signal generator 172 turns on the read gate 152.

In the data read operation, the write / read designation signal ФR Remains at the low level.

As a result, the write gate 151 is in the off state, and the bit line load circuit 157 and the bit line equalization transistor 159 remain in the on state (signal Ф from the read / write detection circuit 170). Is at the low level).

The transition amplitude appearing on the bit lines 155a and 155b is determined by the current driving capability of the memory cell, the resistance of the on-line state of the bit line equalization transistor 159, and the on-state resistance of the transistors 185a and 185b included in the bit line load circuit 157, and the like. .

The potential of the bit line is transferred to the read data lines 164a and 164b through the read gate 152.

Sense amplifier 171 is activated to differentially amplify the potential of read data lines 164a and 164b.

The data amplified by the sense amplifier 171 is output as the output data Dout through the global sense amplifier and the Dout buffer shown in FIG.

In BiCNOS_SRAM, the sense amplifier circuit 171 is constituted by a differential amplifier circuit employing a bipolar transistor.

Therefore, 30m between bitlines 155a and 155b Even small potential differences can be sense amplified by the sense amplifier 171, and data can be read at high speed.

The precharge circuits 162a and 162b do not operate because the potentials of the internal write data lines 163a and 163b are previously charged to a high level at the time of data reading.

Next, the recording operation will be described with reference to FIG.

When writing data, the memory cells are selected in a similar manner as when reading data.

During data writing, the read gate 152 is also turned on by the output of the column select signal generation circuit 172.

The sense amplifier circuit 171 does not operate.

At the time of data writing, the external recordable signal / WE gets a low level.

Short pulse write / read designation signal ФR in response to the low-level writeable signal / WE Is generated.

In response to one short signal ФRW, the read / write detection circuit 170 similarly performs a short signal Ф Occurs.

Thus, transistors 186a and 186b of write gate 151 are turned on and are connected to bit line 155a and internal write data lines 163a and 163b.

The transistors 185a and 185b of the bit line load circuit 157 are turned off, and the bit line equalization transistor 159 is also turned off.

The write drive circuit, not shown in the figure, generates complementary internal write data from the internal write data Din and transfers it to the write data lines 163a and 163b.

As a result, the potentials of the internal write data lines 163a and 163b obtain the CMOS high level and the CMOS low level according to the write data.

Assume that the potential of the write data line 163a is at the level of Vcc and the potential of the write data line 163b is at the level of Vcc.

The bit line 155b is discharged to the level of Vcc via the write gate 151 (transistor 186b).

As a result, in the selected memory cell (e.g., memory cell 153a), data is written such that transistor 183a is turned off and transistor 183b is turned on.

At the time of data writing, since the transistor 185b is turned off, no penetrating current through the transistor 185b is generated.

After the specified time has elapsed, the signal Ф Goes to the low level, and both the write gates 186a and 186b are turned off.

The column select signal from the column select signal generator 172 is at the low level, indicating the selection state.

Signal ФR Becomes low level, both transistors 188a and 189a of precharge circuits 162a and 162b are turned on.

In the precharge arcs 162a and 162b, the potentials of the internal write data lines 163 and 163b are transferred to the gates of the transistors 188b and 189a.

The period during which the write drive circuits for driving the internal write data lines 163a and 163b are activated has the same length as the period during which the external writeable signal / WE is activated (that is, there is a delay).

Therefore, when the potential of the internal write data line 163a is at the low level, the precharge circuit 162b precharges the internal read data line 164b to the level of the first power source potential Vcc.

In the precharge circuit 162a, the transistor 188b is turned off.

The potential of the Vcc level transferred from the precharge circuit 162b to the internal read data line 164b is transferred to the bit line 155b through the transistor 187b of the read gate 152.

As a result, the potential of the bit line 155b rises.

When the write drive circuit not shown in the figure is deactivated, the precharge operation of the precharge circuit 162b is completed.

The bit line load circuit 157 and the equalization transistor 159 have a signal Ф Operates when the signal is at the low level, and equalizes and precharges the potentials of the bit lines 155a and 155b.

Therefore, the bit line 155b of the low potential can be charged at a high speed, and the time required to equalize the bit line potential can be shortened.

Therefore, even if the data read operation is performed immediately thereafter, since there is no time for reading the inverted data, the data can be read at high speed and the margin for recovery after writing is large enough.

For clarity, no precharge circuit is provided and the write / read designation signal ФR Is generated in response to the external write enable signal / WE (as shown by the broken line in FIG. 15), the charging of the bit lines 155a and 155b is performed only by the bit line load circuit 157 and the equalizing transistor 159, The potential rise becomes slow, and the bit line equalization time is delayed by time td, so that data cannot be read at high speed.

FIG. 26 shows a generation path of an address signal, internal write data, a write / read designation signal, and the like.

Referring to Fig. 26, the external address signal, external write data Din, external writeable signal / WE, and the like are buffered (or level converted) by inverters 200a, 200b, 200c and the like.

The Z predecoder 16 includes two stages of inverters 201 and 202.

In the predecoder circuit, the "wired OR" logic is used in the ECL-SRAM, so the delay time in the predecoder 16 is represented by the two stage inverters 201 and 202.

The Z decoder 25 includes a two input NAND gate 203 and a two input NOR gate 204 that receives the output of the NAND gate 203.

Since the delay time of the 1-bit address signal is discussed, the two input terminals of the 2-input NAND gate 203 and the 2-input NOR gate 204 are shown to be interconnected.

In practice, another address signal is applied to the remaining input terminals.

The block select signal? B1 is generated from the Z decoder 25.

The Y decoder 6 is composed of an inverter circuit 205 that receives the output of the Z decoder 25, an inverter 206 that receives the output of the inverter 205, a NAND gate 207 that receives the output of the inverter 206, and an inverter 208 that inverts the output of the NAND gate 207. .

The inverter 208 applies the column select designation signal [Delta] SE to the column select signal generation circuit.

Another address signal (Y address signal) is applied to the two-input NAND gate 207.

Between the input data Din and the internal write data INTD (data transferred to the write data lines 163a and 163b), a global write driver 31 and a local write driver 33 are provided.

The global write driver 31 outputs the internal write designation signal from the gate circuit 208 generating the internal write designation signal and the NAND gate 210 receiving the output of the gate 200b, the inverter 211 for inverting the output of the NAND gate 210, and the output of the inverter 211. A two-input NAND gate 212 to receive, an inverter 213 for inverting the output of the two-input NAND gate 212, a three-input NAND gate 214 to receive the output of the inverter 213, and the like.

The NAND gates 212 and 214 are applied with control signals (signals generated from the writeable signal WE and the chip select signal CS) related to data writing.

Since only the delay time of the recording data is discussed, the other input signals of the NAND gates 212 and 214 are not shown.

At the time when the recording data reaches the NAND gates 212 and 214, the state of the remaining input signals of each data is already determined.

The local write driver 33 supplies the NAND gate 215 which receives the internal write enable signal from the internal write enable signal generation circuit 228, the inverter 216 which receives the output of the NAND gate 215, the output of the inverter 216 and the block select signal øbl. A receiving NAND gate 217, an inverter 218 receiving the output of the NAND gate 217, an inverter 219 receiving the output of the inverter 218, and the like.

The local write enable signal is also applied to the local write driver 33 for the following reasons.

The global write driver 31 has a delay time of five gates.

It is assumed that the delay time of the inverter and the delay time of the logic gate are the same.

The delay time of the local write driver 33 is also the delay time of the five gates.

The output of the global write driver 31 is deactivated after the delay time of the five-stage gate elapses after the internal write enable signal is deactivated.

Similarly, the output of the local write driver 33 is deactivated after the delay time of the five-stage gate elapses after the internal write data is deactivated.

That is, the timing at which the output data of the global write driver 31 and the local write driver 33 transition to the inactive state can be the same.

The path for generating the write / read designation signal includes an internal write enable signal generation circuit 190, a one shot pulse generation circuit 191 for generating one pulse in response to the output of the internal writeable signal generation circuit 190, And a control signal generation circuit 192 for generating a write / read designation signal? RW in accordance with the output of the one-shot pulse generation circuit 191 and the block selection signal? Bl.

The internal write enable signal generation circuit 190 includes four stage cascaded inverters 220 to 223, an NAND gate 224 that receives the outputs of the inverters 223 and 200C, an inverter 225 that receives the outputs of the NAND gate 224, and the like.

The NAND gate 224 outputs a low level signal when both input signals are high level.

Inverters 220 to 223 constitute a delay circuit.

Therefore, the output of the NAND gate 224 drops to the low level after the delay time of the inverters 220 to 223 elapses after the output of the inverter 220 drops to the low level.

The timing at which the change of the write enable signal / WE is started is also delayed in this manner, thereby preventing malfunction due to noise.

The control signal generation circuit 192 includes a NAND gate 230 that receives the one-shot pulse from the block selection signal? Bl and the one-shot pulse generation circuit 191 and an inverter 231 that receives the output of the NAND gate 230.

After the delay time of the two-stage gate has elapsed after the one-shot pulse generation circuit 191 is generated, the write / read designation signal? RW is generated.

The read / write detection circuit 170 is configured as a gate circuit 232 which receives a write / read designation signal? RW and a column select signal from the column select signal generation circuit.

The column select signal generation circuit 172 (see FIG. 23) outputs a low level signal to the selected column.

The output of the gate circuit 232 is applied to the write gate, bit line load circuit and bit line equalization transistor of the corresponding bit line pair.

Gate circuit 232 is given for each bit line.

Next, the operation of the circuit shown in FIG. 26 will be described with reference to FIG. 27, which is an operation waveform diagram.

In Fig. 27, the address signal and the external write data Din are shown to change at about the same time.

After time 4T elapses after the address changes, the block select signal? Bl rises to a high level to select a block.

Here, T represents the delay time of the gate 1 stage.

After 4T elapses after the block select signal? Bl rises to the high level, the column select designation signal? Se from the Y decoder 6 rises to the high level.

When the external write enable signal / WE falls to the low level to indicate data recording, the output of the inverter 200C rises to the high level.

After 4T elapses after the output of the inverter 200C rises to the high level, that is, after 5T elapses after the write enable signal / WE falls to the low level, the output of the NAND gate 224 becomes low level.

After time T elapses after the output of NAND gate 224 drops to a low level, the output of inverter 225 rises to a high level.

When the output of the inverter 225 rises to a high level, the NAND gate 210 acts as a buffer so that the input data Din passes through the inverter 200b.

The output state of the global write driver 31 is confirmed after 5T elapses after the output of the inverter 225 rises to a high level.

After the output of the NAND gate 214 is confirmed, the internal recording data INTD is confirmed after 5T has elapsed in the local recording driver 33, and the potentials of the recording data lines 163a and 163b shown in FIG. 23 are high and level according to the recording data INTD. Change to the low level.

The one-shot pulse generation circuit 131 generates a one-shot pulse signal having a predetermined pulse width in response to the rising of the output of the inverter 225.

After 2T has elapsed after the one-shot pulse is generated in the one-shot pulse generating circuit 191, the write / read designation signal? RW is generated.

Up to this point, the block select signal? Bl is at a high level, that is, in a selected state.

Therefore, by appropriately adjusting the pulse width and generation time of the pulse generated from the one-shot pulse generating circuit 191, recording / reading is designated for a predetermined period from one point before the internal recording data INTD is confirmed to one point after the internal recording data is confirmed. It is possible to set the signal øRW to a high level.

Data recording is performed while the internal recording data INTD is confirmed and the recording / reading designation signal? RW is at a high level.

When the internal write data INTD is in the definite state and the internal write / read designation signal? RW is at the low level, the low potential bit line is charged by the precharge circuit shown in FIG.

By the above-described structure, the precharge circuits 162a and 162b can be set in the operating state.

28 shows another method of charging a low potential bit line.

In the structure shown in Fig. 28, the write / read designation signal? RW and the internal write enable signal have the same time width.

One shot pulse is not generated.

Only the delay time of the internal recording data is increased.

In this case, even if the write / read designation signal? RW is at a low level, the internal write data lines 163a and 163b remain in a fixed state.

The low potential bit line is precharged using the determined write data.

In the method shown in FIG. 28, it is not necessary to generate a one shot pulse.

Therefore, the bit line of low potential can be easily precharged by a simpler circuit structure.

FIG. 29 shows a circuit structure for realizing the precharge method of the bit line shown in FIG.

In Fig. 29, parts corresponding to those shown in Fig. 28 are denoted by the same reference numerals.

In the structure shown in FIG. 29, the internal write enable signal is not applied to the NAND gate 215a, which is the first stage of the local write driver 33. In FIG.

Therefore, the internal write data INTD (INT / D) is in an indeterminate state until the delay time provided by the global write driver 31 and the local write driver 33 elapses after the internal write enable signal is deactivated.

Therefore, as shown in FIG. 30, even when the write / read designation signal? RW drops to a low level, the internal write data INTD is kept in a fixed state.

Therefore, during this time, the precharge operation can be performed.

For clarity, as shown in Fig. 30, the output of inverter 225 drops to low level even if the output of inverter 225 goes low and the output of NAND gate 210, the first stage of global write driver 31, is fixed at high level. Until 10T has elapsed, the internal write data INTD (INT / D) is not set to high level in response to the output of NAND gate 210.

Therefore, even if the write / read designation signal? RW falls to the low level after 2T after the output of the inverter 225 falls to the low level, the internal write data INTD (INT / D) is kept in a fixed state.

Therefore, it is possible to easily precharge the low potential bit line without adding a complicated circuit structure.

In the structure shown in FIG. 29, the gate delay of one stage occurs in the read / write designation detection circuit 170. FIG.

Therefore, there is a possibility that precharge is performed while the gate 151 (Fig. 23 chopping tank) is in the conducting state.

In this case, by inserting a gate circuit (buffer circuit) having a delay time equal to the delay time of the read / write detection circuit 170 to the output of the control signal generation circuit 192 as described above while the write gate 151 is in the conducting state. It is possible to prevent the precharge operation from being performed.

As described above, according to the bit line precharge method, since the bit line potential is charged through the read data line using the internal write data after the writing is completed, the recovery of the bit line potential can be made early after the writing is completed. In other words, the time required for equalization is shorter, the data read time point of the read cycle after the write cycle can be advanced, and the access time can be shortened because the margin for recovery after the write is increased.

What is required is to provide only two precharge circuits for one block, and since the occupied area on the chip is not increased, the precharge circuit can be formed with sufficient margin.

Bitline Pull Up Devices

31 shows the basic structure of a bit line pull-up device according to the present invention.

31, for the bit lines 155a and 155b, the write gate 151, the bit line load circuit 157 and the bit line equalization transistor 159 are provided.

These components are as shown in FIG.

Corresponding parts are denoted by the same reference numerals and detailed description thereof is omitted.

Referring to FIG. 31, for the bit line pairs 155a and 155b, a bit line pull-up element 240 is additionally provided.

The bit line pull-up element 240 is composed of a p-channel MOS transistor 242 in which one conductive terminal is connected to the first power potential Vcc, a gate is connected to the bit line 155a, and the other conductive terminal is connected to the bit line 155b.

Transistors 241 and 242 form a latch circuit.

The operation will be described next.

Assume that high level data is written to bit line 155a and low level data is written to bit line 155b.

In this case, the potential of the write data line 163a is at the high level and the potential of the write data line 163b is at the low level.

These potentials are transferred to the bit lines 155a and 155b through the recording gate 151.

At the time of data writing, the signal? W is at the high level, and the transistors 185a and 185b of the equalizing transistor 159 and the bit line load circuit 157 are turned off.

The bit line 155b is discharged to the second power potential Vee through the transistor 186b of the recording gate 151, and the bit line 155a is charged to the level of the first power potential Vcc through the transistor 186a.

At this time, the charge potential of the bit line is lowered by the threshold voltage of the transistor 186a.

In addition, the potential rise of the bit line is slowed down by the resistance of the write gate transistor.

Therefore, when low-level data is written to the bit line 155a in the previous cycle, the potential of the bit line 155a is not sufficiently raised and the data signal potential written to the memory cell becomes low, resulting in unstable data storage in the memory cell. This is done.

In this case, in the bit line pull-up device 240, the transistor 242 decreases in conductivity as the potential of the bit line 155a increases, whereas the transistor 241 increases in conductivity as the potential of the bit line 155b decreases, thereby turning on.

Therefore, the bit line 155a is surely pulled up to the level of the first power source potential Vcc, and the correct signal potential can be written to the memory cell.

Since the bit line raised to the high potential according to the recording data does not experience current suction by the memory cell, even if the latch capability of the bit line pull-up element 240 is small, the bit line potential of the high potential is approximately at the level of the first power potential Vcc. Is maintained on.

In reading data, the potentials of the bit lines 155a and 155b are sufficiently high, and the transistors 241 and 242 are almost turned off.

In this case, even if the transistor whose gate is connected to the bit line of the low potential is turned on, only the bit line of the high level potential is pulled up, so that data reading is not adversely affected.

32 shows a modification of the bit line pull-up device.

In the structure shown in FIG. 32, an npn bipolar transistor 243 is provided in which a collector and a base are connected to a node supplying a first power supply potential Vcc and an emitter is connected to a conducting terminal of transistors 241 and 242.

Bipolar transistor 243 transfers the potential of Vcc-VBE to bitline pullup device 240.

In this case, at the time of data writing, one potential having a higher level among the bit lines 155a and 155b can be set to the Vcc-VBE level, and since the potential amplitude of the bit line at the time of data writing can be reduced, after writing The margin for recovery could be expanded.

When data is to be written through the write gate 151, the transistors 186a and 186b sometimes fail to sufficiently drive the bit lines 155a and 155b so that the write data does not rise sufficiently (due to the resistance of the write gate).

However, in FIG. 32, since the potential of the bit line having the higher level among the bit lines 155a and 155b is pulled up directly through the bit line pull-up element 240, the potential of the high level bit line can be reliably pulled up. Therefore, even when the inverse data (as opposed to the data of the previous cycle) is written, the data is correctly recorded in the memory cell.

Instead of the bipolar transistor 243 of FIG. 32, a diode connected MOS transistor can be used.

As the first power source potential Vcc source, a power line dedicated to bit line pullup can be used.

By making the power supply line separate from the line supplying the power supply voltage to the memory cell, the bit line potential can be pulled up without adversely affecting the power supply potential of the memory cell.

[Spare circuit]

FIG. 33 shows the specific structure of the X decoder shown in FIG.

Referring to FIG. 33, the X decoder 24 includes a conventional X decoder circuit 250 and a spare decoder circuit 260.

In memory plane 1 shown in FIG. 1, normal word lines and spare word lines are provided.

If the normal word line is defective, the defective normal word line is replaced with the spare word line.

In order to select a spare word line, a spare decode circuit 260 is provided.

The normal decode circuit 250 includes a two-input NAND gate 251 that receives one bit of predecode signal IN1 and one bit of predecode signal IN2 from the X predecoder 18, an output of the NAND gate 251, and one bit of predecode. And an NOR gate 252 receiving the signal IN3, an inverter 253 receiving the output of the NOR gate 252, an inverter 254 receiving the output of the inverter 253, and the like.

The inverter 254 generates a word select signal for selecting the main word line MWL.

A typical decoder 250 is provided corresponding to each main wordline MWL.

The preliminary decode circuit 260 includes an inverter 261a receiving a 1-bit predecode signal IN1, an inverter 261b receiving a 1-bit predecode signal IN2, an inverter 261C receiving a 1-bit predecode signal IN3, and outputs of the inverters 261a and 261b. And a NOR gate 262 receiving the NOR gate 262, an NAND gate 263 receiving the outputs of the NOR gate 262 and the inverter 261c, an inverter 264 receiving the output of the NAND gate 263, and the like.

Inverter 264 generates a signal for selecting the preliminary main wordline RMWL.

The predecode signals IN1, IN2 and IN3 each consist of 4 bits.

If a bad word line exists, the address of the bad word line needs to be programmed.

In order to program the address of the bad word line, four inverters 261a, 261b and 261c are provided for the input predecode signals IN1, IN2 and IN3 respectively.

At the time of programming, one inverter is selected corresponding to each predecode signal.

In this example, the X predecoder 18 drives 12 inverters of the preliminary decode circuit 260.

However, the inverter has a similar driving capability as the NAND gate and the NOR gate even though the transistor size is smaller than that of the NAND gate and the NOR gate.

Therefore, the load capacity of the X predecoder 18 is small, and the X predecoder 18 can drive the predecode signal at high speed.

In addition, since the load capacity of the X predecoder 18 is reduced, the current consumption can also be reduced.

The gate of a conventional decode circuit 250 has four stages.

The gate of the predecoding circuit 260 is also four stages.

Therefore, the delay time of the ordinary decode circuit 250 and the spare decode circuit 260 can be the same.

Therefore, the operation speed when the normal main word line is selected and the spare main word line are selected can be the same.

34 shows a schematic structure of the X predecode.

Referring to FIG. 34, the X predecoder 18 includes a predecoder circuit 18a for precoding the address bits X0 and X1 from the address input buffer, and a predecoder for precoding the address bits X2 and X3 from the address input buffer. Circuit 18b and predecoder circuit 18c which predecodes the address bits X4 and X5 from the address input buffer.

All.

The predecode circuit 18a generates the predecode signal m0i.

Here i = 0-3.

The predecode signal m0i from the predecoder circuit 18a corresponds to the predecode signal IN1 in FIG.

The predecoder circuit 18b generates the predecode signal m1j.

Here j = 0-3.

The predecode signal m1j from the predecoder circuit 18b corresponds to the predecode signal IN2 in FIG.

The predecode circuit 18c generates the predecode signal Mk.

Here k = 0-3.

The predecode signal Mk corresponds to the predecode signal IN3 of FIG.

35 shows the detailed structure of the conventional predecode 250 of FIG.

Referring to FIG. 35, NAND gate 251 receives address bits m0i and m1j.

The NOR gate 252 receives the NAND gate 251 and the address bit Mk.

Inverter 253 is a p-channel MO transistor PM where one conducting terminal is connected to the first power potential Vcc, the gate is connected to receive the output of NOR gate 252, and the other conducting terminal is connected to the output node, and one conducting terminal is an output node. N-channel MOS transistor NM, and the output node and the first power potential which are connected to and connected to the gate to receive the output of the NOR gate 252, and the other conductive terminal to receive the second power potential Vee through a fuse element. It consists of the high resistance element R etc. provided between the supplying node.

When a normal predecode 250 is provided corresponding to a normal word line, the fuse element Fu is in a conductive state, and the inverter 253 inverts the output of the NOR gate 252.

When the main word line connected to the normal predecode 250 is defective, the fuse element Fu is cut by, for example, "laser blowing".

The output node of the inverter 253 is pulled up to the level of the first power source potential Vcc by the resistor R.

Therefore, the output of the inverter 254 is fixed at a low level, thereby preventing selection of a bad word line.

The transistor size of the inverter can be made smaller than the transistors of the NAND gate and the NOR gate.

Therefore, the fuse element Fu can be arranged with a sufficient area margin.

If a fuse element is made at the output of the NAND gate 251, the following problem occurs.

The transistor size of the NAND gate 251 and the NOR gate 252 is larger than the transistor size of the inverter, and the number of elements of the gates increases.

Therefore, if a fuse element is made in this portion, there is no margin in area, and the fuse is blown off when the fuse is melted and cut off, and the signal line is likely to be shorted.

This leads to a failure of correct programming.

34A shows the specific structure of the spare diode circuit shown in FIG.

Referring to FIG. 36A, inverters 261aa, 261ab, 261ac and 261ad that receive address bits m0, m1, m2, m3 are provided in parallel.

The outputs of inverters 261aa to 261ad are delivered to signal lines 275 through fuse elements F00 to F03.

Inverters 261aa to 261ad correspond to inverter 261a shown in FIG.

When the spare decode circuit is used, only the fuse elements F00 to F03 are in the conducting state, and the remaining fuse elements are cut off.

Corresponding to inverter 261b shown in FIG. 33, inverters 261ba to 261bd are provided.

Inverters 261ba to 261bd receive address bits m10 to m13.

The outputs of the inverters 261ba to 261bd are transmitted to the signal line 274 through the fuse elements F10 to F13.

When the spare memory cell is used, only the fuse elements F10 to F13 are in the conducting state, and the remaining fuse elements are cut off.

Signals on signal lines 275 and 274 are delivered to NOR gate 262.

Corresponding to inverter 261c shown in FIG. 33, inverters 261ca to 261cd receiving address bits M0 to M3, respectively, are provided in parallel.

The outputs of inverters 261ca to 261cd are delivered to signal lines 278 through fuse elements F0 to F3.

Signals on signal lines 277 and 278 are delivered to NAND gate 263.

When the spare memory cell is used, one of the fuse elements F0 to F3 is in a conductive state, and the other fuse element is transferred.

An extra activation circuit 270 is provided to control activation / deactivation of the spare decode circuit.

The preliminary activation circuit 270 comprises a fuse element 272 provided between the signal line 279 and a node providing the first power potential Vcc and an inverter 271 for inverting a signal on the signal line 279.

The output signal line 280 of the inverter 271 is connected to a node that supplies another power potential to the inverters 261aa to 261ad and 261ba to 261bd.

Signal line 279 is connected to a node supplying one power potential to inverters 261ca to 261cd.

The preliminary activation circuit 270 controls the power supply potential of the inverter which receives the address bits as the predecode circuit is used / disused.

On the other hand, as shown in FIG. 36B, the preliminary activation circuit 270 may be composed of a fuse element 272, a high resistance element RE connected in series with the fuse element 272, inverters 271a and 271b of two stages, and the like.

In this structure, the signal line 279 can be prevented from floating when the fuse element 272 is cut off.

The operation will be described next.

When the spare memory cell is used, in other words, when the spare decode circuit is operated, the fuse element 272 of the preliminary activation circuit 270 is in a conductive state.

As a result, the potential of the signal line 279 becomes the first power potential Vcc, and the potential of the signal line 280 becomes the second power potential Vee.

According to the address of the bad word line, the fuse elements are cut in the fuse groups F00 to F03, F10 to F13, and F0 to F3, respectively.

In this way, the address of the bad word line is programmed into the spare decoding circuit.

For a moment, assume that only fuse elements F00, F10 and F0 are programmed to be in a conductive state.

In this case, the address bits m0 and m10 are at the high level, M0 is at the low level, and the output of the preliminary decode circuit 260 is at the high level so that the spare main word line is selected.

In other words, signal lines 274 and 275 are both at low level, potentials at signal lines 276 and 277 are at high level, output of NAND gate 263 is at low level, and output of inverter 264 is at high level.

If a bad memory cell does not exist, the fuse element 272 of the preliminary activation circuit 270 is cut.

Other fuse elements F00 to F03, F10 to F13, F0 to F3, and the like are in a conductive state.

In this state, the signal line 279 is suspended.

In operation, one of the address bits M0 to M3 is at the high level.

Therefore, signal line 278 is discharged to the level of the second power potential Vee and the p-channel MOS transistor of inverter 261c (one of 261ca to 261cc) is turned on (since the three bits of address bits M0 to M3 are at the low level), thus the signal Line 279 is discharged through the conducting MOS transistor.

As a result, the output of the inverter 271 is stably at a high level, and the outputs of the inverters 261aa to 261ad and 261ba to 261bd, which receive the signal potential on the signal line 280 to the power potential supply node, have a high level Vcc regardless of the value of the address bit. Then, the potentials of the signal lines 274 and 275 become high level, and the output of the NOR gate 262 becomes low level.

Since both inputs are at a low level, the output of NAND gate 263 is at a high level, and the output of inverter 264 is at a low level.

Therefore, the spare memory cell is in an unselected state.

As described above, when the spare memory cell is not used, it is only necessary to melt and blow off the fuse element 272 of the preliminary activation circuit 270.

Therefore, the number of fuse elements to be cut is reduced, and the process of programming the address of the bad word line is simplified.

In addition, since the fuse elements are provided only to the inverter, these fuse elements can be arranged with sufficient margin.

Accordingly, the occurrence of a short circuit caused by the scattering of the molten fuse can be reliably prevented.

In the structure shown in FIG. 36A, a high resistance resistive element can be provided to the preliminary activation circuit 270 to bring the signal line 279 down to the level of the second power potential Vee.

As described above, since the inverter is provided at the input terminal of the preliminary decode circuit, even if the inverter is provided corresponding to each address bit, the output load of the X predecoder does not increase so much that the predecode signal can be determined at high speed. have.

In addition, since the output load of the X predecoder is small, the current consumption is small.

When the spare memory cell is not used, the power supply potential of the input terminal of the spare decoding circuit is controlled, so that the generation of through current through the inverter of this input terminal can be prevented, so that the consumption current can be greatly reduced.

Since the inverter is provided only corresponding to the bits of the predecode circuit, the layout is easy and the occupied area can be reduced.

37 shows an example of changing the components of the preliminary decode circuit.

In FIG. 37, parts corresponding to the preliminary decode circuit shown in FIG. 36 are denoted by the same reference numerals.

The preliminary decode circuit shown in FIG. 37 can select two preliminary word lines (preliminary main word lines) RWLa and RELb.

Components associated with RWLb in the preliminary wordline RWLa are distinguished through corresponding subscripts a and b.

Fuse elements F00a to F03a are respectively provided between the signal lines 275a and the outputs of the inverters 261aa to 261ad.

Fuse elements F00b to F03b are provided between the signal lines 275b and the outputs of the inverters 261aa to 261ad, respectively.

Fuse elements F10a to F13a are provided between the signal line 274a and the outputs of the inverters 261ba to 261bd, respectively.

Fuse elements F10b to F13b are provided between the signal line 274b and the outputs of the inverters 261ba to 261bd, respectively.

Fuse elements F0a to F3a are provided between the signal lines 276a and the output portions of the inverters 261ca to 261cd, and fuse elements F0b to F3b are provided between the signal lines 276b and the output portions of the inverters 261ca to 261cd.

Signal lines 275a and 274a are connected to the input of the NOR gate 262a.

The signal line 276a and the output signal line of the NOR gate 262a are connected to the input of the NAND gate 263a.

The output of NAND gate 263a is delivered to inverter 264a.

In the inverter 264a, a signal for driving the preliminary word line RWLa is generated.

Signal lines 274a and 275a are provided with p-channel MOS transistors 291a and 292a which are conducted in response to the output signal NX1 from the preliminary selection signal generation circuit 285, respectively.

The signal line 276a is provided with an n-channel MOS transistor 293a which is conducted in response to the output signal PX1 of the preliminary selection signal generation circuit 285.

The transistors 291a and 292a charge the signal lines 274a and 275a to the level of the first power supply potential Vcc during conduction.

The transistor 293a discharges the signal line 276a to the level of the second power source potential Vee when it is turned on.

Signal lines 274b and 275a are provided with p-channel MOS transistors 291b and 292b which are conducted in response to the output signal NX2 of the preliminary selection signal generation circuit 285, respectively.

The signal line 276b is provided with an n-channel MOS transistor 293b which is conducted in response to the output signal PX2 of the preselection signal generating circuit 285.

The transistors 291b and 292b charge the signal lines 274b and 275b to the level of the first power source potential Vcc at the time of conduction.

The transistor 293b discharges the signal line 276b to the level of the second power source potential Vee at the time of conduction.

The signal RSL from the preliminary selection signal generating circuit 285 is transmitted to the power supply potential supply signal line 279 of the inverters 261ca to 261cd.

The power supply potential supply nodes of the inverters 261aa to 261ad and 261ba to 261bd are connected to the output signal line 280 of the inverter 271.

The connection method is the same as the connection method of each inverter shown in FIG. 36. The second power potential supply nodes of the inverters 261aa to 261ad and 261ba to 261bd are connected to the signal line 280, and the first power potential supply of the inverters 261ca to 261cd is supplied. The node is connected to signal line 279.

Although the detailed structure will be described later, the preliminary selection signal generating circuit 285 can set the level of the output signal by the fuse element.

The operation will be described next.

When the bad word line does not exist, the signal RSL from the preliminary selection signal generating circuit 285 is set to low level, the signals NX1 and NX2 are set to low level, and the signals PX1 and PX2 are set to high level.

Therefore, the output signals of the inverters 261aa to 261ad and 261ba to 261bd are at the high level regardless of the level of the predecode signal, and the output signals of the inverters 261ca to 261cd are at the low level regardless of the logic level of the predecode signal.

The fuse elements for programming the bad word lines are all in a conductive state.

On the other hand, transistors 291a, 292a, 291b, 292b, 293a and 293b provided for signal lines 274a, 274b, 275a, 275b, 276a and 276b are all on.

As a result, the potential levels of the signal lines 274a, 274b, 275a and 275b become high levels, and the potential levels of the signal lines 276a and 276b become low levels.

Therefore, the outputs of the NAND gates 263a and 263b are at a high level, and the preliminary word line selection signals output from the inverters 264a and 264b are maintained in an inactive state.

When at least one of the spare word lines RWLa and RWLb is used, the signal RSL from the preliminary selection signal generation circuit 285 becomes high.

As a result, the inverters 261aa to 261ad, 261ba to 261bd, 261ca to 261cd, and the like are all in an operating state.

Assume that the spare word line RWLa is used.

In this case, the fuse elements F00a to F03a, F10a to F13a, F0a to F3a, and the like are programmed according to the address of the bad word line.

The output signal NX1 of the preliminary selection signal generating circuit 285 becomes high level, and the signal PX1 becomes low level.

As a result, the transistors 291a, 292a, 293a and the like are all turned off.

When the bad word line is specified in this state, the spare word line RWLa is selected similarly to the operation of the spare decoder circuit shown in FIG.

Assume that the spare word line RWLb is not used in this state.

Fuse elements F00b to F03b are wired OR connected to signal line 275b.

Fuse elements F10b to F13b are wired OR connected to signal line 274b, and fuse elements F0b to F3b are wired OR connected to signal line 276b.

Transistors 291b and 292b are turned on in accordance with signal NX2, and transistors 293b are turned on in accordance with signal PX2.

In this state, the output of the NAND gate 263b becomes high level regardless of the state of the predecode signal, and the spare word line RWLb is not selected.

If all of the fuse elements F00b to F03b, F10b to F13b, F0b to F3b, etc., associated with the unused spare word line RWLb are conductive, they may be wired OR connected, so that a through current may occur.

When the predecode signal m0 is at the high level, the output of the inverter 261aa becomes the low level, and the outputs of the remaining inverters 261ab to 261ad become the high level.

When the signal line 275b is set to a high level, it is possible for current to flow from the transistors 291b and 292b to the signal line 280 through the n-channel MOS transistor in the conduction state of the inverter 261aa.

Similarly, a through current can flow from the first power supply supply node to the signal line 280 through the conductive p-channel MOS transistors of the inverters 261ab to 261ad and the n-channel MOS transistors of the conductive state of the inverter 261aa.

In order to prevent the generation of such a through current and to reduce power consumption, all of the unused spare word line fuse elements may be cut.

When both preliminary word lines RWLa and RWLb are used, each fuse element is programmed.

In the preliminary decode circuit of FIG. 37, the inverter of the input stage can be shared by two spare word lines.

Therefore, a preliminary decode circuit having a small footprint can be realized.

38 shows an example of the structure of the preliminary selection signal generation circuit 285 shown in FIG.

38, the preliminary selection signal generation circuit 285 includes a fuse element 301a provided between the node supplying the first power potential Vcc and the internal node 315a, and the node supplying the output node 315a and the second power potential Vee. N-channel MOS transistor 302a provided at and receiving a first power potential Vcc at the gate, p-channel MOS transistor 303a and n-channel MOS transistor 304a constituting a CMOS inverter that inverts the signal potential of node 315a, and the signal potential of node 316a N-channel MOS transistor 305a that is conductive in response to and discharges node 315a to the level of second power potential Vee.

The resistance of the on state of the transistor 302a is sufficiently large.

The circuit 285 further includes a p-channel MOS transistor 306a and an n-channel MOS transistor 307a that constitute a CMOS inverter that inverts the signal potential of the node 316a.

These transistors 306a and 307a generate the signal PX.

At node 316a, signal NX1 is generated.

In order to generate signals PX2 and NX2, a structure in which signals NX1 and PX1 are similar is provided.

Since the paths through which the signals PX2 and NX2 are generated are the same as the circuit structure where the signals PX1 and PX2 are generated, the corresponding parts are denoted by the same reference numerals and are distinguished by the subscript b.

The path for generating the signal RSL is provided between the p-channel MOS transistor 308 at the gate, the potential of the node 316a, between the MOS transistor 308 and the node 317, and at the gate of the p-channel MOS transistor 310, at the node 317b. N-channel MOS transistor 309 provided between the nodes supplying the second power potential Vee and receiving the potential of node 316a to the gate, and between the node 317 and the node supplying the second power potential Vee and the signal of node 316b to the gate. N-channel MOS transistors 311 and the like that receive electric potential.

The transistors 308 to 311 constitute a two-input NOR gate.

In addition, a p-channel MOS transistor 312 and an n-channel MOS transistor 313 which constitute a CMOS inverter for inverting and amplifying the signal potential of the node 317 are provided.

Signals RSL are generated by transistors 312 and 313.

When there is no bad word line, the fuse elements 301a and 301b are both in a conductive state.

As a result, the potentials of the nodes 315a and 315b are at the high level of the first power source potential Vcc, and the potentials of the nodes 316a and 316b are at the mode low level.

Transistors 308 and 310 are turned on and transistors 309 and 311 are turned off, so that the potential at node 317 is at a high level and the signal RSL is at a low level.

As a result, the inverter of the first stage of the preliminary decoder (see FIG. 37) is in an inoperative state.

Since the potentials of the nodes 316a and 316b are both at the low level, the signals PX1 and PX2 are both at the high level.

Signals NX1 and NX2 are at the low level.

Therefore, transistors 291a, 291b, 292a, 292b, 293a, 293b, and the like in FIG. 37 are all turned on.

Now, the fuse element 301a is cut off.

As a result, the node 315a is discharged to the level of the second power source potential Vee by the transistor 302a.

The potential at node 316a is raised.

Since the potential of the node 316a rises, the transistor 305a is turned on to completely discharge the node 315a to the level of the second power source potential Vee.

Therefore, node 316a obtains the level of the first power potential Vcc.

As a result, the signal P1 becomes the low level of the second power source potential Vee.

As a result, transistor 293a in FIG. 37 is turned off and transistors 291a and 292a are turned off.

Since the potential of the node 316a is at the high level, the transistor 309 is turned on, so that the potential at the node 317 is at the low level, and the signal RSL obtains the high level of Vcc.

Therefore, all the inverters of the first stage shown in FIG. 37 are set to the operating state.

In this state, the decode operation is performed in accordance with the predecode signal.

In the structures shown in FIGS. 37 and 38, the first stage inverters are shared to select two spare word lines.

The number of preliminary word lines to be selected can be three or more, because it can easily cope with the expansion of the circuit shown in FIG. 37 and FIG.

[Column shift redundancy]

FIG. 39 shows the structure of the Y decoder, memory array and X decoder portions shown in FIG.

Referring to FIG. 39, the memory array 2 is divided into four I0 blocks I0 # 1 to I0 # 4 as an example.

The number of I0 blocks included in memory block 2 varies depending on the number of I0 pins, that is, the number of bits of data.

I0 blocks I0 # 1 to I0 # 4 are connected to different I0 pins (data input / output pins).

The local X decoder 27 selects one word line in the memory array of memory block 10.

In one example, four local X decode circuits 38a through 38d are provided for one main wordline MWL.

When the main word line MWL is selected, the local X decode circuits 380a to 380d are enabled, the VZ predecode signal from the VZ decoder is decoded, and one of the word lines WL1 to WL4 is selected.

The output of the VZ decoder (see FIG. 1) consists of a block select signal and a signal for selecting one of four word lines.

Y decoder 6 (see FIG. 1) includes column decoder circuits CD1 to CD4 provided corresponding to I0 blocks I01 to I04, respectively.

An example of a structure in which one I0 block includes eight bit line pairs is shown.

Each column decode circuit CD1 to CD4 is provided corresponding to the bit line pairs of the I0 blocks I0 # 1 to I0 # 4, and is enabled in response to the block select signal øb1 (occured in the Z decoder of FIG. 1) and is Y predecoder. And a NAND decode circuit 381 for decoding the Y predecode signal from (see FIG. 1), an inverter 382 for inverting the output of the NAND decode circuit 381, and an inverter 383 for inverting the output of the inverter 382.

The column select signal from the column decode circuits CD1 to CD4 is applied to the column shift redundancy circuit.

The column shift redundancy circuit 5 and the Y decoder 6 correspond to the column select signal generation circuit shown in FIG.

The column decode circuits CD1 to CD select one bit line pair of the corresponding I0 blocks I0 # 1 to I0 # 4, respectively.

40A and 40B show a schematic structure of a column redundancy circuit.

Referring to FIG. 40A, eight bit line pairs Bm1 to Bm8 are provided corresponding to the block data input / output circuits I / 0 # 1 to I / 0 # 4.

One extra bit line pair SBP is provided for the I0 blocks I0 # 1 to I0 # 4.

Corresponding to each bit line pair, a switch circuit SW is provided which connects one of the two recognized bit line pairs to the data input / output circuit I / 0 # m.

The connection path of the switch circuit SW is programmed by the fuse.

If the bad bit line phase does not exist, the switch circuits SW are all in the same connection state.

More specifically, the bit line pairs Bm1 to Bm8 are connected to the corresponding block data input / output circuit I / 0 # m.

The selection / non-selection of the bit line pair is determined according to the column selection signal from the Y decoder.

In this state, it is assumed that the bit line pair B37 is a bad bit line pair.

In this case, as shown in FIG. 40B, the switch circuit of the switch circuit SW provided corresponding to the bit line pair B48 from the bit line pair B37 is provided with the switch path corresponding to the bit line pairs B11 to B36. It is different from the path of SW.

As a result, the bit line pair B37 is unselected, and instead, an extra bit line pair SBP is used.

Since only the switching of the propagation path of the column selection signal occurs, there is no delay of signal propagation and the access time for accessing the bad bit line pair does not increase, and high speed operation can be realized.

41 shows a schematic structure of a switch circuit.

41 shows switch circuits SWA, SWB and SWC which receive column select signals YIA, YIB and YIC from the Y decoder (column decoder).

The switch circuits SWA to SWC have the same structure, and the corresponding parts are denoted by the same reference numerals.

In order to distinguish each component, subscripts A, B and C representing corresponding switch circuits are assigned.

The switch circuit SWA is complementary to the inverter 411A receiving the potential at one end of the fuse element 410A, the transmission gate 412A conducting in response to the input and output of the inverter 411A, and the transmission gate 412A in response to the input and output of the inverter 411A. N-channel MOS conducting in response to the potential of the transmission gate 413A conducting normally, the n-channel MOS transistor 414A conducting in response to the output of the inverter 411A, and the other end of the fuse element 410A (one end of the fuse element 410B). It consists of a transistor 415A.

The transmission gate 412A transfers the column select signal YIA to the output node YOA.

The transmission gate 413A transfers the column select signal YIA to the output node YOB.

Transistors 414A and 415A are provided in series between the transmission gate 413A and the node supplying the second power potential Vee.

The switch circuit SWB transfers the column select signal YIB to the output nodes YOB and YOC.

The switch circuit SWC transfers the column select signal YIC to the output nodes YOC and YOD.

The fuse elements 410A, 410B and 410C are provided in series between the output node of the redundant activation circuit 400 and the node supplying the first power potential Vcc.

The redundant activation circuit 400 is provided between the fuse element 402 provided between the node 401 and the first power potential Vcc supply node and the n-channel MOS transistor provided between the node 401 and the second power potential Vee supply node and receiving a reference voltage Vcs at the gate. 404, an inverter 406 for inverting the potential of the node 401, and an n-channel MOS transistor 408 that conducts in response to the output of the inverter 406 and transfers a second power supply potential Vee to one end of the fuse element 410A.

The operation is briefly described next.

If there is no bad bit line, both fuse elements 402 and 410A to 410C are conducted.

In this state, the potential level of the node 401 of the redundant active circuit 400 becomes high level, so that the transistor 408 is kept off by the inverter 406.

Therefore, the fuse elements 410A, 410B and 410C transfer the first power potential Vcc.

The outputs of the inverters 411A to 411C are at a low level, the transmission gates 412A, 412B and 412C are turned off, and the transmission gates 413A, 413B and 413C are turned on.

As a result, the column select signals YIA to YIC are transmitted to the output nodes YOB to YOD.

At this time, the transistors 414A, 414B, and 414C are turned off.

Now assume that the bit line pair corresponding to output node YOB contains a bad bit line.

In this state, the fuse element 410A is melted away.

In the spare activation circuit 400, the fuse element 402 is melted away.

In the redundant activation circuit 400, the output of the inverter 406 becomes high level, the transistor 408 is turned on, and a low level signal is applied to the inverter 411A.

As a result, the transmission gate 412A is turned on and the transmission gate 413A is turned off.

In the switch circuits SWB and SWC, the fuse elements 410B and 410C are conducted so that the inverters 411 and 411C receive high level signals, respectively.

Therefore, the transmission gates 413B and 413C are turned on, and the transmission gates 412B and 412C are turned off.

Transistors 414A and 415A of the switch circuit SWA are turned on because they receive a high level signal at the gate, and discharge the output node YOB to the level of the second power supply potential Vee.

As a result, the output node YOB is set to the non-selected state.

The column select signals YIA are sent to the output node YOA, and the column select signals YIB and YIC are sent to the output nodes YOC and YOD.

The bit line pair connected to the output node YOB is replaced with the bit line pair connected to the output node YOA, and the bad bit line pair is saved.

42 shows the structure of the data input / output unit of the I0 block.

42 shows only the I0 blocks I0 # 1 and I0 # 2.

Y decoder 6 provides eight column select signals # 0 to # 7.

The eight selection signals are shared by I0 blocks I0 # 1 to I0 # 4.

In the I0 blocks I0 # 1 to I0 # 4, the bit line pairs at the same position are set to the selected state.

A pair of switch circuits SW1 to SW8 is provided corresponding to the outputs # 0 to # 7 of the Y decoder 6.

In the shift redundancy circuit 4, a set of switch circuits SW1 to SW8 is provided for each of the I0 blocks I0 # 1 to I0 # 4.

Read / write gate 4 (see FIG. 1) includes transfer gate TG provided corresponding to each bit line pair.

In I0 block I0 # 1, transfer gates TG1 to TG8 are provided corresponding to bit line pairs B11 to B18.

Each transfer gate TG1 to TG8 connects the corresponding bit line pair with the local data bus LDB1 when selected.

In Fig. 42, the write data bus and the read data bus are shown by the same data bus LDB1.

The transfer gates TG1 to TG8 are shown to include both the recording gate and the read gate.

For local data bus LDB1, in-block input / output circuit I / 0 # 1 is provided.

In-block input / output circuit I / 0 # 1 includes a local write driver and a local sense amplifier (see Figure 1).

In-block input / output circuit I / 0 # 1 is combined with global data bus GB1.

The global data bus GB1 is combined with the global record driver and global sense amplifier shown in FIG.

Four I / 0 blocks are provided, and four corresponding global data buses GB1 to GB4 are provided, respectively.

For memory block I0 # 2, local data bus LDB2 and in-block input / output circuit I / 0 # 2 are provided.

In-block input / output circuits I / 0 # 2 are combined with global data bus GB2.

For the first column bitline pair B21 of the memory block I0 # 2, a transfer gate TG9 is further provided.

This is because the bit line pair B21 may be connected to the local data bus LBD1 in order to repair the bad bit line.

When a bad bit line pair exists in the memory block I0 # 1, the bit line pair B21 needs to perform a write / read operation from the local data bus LDB1 to 1 via the transfer gate TG9.

If a bad bit line pair exists in any one of the bit line pair B22 to the last column of the memory block I0 # 4, the bit line pair B21 is connected to the local data bus LDB2.

The transfer gate TG9 is conducted in response to the column select signal ФW1 transmitted through the switch circuit SW8.

The transfer gate TG1 is conducted in response to the column select signal ФW2 provided through the switch circuit SW1.

The transfer gate TG2 (provided for the bit line pair B22) is conducted by the column select signal ФW3.

The column select signal ФW3 is transmitted from the switch circuit SW1 or SW2.

43 shows the structure of the transfer gate portions of the bit line pairs B21 and B22 shown in FIG.

43 shows only a portion of the transfer gate that operates when data is written.

The read gate portion is not shown.

43, n-channel MOS transistors 421a and 421b which are conducted in response to the column select signal ФW1 (generated at the time of writing) with respect to the bit line pair B21, and the p channel which are conducted when the column select signal ФW1 are deactivated. MOS transistors 423a and 423b are provided.

Transistors 421a and 421b together correspond to transfer gate TG9 shown in FIG. 42, and when selected, these transistors connect bit line pair B21 to local write data bus WB1.

The local write data bus LWB1 is included in the local data bus LDB1 shown in FIG.

For the bit line pair B21, the n-channel MOS transistors 420a and 420b that are conducted in response to the column select signal ФW2 (which is generated at the time of writing) and the p-channel MOS transistors 422a and 422b that are turned on when the column select signal ФW2 are deactivated are Additionally provided.

Transistors 420a and 420b together correspond to transfer gate TG1 shown in FIG. 42, and upon selection connect bit line pair B21 to local write data bus LWB2.

The local write data bus LWB2 is included in the local data bus LDB2 shown in FIG.

For the bit line pair 21, there is further provided a p-channel MOS transistor 424b that is turned on when the column select signal ФW1 is deactivated, and a p-channel MOS transistor 424a that is turned on when the column select signal ФW2 is deactivated.

Transistors 424a and 424b are connected in series between the bit lines of bit line pair B21.

N-channel MOS transistors 425a and 425b which are conducted in response to the column select signal ФW3 (which is generated at the time of writing) for the bit line pair B22, and p-channel MOS transistors 426a and 426b which are conducted when the column select signal ФW3 is deactivated. 427 is provided.

The transistors 425a and 425b connect the bit line pair B22 to the local write data bus LWB2 at the time of conduction.

The transistors 426a and 426b raise the potential of each bit line of the bit line pair B22 at the time of conduction.

Transistor 427 equalizes the potentials of the bit lines of bit line pair B22 when conducting.

The gate widths of the transistors 422a, 422b, 423a and 423b are made to be twice as large as the gate width W2 of the transistors 426a and 426b.

In this way, the degradation of the bit line driving ability caused by the series connection can be prevented.

The current driving capability of the transistors 424a and 424b, ie the gate width, is also made about twice the gate width of the transistor 427.

The bit line potential amplitude when reading data is made equal to the potential amplitude of other bit lines.

Since the precharge time of the bit lines when the bit line pair b21 is subjected to data read following the data write is made the same as in the other bit line pairs, the margin of recovery after writing can be prevented from being reduced.

Only one of the signals ФW1 and ФW2 is used, and the other is usually kept inactive (see FIG. 41).

As described above, as a write gate for a pair of bit lines located at the boundary of the I0 block, a write gate that operates in accordance with the signals? W1 and ФW2 is provided, so that column shift redundancy even when a plurality of I0 blocks are provided in one memory block. Circuitry can be used, and since only one spare bitline pair is used in the memory block, efficient use of redundant bitlines is possible.

Since only one spare bitline pair is required, the area of the array can be reduced.

Corresponding components of bit line pairs (e.g., bit lines B22) having different gate widths of equalization transistors 424a and 424b and load transistors 422a, 422b, 423a and 423b of the bit line pairs located at the boundary (transistors 427, Since the current driving capability is doubled because it is made twice as large as the gate widths of 426a and 426b, the degradation of the current driving capability due to the on-state resistance caused by the series connection of the transistors can be prevented, thus, The reduction in the margin for recovery after recording can be reliably prevented.

In the structure shown in FIG. 43, when the bit line pair B21 is not selected at the time of data writing, the signals ФW1 and ФW2 are both at the low level, and the transistors 422a, 422b, 423a, 423b, etc., 424a and 424b are turned on. .

Therefore, the potential amplitude generated in the bit line pair B21 becomes the same as in the data reading.

Therefore, equalization of the potentials of the bit line pairs B21 in the write cycle can be performed at high speed.

44 shows an example of a change in the bit line load sharing circuit of the bit line pair B21 shown in FIG.

In FIG. 44, p-channel MOS transistors 425a and 426a are provided in parallel with transistors 422a and 423a, and p-channel MOS transistors 425b and 426b are provided in parallel with transistors 422b and 423b.

Transistors 425a and 425b receive the column select signal ФW2 at the gate.

The remaining structure is as shown in FIG.

One of the signals ФW1 and ФW2 is fixed at the low level, which is inactive.

When the signal ФW1 is normally in an inactive state, the transistors 423a and 423b are normally set to the on state.

When the signal ФW2 changes from a high level to a low level, transistors 422a and 422b receive current from the first power supply potential Vcc through transistors 423a and 423b to charge the bit line pair.

At this time, since the transistors 425a and 425b are normally turned on, the transistors 426a and 426b charge the bit line through the transistors 425a and 425b.

On the other hand, when the column select signal ФW2 is fixed at the low level, which is normally inactive, the transistors 422a, 422b, 426a, 426b and the like are normally set to the on state.

Transistors 423a and 423b are connected to the bit lines through transistors 422a and 422b which are normally on.

On the other hand, transistors 425a and 425b are connected to the first power potential supply node through transistors 426a and 426b which are normally on.

When the signal ФW1 changes or the signal ФW2 changes, the transistor close to the power supply node and the transistor close to the bit line are turned on / off in accordance with the control signal.

Therefore, even if either of the column select signals ФW2 and ФW1 is activated, the operating characteristics of the bit line load circuit are the same.

The structures of the bit line load circuit and the write gate shown in FIGS. 43 and 44 are provided corresponding to the bit lines located at the boundary of the I0 block.

However, the structure provided for the bit line pair B21 is also applicable to a multi-terminal memory in which a plurality of I0 terminals (data input / output terminals) are input and data is input / output independently from each I0 terminal.

In this case, the column select signals ФW1 and ФW2 act as recording column select signals generated corresponding to the I0 terminals.

Further, the gate widths of the transistors 425a, 425b, 426a, and 424b are made to be twice the gate width W2 of the transistors 426a and 426b of FIG.

[Preliminary Circuit]

45 shows an example of a preliminary circuit.

45 shows an example of a preliminary circuit for generating a reference voltage.

As already described with reference to FIG. 21, in the reference voltage generating circuit, in order to compensate for the second power source potential Vee, in order to compensate for the second power source potential Vee, in parallel with the current mirror transistor RP2, Is provided.

This potential change compensation transistor needs to be optimized.

For this purpose, a plurality of transistors having different parameters such as gate width and / or on-state resistance and the like are prepared, and one transistor having optimal characteristics can be selected to optimize circuit characteristics.

When selecting one circuit from a plurality of preliminary circuits, one method is to select a preliminary circuit using a specific patterning mask for aluminum wiring or contact.

However, if such a method is used, the preliminary circuit to be used must be determined prior to the characterization.

Therefore, even if it is known that the circuit used later is not the optimal circuit, this preliminary circuit cannot be switched.

Further, a method of selecting a spare transistor by using a fuse element and cutting the fuse element can be considered.

However, once the fuse element is melted and blown, the fuse cannot be conducted again.

Therefore, there is a problem in that it is difficult to select the optimum circuit because of the lack of flexibility in the selection of the preliminary circuit.

In view of this, as shown in FIG. 45, preliminary circuits 430a, 430b and 430c are provided in parallel.

The preliminary circuits 430a to 430c include p-channel MOSs having different gate widths or on-state resistances.

Corresponding to the preliminary circuits 430a to 430c, the preliminary control circuits 432a, 432b and 432c are provided.

For each of the preliminary control circuits 432a to 432c, two fuse elements FA and FB are provided.

The fuse elements corresponding to the preliminary control circuits 432a to 432c are distinguished by subscripts a, b and c, respectively.

The preliminary control circuits 432a and 432c activate the corresponding preliminary circuit when one of the two related fuse elements is blown.

If both fuse elements are blown, the corresponding spare circuit is deactivated.

If both fuse elements are in a conductive state, the corresponding spare circuit is deactivated.

In the transistors of the preliminary control circuits 432a to 432c, one conducting terminal is connected to the first power supply potential Vcc supply node, and the other conducting terminal is commonly connected to the node ND4.

The operation is briefly described next.

In the initial state, both the fuse elements FA and FB are in a conductive state.

In this state, the deactivation signal (high level in the embodiment shown in FIG. 45) is output from the preliminary control circuits 432a to 432c.

The transistors of the preliminary circuits 430a to 430c are all in the off state.

First, fuse element FAa is cut | disconnected.

As a result, the output of the preliminary control circuit 432a is deactivated, and the transistor of the preliminary circuit 430a is turned on.

In this state, the reference voltage generating circuit is operated and the presence or absence of dependency on the voltage difference between the second power source potential Vee and the first power source potential Vcc of the reference voltage Vcs1 is measured.

In this example, the dependency on the power supply potential is tested while varying the low level potential supplied from the preliminary control circuits 432a and 432c.

If the preliminary circuit 430a provides the optimum operating characteristics, the preliminary circuit selection operation is completed at this point.

If the optimum result is not obtained, the fuse element FBa is cut off, the output of the preliminary control circuit 432a is deactivated, and the preliminary circuit 430a is in an inoperative state.

Next, the fuse element FAb is cut and similar operation characteristics are measured using the preliminary control circuit 432b.

If reserve circuit 430b gives the best results, reserve circuit 430b is selected.

Otherwise, the preliminary circuit 430b is deactivated by cutting the fuse element FBb, and a similar processing operation is performed using the preliminary circuit 430c.

Through the series of operations described above, a preliminary circuit that provides the optimum operating characteristics can be selected.

This structure is used as an extremely effective means in determining the size of a transistor that provides optimum operating characteristics in a test product for evaluating the characteristics of a semiconductor memory device.

46 shows another application of the preliminary circuit.

In FIG. 46, address program circuits 440a and 440b for selecting a spare word line are shown as examples of the spare circuit.

The address program circuits 440a and 440b correspond to the structure shown in FIG. 36, and generate selection signals for driving the spare word lines RWL1 and RWL2 through the driving circuits 444a and 446b, respectively.

Predecode signals are applied to the address program circuits 440a and 440b, respectively.

Preliminary control circuits 442a and 442b are provided for the address program circuits 440a and 440b, respectively.

The preliminary control circuits 442a and 442b generate a potential applied to the power supply node of the inverter in the structure shown in FIG.

In this way, activation / deactivation of the address program circuits 440a and 440b is controlled.

The preliminary control circuits 442a to 442c include fuse elements FCa and FDa, FCb and FDb, respectively.

When both fuse elements FC and FD are in a conducting state, the preliminary control circuits 442a and 442b output signals in an inactive state.

When one of the two fuse elements is blown, the preliminary control circuit 442a (or 442b) generates an activation signal.

If both fuse elements FC and FD are disconnected, the preliminary control circuit generates a deactivation signal.

In this structure, when the address of the bad word line is programmed in the address program circuits 440a and 440b, the spare word line RWL1 may also be bad.

In this case, when the fuse elements FCa and FDa of the preliminary control circuit 442a are cut off, the preliminary word line RWL1 can be set to the non-select state in the normal case.

Therefore, the bad word line can be prevented from being incorrectly replaced with the bad spare word line.

Since the outputs of the preliminary control circuits 442a and 442b are configured to be delivered to the power supply potential supply node of the inverter shown in FIG. 36, deactivation → activation → deactivation of the address program circuits 440a and 440b can be easily realized.

In case of using the preliminary control circuit 442 shown in FIG. 46 instead of the extra activation circuit 270 shown in FIG. 36, the activation / deactivation of the predecode circuit can be easily controlled without increasing the number of fuse elements to be melted and blown. have.

In the structure of the preliminary decoded circuit shown in FIG. 36, the use of the defective spare word line can be prevented.

It is only necessary to cut the fuse element 272 (included in the spare activation circuit 270) after programming.

However, when the preliminary control circuit 442 shown in FIG. 46 is used, if a defective memory cell exists, no fuse element needs to be cut, and the number of steps can be reduced (bad memory cell in the structure shown in FIG. 36A). If there is no (bad word line), the fuse element 272 of the extra activation circuit 270 needs to be cut and in the structure shown in Fig. 36B, the fuse element 272 is not cut when no defective memory cell exists. ).

In the above description, the reference voltage generating circuit and the address program circuit have been described as examples of the spare circuit.

However, the preliminary control circuit shown in FIGS. 45 and 46 is also applicable to any structure in which a plurality of circuits which are not used simultaneously are provided on the semiconductor chip and one of the plurality of circuits is selected and used as necessary.

The circuit to be used may be determined while checking the operation of the circuit.

FIG. 47 shows the logic structure of the preliminary control circuit shown in FIG. 45 and FIG.

Referring to FIG. 47, the preliminary control circuit 449 includes the first fuse element 450a provided between the first power potential supply node and the node 454 and the resistance element 451a of the fixed term provided between the node 454 and the second power potential Vee supply node. And a fuse element 450b provided between the first power potential Vcc supply node and the node 455, a high resistance resistor 451b provided between the node 455 and the second power potential Vee supply node, and a potential of the nodes 454 and 455. A two-input ExOR gate 452 and an inverter 453 that inverts the output of the ExOR gate 452.

The two-input ExOR gate 452 outputs a low level signal if the logic levels of both inputs match, otherwise it outputs a high level signal.

The operation will be described next.

When both of the fuse elements 450a and 450b are in the conducting state, the potential levels of the nodes 454 and 455 become high level, the output of the ExOR gate 452 becomes low level, and the high level signal is output by the inverter 453.

When one of the fuse elements 450a and 450b is cut, the potential level of one of the nodes 454 and 455 becomes a high level and the other potential level becomes a low level.

As a result, the output of the ExOR gate 452 becomes high level, and the output of inverter 453 becomes low level.

When both of the fuse elements 450a and 450b are cut, the potentials of the nodes 454 and 455 are all at a low level.

In this state, the output of the ExOR gate 452 goes low and the output of the inverter 453 goes high.

Logic may be used such that the output of the preliminary control circuit goes high when activated and low when deactivated.

48 shows another structure of the preliminary control circuit.

Referring to FIG. 48, the preliminary control circuit 449 includes an n-channel MOS transistor 462a provided between the node 469a and the second power source Vee advanced node, the inverter 463a for inverting the signal potential of the node 469a, and the output of the inverter 463a. N-channel MOS transistor 464a that conducts in response and discharges node 469a to the level of the second power potential Vee, and p-channel MOS transistors 467a and 468a that receive the output of inverter 463a at the gate, and p receive the signal potential at node 469a at the gate. Channel MOS transistors 465a and 466a.

Transistors 465a and 466a are connected in series, and transistors 467a and 478a are also connected in series.

Transistor 462a receives a first power potential Vcc at its gate.

A fuse element 460a is provided between the node 469a and the first power potential Vcc.

The structure of the fuse element 460b is provided between the node 469b and the second power potential Vee supply node, the n-channel MOS transistor 462b receiving the first power potential Vcc at the gate, the inverter 463b for inverting the potential of the node 469b, and the inverter. N-channel MOS transistor 464b that conducts in response to the output of 463b to discharge node 469b to the level of the second power potential Vee, p-channel MOS transistor 465b that receives the signal potential of node 469b at its gate, and signal potential of node 469b And an n-channel MOS transistor 468b for receiving a gate at the gate, an n-channel MOS transistor 466b and a p-channel MOS transistor 467b for receiving the output of the inverter 463b at the gate.

Transistor 465b is provided between the first power potential Vcc supply node and transistor 465a.

Transistor 467b is provided between the first power potential Vcc supply node and transistor 467a.

Transistor 466b is provided between the second power supply potential Vee supply nodes.

Transistor 468b is provided between transistor 468a and the second power supply potential Vee supply node.

The operation will be described next.

When both of the fuse elements 460a and 460b are in a conductive state, the potentials of the nodes 469a and 469b are both at a high level.

The outputs of inverters 463a and 463b both go low and transistors 467a and 467b both turn on.

Transistor 468a is turned off, transistor 466b is turned off and transistor 465b is turned off.

Therefore, output node 470 is charged to the level of the first power supply potential Vcc through transistors 467a and 467b.

As a result, a high level signal indicating an inactive state is output.

Suppose one of the fuse elements is cut off.

For example, assume that fuse element 460a is cut and fuse element 460b is in a conductive state.

Node 469a is discharged by transistor 462a to obtain a low level.

The potential of the node 469b is at a high level.

The output of inverter 463a goes high and the output of inverter 469b goes low.

In this state, the transistors 468a and 468b are turned on.

Transistor 467a is off, transistor 465b is off and transistor 466b is off.

Therefore, the output node 470 is discharged to the level of the second power source potential Vee through the transistors 468a and 468b.

As a result, a low level signal indicating the active state is output.

Suppose both fuse elements 460a and 460b are cut.

In this state, nodes 469a and 469b are both at a low level, that is, at the level of the second power supply potential Vee.

The outputs of the inverters 463a and 463b go high.

Both transistors 465a and 465b are turned on.

Transistors 466a and 466b are turned off, transistors 467a and 467b are turned off, and transistor 468b is turned off.

Therefore, the output node 470 is charged to the level of the first power source potential Vcc through the transistors 465b and 465a, and a high level signal indicating an inactive state is output.

By providing a plurality of sets of preliminary control circuits and preliminary circuits as described above, it is possible to determine a circuit to be used during the switching of the preliminary circuits to confirm the circuit operation, so that a circuit realizing a desired operating characteristic can be easily realized.

[Buffer circuit]

49 shows a specific structure of the address buffer.

The address buffer shown in FIG. 49 is a buffer circuit for buffering the 1-bit address signal Ai.

The address buffer circuit 500 corresponds to a buffer circuit for supplying internal address signals to the X predecoder, the Y predecoder, and the Z predecoder in the structure shown in FIG.

Referring to FIG. 49, the address buffer circuit 500 receives the bit Ai of the address signal at the base, the npn bipolar transistor 501 whose collector is connected to the first power supply potential Vcc supply node and the emitter is connected to the node 513, and the collector is the first one. A npn bipolar transistor b 502 connected to a power supply Vcc supply node, receiving a first reference potential Vref1 at the base, and an emitter connected to node 513, and provided between a node 513 and a second power supply potential Vee supply node to a second gate. An n-channel MOS transistor 509 that receives a reference voltage Vcs1 is included.

Transistors 501 and 502 constitute an emitter coupled logic circuit, and transistor 509 serves as a constant current source for the ECL gate.

The address buffer circuit 500 receives the signal potential of the node 513 at the base, and the npn bipolar transistor 503 at which the collector is connected to the first power potential Vcc supply node through the resistor 511 and the emitter is connected to the node 514 and the first reference voltage Vref1 at the base. And a collector is connected between the npn bipolar transistor 504 with resistor 512 connected to the first power potential Vcc supply node and the emitter connected to node 514, and between the node 514 and the second power potential Vee supply node and connected to a second gate. The device further includes an n-channel MOS transistor 510 that receives the reference voltage Vcs1.

Transistors 503 and 504 constitute one ECL gate, and transistor 510 serves as a constant current source for the ECL gate.

The address buffer circuit 500 carries npn bipolar transistors 505 and 506 which transfer the signal potential of the node 515 (node between the resistor 511 and the collector of the transistor 503) in an emitter follower, and the node 516 (between the collector of the resistor 512 and the transistor 504). Npn bipolar transistors 507 and 508 that transfer the signal potential of the node of the &lt; RTI ID = 0.0 &gt;

From the emitters of the transistors 505 to 508, the internal address signals AB1, AB2, AB3 and AB4 are output.

The operation is briefly described next.

The transistors 501 and 502 have a high / low judgment function of the input signal and a level shift function.

When bit Ai of the input address signal is at the high level, transistor 501 is turned on and transistor 502 is turned off.

When the potential level of the bit Ai of the input address signal is represented by V (Ai), the potential of the node 513 can be represented by V (Ai)-VBE.

Since V (Ai)-VBE &gt; Vref1, current flows through transistor 503 to bring down the potential of node 515.

As a result, the internal address signal bits AB1 and AB2 become low level, and the bits AB3 and AB4 of the internal address signal become high level.

When the bit Ai of the internal address signal is at the low level, the transistor 502 is turned on and the potential of the node 513 is Vref1-VBe.

In this state, transistor 504 is turned on and the potential at node 516 is discharged.

As a result, the bits AB1 and AB2 of the internal address signal become high level, and the bits AB3 and AB4 of the internal address signal become low level.

50 shows the structure of the V address input buffer circuit.

In the V address input buffer circuit 520 shown in FIG. 50, the internal address signals AV1 to AV4 are applied to the first V predecoder.

In addition to the 49th address input buffer circuit 500, the V address input buffer 520 shown in FIG. 50 includes a diode 521 having an anode coupled to the node 515, a diode 522 having an anode coupled to the node 516, and burn-in (see FIG. an n-channel MOS transistor 523 that is turned on in response to the burn-in) mode designation signal BI, and an n-channel MOS transistor 524 that receives a second reference voltage Vcs1 at its gate.

The cathodes of diodes 521 and 522 are commonly connected to form a connected OR logic gate.

Transistor 523 is provided between diodes 521 and 522, and transistor 524.

Transistor 524 functions as a constant current source.

The operation will be described next.

The burn-in mode is an operation mode in which the semiconductor memory device is operated under conditions of high voltage and high temperature to sort out an initial defect, that is, to present a potential defect.

When the burn-in mode designation signal BI becomes high, the transistor 523 is turned on.

In this state, the diode 521 or 522 connected to the high level node 515 or 516 is turned on, and the nodes 515 and 516 are set to a low level regardless of the level of the bit Vi of the V address signal.

As a result, bits AV1 to AV4 of the internal address signals output from the transistors 505 to 508 are at a low level, that is, enabled.

More specifically, in the burn-in mode, a plurality of word lines are simultaneously selected.

This is to increase the power consumption in the burn-in mode.

When the burn-in mode designation signal BI is at the low level, the transistor 523 is turned off.

In this state, diodes 521 and 522 are turned off.

Therefore, the V address input buffer 520 operates in a similar manner to the address buffer of FIG.

In response to the address signal from the address buffer circuit of FIG. 49, one main word line is selected.

A plurality of subordinate word lines are connected to one main word line (see FIG. 39).

Selection of the plurality of dependent word lines is performed in accordance with the output of the V address input buffer circuit shown in FIG.

In other words, if the outputs of the V address input buffer circuit are all set in the select state in the burn-in mode, all the sub word lines connected to one main word line can be set in the select state at the same time.

When the V address input buffer circuit of Fig. 50 is used as an address input buffer circuit for generating the predecode signal IN3 shown in Figs. 33 and 34, a plurality of main word lines can be set to a selection state at the same time.

In this case, the address input buffer performs a normal buffer operation and generates a signal for selecting one dependent word line.

Therefore, one dependent word line is selected for each of the plurality of main word lines.

As a result, the plurality of dependent word lines are set to the selected state.

Either structure can be used.

FIG. 51 shows another structure of the V address input buffer circuit.

Referring to FIG. 51, the V address input buffer circuit 520 includes n-channel MOS transistors 530 and 533 which receive bit Vi of the input address signal at the base, and npn bipolar transistors b 531 and 532 which receive the first reference potential Vref1 at the base. do.

The collectors of transistors 530 and 532 are both connected to a first power supply potential Vcc supply node through a resistor 534.

The collectors of transistors 531 and 533 are connected to the first power supply potential Vcc supply node through a resistor 535.

Emitters of transistors 530 and 531 are commonly connected and emitters of transistors 532 and 533 are commonly connected.

The V address input buffer circuit 520 further includes n-channel MOS transistors 536 and 537 which receive the second reference potential Vcs1 at the base, and n-channel MOS transistor 538 which receives the burn-in mode designation signal BI at the gate.

Transistor 536 functions as a constant current source for transistors 530 and 531, and transistor 537 serves as a constant current source for transistors 532 and 533.

Transistor 538 is provided between transistor 537 and transistors 532 and 533.

The V address input buffer circuit 520 further includes npn bipolar transistors 505 and 506 for receiving the potential of the node 539a on the base through the signal line 539b, and npn bipolar transistors 507 and 508 for receiving the potential of the node 540a on the base through the signal line 540b. Include.

The collectors of transistors 505 to 508 are connected to the first power supply potential Vcc supply node.

Internal address signals AV1 to AV4 are generated from the emitters of the transistors 505 to 508.

The operation is briefly described next.

When the burn-in mode designation signal BI is at the low level, no current flows in the transistors 532 and 533, and the transistors 532 and 533 are in an inoperative state.

Transistors 530 and 531 perform differential amplification by comparing bit Vi of the input address signal with the first reference potential Vref1.

In response to the high level / low level of the bit Vi of the input address signal, the currents of the signal lines 539 and 540 become the low level / high level.

As a result, the internal address signal bits AV1 to AV4 corresponding to the level of the bit Vi of the input address signal are generated.

When the burn-in mode designation signal BI is at the high level, the transistor 538 is turned on.

In this state, transistors 530, 531, 532, and 533 are all operable.

When the input signal Vi is higher than the first reference voltage Vref1, the transistors 530 and 533 are turned on, bringing both the nodes 539a and 540a to a low level.

On the other hand, when the bit Vi of the input address signal is lower than the first reference voltage Vref1, the transistors 531 and 532 are turned on.

In this state, nodes 539a and 540a are discharged to low level through transistors 532 and 531.

Therefore, in the burn-in mode, the bits AV1 to AV4 of the internal address signal can be set to the low level selection state irrespective of the bit Vi of the input address signal.

If the transistors 530 to 533 have the same size in the structure of the address signal input buffer circuit shown in FIG. 51, the signal lines 539b and 540b can be surely set to a low level even in the burn-in mode.

Since the low level potential is given by the product of the resistors 534 and 535 and the current supplied by the current source transistors 536 and 537, the low level potential can be set accurately.

FIG. 52 shows the specific structure of the CS buffer of FIG.

Referring to FIG. 52, the CS buffer 12 includes an npn bipolar transistor 550 that receives a chip select signal / CS applied from an external device through a pad 570, and an npn bipolar transistor 511 that receives a first reference potential Vref 1. And an n-channel MOS transistor 559 that serves as a constant current source transistor that receives a second reference voltage Vcs1 at its gate and provides a current path to transistors 550 and 551.

The collectors of transistors 550 and 551 are connected to a first power potential Vcc supply node and the emitter is connected to transistor 559 via node 566.

The CS buffer 12 receives an npn bipolar transistor 552 receiving a signal potential of the node 566 at the base, an npn bipolar transistor 553 receiving a first reference potential Vref1 at the base, and a control terminal CS, W, and CUT at the gate. And an n-channel MOS transistor 560 connected to the emitters of transistors 552 and 553, and an n-channel MOS transistor 561 provided between the transistor 560 and the second power supply potential Vee supply node and receiving a second reference voltage Vcs1 at its gate. .

The collectors of transistors 552 and 553 are connected to the first power potential Vcc supply node through resistors 564 and 565.

The CS buffer 12 includes an inverter 570 receiving the control signal CS, W, and CUT, an n-channel MOS transistor 572 receiving an output of the inverter 570 at its gate, an emitter connected to one conducting terminal of the transistor 572, and a collector signal line 568. A npn bipolar transistor 571 connected to the base and receiving a first reference voltage Vref1 at a base, a npn bipolar transistor 554 receiving a collector potential of the transistor 552 through a signal line 567 at a gate, and a collector potential of the transistor 553 through a signal line 568. And npn bipolar transistors 555 to 558 received in the base.

The other conductive terminal of transistor 572 is connected to one conductive terminal of transistor 561.

In the emitter of the transistor 554, the memory cell potential change indicating signal CS-CUTN is generated.

In the transistors 555 to 558, internal chip select signals CS1 to CS4 are generated.

The internal chip select signals CS1 to CS4 are used to control activation / deactivation of the word line selection row address signal.

A chip select signal for controlling data write / read is propagated from the pad 570 through a separate signal path, and an internal write enable signal from the WE buffer 28 (see FIG. 1) and a logic operation are taken to record / read. To control.

In the CS word line cut mode, the signal CS W W CUT is at a high level.

In this state, when the chip select signal / CS is at the high level, all of the internal address signals are set to the unselected state (as will be described later, the connection OR logic is taken at the predecode stage).

The chip select signal / CS does not control the operation of the address buffer 14 shown in FIG.

This is to advance the time when the internal address signal is generated when the chip select signal / CS changes from the non-select state (high level) to the select state (low level).

When the current source transistor at the input terminal of the address buffer is driven after the state of the chip select signal / CS is determined, the access time becomes long because the internal chip select signal needs to be determined until the internal address signal is confirmed.

In addition, since all word lines are set to the non-selected state in the CS word line cut load, the potentials of the word lines are all fixed at a low level, thereby consuming no current.

Next, the operation of the CS buffer shown in FIG. 52 will be described.

In the normal operation mode, the control signals CS, W, and CUT are at low levels.

In this state, transistor 560 is off and transistor 572 is on.

Therefore, transistors 552 and 553 are in an inoperative state.

The potential of signal line 568 drops to low level through bipolar transistors 571 and MOS transistors 572 and 561.

At this time, since the first reference voltage Vref1 is applied to the bipolar transistor 571, when the bipolar transistor 553 is turned on, a low level signal equal to the low level potential shown in the signal line 568 can be obtained.

As a result, all of the internal chip select signals CS1 to CS4 achieve a low level.

On the other hand, the potential of the signal line 567 is pulled up by the resistor 564 so that the potential level is set to a high level, and the control signal CS-CUTN becomes a high level.

In this state, the potential of the memory cell (potential applied to the load resistance) is not changed.

Since the internal chip select signals CS1 to CS4 are all set to a low level, as described later, when the connection OR logic with the address signal provided from the X predecode circuit is taken, the predecode circuit is internally addressed from the address buffer. Performs a predecode operation according to the signal.

In the CS word line cut mode, the control signal CS W W CUT is set to a high level.

In this state, the transistor 560 is turned on and the transistor 572 is turned off.

The transistors 552 and 553 are turned on / off according to the level of the selection signal / CS applied to the pad 570, and the internal chip selection signals CS1 to CS4 also change to high level / low level.

When the chip select signal / CS is at the high level, the internal chip select signals CS1 to CS4 are all at the high level, and the result obtained by the connection OR with the internal address signal is at the high level, so that all of the address signals are set to the non-selected state. And the word lines can all be set to an unselected state.

When the chip select signal / CS is at the low level, the transistor 553 is turned on, the internal chip select signals CS1 to CS4 are at the low level, and the word line selection operation is executed in accordance with the address signal.

In the CS word line cut mode, all word lines can be set to an unselected state in the standby state, thereby reducing power consumption.

When the CS word line cut mode is not set, regardless of the level of the chip select signal / CS, the decode operation is performed internally in accordance with the address signal to execute the word line selection operation.

The data input / output operation is controlled by the chip select signal / CS (this structure is described later).

As described above, it becomes a structure that receives an address signal and generates an internal address signal irrespective of the high level low level of the chip select signal / CS, thereby achieving high-speed access.

FIG. 53 shows the specific structure of the X predecoder shown in FIG.

Fig. 53 shows a circuit portion for predecoding the two-bit address signals X2 and X3.

The address input buffer circuits 500a and 500b have the same structure as the address input buffer circuit shown in Fig. 49, and normally generate an internal address signal in accordance with bits X2 and X3 of the applied address signal.

CS buffer 12 has the same structure as in FIG.

External chip select signal / CS and internal control signal CS, The internal chip select signals CS1 to CS4 are generated according to the CUT.

The control signals CS and CUTN are not shown in FIG. 53 since they are not directly related to the predecode operation.

The X predecoder 18 is provided to correspond to the signal input lines 610 to 613 to which the address input buffer circuits 500a and 500b and the output of the CS buffer circuit 12 are connected or connected, respectively. Level conversion circuit 600a, 600b, 600c and 600d.

In the level conversion circuits 600a to 600d, the predecode signals OUT1 to OUT4 are output.

The outputs of the level conversion circuits 600a to 600d correspond to the predecode signal IN1 shown in FIG. 33, for example.

In order to generate the predecode signals IN2 and IN3 shown in FIG. 33, a structure similar to the predecode circuit shown in FIG. 53 is provided.

In the level converting circuits 600a to 600d, portions corresponding to the level converting circuit and the components of FIG.

The level converters 600a to 600d are provided between the signal line 620 and the second power supply potential Vcc, and the two-stage slaves that amplify the signal potential of the n-channel MOS transistor 601 and the output node 621 of the level converter which receive a first reference potential Vcs1 at the gate. It further includes connected inverters 602 and 603.

Transistor 601 functions as a constant current source for the emitter follower transistors of the address input buffers 500a, 500b and emitter coupled to signal line 610 and the CS input buffer.

The signal AB 610 receives the output AB4 of the address input buffer 500a, the output BA4 of the address input buffer 500b and the output CS4 of the CS input buffer 12.

The signal AB 611 receives the output AB2 of the address input buffer circuit 500a, the output AB3 of the address input buffer circuit 500b, and the output CS3 of the CS input buffer 12.

The signal line 612 transmits the output AB3 of the address input buffer circuit 500a, the output AB2 of the address input buffer 500b, and the output CS2 of the CS input buffer 12 in the form of an emitter follower.

To signal line 613, output AB1 of address input buffer circuit 500a, output AB1 of address input buffer circuit 500b, and output CS1 of CS input buffer 12 are transmitted in the form of an emitter follower.

54 shows the connection of the emitter follower transistor of the buffer circuit associated with the signal line 610. FIG.

Referring to FIG. 54, transistors 558, 508a, and 508b are emitter coupled to signal line 610.

On the bases of the transistors 508a, 508b and 558, the signal line 516 of the address input buffer circuit 500a of the address bit X2, the signal line 516 of the address input buffer circuit 500b of the address bit X3, and the CS buffer circuit 12 of the chip select signal CS Signal line 568 is connected (see FIGS. 49 and 52).

The emitters of transistors 508a, 508b and 558 are provided with an internal address AB4 of address bit X2, an internal address AB4 of address bit X3 and an internal chip select signal CS4 of chip select signal CS, respectively.

In the connection configuration shown in FIG. 54, when a high level signal is applied to the base of either transistor, the signal line 610 is at a high level.

More specifically, the highest base signal potential of transistors 508a, 508b, and 558 is transferred to signal line 610 in the form of an emitter follower.

When the internal chip select signal CS4 is at a high level, the signal line 610 is at a high level regardless of the values of the address signals X2 and X3.

When the internal chip select signal CS4 is at a low level, the potential of the signal line 610 is determined by bits X2 and X3 of the address signal.

By such emitter coupling, a concatenation OR logic is constructed, whereby shortening of access time in CS wordline cut mode and normal mode can be realized.

Since the internal address signal is continuously applied, when the chip select signal CS4 falls from the high level to the low level, the signal potential of the signal line 610 immediately becomes a level corresponding to the values of bits X2 and X3 of the address signal.

Since the operation of the level converter included in the level converters 600a to 600d is the same as the operation described above with reference to FIG. 2, a detailed description thereof will be omitted.

This level converter inverts the logic of the signal of the ECL level applied to the signal line 610, and converts the level into a CMOS level signal.

The output of this level converter is amplified by inverters 602 and 603.

Therefore, the selection of the level conversion circuits 600a to 600d shows a combination of the logic of the address signals appearing on the corresponding signal lines 610 to 613 and the address signal bits when selected.

As shown in FIG. 55, on the signal line 610, a signal indicating the result of the address bits X2 + X3 appears. Addition is performed according to the number of Boolean (Boolear).

The logic of the address signal bits appearing on the signal line 611 indicates / X2 + X3 inversion.

The logic of the signal appearing in signal line 612 is X2 + / X3.

The logic of the address signal bits appearing on signal line 613 is / X2 + / X3.

Therefore, the signal lines 610 to 613 become the low level selection states when the address signals are (0,0), (0,1), (0, 1), and (1, 1), respectively.

The outputs OUT1 to OUT4 become high levels when selected.

56 shows a schematic structure of the WE buffer shown in FIG.

56 shows only the functional structure, and no detailed structure is shown.

Referring to FIG. 56, the WE buffer 28 receives the nPn bipolar transistor 630 which receives the external chip selection signal / CS applied through the pad 570 to the base, and the external write enable signal / WE applied through the pad 636 to the base. nPn bipolar transistor 631.

Transistors 630 and 631 operate in the form of emitter followers to shift the levels of external control signals / CS and / WE.

For transistors 630 and 631 a constant current source operating in emitter follower mode is not shown.

The WE buffer 28 includes a level converter 632 for converting the emitter potential of the transistor 630 to a CMOS level signal, a level converter 633 for converting the emitter output of the transistor 631 to a CMOS level signal, and outputs of the level converters 632 and 633. And a gate circuit 634 for generating an internal output enable signal I0E in response to the gate circuit 634 and a gate circuit 635 for generating an internal write enable signal INTWE in response to the outputs of the level converters 632 and 633.

The level converters 632 and 633 have the structure shown in FIG. 2 or the structure shown in FIG. 53, and generate the internal control signal by inverting the logic of the applied external control signal.

The gate circuit 634 generates the internal output enable signal I0E when the output of the level converter 632 is at a high level and the output of the level converter 633 is at a low level.

The internal output enable signal I0E is applied to Dout and buffer 30 shown in FIG. 1 to determine the timing of the data output.

The gate circuit 635 generates the internal write enable signal INTWE in the active state (high level) when the outputs of the level converters 632 and 633 are both at high level.

The internal write enable signal INTWE corresponds to the output of inverter 200c shown in FIG.

Therefore, the internal read command signal IOE and the internal write enable signal INTWE generated in the WE buffer 28 are generated independently of the chip select signals CS1 to CS4 (see FIG. 52).

Therefore, regardless of the setting / not setting of the CS word line cud mode, control of data input / output can be performed in accordance with the external chip selection signal / CS.

[Special Mode Setting Circuit]

57 is a diagram showing the functional structures of the mode detection circuit and the operation mode command signal generation circuit shown in FIG.

Referring to FIG. 57, the mode detection circuit 35 activates the first detection circuit 650 comparing the input signal IN with the first reference potential and the output signal IN in response to the output? C of the first detection circuit 650. A second detection circuit 660 to compare with the reference level.

The operation mode instruction signal generation circuit 36 is activated in response to the output? C of the first detection circuit 650, and operates in response to the output signal of the second detection circuit 660, that is, the CS word line cut mode designation signal Cs. W. Generate the CUT and the burn-in mode designation signal BI.

Since the reference level of the first detection circuit 650 and the second detection circuit 660 are different, a plurality of operation mode indication signals can be easily generated without increasing the number of input terminals.

Next, the specific structure of each circuit is demonstrated.

58 is a diagram showing the specific structure of the first and second detection circuits of FIG.

Referring to FIG. 58, the first inspection circuit 650 includes an nPn bipolar transistor 700 receiving an input signal IN at a base, a bipolar transistor 705 receiving a reference voltage Vcs0 at a base, and an nPn receiving an emitter potential of the bipolar transistor 705 at a base. A bipolar transistor 701 and a stabilizing resistor 704 provided between the base and the emitter of the bipolar transistor 701.

Bipolar transistors 705 and 701 are connected to Darlington, and their collectors are connected to the first power potential Vcc supply node through resistor 706.

The emitters of the bipolar transistors 700 and 701 are commonly connected.

Between the emitters of the bipolar transistors 700 and 701 and the second power supply potential Vcc is provided an n-channel MOS transistor 702 that receives a reference voltage Vcs1 at its gate.

Transistor 702 functions as a constant current source for transistors 700 and 701.

The level of the reference voltage Vcs0 is shifted by the multi-arling tone connected transistors 705 and 701 to set the optimum reference voltage level for the input signal IN.

By the Darlington connection, the load capacity for the reference voltage Vcs0 source is reduced.

This is because the input impedance of the bipolar transistor can be reduced by the dahling connection.

The first detection circuit 650 includes two diodes 707a and 707b connected in series between the first power supply potential Vcc supply node and the signal line 718, an nPn bipolar transistor 708 that receives the signal potential of the signal line 718 at the base, and a bipolar transistor b 708. A p-channel MOS transistor 709 selectively conducting in response to the emitter potential of &lt; RTI ID = 0.0 &gt;, &lt; / RTI &gt; a current limiting resistor 710 for limiting the current flowing through transistor 709, and an n-channel constituting a current mirror circuit receiving current from resistor 710. MOS transistors 711 and 712, a p-channel MOS transistor 713 that receives the signal potential of signal line 718 at the gate, a transistor 712 and output signal line 719, and a resistor 714 for current / voltage conversion and current limiting, and signal line 719. And an inverter 715 that inverts the signal potential of the phase.

The emitter of transistor 708 is provided with a resistor 716 that functions as a stabilizing current source that provides a current path for transistor 708 when transistor 709 is off.

Transistor 709 receives a reference voltage Vref2 at its gate.

Transistor 708 transmits a signal on signal line 718 to one conducting terminal of transistor 709 in the form of an emitter follower.

The transistor 713 charges the output signal line 719 to the level of the first power supply potential Vcc at the time of conduction.

Next, the operation of the first detection circuit 650 will be described.

When the input signal IN is higher than the base potential of the transistor 701, the transistor 701 is turned off. The potential of the signal line 718 is turned high by the resistor 706, and the transistor 713 is turned off.

Transistor 708 transfers the signal potential on signal line 718 to one conducting terminal of transistor 709 in the form of an emitter follower.

Transistor 709 conducts and supplies current to transistor 711 through resistor 710 as long as the applied potential is at a high level (ie, greater than the sum of the absolute value of the threshold voltage of transistor 709 and reference voltage Vref2).

The transistor 712 discharges the signal line 719 by the mirror current of the current flowing through the transistor 711.

Since the potential of the signal line 719 is lowered, the output? C of the inverter 715 is at an active high level.

When the input signal IN is at the low level, current flows through the transistor 702, and the potential of the signal line 718 is at the low level.

The low level of signal line 718 is clamped by diodes 707d and 707b.

In response to the low level signal on signal line 718, transistor 713 is turned on to charge output signal line 719.

On the other hand, the emitter potential of transistor 708 is at the low level, and transistor 709 is turned off (since the emitter potential of transistor 708 is lower than the sum of the absolute values of the threshold voltages of Vref2 and MOS transistor 709), transistor 711 And 712 are turned off.

Since the potential of the output signal line 719 rises, the output? C of the inverter 715 becomes the low level in the active state.

The second detection circuit 660 is activated / deactivated by the output? C of the first detection circuit 650.

The second detection circuit 660 has nPn bipolar transistors 720 and 721 connected to the emitter in common, and receives an input signal IN and a reference voltage Vref1 to the base, and an nPn bipolar transistor 723 to receive the emitter potentials of the transistors 720 and 721 at the base. And a nPn bipolar transistor b 727 which receives the collector potential of the transistor 722 at the base, a level converter 732 for converting the level of the emitter potential of the transistor 726, and a level converter 730 for converting the level of the emitter potential of the transistor 727. Include.

The level converters 730 and 732 have the same structure as the level converter circuit shown in the second, converts the signal of the ECL level to the signal of the CMOS level and inverts its logic.

The second level detection circuit 660 includes an n-channel MOS transistor 728 connected between an emitter of transistors 720 and 721 and a second power supply potential Vcc supply node connected between the emitter of the second power supply potential Vcc, and a transistor; N-channel MOS transistor 729 connected between the emitter of 727 and the second supply potential Vcc supply node, and activation / deactivation control

Inverter for inverting the n-channel MOS transistor 733 which transfers the reference voltage Vcs1 to the gates of the transistors 736, 737, 738, and 729 in response to the signal? C (added from the first detection circuit 650), and the active / inactive control signal? C. 734 and an n-channel MOS transistor 735 that transfers the first power potential Vcc to the gates of transistors 736, 737, 728, and 729 in response to the output of inverter 734.

The operation will be described next.

When the output signal? C of the first detection circuit 650 is at the low level, the transistors 735 are turned on, the gates of the transistors 736, 737, 728 and 729 are at the level of the second power supply potential Vcc, and all of these transistors are turned off. .

As a result, no current flows through the transistors 720, 721, 722 and 723, and the base potentials of the transistors 726 and 727 are at the level of the first power potential Vcc by the resistors 724 and 725, and the emitters of the transistors 726 and 726 The potential level is also high.

In this state, the control signals? A and? B output from the level converter circuits 730 and 732 are both at the CMOS low level.

When the output signal? C from the first detection circuit 650 is at a high level, the transistor 735 is turned off, the transistor 733 is turned on, and the gate potentials of the transistors 736, 737, 738, and 729 become the potential levels of the reference voltage Vcs1. These transistors function as constant current sources.

In this state, the states of the output signals? A and? B change depending on the high / low / state of the input signal IN and the reference voltage Vref1.

When the input signal IN is higher than the reference voltage Vref1, the collector potential of the transistor 722 is lower than the collector potential of the transistor 723.

The collector potentials of transistors 722 and 723 are transferred by bipolar transistors 726 and 727 to level converters 730 and 732 in the form of emitter followers, where these potentials are level converted and logically inverted.

In this state, therefore, the signal? A is at a low level and the signal? B is at a low level.

When the input signal IN is in the open state OPEN, the transistors 700 and 720 are turned off (since the base current is not supplied), so that the signals? A,? B and? C in the same state as when the input signal IN is at a low level are output.

59 is a diagram showing the specific structure of the operation mode instruction signal generation circuit shown in FIG.

Referring to FIG. 59, the operation mode instructing signal generation circuit 36 includes a two-input NAND gate 740 that receives the signals? A and? B, an inverter 741 that inverts the output of the NAND gate 740, and a two-input that receives the signals? B and? C. A NAND gate 742 and an inverter 743 that inverts the output of the NAND gate 742.

From the inverter 741, the CS word line cut mode designation signal CS. W. The CUT is output, and the burn-in mode designation signal BI is output from the inverter 743.

The operation will be described next.

When the signal? C is in a low level inactive state, the outputs of the NAND gates 740 and 742 become the high level, and the signal CS. W. Both the CUT and BI are inactive at low level.

When the signal? C is at the low level, as described above with reference to Fig. 58, the output signals? A and? B of the second detection circuit 660 are both at the low level.

When the signal? C is at a high level, the NAND gates 740 and 742 function as inverters.

If the signal is high in this state, the CS word line cut mode designation signal CS. W. CUT goes to high level.

When the signal? B is at the high level, the burn-in mode setting signal BI is at the high level.

60 is a diagram showing the functional configuration of the memory cell potential supply circuit shown in FIG.

Referring to FIG. 60, the memory cell CS. W. A mode detection circuit 750 which is activated in response to the CUT, detects the level of the input signals INA and INB, and detects whether the memory cell hold test mode is designated according to the detection result, and for the HOLD and DOWN. The mode detection signal HOLD from the step-down circuit 760 and the mode detection circuit 750 which are activated in response to decrease the level of the first power supply voltage Vcc according to the levels of the input signals INA and INB. And a voltage switching circuit 770 which is activated in response to DOWN and supplies the stepped-down voltage of the step-down circuit 760 to the memory cell MC instead of the first power supply voltage Vcc.

The voltage from the voltage switching circuit 770 is transferred to the power supply voltage supply node 775 of the load resistors Ra and Rb included in the memory cell MC.

61 is a diagram showing the specific structure of the mode detection circuit and the step-down circuit shown in FIG.

Referring to FIG. 61, the mode detection circuit 750 includes nPn bipolar transistors 800 and 801 which receive input signals X2 and X3 from the transistors 811 and 812 (included in the step-down circuit) in the form of an emitter follower, and npn bipolars received from the base. The transistor 802 and the control signal CS. . An n-channel MOS transistor 804 at the gate of the CUT and an n-channel MOS transistor 805 for receiving the reference voltage Vcs1 at the gate.

The collectors of transistors 800 and 801 are connected to a first power potential Vcc supply node through a resistor 806, and the collector of transistors 802 is connected to a first power potential Vcc supply node through a resistor 807.

Emitters of transistors 800, 801 and 802 are commonly connected.

Transistor 804 is provided between the emitters of transistors 800-802 and transistor 805.

The transistor 805 functions as a constant current source transistor with respect to the transistors 800 to 802.

A nPn bipolar transistor 803 that receives collector potentials of transistors 800 and 801 at the base of the mode detection circuit 750, a level converter 808 for converting the ECL level emitter potential of the transistor 803 into a CMOS level signal and logic inversion; It further includes a two-stage inverter 809 for amplifying the output of the unit 808, and 810.

The level converter 808 has the same structure as the level converter circuit shown in FIG. 2 and functions the same.

The emitter of the transistor 803 includes a control signal CS. CUTN is connected or connected.

In addition, the emitter of the transistor 803 is provided with an n-channel MOS transistor 829 serving as a constant current source load.

Transistor 829 receives a reference voltage Vcs1 at its gate.

When the transistor of the input portion of the level conversion circuit 808 is turned off, the transistor 829 is connected to the transistor 803 and the control signal CS. A current path is provided for the CUTN generation transistor (see FIG. 52).

Next, the operation of the mode detection circuit 750 will be described.

In the hold down mode, a test of the data retention characteristic of the memory cell is performed.

In this case, the power supply potential of the memory cell is reduced in voltage.

Since the word line is set to the unselected state, the address signal is meaningless.

Therefore, in the memory cell hold test mode, the address signal is used as a test mode designation signal for designating the mode, and also as a signal for setting the voltage supplied to the memory cell.

Signal CS. W. Transistor 804 goes off when the CS word line cut mode is not specified because the CUT is at a low level.

In this state, the collector potentials of the transistors 800 and 801 are pulled up to the level of the first power source potential Vcc by the resistor 806.

Signal CS. W. When the CUT is at low level, signal CS. The CUTN is at the high level (see FIG. 52).

Since the base potential of the transistor 830 is at a high level, the emitter potential of the transistor 803 is also at a high level.

In this state, the output of the level converter circuit 808 becomes the CMOS low level, and the signal HOLD DOWN becomes the low level.

Therefore, the operation does not enter the memory cell hold test mode.

Signal CS. W. When the CUT is at high level, transistor 804 is turned on.

When the input signals X2 and X3 are both at low level, the collector potentials of the transistors 800 and 801 are at high level.

In this state, the output of the level converter 808 becomes the CMOS low level, and the signal HOLD and DOWN become the low level, so that the operation does not enter the memory cell hold test mode.

When one of the input signals X2 and X3 is at the high level, the collector potentials of the transistors 800 and 801 are at the low level, and the output of the transistor 803 is at the low level.

When the signal CS / CUTN is at the low level, the output of the level converter circuit 808 becomes the CMOS high level, and the signal HOLD / DOWN becomes the high level, and the operation enters the memory cell hold test mode.

In the CS word line cut mode, when the signal / CS is at the high level, the signal CS / CUTN is at the low level and the signals CS, W, and CUT are at the high level.

In other words, when the semiconductor memory device is in the non-selected state in the CS word line curd mode, the memory cell hold test mode is started.

When the signal CS / CUTN is at the high level and the output of the level converter circuit 808 is at the CMOS low level, the signal HOLD DOWN is at the low level.

In this state, the operation does not enter the memory cell hold test mode.

Signal CS. W. When the CUT is at the high level, that is, when the operation is in the CS word line cut mode, when the chip select signal / CS is at the low level, the CS CUTN is at the high level, the structure shown in FIG. As can be clearly seen from the description, the semiconductor memory device (SRAM) is placed in a selected state and access is performed (all internal chip select signals CS1 to CS4 are at a low level, and the output of the predecoder is converted according to the state of the internal address signal. ).

The step-down circuit 760 includes an nPn bipolar transistor 811 receiving the input signal X2 at the base, an nPn bipolar transistor 812 receiving the input signal X3 at the base, an n-channel MOS transistor 813 receiving the emitter potential of the bipolar transistor 811 at the gate, and a bipolar transistor. An n-channel MOS transistor 818 that receives the emitter potential of the transistor 812 at the gate, and an n-channel MOS transistor 820 which is provided between the signal line 835 and the node 836 and receives a reference voltage Vref1 at the gate.

Transistor 813 is placed between the first power potential Vcc supply node and node 836.

Transistor 818 is placed between the first power potential Vcc supply node and node 837.

The step-down circuit 760 includes a p-channel MOS transistor 821 disposed between the first power supply potential Vcc supply node and the signal line 835, a p-channel MOS transistor 822 connected to the transistor 821 in the form of a current mirror, and a resistor that receives current from the transistor 822. 823, diodes 824 and 825 connected in series with resistor 823, n-channel MOS transistor 828 placed between diode 825 and second power potential Vee supply node, and nPn bipolar transistor 827 receiving a potential at one end of resistor 823 at the base. And an n-channel MOS transistor 826 placed between the emitter of the transistor 827 and the second power supply potential Vee supply node and receiving a reference voltage Vcs1 at its gate.

Transistor 828 is turned on when the signal HOLD DOWN goes high in the memory cell hold test mode.

In this state, current flows through resistors 823 and diodes 824 and 825.

The base potential of the transistor 827 is i · R + 2 · Vth.

Where I represents the current flowing through resistor 823, R represents the resistance of resistor 823, and Vth represents the forward voltage drop of diodes 824 and 825.

Transistor 827 operates in an emitter follower manner.

Therefore, the voltage? D output from the transistor 827 is converted in accordance with the base potential of the transistor 827.

Between the transistor 821 and the second power supply potential Vee supply node, an n-channel MOS transistor 852 is provided which receives a reference voltage Vcs1 at its gate.

The step-down circuit 760 includes an n-channel MOS transistor 814 provided between the emitter of the transistor 811 and the second power potential Vee, an n-channel MOS transistor 816 provided between the node 836 and the second power potential Vee supply node, and the transistor 812. N-channel MOS transistor 817 provided between the emitter of the second power supply potential Vee supply node, n-channel MOS transistor 819 provided between the node 837 and the second power supply potential Vee supply node, and a response to the signal HOLD DOWN N-channel MOS transistor 830 for conducting the reference voltage Vcs1 to the gates of transistors 814, 816, 817, and 819, inverter 851 for inverting signal HOLD and DOWN, and conducting in response to the output of inverter 851 for transistor 814 And n-channel MOS transistors 831 for discharging the gate potentials 816, 817 and 819 to the second power potential Vee.

Transistors 816 and 819 are different in size.

The operation will be described next.

(a) When the signal HOLD DOWN is at the low level, the transistors 828 and 830 are turned off and the transistor 831 is turned on.

In this state, transistors 814, 186, 817, and 819 are all turned off, so that a constant current flows through transistors 821 and 852.

The current mirror circuit constituted by the transistors 821 and 822 generates a mirror current of the current flowing through the transistors 821 and 852.

Since transistor 828 is off, no current flows through resistors 823 and diodes 824 and 825.

Therefore, the base potential of the transistor 827 is charged to the high level by the transistor 822.

In this state, the signal? D is at a high level lower than the first power supply potential Vcc.

(b) When the signal HOLD DOWN becomes high, the transistors 828 and 830 are turned on and the transistor 831 is turned off.

In this state, transistors 814, 816, 817, and 819 all function as constant current sources.

The base potential of transistor 827 translates according to the current flowing through transistor 822.

Input signals X2 and X3 are delivered to the gates of transistors 813 and 818 in the form of emitter followers.

When the signal HOLD DOWN goes high, the operation is in the CS word line cut mode (the signal CS CUTN is at the low level (the signal / CS is the high level), and at least one of the input signals X2 and X3 is high). If you are in a level.

When the signal X2 is at the high level, the transistor 813 is turned on, and the potential of the node 836 is raised to turn the transistor 815 off.

In this state, when the input signal X3 is at the low level, the transistor 818 is turned off, and current flows through the transistor 820 from the signal line 835 to the node 837.

In contrast, when the input signal X3 is at the high level and the input signal X2 is at the low level, the transistor 813 is turned off and the transistor 818 is turned on, and current flows from the signal line 835 to the node 836.

Since the constant current sources 816 and 819 have different sizes, the transistors 815 and 820 have different magnitudes of current flowing when they are turned on.

Since the current flowing through the signal line 835 is reflected by the current mirror circuit formed by the transistors 821 and 822, the mirror current flows through the resistor 823.

Therefore, a mirror current flows through the transistor resistor 823.

Therefore, the base potential of transistor 827 changes with each state, such as (i) when only transistor 815 is on, (ii) when only transistor 820 is on, and (iii) when both of transistors 815 and 820 are on. do.

The signal? D is applied to the voltage switching circuit 770 described later and used as a memory cell power supply potential determination signal in the memory cell hold test mode.

Although signals X2 and X3 have an ECL level, transistors 813 and 815 constitute a source coupled logic gate, and transistors 818 and 820 constitute a source coupled logic gate.

Depending on the level of the input signals X2 and X3, current flows into one of the pair of transistors constituting the source coupled logic gate, similar to the emitter coupled logic gate.

At this time, a CMOS level signal can be used as the input signals X2 and X3.

In the above-described structure, when the signal HOLD.DOWN is at the high level in the memory cell hold test mode, the signal? D, that is, the voltage delivered to the power supply potential supply node of the memory cell can be switched in three steps.

62 is a diagram showing the specific structure of the voltage switching circuit shown in FIG.

Referring to FIG. 62, the voltage switching circuit 770 includes an inverter 841 for inverting the signal HOLD and DOWN, an n-channel MOS transistor 842 for transmitting a second power supply potential Vee to the signal line 846 in response to the output of the inverter 841, And an n-channel MOS transistor 840 which transfers the reference voltage Vcs1 to the signal line 846 in response to the signal HOLD DOWN.

The transistor 842 transfers the second power supply potential Vee to the signal line 846 when the signal HOLD DOWN is at a low level.

The transistor 840 transfers the reference voltage Vcs1 to the signal line 846 when the signal HOLD DOWN is at the high level.

The voltage switching circuit 770 includes an nPn bipolar transistor 843 which receives the voltage signal? D at the base, a p-channel MOS transistor 844 which transfers the first power potential Vcc to the output signal line 847 in response to the signal HOLD DOWN, and a signal line 847. And an n-channel MOS transistor 845 interposed between the second power supply potential Vee supply node and whose gate is connected to signal line 846.

The memory cell power supply potential Vcel1 is generated from the output signal line 847.

The operation will be described next.

(a) When signal HOLD ・ DOWN is low level:

In this state, the output of the inverter 841 becomes high level, and the transistor 842 is turned on.

On the other hand, transistor 840 is off.

Therefore, the potential level of the signal line 846 becomes the level of the second power source potential Vee, and the transistor 845 is turned off.

When the signal HOLD DOWN is at the low level, as described above with reference to Fig. 61, the step-down circuit 760 becomes inactive and the signal? D is at a level lower than the first power supply potential Vcc.

On the other hand, since the transistor 844 is turned on, the output signal line 847 is charged to the level of the first power source potential Vcc by the transistor 844.

As a result, the transistor 843 is turned off.

In the output signal line 847, the memory cell power supply potential Vcel1 is generated at the level of the first power supply potential Vcc.

(b) When signal HOLD DOWN is high level:

When the signal HOLD DOWN is at the high level, the memory cell hold test mode is specified.

In this state, the transistor 840 is turned on, the transistor 842 is turned off, and the potential of the signal line 846 becomes the reference voltage Vcs1, and the transistor 845 functions as a constant current source.

Transistor 844 is turned off.

Therefore, the memory cell power supply potential Vcell on the output signal line 847 becomes VBE lower than the static voltage level of the signal? D transmitted in the form of an emitter follower through the transistor 843.

As described with reference to Fig. 61, when the signal HOLD-DOWN is at the high level, the voltage level of the signal? D varies depending on the states of the input signals X2 and X3.

The potential level of the Merolicell power supply potential Vcell also changes in accordance with the signal? D of different potential levels.

In this way, the memory cell hold test is executed.

First, the signal HOLD DOWN goes low, and data is written to the memory cell by the normal access method.

Next, in the CS word line cut mode, the signal / CS is set to a high level, at least one of the input signals X2 and X3 becomes a high level, and the memory cell hold test mode designation signal HOLD DOWN is set to a high level. .

In this state, the voltage applied from the voltage switching circuit 770 to the power supply potential supply node of the memory cell is lowered.

In this memory cell hold test mode, the CS word line cut mode is specified for the following reason.

As shown in FIG. 1, the Y decoder 6, the bit line load circuit 3, and the read / write gate 4 operate independently of the chip select signal / CS.

When the word line is selected in this state, current flows from the bit line load circuit to the memory cell, and the potential of the data stored in the memory cell rises.

Therefore, it is impossible to perform the memory cell hold test.

For this reason, the CS word line cut mode is specified to set all word lines to the unselected state.

In the memory cell hold test mode, the state in which the step-down power supply potential is applied to the power supply supply node of the memory cell is maintained for a predetermined time.

Thereafter, the memory cell hold test mode is released, and according to a normal access method, when the data of the memory cell coincides with the written test data, it is determined that the memory cell operates normally.

Otherwise, it is determined that the memory cell does not satisfy the predetermined data retention characteristic.

More specifically, when the power supply voltage of the memory cell is lowered, if the data of the polyp-flop (composed by the cross-coupled transistor) is inverted, the memory cell is determined to be defective.

In this way, the dependence on the power supply voltage of the data retention characteristic of the semiconductor memory device is examined.

As described above, by connecting the plurality of detection circuits having different comparison reference voltage levels to each other and setting the internal operation mode based on the detection result of each level detection circuit, the semiconductor memory device is reliably set to the predetermined internal operation mode. Can be set to

As for the operation mode actually performed, the burn-in mode in which a plurality of word lines are set to the selected state at the same time, and the CS word line cut in which all the word lines are set to the unselected state when the semiconductor memory device is set to the unselected state. Mode, the memory cell hold test mode in which the power supply potential of the memory cell is lowered when the semiconductor memory device is not selected in the CS word line cut mode, and the normal mode in which normal access is made can be easily and accurately realized. have.

63 shows another structure of the mode detection circuit.

Referring to FIG. 63, the mode detecting circuit 35 includes an nPn bipolar transistor 901 receiving an input signal IN at a base, a diode 902 provided between an emitter (node 930) and a node 931 of the bipolar transistor 901, and nodes 931 and 932. And an n-channel MOS transistor 914 placed between the node 932 and the second power supply potential Vee supply node and receiving a reference voltage VCS at its gate.

Diode 902 lowers the emitter potential of bipolar transistor 901 by forward voltage drop.

Diode 903 lowers the potential at node 931 by forward voltage drop Vth.

Transistor 914 serves as a current source for transistor 901 and diodes 902 and 903.

The mode detection circuit 35 includes an nPn bipolar transistor 904 which receives the potential of the node 930 at the base, an nPn bipolar transistor 905 which receives the first reference transistor Vref1 at the base, a collector connected to the emitters of the transistors 904 and 905, and the base being a node. NPn bipolar transistor 906 connected to 931, nPn bipolar transistor 908 connected to the emitter of 907 and the base connected to node 932, nPn bipolar transistor 909 receiving a third reference voltage Vref3 as a base, and a reference voltage VCS at the gate. Further includes an n-channel MOS transistor 915 in which transistor 908 functions as a current source for 909.

The collector of transistor 904 is connected to a first power supply potential Vcc supply node through a resistor 920.

The collector of transistor 905 is connected to the first power supply potential Vcc supply node through a resistor 921.

The collector of transistor 907 is connected to a first power supply potential Vcc supply node through a resistor 922.

The collector of transistor 909 is connected to a first power supply potential Vcc supply node through a resistor 923.

The mode detection circuit 35 supplies nPn bipolar transistors 910, 911, 912, 913, and the like, which receive collector potentials of the bipolar transistors 904, 905, 907, and 909 to the base, respectively, and emitters of the transistors 910 to 913 and the second power supply potential Vee. And n-channel MOS transistors 916, 917, 918, 919, respectively provided between the nodes and receiving the reference voltage VCS at the gate.

The transistors 910 to 913 operate in an emitter follower manner to generate mode designation signals MODE-A, MODE-B, MODE-C, and MODE-D, respectively.

The reference voltages Vref1, Vref2 and Vref3 are set to, for example, -0.9V, -2.1V and -3.3V, respectively.

The difference between the reference voltages is set to be slightly greater than the forward voltage drop Vth of diodes 902 and 903.

The operation will be described next.

The input signal IN is transmitted to the node 930 in the form of an emitter follower by the bipolar transistor 901.

When the potential of the node 930 is represented by V (IN), the potentials of the nodes 931 and 932 may be represented by V (IN) -Vth and V (IN) -2.Vth.

When V (IN) &gt; Vref1, transistors 904, 906, and 908 are turned on.

In this state, the collector potentials of the transistors 909, 907, and 905 become high level, and the collector potential of the transistor 904 becomes low level.

Therefore, the signal MODE-A becomes low level, and the remaining signals MODE-B, MODE-C, MODE-D, etc. become high level.

When Vref1 &gt; V (IN) &gt; Vref2, bipolar transistors 904 are turned off and transistors 906 and 908 are turned on.

In this state, the collector potential of the transistor 904 becomes high level, the collector potential of the transistor 905 becomes low level, and the collector potential of the transistors 907 and 909 becomes high level.

Therefore, in this state, the signal MODE-B becomes low level and the remaining signals MODE-A, MODE-C, MODE-D, etc., all become high level.

When Vref2> V (IN)> Vref3, bipolar transistors 904 and 906 are turned off, and bipolar transistor 908 is turned on.

Since no current flows through the bipolar transistors 904 and 905, the collector potentials of the transistors 904 and 905 become high.

The collector potential of transistor 907 is discharged through transistors 908 and 915 to a low level.

The collector potential of the transistor 909 is at a high level because the transistor 908 is on.

In this state, MODE-C is at a low level, and signals MODE-A, MODE-B, and MODE-D are at a high level.

In the case of V (IN)> Vref3, all the transistors 904, 906, 908, etc. are turned off.

Therefore, the collector potentials of the transistors 904, 905, and 907 are at the high level, and the collector potential of the transistor 909 is at the low level.

More specifically, the signal MODE-D becomes low level, and the remaining signals MODE-A, MODE-B, MODE-C, etc. become high level.

By setting the potential level of the input signal IN to an appropriate level, it is possible to set one of the mode designating signals MODE-A to MODE-D to an active low level, whereby a desired operation mode can be specified.

The mode detection circuit shown in FIG. 63 can also be applied to a general operation mode detection circuit.

However, when this is applied to the structure for designating the CS word line cut mode, the memory cell hold test mode, and the burn-in mode, the operation mode designating signal generating circuit shown in FIG. 64 can be used.

Referring to FIG. 64, the operation mode designation signal generating circuit 36 receives the outputs of the level converters 920a to 920d, the level converter 920a and the output and the level converter 920b provided for the mode designation signals MODE-A to MODE-D, respectively. It consists of an input OR gate 921.

Each level converter 920A-920b has a structure similar to that of the level conversion circuit shown in FIG. 2, for example, converts an ECL level signal into a CMOS level signal and logically inverts it.

The signal HOLD / DLOWN is generated by the level converter 920a and applied to the step-down circuit 760 and the voltage switching circuit 770 shown in Figs.

The OR gate 921 generates the CS word line cut mode designation signal CS / W / CUT when the output of the level converter 920b is at the high level or the signal HOLD / DOWN is at the high level, and the CS buffer shown in FIG. To 12.

The level converter 920c generates the burn-in mode designation signal BI and applies this signal to the V address buffer circuit 520 shown in FIG. 50 and FIG.

The output of the level converter 920d is a normal mode designation signal and is not always used.

The OR gate 921 is provided because, when the memory cell hold test mode is executed under the condition that the operation is a CS wordline cut mode, it is necessary to set the signals HOLD DOWN and CS W W CUT to the active high level. .

The correspondence between the mode signals MODE-A to MODE-D and the internal operation mode designation signal is merely an example, and other combinations may be used.

By using the mode designation circuit shown in FIG. 63, any operation mode can be designated in the plurality of operation modes according to the potential level of one input signal.

The main effects obtained by the present invention are as follows.

(1) Since the input signal is transmitted to the control electrode of the second switch element which drives the signal output node at the power potential level by the current mirror operation, the semiconductor circuit which performs the switch operation at high speed can be realized. .

At this time, when the current driving capability of the first current mirror circuit is reduced, the current consumption can be reduced.

(2) An input signal is applied to the control electrode of the switching element maintained at a predetermined potential through the capacitor, and the signal output node is driven to the level of the power supply potential through this switching element.

Therefore, the switching element can be driven at high speed, and the input signal is coupled with the switching element by capacitive coupling, so that no current flows from the signal input node to the power supply potential supply node, so that the current consumption can be reduced.

(3) Since the signals applied to the first and second signal input nodes are transmitted to the second switching element through the connecting OR logic gate, the current mirror circuit is driven according to the on / off state of the first switching element to output the node. Drive to the level of the power supply potential.

Therefore, the amount of current flowing in the current mirror circuit can be made constant regardless of the logical combination of signals applied to the first and second signal input nodes, and thus the same operation regardless of the combination of logics of the first and second input signals. By nature, the output node can be driven.

(4) Also, since the signal obtained by the connection OR logic is transferred to the control electrode of the transistor constituting the current mirror circuit by capacitive coupling, the current mirror circuit can be driven at high speed.

(5) Third and fourth transistors are provided corresponding to the first transistor element for receiving the reference voltage used in the level conversion circuit at the control electrode and the second transistor element for charging the output node according to the input signal. The reference voltage is generated and transmitted to the control electrode of the first transistor element so that the current ratio flowing through the third and fourth transistors is constant.

Therefore, the current ratio flowing through the first and second transistor elements of the level converting circuit can be kept constant, so that the reference voltage can be accurately generated according to the operating characteristics of the level converting circuit.

(6) The third and fourth transistor elements are provided corresponding to the first transistor element serving as a current source of the current mirror circuit constituting the level conversion circuit and the second transistor element charging the output node. A reference voltage is generated by converting the currents supplied by the third and fourth transistor elements into voltages and differentially amplifying them, and the generated reference voltage is applied to the control electrode of the first transistor element.

Therefore, the differentially amplified reference voltage is fed back to the control electrode of the fourth transistor element, and the ratio of the current supplied by the third and fourth transistor elements is kept constant, so that the first and second transistors of the level conversion circuit are maintained. The ratio of the current flowing through the device is kept constant.

Therefore, a reference voltage can be generated that can compensate for variations in the characteristics of the transistor elements constituting the level conversion circuit and can realize desired operating characteristics.

(7) a first switching transistor which receives a reference voltage to the control electrode and is connected according to the level of the input signal to supply current to the current mirror circuit and a second switching transistor that is turned on to charge the output node according to the level of the input signal. A third transistor element is provided corresponding to the second switching transistor, and the current supplied by the third transistor element is 'reflected' in the form of a current mirror to generate a reamer current. The mirror current is converted into a voltage to generate a reference voltage, which is applied to the control electrode of the first transistor element.

In this case, the ratio of the mirror current and the current supplied by the third transistor element corresponds to the ratio of currents supplied by the second and first transistor elements, respectively.

Therefore, a reference voltage can be generated that realizes the desired output signal amplitude depending on the characteristics of the components of the level converting circuit.

(8) A current is generated from a constant potential to generate a mirror current, and a reference voltage is generated from this mirror current, and a reference circuit is provided to adjust the reference voltage in inverse proportion to the change in the power supply voltage. A constant reference voltage can be generated without.

(9) In a circuit including a resistor connected to a first power supply supply node and a current source for supplying a constant current to the resistor, the potential of the voltage output node of the resistor is adjusted in inverse proportion to the change in the second power supply potential. Thus, a constant reference voltage can be generated regardless of the fluctuation of the power supply potential.

(10) Since the preliminary decode circuit and the normal decode circuit have the same logic number and are made to have different logic configurations, the output load of the preceding circuit can be reduced, and it is related to the selection of the preliminary decode circuit and the ordinary decode circuit. Without this, the device can operate at the same speed, thereby reducing access time.

(11) When the spare memory cell is not used, the operating power potential is not supplied to the logic gate which is a component thereof, and the spare circuit can be set to the non-selected state without cutting the fuse device. The number can be greatly reduced.

(12) Since the activation / deactivation of the controlled circuit can be controlled by cutting / de-cutting the first and second fuse elements, the circuit once activated or deactivated can be reactivated or deactivated, thereby preventing incorrect programming of the circuit. You can prevent it.

In addition, when a plurality of active control circuits and controlled circuits are provided, a controlled circuit having an optimal characteristic can be selected by operating the controlled circuit and measuring its operating characteristics.

Therefore, a circuit for realizing an optimum circuit operation can be easily realized.

(13) To raise the potential of the bit line of the bit line pair, cross-coupled transistor pairs are used.

Therefore, the high level potential of the bit line can be high enough.

Since a voltage lower than the power supply voltage is supplied to the power supply node of the cross-coupled transistor pair, the high level of the bit line current is lower than the level of the power supply potential, so that the amplitude of the bit line current at the time of data writing can be reduced. After recording, the margin for recovery will increase.

(14) A gate for connecting the first and second data buses to a specific bit line pair in accordance with the first and second column selection signals is provided, and the bit line potential of the specific bit line pair is determined by the first and second columns. Only when the column select signal of 2 is inactive, indicating a non-select state, is pulled to the level of the power potential, and this gate is turned on when the first and second column select signals are in an inactive state, which is not selected. The bit lines of the pair of bit lines are connected so that a particular word line pair can be selected by a separate bit line pair.

(15) Even if the write gate corresponding to the selected bit line pair is turned off after data writing, the write data bus is maintained at the potential level of the internal write data for a predetermined period, and the potential of the write data bus is connected to the read data bus and the read gate. Is passed on to the bitline pair.

Therefore, the bit potential of the low potential can be raised quickly, and the equalization of the bit line potential can be completed at a high speed, and the margin for recovery after writing becomes large.

(16) Since the input signal is compared with a plurality of comparison reference voltages to generate a predetermined operation mode designation signal, and the internal circuit is set to the predetermined operation mode, the operation mode in which the internal circuit is easily desired by the simple circuit structure is assured. Can be set.

(17) The input signals are compared by the first and second comparing means according to different levels of reference voltage, the second comparing means is activated in response to the output of the first comparing means, and the first and second The first operation mode designation signal is generated according to the output of the comparison means, the level of the second input signal activated in response to the first operation mode designation signal is detected, and the mode detection signal is generated according to the mode detection result. In accordance with the non-mode detection signal, the internal circuit is set to a predetermined operation mode.

Therefore, the internal circuit is set to the predetermined operation mode only when the input signal reaches the predetermined level.

Therefore, it is possible to accurately set the internal operation mode without malfunction.

(18) Also, since the power supply voltage is stepped down in accordance with the mode detection signal, and the output of the step-down circuit is output in accordance with the mode detection signal, the internal power supply voltage can be surely lowered only in the predetermined operation mode.

While the invention has been described and illustrated in detail, it is clear that this is only a description and example and should not be taken as a limitation, and the spirit and scope of the invention is limited only by the terms of the appended claims.

Claims (73)

A signal input node (NA; NA1); A first switching element (Q2; MQ2), in which one conductive electrode node and a control electrode node are connected to each other, and connected according to a potential level of an input signal applied to the input node; A signal output node NB; A second switching element (Q4; MQ4) connected to a control electrode node of the first switching element and driving the signal output node to a predetermined potential level; And a capacitor (Cs) for transferring the input signal to the control electrodes of the first and second switching elements by capacitive coupling. The semiconductor circuit according to claim 1, further comprising a third switch element (Q1) provided between said signal input node and said one conducting electrode node and receiving a predetermined reference potential at a control electrode node. The semiconductor circuit according to claim 1, further comprising a third switching element (Q3) connected between said output node and a node receiving another power supply potential, and a control electrode node connected to said input node. The method of claim 1, wherein the capacitor Cs is formed between the first conductive layer 52, the second conductive layer 53, and the first and second conductive layers, respectively, connected to the input node. And a third conductive layer (54) connected to an electrode node and said one conductive electrode node of said first switching element. 2. The semiconductor circuit according to claim 1, further comprising a clamping element (06; PQ2) for clamping the potential of the control electrode node of the first switching element to a predetermined potential level. 6. The semiconductor circuit according to claim 5, wherein the clamping element (06; PQ2) consists of a bipolar transistor (Q6) which operates in an emitter follower manner to transfer a reference potential to the control electrode node of the first transistor element. 2. The method of claim 1, wherein (a) a threshold voltage for turning on is received and a reference voltage is received at the control electrode node through the resistor R, and a conductive terminal has a potential lower than the potential of the control electrode node by the threshold voltage. A transistor element Q6 for transmitting a to the control electrode node of the first switching element, and (b) another capacitor element Cc connected between the input node and the control electrode of the transistor element Q6. The semiconductor circuit further having. A semiconductor circuit according to claim 1, wherein said first switching element (Q2) and said second switching element (Q4) constitute a current mirror circuit. 2. The apparatus of claim 1, further comprising: another signal input node (NA2) for receiving another input signal complementary to the input signal; And a third switching element (MQ3) for supplying current to the second switching element in response to the another input signal. A semiconductor circuit according to claim 1, further comprising latch / amplification means (IV, Q5; IVA, IVB) for amplifying and latching the potential of the output node. A signal input node NA; A signal output node NB; A switching element (QA; QB) having a control electrode node and driving the output node to a level of a power potential according to the potential of the control electrode node; A capacitor (CA; CB) provided between the signal input node and a control electrode node of the switching element; And a potential holding means (RA; RB) for holding the control electrode node of the switching element at a predetermined potential level. 12. The switching element (QA; QB) has a threshold voltage for turning on, one conducting electrode node is connected to receive the power potential, and the other conducting electrode node is connected to the signal output node. A semiconductor including an element for maintaining the voltage between the control electrode node and the one conductive electrode node of the switching element at the threshold voltage. Circuit. 12. The apparatus of claim 11, further comprising: another switching element (QB) QA having a control electrode node and transferring another power supply potential to the signal output node in response to a potential of the control electrode node; A potential holding means (RB) RA for holding the potential of the control electrode node of the element at a predetermined potential and another capacitor connected between the signal input node and the control electrode node of the another switching element; A semiconductor circuit further comprising (RB; RA). The method of claim 13, wherein the switching element (QB; QA) has a threshold voltage for turning on, one conducting electrode node is connected to receive another power supply potential, and another conducting electrode node is connected to the An insulated gate transistor connected to a signal output node, wherein said another potential holding means (RB) RA has a potential equal to the sum of said threshold voltage of said another switching element and said another power supply potential; A semiconductor circuit comprising an element RB; A first signal input node (/ IN1, IN1); Second signal input nodes (/ IN2, IN2); Signal output nodes D1, D2; D3, D4; A connecting OR logic gate receiving potentials of the first and second signal input nodes; A first transistor element Q2 conducting in response to the potential level of the output of the connected OR logic gate; And a second transistor (Q4) or the like connected to the first transistor in a current mirror form to drive the signal output node at a level of a power potential. The capacitor Cs of claim 15, wherein the control electrode nodes of the first and second transistors Q2 and Q4 are capacitively coupled to the output nodes of the connection OR logic gates D1, D2; D3 and D4. The semiconductor circuit further having. 16. The circuit of claim 15, wherein the connected OR logic gates (D1, D2; D3, D4) comprise a first diode (D1; D3) with an anode connected to the first signal input, and an anode with the second signal. And a second diode (D2; D4) connected to an input and having a cathode of the first diode and a cathode of the second diode connected to each other. 17. The first conductive layer (65) of claim 16, wherein the capacitor (Cs) is connected to the control electrode nodes of the first and second transistors (Q2, Q4) and the first conductive layer. And a second conductive layer (64) formed at and connected to a signal output node of the connection OR logic gates (D1, D2; D3, D4). 18. The n-type impurity formed in the surface of the semiconductor body according to claim 17, wherein the first diode D1 has an anode as the first p-type impurity region 61 formed on the surface of the semiconductor body region 60. A semiconductor circuit comprising a region (63) as a cathode, and a second diode (D2) including the p-type impurity region formed on the surface of the semiconductor body as an anode and the n-type impurity region as a cathode. 16. The third transistor device of claim 15, further comprising: a third transistor device having a control electrode node connected between an output node of the connection OR logic gates D3 and D4 and the first transistor element Q1, and receiving a predetermined reference potential. A semiconductor circuit further having (Q1). The method of claim 15, wherein the third signal input node (IN1) receiving the input signal complementary to the input signal applied to the first input node (IN1) and one conductive electrode node to receive another power potential. A third transistor element (PQ1) connected with another conducting electrode node connected to said first transistor element, and a control electrode node receiving an input signal applied to said third signal input node; A fourth signal input node IN2 receiving an input signal complementary to the input signal applied to the second input node, and one conducting electrode node are connected to receive another power potential; And a fourth transistor (PQ2) connected to the first transistor (Q1) and having a control electrode node receiving an input signal applied to the fourth signal input node. The third transistor device (PQ3; PQ5) connected in response to an input signal applied to the first signal input node (/ IN, IN1), and the second signal input node (/ IN2, A fourth transistor element (PQ4; PQ6) which is conducted in response to an input signal applied to IN2), and a semiconductor further having another power supply potential transferred when both the third and fourth transistor elements are conducted; Circuit. A circuit for generating a reference voltage used in the level converting circuit 65 for converting the logic amplitude of an input signal, wherein the level converting circuit 65 is turned on in response to a first level potential of the input signal to generate a signal output node ( A first transistor element Q2 for driving Out to a level of a first power supply potential, and a second transistor element Q1 that is connected when the input signal is at a potential of a second level while receiving the reference voltage from a control electrode node; ) And driving stages Q3 and Q4 which operate in the form of a current mirror when the second transistor element Q1 is conductive to drive the output node to a second power potential level, and the first transistor. A third transistor element MP1 provided corresponding to element Q2 and electrically conducting when the first level potential is received by a control electrode to supply current from the first power supply potential supply node; and the second transistor element For A fourth transistor element provided in response to the second level potential at one conductive electrode node, receiving the reference voltage at a control electrode node, and supplying current from the one conductive electrode node to the other conductive electrode node; (MP2) and means (OP) for maintaining a constant ratio of the current supplied from the third and fourth transistor element, and the reference voltage according to the current supplied from the third and fourth transistor element And a means for generating the reference voltage (OP, R1, R2) and the like including means for generating. 24. The apparatus of claim 23, wherein the means for generating the reference voltage (OP, R1, R2) comprises: current / voltage converting means (R1, R2) for converting current supplied from the third and fourth transistor elements into voltage; And differential amplifying means (OP) for differentially amplifying the voltage converted by said current / voltage converting means to generate said reference voltage. 25. The device of claim 24, wherein the current / voltage converting means (R1, R2) are connected between the fourth transistor element (MP2) and the second power supply potential supply node and the applied voltage is applied to the negative input of the differential amplifying means. A second positive element connected between the applied first resistance element R2, the third transistor MP1 and the second power supply potential supply node, and the applied voltage being applied to the positive input of the differential amplifying means; A semiconductor circuit comprising a ruler (R1). 25. The method of claim 24, wherein the first transistor element Q2 comprises a first transconductance β1 and the second transistor element Q1 comprises a second transistor conductance β2. 3. The semiconductor circuit of the third transistor β3, wherein the fourth transistor element (MP2) has a fourth transconductance β4, and is β1 / β2〓β3 / β4. A circuit for generating a reference voltage for use in a level conversion circuit (65) for converting a logic amplitude of an input signal, wherein the level conversion circuit (65) is conducted in response to a first level potential of the input signal so as to output a signal output node. A first transistor element (Q2) for driving N to a first power potential level, a second transistor element (Q1) receiving the reference voltage from a control electrode node and conducting when the input signal is at a second level potential; And a driving stage (Q3, Q4) for operating the signal output node to the second power potential level by operating in the form of a current mirror when the second transistor element is turned on, and receives the first level potential from the control electrode node. A third transistor element DQ2 for supplying current from the first power potential supply node; Mirror current is generated by 'reflecting' the current supplied from the third transistor element DQ2 in the form of a current mirror, and the ratio of the mirror current and the current supplied by the third transistor is the second transistor element Q1. Current mirror means (DQ3, DQ4) corresponding to a ratio of the current supplied by the current supplied by the first transistor element (Q2); A reference voltage generating circuit having means (DQ1; DQ1, BP1, MN1) for converting the mirror current into a voltage to generate the reference voltage The current mirror means of claim 27, wherein the conversion means DQ1 (DQ1, BP1, MN1) receives the second level potential at one conductive electrode node, and a control electrode node and the other conductive electrode node are connected to each other. A semiconductor circuit comprising a fourth transistor (DQ1) for supplying current to (DQ3, DQ4). 29. The method of claim 28, wherein the first transistor element (Q2) is a first transistor conductance β1, the second transistor element (Q1) is a second transistor conductance β2, the third transistor element (DQ2) is a third transistor conductance. and a fourth transistor element (DQ1) has a fourth transistor (β4), and is β1 / β2 / β3 / β4. 28. The apparatus of claim 27, wherein the means for conversion (DQ1; DQ1, BP1, MN1) are resistor connected to provide current to the current mirror means (DQ3, DQ4) for generating the mirror current from a first power supply potential supply node. A fifth transistor device BP1 having a fourth transistor DQ1 and a threshold voltage for turning on, and transferring the voltage lower than the voltage generated by the fourth transistor device by the threshold voltage to generate the reference voltage; Semiconductor circuit comprising a. Reference potential generating means (80) for generating a reference potential; Current generating means (RQ6) for generating a current according to the reference potential; Current mirror means (RP2, PR1) for generating a mirror current flowing in the current mirror form from the current generated by the current generation means from the first power potential supply node (Vcc) to the second power potential supply node (Vee) and Reference voltage generating means (RN1) for generating a reference voltage from the mirror current; A reference voltage generating circuit having means (MP2; RN2) or the like for adjusting the reference voltage in inverse proportion to the change in the second power supply potential 32. The device of claim 31, wherein the current mirror means (RP2; RN2) is (a) a first transistor element (RP2) and (b) the diode is connected between the first power supply potential supply node and the current generating means (RQ6). And a second transistor element RP1 connected to the first transistor element RP2 in the form of a current mirror to generate the mirror current, wherein the adjusting means MP3 and RN1 are arranged in parallel with the first transistor element. And a third transistor element (MP3) connected to and receiving a second power supply potential at a control electrode node. The semiconductor circuit according to claim 32, wherein the conductivity of the first transistor element (RP2) and the third transistor element is the same. 32. The method of claim 31, wherein the reference voltage generating means (RN1) is commonly connected to one conductive electrode node and an output node (ND3) in which the control electrode node generates the reference voltage, and the other conductive electrode node is formed. A second transistor element having a first transistor element connected to receive a second power potential, and the means for adjustment (MP3; RN2) is connected in parallel with the first transistor element and receives a first power potential at a control electrode node; A semiconductor circuit having (RN2). 32. The semiconductor circuit according to claim 31, wherein said current generating means (RD6) comprises a bipolar transistor (RQ6) receiving said reference voltage at a base electrode node. A resistor element RR20 whose one end is connected to the first power potential supply node; Current source means (RQ2, RQ1, RQ3, RQ4, RR1 to RR6) provided with the other end (ND2) of the resistance element between the second power supply potential supply node and determining the amount of current flowing through the resistance element; An output transistor (RQ10) for generating a reference voltage (VREF1) by transferring a potential of the other end of the resistance element in the form of an emitter follower; And a reference voltage generating circuit (80) having means (MP4, RR21) or the like for adjusting the potential of the other end of the resistance element in inverse proportion to the change of the second power source potential. 37. The control device according to claim 36, wherein the means for adjusting (MP4, RR21) includes a variable resistance means (MP4) connected in parallel with the resistance element (RR20) and receives the second power potential at a control electrode node. A semiconductor circuit comprising a transistor element (MP4) whose conductance changes in inverse proportion to a change in power supply potential. Ordinary decoding means for generating a signal for decoding the address signal and selecting a memory cell designated by the address signal when the address signal designates a normal memory cell in a memory array including a plurality of memory cells; When the address signal designates a bad memory cell in the memory array, a signal is generated which decodes the address signal to select a spare memory cell for replacement with the bad memory cell and has the same number of logic gates as the normal decode means. A circuit for decoding an address signal having a preliminary decoding means (260) having a logical gate structure different from the number of logical stages. 39. The apparatus of claim 38, wherein the address signal comprises a plurality of bits and a conventional decode means 250 includes a multi-bit logic gate that receives a predetermined combination of the plurality of bits at an input, wherein the preliminary decode Means (260) comprising input stage inverters (261a to 261c) provided at the input stages corresponding to the plurality of bits. 39. The apparatus according to claim 38, further comprising pre-decoding means (18) for pre-decoding an address signal corresponding to an externally applied address signal and applying a pre-decoded signal as said address signal to said normal and spare decode means (250,260). A semiconductor circuit comprising. A transistor device pair (PM, NM) and the transistor according to claim 31, wherein said ordinary decode means (250) comprises an inverter (253) at its output stage and said inverter (253) is usually turned on and off complementary to each other. A semiconductor circuit comprising a fusible conductor (Fu) connected between one of a pair of devices and a power supply potential supply node. 39. The apparatus of claim 38, further comprising activation means (270; 285) programmed to generate an activation signal when a bad memory cell is present in the memory array, and wherein the preliminary decode means (260) uses the address signal as an input signal. And an inverter (261aa to 261cd) for receiving the activation signal as one operating power supply potential at an input terminal. Means for generating a spare memory cell use instruction signal indicating that the spare memory cell is usable as a spare decode circuit for replacing the designated defective memory cell with a spare memory cell when the multi-bit address signal designates a defective memory cell; ; 285); A plurality of logic gates 261aa to 261cd receiving each bit of the address signal; Extra activation means (271; 285) for supplying an operating power supply potential to each of said plurality of logic gates in response to said preliminary memory cell use instruction signal; Logic gates (262, 263; 262a, 262b, 263) of a next stage receiving an output signal of a logic gate selected from the plurality of logic gates through an input signal line; And a fuse device (F00 to F13, F0 to F3; F00a to F13a) provided between each output of the plurality of logic gates and an input signal line of the next logic gate. The semiconductor circuit according to claim 43, wherein said plurality of logic gates (261aa to 261cd) comprise an inverter. 44. The logic gate of claim 43 wherein the plurality of logic gates 261aa-261cd are grouped into groups corresponding to each bit of the address signal, and the next logic gates 262, 263; 262a, 263 are (a). First logic gates 262 and 262a receiving the outputs of the first and second groups of the plurality of logic gates on the first and second conductor lines 274, 275; 274a and 275a, respectively, through corresponding fuse elements; b) an output of the first logic gate and an output of the third group of the plurality of logic gates are received through a corresponding fuse element to a third conductor line, wherein the first to third conductor lines are connected to the input signal line; And a second logic gate (263; 263a) constituting the semiconductor circuit. 45. The logic circuit of claim 43, wherein the logic gate 263b of another next stage receiving the outputs of logic gates 261aa to 261cd among the plurality of logic gates and the output of the corresponding logic gate are connected to the next next stage. And another fuse element (F00b to F13b) provided correspondingly to each of said plurality of logic gates for selective transfer to a logic gate. A circuit for controlling the activation and deactivation of a predetermined circuit, comprising: first and second fuse elements FAa, FBa to FAc, FBc; FCa, FDa, FCb, FDb; 450a, 450b; First setting means (451A, 452) for detecting a break in one of the first and second fuse elements and setting the predetermined circuit in an active or inactive state according to a detection result; Second setting means 451b, 452 for detecting simultaneous connection or simultaneous disconnection of the first and second fuse elements and setting the predetermined circuit to a state different from that set by the first setting means according to a detection result; Activating control circuit. A circuit for controlling activation and deactivation of a predetermined circuit, comprising: first fuse elements 450a and 460a; First detection elements (451a; 462a) for detecting whether the fuse is cut; Second fuse elements 450b and 460b provided separately from the first fuse element; Second detection devices (451b and 462b) for detecting whether the second fuse device is cut off; An activation control circuit having logic gates (452,453; 463a to 468a, 463b to 468b) logic gates for controlling activation or deactivation of the predetermined circuit in response to outputs of the first and second detection elements. 49. The gate controller 452 of claim 48, wherein the logic gates 452, 453; 463a to 468a, 463b to 468b detect that the outputs of the first and second detection elements are equal in logic to each other. Activation control circuit consisting of -468b). 49. The display device of claim 48, wherein the logic gates 452 and 453; 463a to 468a and 463b to 468b invert the output of the first detection element 462a and the second detection element 462b. A second inverter 463b for inverting the output of the first transistor, a first transistor element 465a for receiving the output of the first detection element at the control electrode node, and a control electrode node receiving the output of the second detection element; A second transistor 465b connected between the first power supply node and an output node receiving one power potential in series with the first transistor element, and a third transistor receiving the output of the first detection element at a control electrode node; A fourth transistor element connected between the element 466a and a second power node receiving the output of the second inverter at a control electrode node and connected in series with the third transistor element in series with the output node; 466b, the control electrode A fifth transistor element 467b receiving an output of a second inverter and a control electrode node connected between the first power node and the output node in series with the fifth transistor element receiving the output of the first inverter; The sixth transistor element 467a, the seventh transistor element 468a receiving the output of the first inverter at the control electrode node, and the seventh transistor element receiving the output of the second detection element at the control electrode node. And an eighth transistor element (468b) connected in series between said output node and said second power node. Bit line pairs 155a and 155b connecting memory cells of one column; A pair of transistor elements (241, 242) in which a first conductive node and a control electrode node are cross coupled to each other and the first conductive node is connected to different bit lines of the pair of bit lines; And a device (243) for supplying a potential lower than a power supply potential to another conducting node of each of the pair of transistor elements. A semiconductor memory device for inputting and outputting multibit data, comprising: a first data bus (LDB1; LWB1) provided corresponding to a first data bit of the multibit data; A second data bus (LDB2; LWB2) provided corresponding to the second data bits of the debit data; A plurality of bit line pairs B11 to B22 including a specific bit line pair B21 and to which memory cells of one column are connected to each other; Column decode means (6) for decoding an address signal and generating a column selection signal for simultaneously designating a pair of bit lines to be connected in parallel to said first and second data buses in said plurality of bit line pairs; First gate means (421a, 421b) connected in response to a first column selection signal from a first output node of said column decode means to couple said particular pair of bit lines to said first data bus; Conducted in response to a second column selection signal from a second output node of the column decode means, connecting the particular bit line pair to the second data bus and having only one of the first and second gate means. Second gate means (420a, 420b) set to a state of operating in response to the generated column selection signal; Load means for each bit line of the specific bit line pair to raise a potential to a power potential when the first and second column select signals are in an inactive state indicating an unselected state; A semiconductor memory device provided in series between said particular pair of bit lines and having first and second switching elements 424a and 424b that are respectively connected in response to an inactive state of said first and second column select signals; . 53. The apparatus of claim 52, wherein the load means (422a, 422b, 423a, 423b; 422a, 422b, 423a, 423b, 25d, 425b, 426a, 426b) transfers a power potential in response to an inactive first column selection signal. A first transistor element 423a, a second transistor element 423b that transmits a power potential in response to an inactive first column selection signal, and a first transistor element in response to an inactive second column selection signal A third transistor element 422a for transmitting the power potential to one bit line through the second transistor element 422a, and a fourth transistor element 422b for transferring the power potential to the other bit line in response to the inactive second column selection signal. And a semiconductor memory device. A fifth transistor element (426a) according to claim 53, wherein said load means (422a, 422b, 423a, 423b; 425a, 425b, 426a, 426b) transfers a power potential in response to an inactive second column selection signal. A sixth transistor element 425a which transfers the power potential received from the fifth transistor to one bit line in response to an inactive first column selection signal; The seventh transistor element 426b which transmits in response to the inactive second column selection signal, and the power supply potential received from the seventh transistor element in response to the inactive first column selection signal to another bit line And an eighth transistor device (425b) or the like. 53. The apparatus of claim 52, wherein the specific bit line pair B21 and the other bit line pairs B11 to B20 and B22 have a smaller current driving capability than the first and second switching elements 424a and 424b. And a switching element (427) for shorting bit lines of corresponding bit line pairs in response to corresponding column selection signals in an inactive state. 54. The current driving device according to claim 53, wherein the current drive is smaller than the first to fourth transistor elements 422a and 423b for each of the specific bit line pair B21 and the other bit line pairs B11 to B20 and B22. And a transistor element (426a, 426b) capable of bringing the bit lines of the corresponding bit line pair to the power potential in response to a corresponding column selection signal in an inactive state. Bit line pairs 155a and 155b for connecting one column of memory cells; Recording means (170) for generating a recording gate selection signal for selecting the bit line pair in response to a column selection signal at the time of data writing; A write gate (151) for connecting the pair of bit lines to write data buses (163a, 163b) in response to the write gate select signal; A read gate (152) for connecting the bit line pair to a read data bus (164a, 164b) in response to the column select signal; A write driver (33) which remains active for a predetermined time and transfers complementary write data to the write data bus when the column select signal is activated even after the write gate select signal is deactivated at the time of data writing; And precharge means (162a, 162b) for supplying a high potential to a low potential bus line of said read data bus in response to deactivation of said write gate select signal and to write data on said write data bus. 58. The device of claim 57, wherein the precharge means (162a, 162b) is turned on in response to a control signal and the first transistor element (188a) responds to a potential on one busline of the write data bus and And a second transistor element 188b connected in series between a power supply node supplying a high potential and a bus line of the read data bus, and a third transistor element turned on in response to the control signal. 189a, and a fourth, which is turned on in response to the potential of the other busline of the write data bus and wherein the third and fourth transistor elements are connected in series between the power node and the other busline of the read data bus. A semiconductor memory device including a transistor element 189b and the like. 58. The apparatus according to claim 57, further comprising: decoding means (25, 6) for decoding the applied address signal to generate said column selection signal with a first delay time, and shorter than said first delay time in response to a recording mode designation signal. A recording control means 190 for generating a write enable signal for a predetermined time after the second delay time, and a third delay longer than the first and second delay times in response to the second write enable signal being active. Means (31) for activating the write driver (33) with time and deactivating the write driver with a fourth delay time shorter than the third delay time in response to the write enable signal being inactive; A pulse generator 191 for generating a one-shot pulse signal having a predetermined activation time in response to the write enable signal being active, and the one short pulse being activated And means (192) for activating the recording means (170) in response to this and activating the precharge means (162a, 162b) in response to the one-shot pulse being inactive. 58. The apparatus according to claim 57, further comprising: recording control means (190) for generating a write enable signal with a first delay in response to a recording mode designation signal, and in response to the recording enable signal being active; Means (31,192) for activating the recording means (170) and for activating the precharge means (162a, 162b) in response to the inactivation of the recording enable signal, and in response to the recording enable signal; And a means (31) for activating the write driver (33) after activation. Level determining means (901 to 913) having a plurality of comparison reference voltage levels for determining the potential level of the input signal; Means (910 to 913) for generating an operation mode designation signal for deciding a predetermined operation mode in accordance with the output of the level determining means; And a mode setting means (36) for setting the internal circuit to the designated operation mode in response to the operation mode designation signal. 62. The apparatus according to claim 61, wherein the level determining circuits are provided in correspondence with a plurality of voltage drop elements 902,903 connected in series to sequentially drop the voltage level of the input signal, and the plurality of voltage drop means. And a plurality of comparators (904 to 909) including a first comparator for comparing an output of the voltage drop element with a different reference voltage and comparing an input signal with a predetermined reference voltage. 63. The semiconductor memory device according to claim 62, wherein each of said plurality of cascaded comparisons comprises emitter coupling logic and a common emitter of emitter coupling logic (904 to 909) is coupled to a next transistor element. 62. The N voltage drop elements 902 and 903 of claim 61, wherein the level determining means 901 to 909 are connected in series between the first node 930 and the second node receiving the input signal when N is an integer. And (N + 1) first transistors 904, 906, and 908 provided between the corresponding first node 930 and the output nodes of the plurality of voltage drop elements and receiving a signal of a corresponding node from a control electrode and connected in series with each other. ), Which is provided corresponding to the (N + 1) first transistors, receives a different reference voltage from each control node, and one conducting node of the first transistor is connected to one conducting node of the corresponding second transistor. And (N + 1) second transistors (905,907,909). 65. The apparatus of claim 64, wherein the means for generating (910-913) is provided corresponding to a first transistor provided for a first node and the (N + 1) second transistors and further conducting a corresponding transistor. And (N + 2) third transistor elements (910-913) for generating signals corresponding to the potentials of the nodes. First comparing means (650) for comparing an input signal with a first reference voltage; Second comparing means 660 for comparing the input signal with a second reference voltage; First operation mode designation signal generating means (36) for generating a first operation mode designation signal in response to an output of said first and second comparing means; Mode detection means (750) which is activated in response to the first operation mode designation signal to detect the potential level of the second input signal and generate a mode detection signal in accordance with the detection result; And a mode switching means (770) for setting an internal circuit to an operation mode designated by the mode detection signal in response to the mode detection signal. 67. The semiconductor memory device according to claim 66, wherein said first comparing means (650) comprises means (701 to 715) for activating said second comparing means in response to said input signal. 67. The apparatus of claim 66, wherein the first comparing means 650 performs the second comparing means 660 and the first operation mode designating signal generating means 36 when the internal input signal is higher than the first reference voltage. Semiconductor memory device activated. 68. The semiconductor memory device according to claim 67, wherein said second comparing means (660) comprises means (726-730) for generating a complementary signal in accordance with a result of comparing said input signal with said second reference voltage upon activation. 63. The apparatus of claim 62, further comprising: step-down means (760) which is activated in response to the mode detection signal to step down the power supply voltage according to the potential level of the second input signal; And a power supply voltage switching means (770) for selectively passing the output of the step-down means and the power supply voltage in response to the mode detection signal. 71. The apparatus of claim 70, wherein the second input signal consists of a plurality of bits (x2, x3) and the step-down means are provided corresponding to the plurality of bits, each of which differs in response to a corresponding bit. A plurality of current elements 813, 815, 818, 820 causing a flow, a current adding means 821 for flowing a current corresponding to the sum of the currents generated by the plurality of current elements, and the current adding means And a converter (822, 826) for converting current into voltage. 71. The semiconductor memory device according to claim 70, further comprising a plurality of memory cells (MC) each including a polyp flop having a power node (775) for receiving a voltage from the power voltage switching means (770). A semiconductor memory device including a plurality of static type memory cells MC arranged in rows and columns and operable in a test mode for testing a hold voltage of a plurality of memory cells, the memory device comprising: A plurality of word lines WL disposed corresponding to the rows of cells and respectively connecting the memory cells of the corresponding rows; Means (12) for responding to a test mode designation signal for designating said test mode for holding said plurality of word lines in a mode non-selected state; Means (750, 760, 770) including means (760, 770) for changing a level of voltage applied to power nodes of a plurality of memory cells in response to the test mode designation signal and for selecting a plurality of predetermined voltage levels in response to an external control signal. And a semiconductor memory device.