JP4830504B2 - Level conversion circuit and display device - Google Patents

Description

  The present invention relates to a level conversion circuit and a display device using the level conversion circuit, and more particularly to a level conversion circuit formed on an insulating substrate and the level conversion circuit formed on the same insulating substrate as the pixel array unit. The present invention relates to a panel type display device.

  Conventionally, a current mirror type level conversion circuit configured using a current mirror circuit as a level conversion circuit (level shift circuit) that converts a first level signal into a second level signal different from the first level. Is known (see, for example, Patent Document 1).

  FIG. 22 is a circuit diagram showing an example of a configuration of a current mirror type level conversion circuit according to a conventional example. As illustrated in FIG. 22, the current mirror type level conversion circuit 100 includes a circuit operation control unit 101, two bias shift units 102 and 103, a level shift unit 104, and an output unit 105.

  The circuit operation control unit 101 includes two Pch MOS transistors (hereinafter abbreviated as “PMOS transistors”) p101 and p102 and an Nch MOS transistor (hereinafter abbreviated as “NMOS transistor”) n101. The PMOS transistor p101 and the NMOS transistor n101 have a power supply line to which a positive power supply potential Vdd is applied (hereinafter referred to as “Vdd line”) and a power supply line to which a negative power supply potential Vss is applied (hereinafter referred to as “Vss line”). Are connected in series, and the gates and drains are connected in common.

  A circuit operation control signal xstb is externally supplied to the gates of the PMOS transistor p101 and the NMOS transistor n101. The circuit operation control signal xstb is always at a low potential when the circuit is in a standby state (when not driven), and is always at a high potential when the circuit is driven. The PMOS transistor p102 has a source connected to the Vdd line and a gate connected to the gates of the PMOS transistor p101 and the NMOS transistor n101.

  The bias shift unit 102 includes two PMOS transistors p103 and p104 and one NMOS transistor n102. The PMOS transistor p103 and the NMOS transistor n102 are connected in series between the Vdd line and the Vss line, the gates are connected in common, and are further connected to the drains of the PMOS transistor p101 and the NMOS transistor n101, and the drains are connected to each other. Commonly connected. The PMOS transistor p104 is connected in parallel to the NMOS transistor n102, and a clock CK is supplied to the gate. In the bias shift unit 102, an operation of shifting the DC bias of the clock CK is performed.

  The bias shift unit 103 includes two PMOS transistors p105 and p106 and one NMOS transistor n103. The PMOS transistor p103 and the NMOS transistor n102 are connected in series between the Vdd line and the Vss line, and the gates and the drains are connected in common. The PMOS transistor p106 is connected in parallel to the NMOS transistor n103, and a clock xCK having a phase opposite to that of the clock CK is applied to the gate. In the bias shift unit 103, an operation of shifting the DC bias of the reverse phase clock xCK is performed.

  The level shift unit 104 includes two PMOS transistors p107 and p108 and two NMOS transistors n104 and n105. The two PMOS transistors p107 and p108 have their sources connected to the Vdd line and their gates connected in common, and the gate and drain of the PMOS transistor p107 are connected to form a current mirror circuit. ing. The drain (gate) of the PMOS transistor p107 is connected to the drain of the PMOS transistor p102.

  The NMOS transistor n104 has a drain connected to the drain (gate) of the PMOS transistor p107, a gate connected to each drain of the PMOS transistor p103 and the NMOS transistor n102, and a negative phase clock xCK applied to the source. The NMOS transistor n105 has a drain connected to the drain of the PMOS transistor p108, a gate connected to the drains of the PMOS transistor p105 and the NMOS transistor n103, and a clock CK applied to the source.

  As is apparent from the above configuration, the level shift unit 104 has a circuit configuration of a source input type current mirror amplifier that uses the negative phase clock xCK and the normal phase clock CK as the source inputs of the NMOS transistors n104 and n105.

  The output unit 105 includes an NMOS transistor n106 having a drain connected to each drain of the PMOS transistor p108 and the NMOS transistor n105, a source connected to the Vss line, and a gate connected to each gate of the PMOS transistor p105 and the NMOS transistor n103. .

JP 2003-347926 A

  In the current mirror type level conversion circuit 100 according to the conventional example having the above configuration, after the DC bias of the clocks CK and xCK is shifted by the bias shift units 102 and 103, the level shift unit 104 finally converts the clocks CK and xCK to Vss. Since it is configured to level shift (level conversion) to a clock having an amplitude of −Vdd, a leak current (through current) always flows in a portion indicated by a dotted arrow in the figure. This is a cause of increasing the power consumption of the level conversion circuit 100.

  In addition, the current mirror type level conversion circuit 100 has a drawback that it is vulnerable to variations in transistor characteristics because the characteristics of the pair of PMOS transistors p107 and p108 constituting the current mirror circuit must be the same.

  Accordingly, an object of the present invention is to provide a level conversion circuit that can reduce power consumption and is resistant to variations in transistor characteristics, and a display device using the level conversion circuit.

  The level conversion circuit according to the present invention includes a first drive transistor connected between a first power supply potential and an output node, and the first drive transistor connected between a second power supply potential and the output node. A second driving transistor having a conductivity type opposite to that of the driving transistor; a first coupling capacitor that applies an input signal to the gate of the first driving transistor; and a signal in phase with the input signal. A second coupling capacitor applied to the gate; a first diode element formed in the vicinity of the first drive transistor; a second diode element formed in the vicinity of the second drive transistor; Prior to the input signal being applied to the gate of the first driving transistor, the gate potential of the first driving transistor is set to the first power supply potential. A first switching circuit that determines a potential on which the threshold value of the Aode element is superimposed; and a gate potential of the second drive transistor before the signal having the same phase is applied to the gate of the second drive transistor, And a second switching circuit that establishes a potential obtained by superimposing a threshold value of the second diode element on the second power supply potential.

  In the level conversion circuit configured as described above, the first and second diode elements are formed in the vicinity of the first and second drive transistors, so that the transistor characteristics are substantially the same as those of the drive transistors. Then, the first switching circuit sets the gate potential of the first driving transistor to the first power supply potential before the input signal is applied to the gate of the first driving transistor, and the threshold value of the first diode element. Is determined as the superimposed potential, and the second switching circuit sets the gate potential of the second drive transistor to the second potential before the signal having the same phase as the input signal is applied to the gate of the second drive transistor. Is determined to be a potential obtained by superimposing the threshold value of the second diode element on the power supply potential. Accordingly, the first and second drive transistors are surely turned off from the relationship of the gate potential at the turn-off timing, so that leakage current (through current) when these drive transistors are turned off can be prevented.

  Another level conversion circuit of the present invention includes a first drive transistor having one end connected to a first power supply potential, and a reverse conductivity type of the first drive transistor having one end connected to a second power supply potential. A second driving transistor; a first coupling capacitor that provides an input signal to the gate of the first driving transistor; and a second cup that provides a signal in phase with the input signal to the gate of the second driving transistor. A ring capacitor is connected between the other end of the first driving transistor and an output node, and is turned off for a certain period before the input signal is supplied to the gate of the first driving transistor. The switching element is connected between the other end of the second drive transistor and the output node, and before the in-phase signal is applied to the gate of the second drive transistor. A second switching element that is turned off during a certain period, and a third switching element that is connected between the gate of the first driving transistor and the second power supply potential and is turned on within the certain period. An element, a fourth switching element connected between the gate of the second drive transistor and the first power supply potential and turned on within the predetermined period; a drain of the first drive transistor; A fifth switching transistor that is connected to a gate and is turned on after the third switching element is turned off within the predetermined period; and between a drain and a gate of the second driving transistor. And a sixth switch that is turned on after the fourth switching element is turned off within the predetermined period. And it has a configuration that includes a ring transistor.

  In another level conversion circuit having the above configuration, the first switching element is turned off in a certain period before the input signal is applied to the gate of the first driving transistor, and the third switching element is turned on in the certain period. After that, the fifth switching transistor is turned on within a certain period, so that the gate potential of the first drive transistor is superimposed on the first power supply potential and the threshold value of the first drive transistor. Become potential. Similarly, the second switching element is turned off in a certain period before the input signal is supplied to the gate of the second driving transistor, the fourth switching element is turned on in the certain period, and thereafter, the certain period. When the sixth switching transistor is turned on, the gate potential of the first drive transistor becomes a potential obtained by superimposing the threshold value of the second drive transistor on the second power supply potential. Accordingly, the first and second drive transistors are surely turned off from the relationship of the gate potential at the turn-off timing, so that leakage current (through current) when these drive transistors are turned off can be prevented.

  According to the present invention, the leakage current (through current) when the driving transistor is turned off can be surely prevented, so that the power consumption can be reduced and the circuit configuration without using the current mirror circuit is adopted. Can provide a level conversion circuit that is resistant to variations.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a level conversion circuit according to the first embodiment of the present invention. In the level conversion circuit 10 according to this embodiment, each switching element is formed on an insulating substrate such as a glass substrate by a thin film transistor (TFT), and operates with the first power supply potential Vss and the second power supply potential Vdd. A first amplitude Vss-Vini that is an input signal to be level-converted, for example, a clock signal ck1 of 0 [V] -3 [V], which is used as a power supply potential, is larger than the first amplitude Vss-Vini. Circuit operation for level conversion (level shift) to a clock signal having an amplitude Vss-Vdd of, for example, 0 [V] -8 [V].

  In FIG. 1, the complementary circuit 11 constituting the drive unit includes first and second drive transistors having opposite conductivity types connected in series between a first power supply potential Vss and a second power supply potential Vdd, That is, it is composed of an Nch MOS transistor n11 and a Pch MOS transistor p11. The drain common connection node of these drive MOS transistors n11 and p11 becomes the output node O and is connected to the output terminal 12.

  A coupling capacitor C11 is connected between the first clock input terminal 13 and the gate (node B) of the driving MOS transistor p11. The first clock signal ck1 input from the first clock input terminal 13 is applied to the gate of the driving MOS transistor p11 by coupling by the coupling capacitor C11.

  A coupling capacitor C12 is connected between the second clock input terminal 14 and the gate (node C) of the driving MOS transistor n11. The second clock signal ck2 input from the second clock input terminal 14 is applied to the gate of the driving MOS transistor n11 by coupling by the coupling capacitor C12. The second clock signal ck2 is a signal in phase with the first clock signal ck1, and the waveform in a certain section is slightly different from that of the clock signal ck1.

  The amount of coupling by the coupling capacitors C11 and C12 is determined by the size ratio between the parasitic capacitances of the nodes B and C and the coupling capacitors C11 and C12. Therefore, the clocks ck1 and ck2 having the amplitude Vss-Vini are not transmitted to the nodes B and C as they are (100%) as they are. That is, gain loss occurs due to the presence of parasitic capacitances at nodes B and C.

  In order to minimize the gain loss, it is preferable to set the capacitance values of the coupling capacitors C11 and C12 to a sufficiently large value with respect to the parasitic capacitances of the nodes B and C. In other words, by setting the capacitance values of the coupling capacitors C11 and C12 to a sufficiently large value with respect to the parasitic capacitances of the nodes B and C, the gain can be made close to 100%, that is, the gain loss is reduced. Since it can be minimized, driving reliability can be improved.

  PchMOS transistors p12, p13, and p14 are connected in series between the node B (the gate of the driving MOS transistor p11) and the second power supply potential Vdd. Further, Nch MOS transistors n12, n13, n14 are connected in series between the node C (gate of the driving MOS transistor n11) and the first power supply potential Vss.

  The MOS transistor n12 is a first switching transistor, and performs a switching operation (on / off operation) in accordance with the first control pulse sw1 applied to the gate. The switching MOS transistor p12 is a fourth switching transistor and performs a switching operation according to an inversion control pulse xsw1 having a phase opposite to that of the control pulse SW1 applied to the gate.

  Both the MOS transistors n13 and p13 have a diode connection configuration in which the gate and the drain are commonly connected, that is, a diode element. These diode-connected MOS transistors n13 and p13 serve to cancel the threshold values of the driving MOS transistors n11 and p11 of the complementary circuit 11 with the threshold values. Although TFT characteristics (threshold and mobility) vary in process, adjacently laid out transistors have almost the same characteristics.

  Accordingly, the MOS transistor n13 and the MOS transistor p13 are formed adjacent to the drive MOS transistor n11, and the direction of the transistors on the layout is aligned, and the layer structure of the transistors is aligned, thereby forming the diode. The threshold values of the driving MOS transistors n11 and p11 can be canceled by the threshold values of the connected MOS transistors n13 and p13. Further, since the threshold value decreases as the W / L ratio of the transistor increases, it is possible to set a threshold cancellation value based on this.

  The MOS transistor n14 is a third switching transistor, and performs a switching operation according to the second control pulse sw2 applied to the gate. The MOS transistor p14 is a sixth switching transistor, and performs a switching operation according to an inversion control pulse xsw2 having a phase opposite to that of the second control pulse sw2 applied to the gate.

  A hold capacitor C13 is connected between the node A which is a common connection node of the MOS transistors p12 and p13 and the ground (Vss). A hold capacitor C14 is connected between the node D, which is a common connection node of the MOS transistors n12 and n13, and the ground. These hold capacitors C13 and C14 hold the voltage after threshold cancellation by the MOS transistors p13 and n13.

  The hold capacitors C13 and C14 are not necessarily essential. However, it is possible to increase driving reliability by arranging the hold capacitors C13 and C14 and holding the voltage after the threshold cancellation.

  An NchMOS transistor n15 is connected between the node A and the first power supply potential Vss. The MOS transistor n15 is a second switching transistor and performs a switching operation according to the second inversion control pulse xsw2. A PchMOS transistor p15 is connected between the node D and the second power supply potential Vdd. The MOS transistor p15 is a fifth switching transistor, and performs a switching operation according to the second control pulse sw2.

  For example, an Nch MOS transistor n16 is connected between the output node O and the first power supply potential Vss. The NchMOS transistor n16 is a switching transistor, and performs a switching operation according to the third control pulse sw3 applied to the gate.

(Circuit operation)
Next, the circuit operation of the level conversion circuit 10 according to the first embodiment will be described with reference to the timing chart of FIG. In the following description, the first power supply potential Vss is referred to as a low potential, and the second power supply potential Vdd is referred to as a high potential.

  The timing chart of FIG. 2 shows the first control pulse sw1, the second control pulse sw2, the third control pulse sw3, the clock signals ck1, ck2, the potentials of the nodes A, B, C, D and the output signal out. Each waveform and timing relationship are shown.

  As is apparent from FIG. 2, the first control pulse sw1 is active (High potential) during the period from time t14 to t15, and the second control pulse sw2 is inactive (Low potential) during the period from time t11 to t12. The third control pulse sw3 becomes active (High potential) during the period from time t13 to time t17. As a matter of course, the low potential is active and the high potential is inactive in the first, second, and third inversion control pulses xsw1, xsw2, and xsw3.

  The clock signals ck1 and ck2 are in-phase clock signals. However, the clock signal ck1 becomes a high potential during a period from time t12 to t18, the clock signal ck2 becomes a low potential during a period from time t13 to t16, and becomes a high potential during a period from time t16 to t18.

  First, when the control pulse sw2 (xsw2) becomes inactive at time t11, the switching MOS transistors p14 and n14 are turned off and the switching MOS transistors n15 and p15 are turned on. Thereby, the node A is charged to the power supply potential Vss via the switching MOS transistor n15 and the hold capacitor C13 is reset. Similarly, the node D is charged to the power supply potential Vdd via the switching MOS transistor p15, and The hold capacitor C14 is reset. At this time, the switching MOS transistors p12, n12, and n16 are in an off state.

  Next, when the control pulse sw2 (xsw2) becomes active at time t12, the switching MOS transistors p14 and n14 are turned on, and the switching MOS transistors n15 and p15 are turned off. When the switching MOS transistor p14 is turned on, the node A is connected to the power supply potential Vdd via the MOS transistors p14 and p13, so that the potential of the node A rises from the power supply potential Vss toward the power supply potential Vdd. At this time, if the threshold value of the MOS transistor p13 is Vthp13, the potential of the node A finally converges to the potential of Vdd− | Vthp13 |.

  Further, since the switching MOS transistor n14 is turned on, the node D is connected to the power supply potential Vss via the MOS transistors n14 and n13, so that the potential of the node D drops from the power supply potential Vdd toward the power supply potential Vss. . At this time, if the threshold value of the MOS transistor n13 is Vthn13, the potential of the node D finally converges to the potential of Vss + | Vthn13 |.

  Next, when the control pulse sw3 becomes active at time t13, the switching MOS transistor n16 is turned on, so that the potential of the output node O, that is, the potential of the output signal out becomes the Low potential. In the active state of the control pulse sw3, when the control pulse sw1 (xsw1) becomes active at time t14, the switching MOS transistors p12 and n12 are turned on.

  When the switching MOS transistor p12 is turned on, the potential of the node B is determined to be the potential of the node A, that is, the potential of Vdd− | Vthp13 |. Further, when the switching MOS transistor n12 is turned on, the potential of the node C is determined to be the potential of the node D, that is, the potential of Vss + | Vthn13 |. Thereafter, at time t15, the control pulse sw1 (xsw1) becomes inactive, and the switching MOS transistors p12 and n12 are turned off.

  Since the switching MOS transistors p12 and n12 are turned off, after time t15, the potential of the node B is (Vss− | Vthp13 | −Vini) in synchronization with the clock signal ck1 due to coupling by the coupling capacitor C11. − (Vdd− | Vthp13 |) and the potential of the node C is (Vss + | Vthn13 |) − (Vdd + | Vthn13 | + Vini) in synchronization with the clock signal ck2 due to coupling by the coupling capacitor C12. ).

  At this time, since the switching MOS transistor n16 is in the on state, the potential of the output node O, that is, the output signal out is fixed to the low potential. At time t17, the control pulse sw3 becomes inactive and the switching MOS transistor n16 is turned off, so that the driving MOS transistor p11 / n11 repeats the on / off operation according to the potentials of the nodes B and C. The output signal out is converted in synchronism with the clock signals ck1 and ck2 with the amplitude of Vss−Vdd.

  Through the above series of operations, the clock signals ck1 and ck2 having the first amplitude Vss-Vini, for example, 0 [V] -3 [V], are converted into the second amplitude Vss-Vdd, for example, 0 [V] -8 [V ] Has been level-converted (level-shifted) into the clock signal out.

  At this time, as apparent from FIG. 2, the threshold values Vthp13 and Vthn13 of the MOS transistors p13 and n13 are superimposed on the potentials of the nodes B and C, but the thresholds Vthp13 and Vthn13 are also included in the output signal out. Also, the thresholds Vthp11 and Vthn11 of the driving MOS transistors p11 and n11 are not included.

  That is, each of the MOS transistors p13 and n13 is laid out adjacent to each of the drive MOS transistors p11 and n11, and the direction and layer configuration of the transistors on the layout are aligned, so that these drive MOS transistors p11 and n11 are arranged. The transistor characteristics (threshold and mobility) are substantially the same. Therefore, in the complementary circuit 11, the threshold values Vthp13 and Vthn13 of the MOS transistors p13 and n13 and the threshold values Vthp11 and Vthn11 of the driving MOS transistors p11 and n11 are canceled (cancelled).

  As is apparent from the above description of the operation, the switching MOS transistors n12, n14, and p15 have the first drive transistor before the clock signal ck2 as the input signal is applied to the gate of the first drive transistor n11. The first switching circuit is configured to determine the gate potential of n11 at a potential (Vss + | Vthn13 |) in which the threshold value Vthn13 of the diode-connected MOS transistor n13 is superimposed on the first power supply potential Vss.

  Further, the switching MOS transistors p12, p14, and n15 change the gate potential of the second driving transistor p11 before the clock signal ck1 having the same phase as the clock signal ck2 is applied to the gate of the second driving transistor p11. The second switching circuit is configured to determine the potential (Vdd− | Vthp13 |) in which the threshold value of the diode-connected MOS transistor p13 is superimposed on the power supply potential Vdd of 2.

  As described above, in the level conversion circuit 10 according to the present embodiment, the drive MOS transistors p11 are canceled by canceling the threshold values Vthp11 and Vthn11 of the drive MOS transistors p11 and n11 by the action of the diode-connected MOS transistors p13 and n13. , N11 can be set so that no current flows through the driving MOS transistors p11, n11. As a result, since the driving MOS transistors p11 and n11 are surely turned off at the timing when they should be turned off, no leakage current (through current) flows through the complementary circuit 11.

  As described above, the leakage current does not flow in the complementary circuit 11, so that the power consumption of the level conversion circuit 10 can be reduced. Further, since the complementary circuit 11 composed of the reverse conductivity type driving MOS transistors p11 and n11 is used as a basic circuit, transistor characteristics (threshold value Vth) can be obtained as compared with the conventional level conversion circuit using a current mirror circuit as a basic circuit. And a level conversion circuit resistant to variations in drain-source current Ids).

  In addition, when the complementary circuit 11 composed of the reverse conductivity type driving MOS transistors p11 and n11 is used as a basic circuit, the operation speed becomes slow due to variations in transistor characteristics of the driving MOS transistors p11 and n11, particularly the threshold value Vth. There is a concern that the thresholds Vthp11 and Vthn11 of the drive MOS transistors p11 and n11 can be canceled by the thresholds Vthp13 and Vthn13 of the diode-connected MOS transistors p13 and n13, so that the influence of the variation of the thresholds Vthp11 and Vthn11 on the operation speed is affected. Therefore, high-speed operation can be realized.

  Incidentally, if the configuration for canceling the threshold values Vthp11 and Vthn11 of the driving MOS transistors p11 and n11 is not adopted, it is necessary to set the W / L ratio of the driving MOS transistors p11 and n11 to be large in order to improve the operation speed. This is a factor causing an increase in circuit scale. On the other hand, the level conversion circuit 10 according to the present embodiment employs a configuration in which the threshold values Vthp11 and Vthn11 of the drive MOS transistors p11 and n11 are canceled, so that operation reliability can be achieved even with a relatively small transistor size. High and fast operation can be realized.

(First modification)
FIG. 3 is a circuit diagram showing a configuration of a level conversion circuit according to a first modification of the first embodiment. In FIG. 3, the same parts as those in FIG.

  In the level conversion circuit 10 according to the first embodiment, the switching MOS transistors p14 and n14 are connected between the power supply potentials Vdd and Vss and the sources of the MOS transistors p13 and n13. On the other hand, in the level conversion circuit 10A according to this example, the switching MOS transistors p14 and n14 are connected between the sources of the switching MOS transistors p12 and n12 and the drains of the switching MOS transistors n15 and p15. ing.

  Thus, even when the switching MOS transistors p14 and n14 are connected between the sources of the switching MOS transistors p12 and n12 and the drains of the switching MOS transistors n15 and p15, the level conversion according to the first embodiment is performed. The same effects as those of the circuit 10 can be obtained.

(Second modification)
FIG. 4 is a circuit diagram showing a configuration of a level conversion circuit according to a second modification of the first embodiment. In FIG. 4, the same parts as those in FIG.

  In addition to the configuration of FIG. 1, the level conversion circuit 10B according to the present modification includes an NchMOS transistor n17 connected between the input terminals of the coupling capacitors C11 and C12, and an input terminal (node E) of the coupling capacitor C12. And an NchMOS transistor n18 connected between the power supply potential Vss. A fourth control pulse sw4 is applied to the gate of the MOS transistor n17, and a control pulse xsw4 having a phase opposite to that of the control pulse sw4 is applied to the gate of the MOS transistor n18.

  FIG. 5 shows the first to fourth control pulses sw1 to sw4, the single clock signal ck, the potentials of the nodes A, B, C, D and E, and the output signal out in the level conversion circuit 10B according to this modification. Each waveform and timing relationship are shown.

  As apparent from the timing chart of FIG. 5, a MOS transistor n17 is connected between the input terminals of the coupling capacitors C11 and C12, and a MOS transistor n18 is connected between the input terminal of the coupling capacitor C12 and the power supply potential Vss. By connecting and controlling these MOS transistors n17 and n18 with the control pulse sw4 and its inverted signal xsw4, it is possible to give a clock signal substantially the same as the second clock signal ck2 to the coupling capacitor C12. .

  As is clear from this, in order to obtain the level-converted output signal out, the level conversion circuit 10 according to the first embodiment requires two clock signals ck1 and ck2, whereas this modification example In the level conversion circuit 10B according to the above, a single clock signal ck is sufficient.

(Other variations)
Furthermore, it is possible to adopt a configuration according to the following modification. First, in the configuration shown in FIG. 1, a PchMOS transistor is connected between the output node O and the power supply potential Vdd instead of the NchMOS transistor n16 connected between the output node O and the power supply potential Vss. In the configuration shown in FIG. 6, a configuration in which a PchMOS transistor is connected between the output node O and the power supply potential Vdd can be employed instead of the NchMOS transistor n16 connected between the output node O and the power supply potential Vss. .

  In the configuration shown in FIG. 4, the MOS transistors p14 and n14 are connected between the sources of the MOS transistors p12 and n12 and the drains of the MOS transistors n15 and p15, and the MOS transistor n17 is coupled to the coupling capacitors C11 and C12. The MOS transistor n18 is connected between the input terminal of the coupling capacitor C11 and the power supply potential Vini, or the MOS transistors p14 and n14 are connected to the sources of the MOS transistors p12 and n12 and the MOS transistor, respectively. n15 and p15 are connected between the drains, the MOS transistor n17 is connected between the input terminals of the coupling capacitors C11 and C12, and the MOS transistor n18 is connected between the input terminal of the coupling capacitor C11 and the power supply potential Vini. Respectively It is possible to adopt a configuration or to continue.

  Even when any of the configurations of these modifications is employed, the same operational effects as those of the level conversion circuit 10 according to the first embodiment can be obtained.

[Second Embodiment]
FIG. 6 is a circuit diagram showing a configuration of a level conversion circuit according to the second embodiment of the present invention. In the level conversion circuit 20 according to the present embodiment, as in the level conversion circuit 10 according to the first embodiment, each switching element is formed on an insulating substrate such as a glass substrate by a TFT, and the first power supply potential Vss and the first The power supply potential Vdd of 2 is used as the operation power supply potential, and the first amplitude Vss-Vini, which is the input signal to be level-converted, for example, the clock signal ck of 0 [V] -3 [V] is used as the first amplitude Vss. A circuit operation is performed for level conversion to a clock signal having a second amplitude Vss−Vdd larger than −Vini, for example, 0 [V] −8 [V].

  In FIG. 6, the complementary circuit 21 constituting the drive unit includes first and second drive transistors of opposite conductivity type connected in series between a first power supply potential Vss and a second power supply potential Vdd, That is, it is composed of an Nch MOS transistor n21 and a Pch MOS transistor p21.

  However, in the complementary circuit 21, an Nch MOS transistor n22 and a Pch MOS transistor p22 are connected in series between the drive MOS transistor n21 and the drive MOS transistor p21. The drain common connection node of the MOS transistors n22 and p22 becomes the output node O and is connected to the output terminal 22. A first control pulse sw1 is applied to the gate of the MOS transistor n22, and a control pulse xsw1 having a phase opposite to that of the first control pulse sw1 is applied to the gate of the MOS transistor p22.

  An Nch MOS transistor n23 is connected between the gate and drain of the driving MOS transistor n21. The MOS transistor n23 is a switching transistor, and performs a switching operation according to the second control pulse sw2 applied to the gate. A Pch MOS transistor p23 is connected between the gate and drain of the drive MOS transistor p21. The MOS transistor p23 is a switching transistor and performs a switching operation according to a control pulse xsw2 having a phase opposite to that of the second control pulse sw2 applied to the gate.

  A Pch MOS transistor p24 is connected between the gate (node B) of the driving MOS transistor n21 and the power supply potential Vdd. The MOS transistor p24 is a switching transistor, and performs a switching operation according to the third control pulse sw3 applied to the gate. An Nch MOS transistor n24 is connected between the gate (node A) of the driving MOS transistor p21 and the power supply potential Vss. The MOS transistor n24 is a switching transistor, and performs a switching operation according to a control pulse xsw3 having a phase opposite to that of the third control pulse sw3 applied to the gate.

  Each end of the coupling capacitors C21 and C22 is connected to the nodes A and B. The other end of the coupling capacitor C21 is connected to the clock input terminal 24 via the level shift circuit 23. The other end of the coupling capacitor C22 is directly connected to the clock input terminal 24.

  The level shift circuit 23 includes NchMOS transistors n25 and n26 connected in series between the third power supply potential Vini, which is the high potential (3 [V] in this example) of the clock signal ck, and the clock input terminal 24. It is configured. The other end of the coupling capacitor C21 is connected to a node C that is a common connection node of the MOS transistors n25 and n26. Fourth and fifth control pulses sw4 and sw5 are applied to the gates of the MOS transistors n25 and n26, respectively. A PchMOS transistor p27 is connected between the output node O and the power supply potential Vdd. The MOS transistor p27 is a switching transistor and performs a switching operation according to a control pulse sw1 applied to the gate.

  The first to fifth control pulses sw1 to sw5 are formed on the same insulating substrate as the level conversion circuit 20, and are generated by the control pulse generation circuit 30 configured using a TFT circuit. A specific circuit configuration of the control pulse generation circuit 30 will be described later. The first to third inversion control pulses xsw1 to xsw3 are generated, for example, by inverting the first to third control pulses sw1 to sw3 by the inverters 26 to 28.

(Circuit operation)
Next, the circuit operation of the level conversion circuit 20 according to the second embodiment having the above configuration will be described with reference to the timing chart of FIG. In the following description, the first power supply potential Vss is referred to as a low potential, and the second power supply potential Vdd is referred to as a high potential.

  The timing chart of FIG. 7 shows the first control pulse sw1, the second control pulse sw2, the third control pulse sw3, the fourth control pulse sw4, the fifth control pulse sw5, the clock signal ck, and the nodes A and B. , C and the waveforms and timing relationships of the output signal out.

  As is apparent from FIG. 7, the first control pulse sw1 is inactive (Low potential) during the period from time t21 to t29, and the second control pulse sw2 is active (High potential) during the period from time t25 to t26. The third control pulse sw3 is active (Low potential) during the period of time t23 to t24, the fourth control pulse sw4 is active (High potential) during the period of time t22 to t27, and the fifth control pulse sw5 is It becomes active (High potential) before time t21 and after time t28.

  As a matter of course, the control pulses xsw1 and xsw2 have the low potential active and the high potential inactive, and the control pulse xsw3 has the high potential active and the low potential inactive. The clock signal ck is not input to the clock input terminal 24 until time t30. Therefore, the potential of the clock input terminal 24 is at the low potential until time t30.

  First, when the control pulse sw1 (xsw1) becomes inactive at time t21, both the switching MOS transistors n21 and p21 are turned off. As a result, the drive MOS transistors p21, n21 and the output node O are blocked by the switching MOS transistors n21, p21. At this time, since the switching MOS transistor p27 is turned on, the potential of the output node O, that is, the output signal out, is fixed to the power supply potential Vdd.

  In this state, when the control pulse sw4 becomes active at time t22, the control pulse sw5 also becomes inactive at this time, so that the state between the clock input terminal 24 and the node C is also cut off. The transistor n24 is turned on. As a result, the potential of the node C becomes the power supply potential Vini.

  Next, when the control pulse sw3 (xsw3) becomes active at time t23, both the switching MOS transistors p24 and n24 are turned on. As a result, power supply potential Vdd is applied as an initial value to node B via switching MOS transistor p24, and power supply potential Vss is applied as an initial value to node A via switching MOS transistor n24. That is, the switching MOS transistors n24 and p24 function to determine the initial values of the nodes A and B.

  When the power supply potentials Vss and Vdd are applied to the nodes A and B as initial values, the drive MOS transistors p21 and n21 are both turned on. At this time, since the switching MOS transistors p22 and n22 are in the OFF state, a current flows from the power supply potential Vdd to the output node O via the drive MOS transistor p21, or a power supply from the output node O via the drive MOS transistor n22. Current does not flow into the potential Vss.

  Thereafter, when the control pulse sw2 (xsw2) becomes active at time t25, both the switching MOS transistors n23 and p23 are turned on. When the switching MOS transistor p23 is turned on, a charging path is formed from the power supply potential Vdd to the node A via the MOS transistors p21 and p23, and charging is performed until the potential of the node A rises to a potential at which the driving MOS transistor p21 is turned off. Done. As a result, when the threshold value of the driving MOS transistor p21 is Vthp21, the potential of the node A becomes Vdd− | Vthp21 |.

  When switching MOS transistor n23 is turned on, a discharge path is formed from node B to power supply potential Vss via MOS transistors n21 and n23 until the potential at node B drops to a potential at which drive MOS transistor n21 is turned off. Discharge occurs. As a result, when the threshold value of the driving MOS transistor n21 is Vthn21, the potential of the node B becomes Vss + | Vthn21 |.

  The operation from time t25 to time t26 when the control pulse sw2 (xsw2) becomes active, that is, the gate potential of the driving MOS transistor p21 (the potential of the node A) is lower than the power supply potential Vdd by the threshold Vthp21 of the MOS transistor p21. The operation of setting the gate potential (potential of the node B) of the driving MOS transistor n21 to a potential higher than the power supply potential Vss by the threshold Vthn21 of the MOS transistor n21 as well as the potential of the driving MOS transistors p21 and n21. , Vthn21 is a threshold value canceling operation for canceling the influence on the circuit operation. That is, the period from time t25 to time t26 is a threshold cancel operation period.

  After the threshold cancel operation period ends, the control pulse sw4 is deactivated at time t27 to turn off the switching MOS transistor n25, and then the control pulse sw5 is activated at time t28 to switch the switching MOS transistor n26. Turns on. At this time, the potential of the clock input terminal 24 is at a low potential (power supply potential Vss). As a result, the potential of the node C is level-shifted from the power supply potential Vini to the power supply potential Vss, and in conjunction with this, the potential of the node A is also level-shifted from Vdd− | Vthp21 | to Vdd− | Vthp21 | −Vini.

  When the control pulse sw1 (xsw1) becomes active at the time t29 after the end of the level shift operation period, both the switching MOS transistors n22 and p22 are turned on, so that the driving MOS transistors p21 and n21 and the output node O Are connected. When the clock signal ck having the amplitude Vss−Vini is input at time t30, the clock signal ck is coupled to the nodes A and B by the coupling capacitors C21 and C22, and inverted by the driving MOS transistors p21 and n21. The level is converted into a clock signal having an amplitude Vss-Vdd, and output as an output signal out from the output terminal 22 through the switching MOS transistors p22 and n22 and the output node O.

  As described above, in the level conversion circuit 20 according to the present embodiment, the drive MOS transistors p21 and n21 are canceled by canceling the threshold values Vthp21 and Vthn21 of the drive MOS transistors p21 and n21 by the action of the switching MOS transistors p23 and n23. Can be set at a place where no current flows through the driving MOS transistors p21 and n21. As a result, since the driving MOS transistors p21 and n21 are surely turned off at the timing when they should be turned off, no leak current (through current) flows through the complementary circuit 21.

  As described above, the leakage current does not flow in the complementary circuit 21, so that the power consumption of the level conversion circuit 20 can be reduced. Further, by using the complementary circuit 21 including the reverse conductivity type driving MOS transistors p21 and n21 as a basic circuit, transistor characteristics (threshold value Vth) can be obtained as compared with the conventional level conversion circuit having a current mirror circuit as a basic circuit. And a level conversion circuit resistant to variations in drain-source current Ids).

  Further, as in the case of the level conversion circuit 10 according to the first embodiment, the threshold values Vthp21 and Vthn21 of the drive MOS transistors p21 and n21 can be canceled, so that the influence of the variation of the threshold values Vthp21 and Vthn21 on the operation speed is eliminated. Therefore, high-speed operation can be realized, and it is not necessary to set a large W / L ratio of the drive MOS transistors p21 and n21. Therefore, operation reliability can be improved even with a relatively small transistor size.

(Modification)
FIG. 8 is a circuit diagram showing a configuration of a level conversion circuit according to a modification of the second embodiment. In FIG. 8, the same parts as those in FIG. 6 are denoted by the same reference numerals.

  In the level conversion circuit 20 according to the second embodiment, the level shift circuit 23 including the Nch MOS transistors n26 and n27 is connected between the clock input terminal 24 and the power supply potential Vini, and the potential of the output node O is fixed. A PchMOS transistor p27 is used as a switching transistor, and the MOS transistor p27 is connected between the power supply potential Vdd and the output node O, and the output node O is fixed to the high potential when the threshold value is canceled.

  On the other hand, in the level conversion circuit 20A according to the present modification, the level shift circuit 23 composed of NchMOS transistors n26 and n27 is connected between the clock input terminal 24 and the power supply potential Vss, and the potential of the output node O is changed. The NchMOS transistor n27 is used as a switching transistor for fixing, and the MOS transistor n27 is connected between the power supply potential Vss and the output node O, and the output node O is fixed to the low potential when the threshold is canceled. .

  FIG. 9 shows the waveforms of the first to fifth control pulses sw1 to sw5, the single clock signal ck, the potentials of the nodes A, B, and C, and the output signal out in the level conversion circuit 20A according to this modification. The timing relationship is shown.

  Even in the level conversion circuit 20A according to this modification, although there is a difference in that the output node O is fixed to the low potential at the time of threshold cancellation, the basic circuit operation is the second as is apparent from the timing chart of FIG. This is the same as the level conversion circuit 20 according to the embodiment. Therefore, the obtained effect is the same as that of the level conversion circuit 20 according to the second embodiment.

  Here, the first to fifth control pulses sw1 to sw5 will be described using the timing chart of FIG. 9 corresponding to the level conversion circuit 20A of FIG. 8 as an example. However, the same applies to the timing chart of FIG. 8 corresponding to the level conversion circuit 20 of FIG.

  First, since the five control pulses sw1 to sw5 are signals for controlling the level conversion circuits 20 and 20A, the amplitude thereof needs to be Vss−Vdd. Therefore, the level conversion from the pulse of Vss-Vini amplitude to the pulse of Vss-Vdd amplitude is performed for these control pulses sw1 to sw5 as well as the case of the clock signal ck.

  However, if level conversion is performed on each of the five control pulses sw1 to sw5, the power consumption in the level conversion unit of the control pulse also becomes a problem. If the number of control pulses for level conversion can be reduced, the power consumption in the level conversion unit of the control pulses can be reduced by the reduced amount.

  Specifically, as shown in the timing chart of FIG. 10, the transition timings of the control pulse sw1, the control pulse sw4, and the control pulse sw5 (the transition timing from the High potential to the Low potential or vice versa) are the same timing. By setting, these control pulses sw1, sw4 and sw5 can be made common. The control pulse sw4 is out of phase with the control pulses sw1 and sw5, but can be easily out of phase by using an inverter.

  Even if the transition timings of the control pulses sw1, sw4, and sw5 are set to the same timing, the threshold cancellation operation and the level shift operation described above can be performed reliably, as is apparent from the timing chart of FIG. In this way, by sharing the control pulses sw1, sw4, and sw5, two control pulses can be reduced, and the five control pulses sw1 to sw5 can be reduced to three control pulses sw1 to sw3. it can.

(Control pulse generation circuit)
Furthermore, by using the control pulse generation circuit 30 described below, as shown in the timing chart of FIG. 11, the transition timing from the low potential to the high potential of the control pulses sw2 and sw3 is set to the same timing, thereby allowing the input. The number of control pulses can be reduced to two types. Also in this case, the above-described threshold cancellation operation and level shift operation can be performed.

  A specific circuit example of the control pulse generation circuit 30 will be described below. The control pulse generation circuit 30 is formed on the same insulating substrate as the level conversion circuit 20 and is configured using a TFT circuit.

(First circuit example)
FIG. 12 is a circuit diagram showing a configuration of a control pulse generation circuit 30A according to the first circuit example. As shown in FIG. 12, the control pulse generation circuit 30A according to this circuit example includes an input circuit 31, a latch circuit 32, and a two-input AND circuit 33. The control pulse sw1 is based on two types of control pulses cntrl1 and cntrl2. To sw5, specifically, the control pulses xsw1, sw2, sw3, sw4, and xsw5 are generated.

  The input circuit 31 includes a Pch MOS transistor p31 and an Nch MOS transistor n31 connected in series between the power supply potential Vdd and the power supply potential Vss. Two types of control pulses cntrl1 and cntrl2 are input to the gates of the MOS transistors p31 and n31, respectively. One control pulse cntrl1 is supplied as it is to the level conversion circuits 20 and 20A as the third control pulse sw3.

  The latch circuit 32 includes inverters 321 and 322 having input / output terminals connected in opposite directions, and a node P that is the input / output terminal is connected to a drain common connection node of the MOS transistors p31 and n31. The latch signal P of the latch circuit 32 is supplied to the level conversion circuits 20 and 20A as the fourth control pulse sw4. The fourth control pulse sw4 is also the first and fifth inversion control pulses xsw1 and xsw5.

  The AND circuit 33 takes the control pulse cntrl1 as one input and the latch signal P of the latch circuit 32 as the other input, and takes the logical product thereof. The output signal of the AND circuit 33 is supplied to the level conversion circuits 20 and 20A as the second control pulse sw2.

  Next, the circuit operation of the control pulse generation circuit 30A according to the first circuit example having the above configuration will be described with reference to the timing chart of FIG.

  As shown in the timing chart of FIG. 13, the control pulse cntrl1 is a pulse signal that becomes active (low potential) for a certain period, specifically, from time t31 to t32. The control pulse cntrl1 is active when the control pulse cntrl1 is active. This is a pulse signal that becomes active (High potential) after a predetermined period, specifically, a period from t32 to t33 has elapsed.

  First, when the control pulse cntrl1 becomes active at time t31, the MOS transistor p31 is turned on in response thereto. At this time, the MOS transistor n31 is in an off state. When the MOS transistor p31 is turned on, the power supply potential Vdd is supplied to the latch circuit 32 through the MOS transistor p31 being turned on, so that the latch circuit 32 latches the power supply potential Vdd.

  Next, when the control pulse cntrl1 becomes inactive at time t32, the MOS transistor p31 is turned off in response thereto. At this time, the AND circuit 33 takes a logical product of the high potential control pulse cntr1 and the high potential latch signal of the latch circuit 32. When the control pulse cntrl2 becomes active at time t33, the MOS transistor n31 is turned on in response to this, and the power supply potential Vss is applied to the latch circuit 32 via the MOS transistor n31.

  Here, the control pulse cntrl1 is directly used as the third control pulse sw3, and the latch signal P of the latch circuit 32 is output as the fourth control pulse sw4 and the first and fifth inversion control pulses xsw1 and xsw5. The signal is supplied to the level conversion circuits 20 and 20A as the second control pulse sw2, respectively.

  As apparent from the circuit operation described above, according to the control pulse generation circuit 30A according to the first circuit example, the first inversion control pulse xsw1 and the second control pulse are based on the two types of control pulses cntrl1 and cntrl2. sw2, the third control pulse sw3, the fourth control pulse sw4, and the fifth inversion control pulse xsw5 can be generated.

(Second circuit example)
FIG. 14 is a circuit diagram showing a configuration of the control pulse generation circuit 30B according to the second circuit example. In FIG. 14, the same parts as those in FIG. 12 are denoted by the same reference numerals. As shown in FIG. 14, the control pulse generation circuit 30B according to this circuit example has a configuration including a two-input OR circuit 34 in addition to the components of the control pulse generation circuit 30A according to the first circuit example.

  The OR circuit 34 takes the control pulse cntrl2 as one input and the latch signal P of the latch circuit 32 as the other input, and takes the logical sum thereof. The output signal of the OR circuit 34 is supplied to the level conversion circuits 20 and 20A as the fourth control pulse sw4 and the first and fifth inversion control pulses xsw1 and xsw5.

  Next, the circuit operation of the control pulse generation circuit 30B according to the second circuit example having the above configuration will be described with reference to the timing chart of FIG.

  As shown in the timing chart of FIG. 15, the control pulse cntrl1 is a pulse signal that becomes active (low potential) during a certain period, specifically, from time t41 to t42, and the control pulse cntrl1 is active when the control pulse cntrl1 is active. This is a pulse signal that becomes active (High potential) in a certain period of time t43 to t44 after a predetermined period of time elapses, specifically, a period of t42 to t43.

  First, when the control pulse cntrl1 becomes active at time t41, the MOS transistor p31 is turned on in response thereto. At this time, the MOS transistor n31 is in an off state. When the MOS transistor p31 is turned on, the power supply potential Vdd is supplied as one input of the latch circuit 32 and the OR circuit 34 through the MOS transistor p31 being turned on, so that the latch circuit 32 latches the power supply potential Vdd, The OR circuit 34 outputs a high potential (power supply potential Vdd).

  Next, when the control pulse cntrl1 becomes inactive at time t42, the MOS transistor p31 is turned off in response thereto. At this time, the AND circuit 33 takes a logical product of the high potential control pulse cntr1 and the high potential latch signal of the latch circuit 32. Next, when the control pulse cntrl2 becomes active at time t43, the MOS transistor n31 is turned on in response to this, and the power supply potential Vss is input to one of the latch circuit 32 and the OR circuit 34 via the MOS transistor n31. As given to.

  Even if the power supply potential Vss is applied as one input to the OR circuit 34, the output signal of the OR circuit 34 maintains the High potential because the control pulse cntr2 of the High potential is applied as the other input. . Then, at time t44 when the control pulse cntr2 becomes inactive, the output signal of the OR circuit 34 changes from the High potential to the Low potential.

  Here, the control pulse cntrl1 is used as it is as the third control pulse sw3, the output signal of the AND circuit 33 is used as the second control pulse sw2, and the output signal of the OR circuit 34 is used as the fourth control pulse sw4 and the first and fifth control pulses sw4. Inversion control pulses xsw1 and xsw5 are supplied to the level conversion circuits 20 and 20A, respectively.

  In the control pulse generation circuit 30A according to the first circuit example, the transition timing from the High potential to the Low potential of the control pulse sw2 and the control pulses sw4, xsw1, and xsw5 is the same timing, whereas the second circuit example The control pulse generation circuit 30B according to FIG. 4 is characterized in that the control pulses sw4, xsw1, and xsw5 are changed from the high potential to the low potential after a predetermined time delay from the transition timing of the control pulse sw2 from the high potential to the low potential. Yes.

  By the way, on the actual TFT circuit, the TFT characteristics have some variation, and there are wiring resistance and parasitic capacitance of the wiring. And it is necessary to consider the case where the control pulses overlap due to the delay caused.

  Here, considering the timing chart of FIG. 11, when the second control pulse sw2 (xsw2) is in the active state, the first control pulse sw1 (xsw1) is in the active state, and the period of both active states When the switching MOS transistor n23 (p23) is in the ON state in FIG. 8, the switching MOS transistor n22 (p22) is turned on. This adversely affects the gate potential.

  On the other hand, according to the control pulse generation circuit 30B according to the second circuit example, the timing t43 when the second control pulse sw2 (xsw2) enters the inactive state and the first period after the lapse of a certain period t43 to t44. Since the control pulse sw1 (xsw1) is in the active state, even if the control pulse is delayed due to variations in TFT characteristics or the presence of wiring resistance or wiring parasitic capacitance, the switching MOS transistor n23 (p23) The threshold cancel operation can be performed reliably.

(Example of third circuit)
FIG. 16 is a circuit diagram showing a configuration of a control pulse generation circuit 30C according to the third circuit example. In FIG. 16, parts equivalent to those in FIG. As shown in FIG. 16, a control pulse generation circuit 30C according to this circuit example uses a three-input OR circuit 35 instead of the two-input OR circuit 34 in the control pulse generation circuit 30B according to the second circuit example, The delay circuit 36 having a delay time of

  The OR circuit 35 uses the latch signal P of the latch circuit 32 as a first input, the latch signal P ′ delayed by the delay circuit 36 as a second input, and the control pulse cntrl2 as a third input. Take the sum. The delay circuit 36 is configured by inverters 361 and 362 connected in two stages, for example. The output signal of the OR circuit 35 is supplied to the level conversion circuits 20 and 20A as the fourth control pulse sw4 and the first and fifth inversion control pulses xsw1 and xsw5.

  The circuit operation of the control pulse generation circuit 30C according to the third circuit example having the above configuration is basically the same as the circuit operation of the control pulse generation circuit 30B according to the second circuit example. FIG. 17 shows the timing chart.

  However, in the case of the control pulse generation circuit 30B according to the second circuit example, since the logical sum of the latch signal P of the latch circuit 32 and the control pulse cntr2 is taken, variations in TFT characteristics, wiring resistance, and wiring If the control pulse cntrl2 is delayed due to the presence of the parasitic capacitance, the fourth control pulse sw4 and the first and fifth inversion control pulses xsw1 and xsw5 may become discontinuous.

  In contrast, in the control pulse generation circuit 30C according to the third circuit example, the latch signal P of the latch circuit 32 and the delay latch signal P ′ obtained by delaying the latch signal P by the delay circuit T by the delay time T1 Since a logical sum with the control pulse cntrl2 is taken, even if a delay occurs in the control pulse cntrl2 due to variations in TFT characteristics and the presence of wiring resistance or wiring parasitic capacitance, the fourth control pulse sw4 and the first control pulse sw4 , The continuity of the fifth inversion control pulses xsw1 and xsw5 can be reliably ensured.

(Fourth circuit example)
FIG. 18 is a circuit diagram showing a configuration of a control pulse generation circuit 30D according to the fourth circuit example. In FIG. 18, parts that are the same as the parts shown in FIG. As shown in FIG. 18, the control pulse generation circuit 30D according to this circuit example has a configuration including delay circuits 37 and 38 in addition to the components of the control pulse generation circuit 30C according to the second circuit example.

  The delay circuit 37 is configured by, for example, inverters 371 and 372 that are cascade-connected in two stages, and delays the control pulse cntrl1 by a predetermined time and supplies it to the level conversion circuits 20 and 20A as the third control pulse sw3. The delay circuit 38 is constituted by, for example, inverters 381 and 382 cascaded in two stages, and delays the output signal Q of the AND circuit 33 by a predetermined time and supplies it to the level conversion circuits 20 and 20A as the second control pulse sw2. To do.

  The circuit operation of the control pulse generation circuit 30D according to the fourth circuit example having the above configuration is basically the same as the circuit operation of the control pulse generation circuit 30C according to the third circuit example. FIG. 19 shows the timing chart.

  As apparent from the timing chart of FIG. 19, the control pulse cntrl1 is delayed by the delay circuit 37 to become the third control pulse sw3, whereby the fourth control pulse sw4 and the first and fifth inversion control pulses xsw1. , Xsw5 transitions from the High potential to the Low potential when the delay time T2 of the delay circuit 37 elapses from the timing t41 when the Xsw5 transitions from the Low potential to the High potential. As a result, the third control pulse sw3 becomes active after the first control pulse sw1 (xsw1) is reliably inactivated.

  Here, when the first control pulse sw1 (xsw1) is in the active state, the third control pulse sw3 (xsw3) becomes active, that is, when both active periods overlap, in FIG. Since the switching MOS transistor n24 (p24) is turned on when the transistor n21 (p21) is in the on state, a through current flows through the driving MOS transistor n21 (p21), which causes an increase in power consumption. End up.

  On the other hand, according to the control pulse generation circuit 30D according to the fourth circuit example, the third control pulse sw3 (xsw3) is changed after the first control pulse sw1 (xsw1) is surely inactivated. By becoming active, a through current does not flow through the drive MOS transistor n21 (p21), so that an increase in power consumption due to the through current can be suppressed.

  In addition, in the relationship between the second control pulse sw2 (xsw2) and the third control pulse sw3 (xsw3), if the periods of both active states overlap, a through current flows in the driving MOS transistor n21 (p21). However, the second control pulse sw2 (xsw2) and the third control pulse sw3 are obtained by delaying the output signal Q of the AND circuit 33 by the delay circuit 38 by the delay time T3 to obtain the second control pulse sw2. Since the active state of (xsw3) can be prevented from overlapping, an increase in power consumption due to the through current can be suppressed.

  By generating the control pulses of the level conversion circuits 20 and 20A using the control pulse generation circuits 30A to 30D according to the circuit examples described above, it is possible to reliably prevent the active state from overlapping between the control pulses. Therefore, there is an advantage that the reliability of the circuit operation of the level conversion circuits 20 and 20A can be improved.

  In each of the above-described embodiments, the case where the input signal to be level-converted is the clock signal ck (ck1, ck2) has been described as an example. Similar effects can be obtained even when conversion is performed.

[Application example]
Subsequently, the level conversion circuit 10A and 10B according to the above-described first embodiment and the modification thereof, the level conversion circuit 20 according to the second embodiment, and the level conversion circuit 20A according to the modification thereof. An application example will be described.

  FIG. 20 is a system configuration diagram showing an outline of the configuration of a display device according to an application example of the present invention. Here, as an example, a case where the present invention is applied to an organic EL display device using an organic EL (electroluminescence) element as an electro-optical element of a pixel will be described as an example. However, the present invention is not limited to application to an organic EL display device, and can be applied to panel display devices in general, such as a liquid crystal display device using a liquid crystal cell as an electro-optical element.

  In FIG. 20, a pixel circuit (pixel) 51 including an EL element is two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a glass substrate 52, thereby constituting a pixel array unit 53. In the pixel array unit 53, a drive line group 54 is wired for each row and a data line 55 is wired for each column, with respect to the matrix pixel array. Here, as the drive line group 54, for example, four lines of a scan line 54-1, a drive line 54-2, and first and second auto zero lines 54-3 and 54-4 are wired.

  On the same glass substrate 52 as the pixel array unit 53, a writing scanning circuit 56 for driving the scanning line 54-1, a driving scanning circuit 57 for driving the driving line 54-2, and the first and second auto zero lines 54-3. , 54-4 are respectively mounted as vertical drive circuits for driving to selectively scan each pixel circuit 51 of the pixel array section 53 in units of rows. .

  Here, the writing scanning circuit 56 and the driving scanning circuit 57 are arranged on one side (for example, the right side of the figure) with the pixel array unit 53 interposed therebetween, and the first and second auto zero circuits 58 and 59 are arranged on the opposite side. However, the arrangement relationship is merely an example, and the present invention is not limited to this.

  The write scanning circuit 56, the drive scanning circuit 57, and the first and second auto-zero circuits 58 and 59 are based on the vertical drive start pulse signal sp, the clock pulse ck, and the enable signal en supplied from the level converters 61 to 64. The operation is performed, and the write signal WS, the drive signal DS, and the first and second auto zero signals AZ1 and AZ2 are supplied to the scanning line 54-1, the drive line 54-2, and the first and second auto zero lines 54-3 and 54-4. As appropriate

  On the glass substrate 52, a data line driving circuit 60 for supplying a data signal corresponding to the luminance information to the data line 55 is mounted as a horizontal driving circuit. The data line driving circuit 60 operates based on the horizontal driving start pulse signal sp, the clock pulse ck, and the enable signal en supplied from the level conversion unit 65, and the data line 55 for each pixel circuit 51 in the selected row. The display data is written through the.

  Thus, on the glass substrate 52, together with the pixel array unit 53, the writing scanning circuit 56, the driving scanning circuit 57, the first and second auto zero circuits 58 and 59, the data line driving circuit 60, and the level converting units 61 to 65. Are integrally formed to form a display panel (EL panel).

  The level converters 61 to 65 receive a first amplitude Vss-Vini, for example, a start pulse signal sp of 0 [V] -3 [V], a clock pulse ck, and an enable signal en inputted from the outside of the panel. A write scanning circuit 56 by converting the level (level shift) to a start pulse signal sp, a clock pulse ck and an enable signal en having a second amplitude Vss-Vdd, for example, 0 [V] -8 [V] necessary for driving The drive scan circuit 57, the first and second auto zero circuits 58 and 59, and the data line drive circuit 60 are given.

  Each of the level converters 61 to 65 is constituted by three level conversion circuits provided corresponding to the start pulse signal sp, the clock pulse ck, and the enable signal en. As the level conversion circuits of the level conversion units 61 to 65, the level conversion circuit 10 according to the first embodiment described above and the level conversion circuits 10A and 10B according to the modifications thereof, or the level conversion circuit according to the second embodiment. 20 and a level conversion circuit 20A according to a modification thereof are used.

  As described above, the level conversion circuits 10 (10A, 10B) according to the first embodiment and the level conversion circuit 20 (20A) according to the second embodiment are used as the level conversion circuits of the level conversion units 61 to 65, respectively. In the case of incorporation, the above-described threshold cancellation operation in these level conversion circuits is periodically performed, for example, in a blanking period every 1H (H is a horizontal period) or 1F (F is a field period).

(Pixel circuit)
FIG. 21 is a circuit diagram illustrating an example of a circuit configuration of the pixel circuit 51.

  The pixel circuit 51 includes a driving transistor 72, a sampling transistor 73, switching transistors 74 to 76, and a capacitor (holding capacitor) 77 as circuit constituent elements in addition to the organic EL element 71 that is an electro-optical element. . That is, the pixel circuit 51 according to the present example has a circuit configuration including five transistors 72 to 76 and one capacitor 77.

  In the pixel circuit 51, N-channel TFTs (thin film transistors) are used as the drive transistor 72, the sampling transistor 73, and the switching transistors 74 to 76. Hereinafter, the drive transistor 72, the sampling transistor 73, and the switching transistors 74 to 76 are described as the drive TFT 72, the sampling TFT 73, and the switching TFTs 74 to 76.

  The organic EL element 71 has a cathode electrode connected to the ground potential GND, for example. The drive TFT 72 is a drive transistor that drives the organic EL element 71 with current, and a source is connected to an anode electrode of the organic EL element 71 to form a source follower circuit. The sampling TFT 73 has a source connected to the data line 55, a drain connected to the gate of the driving TFT 72, and a gate connected to the scanning line 53.

  The switching TFT 74 has a drain connected to, for example, the positive power supply potential Vdd, a source connected to the drain of the drive TFT 72, and a gate connected to the drive line 54. The switching TFT 75 has a drain connected to a predetermined potential Vofs, a source connected to the drain of the sampling TFT 73 (gate of the driving TFT 72), and a gate connected to the first auto-zero line 55.

  The switching TFT 76 has a drain connected to a connection node N11 between the source of the driving TFT 72 and the anode electrode of the organic EL element 71, and a source connected to a power supply potential Vss (in this example, Vss = GND). Note that a negative power supply potential can be used as the third power supply potential Vss. The capacitor 77 has one end connected to a connection node N12 between the gate of the driving TFT 72 and the drain of the sampling TFT 73, and the other end connected to a connection node N11 between the source of the driving transistor TFT72 and the anode electrode of the organic EL element 71.

  In the pixel circuit 51 in which the circuit elements are connected in the connection relation described above, the circuit elements perform the following actions. That is, the sampling TFT 73 samples the input signal voltage Vsig supplied through the data line 55 by being turned on (conductive). The signal voltage Vsig sampled by the sampling TFT 73 is held in the capacitor 77. The switching TFT 74 is turned on to supply current to the driving TFT 72 from the power supply potential Vdd.

  The drive TFT 72 current-drives the organic EL element 71 according to the signal voltage Vsig held in the capacitor 77. The switching TFTs 75 and 76 are appropriately turned on to detect the threshold voltage Vth of the driving TFT 72 prior to current driving of the organic EL element 71, and the detected threshold voltage Vth is used as a capacitor in order to cancel the influence in advance. 77.

  As described above, in the panel type display device, the pulse signals (in this example, the start pulse signal sp, the clock pulse ck, and the enable signal en) for driving the vertical and horizontal driving systems are supplied to the first display outside the panel. Level conversion circuit for converting the level from the amplitude Vss-Vini (for example, 0 [V] -3 [V]) to the second amplitude Vss-Vdd (for example, 0 [V] -8 [V]) inside the panel As described above, by using the level conversion circuit 10 (10A, 10B) according to the first embodiment and the level conversion circuit 20 (20A) according to the second embodiment, the level conversion circuits 10, 20 have low power consumption. In addition, since the high-speed operation is possible, the power consumption of the entire display device can be reduced and the display operation speed can be increased.

  In particular, in the case of an organic EL display device using an organic EL element as a pixel electro-optical element, as a vertical driving system, for example, a writing scanning circuit 56, a driving scanning circuit 57, and first and second auto-zero circuits 58 and 59. 4 are used, and for each of these drive circuits, for example, three pulse signals of a start pulse signal sp, a clock pulse ck, and an enable signal en are used. A level conversion circuit is arranged for each of ck and enable signal en.

  Therefore, in the vertical scanning system, a total of 12 level conversion circuits are arranged as the level conversion units 61 to 64. Accordingly, considering the power consumption of the entire level converters 61 to 64, the power consumption can be reduced by 12 times the power consumption that can be reduced by one level conversion circuit. This can greatly contribute to power generation.

  In the application example, the level conversion circuit 10 according to the first embodiment and the level conversion circuits 10A and 10B according to the modification, the level conversion circuit 20 according to the second embodiment, and the level conversion circuit according to the modification. The case where 20A is used as a level conversion circuit mounted on a panel of a display device has been described as an example. However, the present invention is not limited to this application example, and the first amplitude signal is not limited to the first amplitude signal. It can be widely used as a level conversion circuit for level conversion (level shift) to a signal having a second amplitude different from the above.

1 is a circuit diagram showing a level conversion circuit according to a first embodiment of the present invention. 3 is a timing chart for explaining the circuit operation of the level conversion circuit according to the first embodiment. FIG. 6 is a circuit diagram showing a level conversion circuit according to a first modification of the first embodiment. FIG. 10 is a circuit diagram showing a level conversion circuit according to a second modification of the first embodiment. It is a timing chart for explaining circuit operation of a level conversion circuit concerning the 2nd modification. It is a circuit diagram which shows the level conversion circuit which concerns on 2nd Embodiment of this invention. 10 is a timing chart for explaining the circuit operation of the level conversion circuit according to the second embodiment. It is a circuit diagram which shows the level conversion circuit which concerns on the modification of 2nd Embodiment. It is a timing chart for explaining circuit operation of a level conversion circuit concerning a modification of a 2nd embodiment. It is a timing chart (the 1) which shows the timing relationship used for description for reducing the number of control pulses. It is a timing chart (the 2) which shows the timing relationship used for description for reducing the number of control pulses. It is a circuit diagram which shows the structure of the control pulse generation circuit which concerns on the 1st circuit example. 6 is a timing chart for explaining the circuit operation of the control pulse generation circuit according to the first circuit example. It is a circuit diagram which shows the structure of the control pulse generation circuit which concerns on the 2nd circuit example. It is a timing chart for explaining circuit operation of a control pulse generation circuit concerning the 2nd circuit example. It is a circuit diagram which shows the structure of the control pulse generation circuit which concerns on the 3rd circuit example. It is a timing chart for explaining circuit operation of a control pulse generating circuit concerning the 3rd circuit example. It is a circuit diagram which shows the structure of the control pulse generation circuit which concerns on the 4th circuit example. It is a timing chart for explaining circuit operation of a control pulse generating circuit concerning the 4th circuit example. It is a system configuration diagram showing an outline of a configuration of an active matrix organic EL display device according to an application example of the present invention. It is a circuit diagram which shows an example of the circuit structure of a pixel circuit. It is a circuit diagram which shows an example of a structure of the current mirror type | mold level conversion circuit which concerns on a prior art example.

Explanation of symbols

  10, 10A, 10B, 20, 20A ... Level conversion circuit, 11, 21 ... Complementary circuit, 23 ... Level shift circuit, 30, 30A, 30B, 30C, 30D ... Control pulse generation circuit, 51 ... Pixel circuit (pixel) 52 ... Glass substrate, 53 ... Pixel array unit 53,54 ... Drive line group, 55 ... Data line, 56 ... Write scan circuit, 57 ... Drive scan circuit, 58 ... First auto-zero circuit, 59 ... Second auto-zero circuit, 60 ... Data line driving circuit, 61-65 ... Level conversion unit, 71 ... Organic EL element

Claims (8)

A first drive transistor connected between the first power supply potential and the output node;
A second drive transistor having a conductivity type opposite to that of the first drive transistor connected between a second power supply potential and the output node;
A first coupling capacitor for providing an input signal to the gate of the first drive transistor;
A second coupling capacitor for providing a signal in phase with the input signal to the gate of the second drive transistor;
A first diode element formed in the vicinity of the first drive transistor;
A second diode element formed in the vicinity of the second drive transistor;
Prior to the input signal being applied to the gate of the first drive transistor, the gate potential of the first drive transistor is set to a potential obtained by superimposing the threshold value of the first diode element on the first power supply potential. A first switching circuit fixed to
Prior to applying the in-phase signal to the gate of the second drive transistor, the gate potential of the second drive transistor is superimposed on the second power supply potential, and the threshold value of the second diode element is superimposed on the second power supply potential. A second switching circuit that determines the potential, and
The threshold value of the first drive transistor and the threshold value of the first diode element are canceled by determining the gate potential of the first drive transistor by the first switching circuit,
A level conversion circuit that cancels a threshold value of the second drive transistor and a threshold value of the second diode element by determining the gate potential of the second drive transistor by the second switching circuit. The first switching circuit is connected between one end of the first diode element and the gate of the first driving transistor, and is turned on before the input signal is applied to the gate of the first driving transistor. A first switching transistor that is in a state; a common connection node between the first diode element and the first switching transistor; and the second power supply potential, and the first switching transistor is turned on. A second switching transistor that is turned on before being turned on, and is connected between the other end of the first diode element and the first power supply potential, and the second switching transistor is turned on. A third switching transistor that is sometimes turned off,
The second switching circuit is connected between one end of the second diode element and the gate of the first driving transistor, and is turned on before the input signal is applied to the gate of the second driving transistor. A fourth switching transistor in a state, a common connection node of the second diode element and the fourth switching transistor, and the first power supply potential, and the fourth switching transistor is turned on. The fifth switching transistor which is turned on before entering the state, and is connected between the other end of the second diode element and the second power supply potential, and the fifth switching transistor is turned on. that having a sixth switching transistor turned off when
Level conversion circuit 請 Motomeko 1 wherein. The first switching circuit is connected between one end of the first diode element and the gate of the first driving transistor, and is turned on before the input signal is applied to the gate of the first driving transistor. A first switching transistor that enters a state, a second switching transistor that has one end connected to the second power supply potential and is turned on before the first switching transistor is turned on, and the first switching transistor A third node that is connected between a common connection node between the diode element and the first switching transistor and the other end of the second switching transistor and is turned off when the second switching transistor is turned on. Switching transistors,
The second switching circuit is connected between one end of the second diode element and the gate of the second driving transistor, and before the in-phase signal is applied to the gate of the second driving transistor. A fourth switching transistor that is turned on, a fifth switching transistor that has one end connected to the first power supply potential and is turned on before the fourth switching transistor is turned on; and The second switching element is connected between a common connection node of the diode element and the fourth switching transistor and the other end of the fifth switching transistor, and is turned off when the fifth switching transistor is turned on. that having a and 6 of the switching transistor
Level conversion circuit 請 Motomeko 1 wherein. A first drive transistor having one end connected to a first power supply potential;
A second driving transistor having one end connected to a second power supply potential and having a conductivity type opposite to that of the first driving transistor;
A first coupling capacitor for providing an input signal to the gate of the first drive transistor;
A second coupling capacitor for providing a signal in phase with the input signal to the gate of the second drive transistor;
A first switching element connected between the other end of the first driving transistor and an output node and turned off in a certain period before the input signal is applied to the gate of the first driving transistor;
A second switching element connected between the other end of the second driving transistor and an output node, and is turned off in the predetermined period before the in-phase signal is applied to the gate of the second driving transistor; When,
A third switching element connected between the gate of the first driving transistor and the second power supply potential and turned on within the predetermined period;
A fourth switching element connected between the gate of the second drive transistor and the first power supply potential and turned on within the predetermined period;
A fifth switching transistor connected between a drain and a gate of the first driving transistor and turned on after the third switching element is turned off within the predetermined period;
The second is connected between the drain and gate of the drive transistor, the level of the said during a fixed period the fourth switching element and a sixth switching transistor which is turned on after turned off Conversion circuit. A first control pulse having opposite phases driving the first and fourth switching transistors, a second control pulse having opposite phases driving the second and fifth switching transistors, and the third and third control pulses, A control pulse generating circuit for generating a third control pulse having opposite phases to drive the sixth switching transistor;
Said control pulse generation circuit, two first based on the control pulse, that generates a second, third control pulse
Level conversion circuit 請 Motomeko 4 wherein. Said control pulse generation circuit, the first, second, first, as the active state does not overlap the third control pulse, that generates a second, third control pulse
Level conversion circuit 請 Motomeko 5 wherein. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
A driving circuit that is formed on the same substrate as the pixel array unit, and that performs driving for writing a display signal to each pixel of the pixel array unit;
A level conversion circuit for level-converting a signal input from the outside of the substrate to operate the drive circuit and providing the drive circuit;
The level conversion circuit includes:
A first drive transistor connected between the first power supply potential and the output node;
A second drive transistor having a conductivity type opposite to that of the first drive transistor connected between a second power supply potential and the output node;
A first coupling capacitor for providing an input signal to the gate of the first drive transistor;
A second coupling capacitor for providing a signal in phase with the input signal to the gate of the second drive transistor;
A first diode element formed in the vicinity of the first drive transistor;
A second diode element formed in the vicinity of the second drive transistor;
Prior to the input signal being applied to the gate of the first drive transistor, the gate potential of the first drive transistor is set to a potential obtained by superimposing the threshold value of the first diode element on the first power supply potential. A first switching circuit fixed to
Prior to applying the in-phase signal to the gate of the second drive transistor, the gate potential of the second drive transistor is superimposed on the second power supply potential, and the threshold value of the second diode element is superimposed on the second power supply potential. have a second switching circuit for determining the potential,
The threshold value of the first drive transistor and the threshold value of the first diode element are canceled by determining the gate potential of the first drive transistor by the first switching circuit,
The threshold value of the second drive transistor and the threshold value of the second diode element are canceled by determining the gate potential of the second drive transistor by the second switching circuit.
Viewing equipment. A pixel array unit in which pixels including electro-optic elements are two-dimensionally arranged in a matrix;
A driving circuit that is formed on the same substrate as the pixel array unit, and that performs driving for writing a display signal to each pixel of the pixel array unit;
A level conversion circuit for level-converting a signal input from the outside of the substrate to operate the drive circuit and providing the drive circuit;
The level conversion circuit includes:
A first drive transistor having one end connected to a first power supply potential;
A second driving transistor having one end connected to a second power supply potential and having a conductivity type opposite to that of the first driving transistor;
A first coupling capacitor for providing an input signal to the gate of the first drive transistor;
A second coupling capacitor for providing a signal in phase with the input signal to the gate of the second drive transistor;
A first switching element connected between the other end of the first driving transistor and an output node and turned off in a certain period before the input signal is applied to the gate of the first driving transistor;
A second switching element connected between the other end of the second driving transistor and an output node, and is turned off in the predetermined period before the in-phase signal is applied to the gate of the second driving transistor; When,
A third switching element connected between the gate of the first driving transistor and the second power supply potential and turned on within the predetermined period;
A fourth switching element connected between the gate of the second drive transistor and the first power supply potential and turned on within the predetermined period;
A fifth switching transistor connected between a drain and a gate of the first driving transistor and turned on after the third switching element is turned off within the predetermined period;
Which is connected between the drain and the gate of the second driving transistor, that the predetermined period within the said fourth switching element having a sixth switching transistor which is turned on after turned off
Viewing equipment.

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