JP2004266817A - Semiconductor device, electronic apparatus, and method for driving semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital circuit which is normally in operation independently of a binary level of an input signal. <P>SOLUTION: A semiconductor device including: a correction means; and a single or more circuit elements is characterized in that the correction means includes first and second capacitive elements, and first and second switches, a first electrode of the first capacitive element and a first electrode of the second capacitive element are connected to an input terminal, the 1st switch controls application of a first level to a second electrode of the first capacitive element, the second switch controls application of a second level to a second electrode of the second capacitive element, and the level of the second electrode of the first capacitive element or the level of the second electrode of the second capacitive element is applied to the single or more circuit elements. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a digital circuit operated by a digital signal, and further relates to a semiconductor device having one or more digital circuits, an electronic device, and a driving method thereof.

  A logic circuit for processing a digital signal (hereinafter, referred to as a digital circuit) is configured by a single logic element as a basic unit or a combination of a plurality of logic elements. A logic element is a circuit that can obtain one output with respect to one or more inputs, and corresponds to, for example, an inverter, an AND, an OR, a NOT, a NAND, a NOR, a clocked inverter, a transmission gate, and the like.

  The logic element is configured by connecting one or more circuit elements such as a transistor, a resistor, and a capacitor. Then, by operating the plurality of circuit elements in accordance with the digital signal input to the logic element, the potential or current of a signal supplied to a subsequent circuit is controlled.

  An inverter, which is one of the logic elements, is taken as an example, and its configuration and operation will be specifically described.

  FIG. 13A shows a circuit diagram of a general inverter. In FIG. 13A, IN means an input signal (input signal), and OUT means an output signal (output signal). VDD and VSS mean the power supply potential, and VDD> VSS.

  The inverter illustrated in FIG. 13A includes a p-channel transistor 1301 and an n-channel transistor 1302. The gate (G) of the p-channel transistor 1301 and the gate of the n-channel transistor 1302 are connected to each other, and the input signal IN is input to the two gates. Then, VDD is supplied to a first terminal of the p-channel transistor 1301, and VSS is supplied to a first terminal of the n-channel transistor 1302. A second terminal of the p-channel transistor 1301 and a second terminal of the n-channel transistor 1302 are connected to each other, and an output signal OUT is output from the two second terminals to a subsequent circuit.

  Note that one of the first terminal and the second terminal corresponds to a source, and the other corresponds to a drain. In the case of a p-channel transistor, the higher potential is the source and the lower potential is the drain. In an n-channel transistor, a source with a lower potential is a source and a drain with a higher potential is. Therefore, in FIG. 13A, in the two TFTs, the first terminal corresponds to the source (S), and the second terminal corresponds to the drain (D).

  Generally, a digital signal having a binary potential is used as an input signal. Two circuit elements included in the inverter operate according to the potential of the input signal IN, and the potential of the output signal OUT is controlled.

  Next, the operation of the inverter illustrated in FIG. 13A is described with reference to FIGS. 13B and 13C. In FIG. 13B and FIG. 13C, each circuit element is shown as a simple switch for easy understanding of the operation state.

FIG. 13B illustrates the operation of each circuit element when the input signal IN has a higher potential. Here, the potential on the high potential side of the input signal IN is assumed to be VDD ′ (VDD ′ ≧ VDD), and the threshold voltage V _THN ≧ 0 of the n-channel transistor 1302 and the p-channel transistor 1301 Assume that the threshold voltage V _THP ≦ 0.

When the potential VDD ′ is applied to the gate of the p-channel transistor 1301, the gate voltage becomes V _GS ≧ 0 because VDD ′ ≧ VDD, and the p-channel transistor 1301 is turned off. Note that a gate voltage corresponds to a voltage obtained by subtracting a source potential from a gate potential.

When VDD ′ is applied to the gate of the n-channel transistor 1302, since VDD ′> VSS, the gate voltage becomes V _GS > 0, and the n-channel transistor 1302 is turned on. Therefore, the power supply potential VSS is supplied to the subsequent circuit as the potential of the output signal OUT.

Next, FIG. 13C illustrates an operation state of each circuit element when the input signal IN has a lower potential. Here, the potential on the low potential side of the input signal IN is set to VSS ′ (VSS ′ ≦ VSS), and the threshold voltage V _THN ≧ 0 of the n-channel transistor 1302 and the threshold voltage of the p-channel transistor 1301 are set to simplify the description. Assume that the threshold voltage V _THP ≦ 0.

When VSS ′ is applied to the gate of the n-channel transistor 1302, the gate voltage becomes V _GS ≦ 0 because VSS ′ ≦ VSS, and the n-channel transistor 1302 is turned off.

When the potential VSS ′ is applied to the gate of the p-channel transistor 1301, the gate voltage becomes V _GS <0 because VSS ′ <VDD, and the p-channel transistor 1301 is turned on. Therefore, the power supply potential VDD is supplied to a subsequent circuit as the potential of the output signal OUT.

  Thus, each circuit element operates according to the potential of the input signal IN, and the potential of the output signal OUT is controlled.

  The operation of the inverter described with reference to FIGS. 13B and 13C is based on the assumption that the binary potentials VDD ′ and VSS ′ of the input signal IN are VDD ′ ≧ VDD and VSS ′ ≦ VSS, respectively. Is the case. Here, the operation of the inverter shown in FIG. 13A will be verified assuming that the binary potentials VDD 'and VSS' of the input signal IN are VDD '<VDD and VSS'> VSS, respectively. Note that VSS '<VDD'.

First, FIG. 14A illustrates an operation state of each circuit element in a case where the input signal IN has a higher potential VDD ′ (VDD ′ <VDD). Here, for simplicity, it is assumed that the threshold voltage V _THN ≧ 0 of the n-channel transistor 1302 and the threshold voltage V _THP ≦ 0 of the p-channel transistor 1301.

When the potential VDD ′ is applied to the gate of the p-channel transistor 1301, the gate voltage becomes V _GS <0 because VDD ′ <VDD. Therefore, when | V _GS |> | V _THP |, the p-channel transistor 1301 is turned on. When VDD ′ is applied to the gate of the n-channel transistor 1302, since VDD ′> VSS, the gate voltage becomes V _GS > 0, and the n-channel transistor 1302 is turned on.

  Therefore, both the p-channel transistor 1301 and the n-channel transistor 1302 are turned on, so that even when the input signal has a high potential side, the output signal OUT is different from the case illustrated in FIG. Does not become VSS.

The potential of the output signal OUT is determined by the current flowing through each transistor. In FIG. 14 (A), the the V _GS of the n-channel transistor 1302 and V _GSn, if the V _GS of the p-channel transistor 1301 and _{V GSp, | V GSn |>} | V GSp | So characteristics of each transistor If there is no difference in the ratio between the channel width W and the channel length L, the potential of the output signal OUT is closer to VSS than VDD. However, depending on the mobility of each TFT, the threshold voltage, the ratio of the channel width to the channel length, and the like, the potential of the output signal OUT may be closer to VDD than VSS. In this case, the operation of the digital circuit is not normal, and there is a high possibility of malfunction. This can cause a malfunction of a digital circuit provided in a subsequent stage in a chain.

FIG. 14B illustrates an operation state of each circuit element when the input signal IN has the low-potential-side potential VSS ′ (VSS ′> VSS). Here, for the sake of simplicity, it is assumed that the threshold voltage V _THN ≧ 0 of the n-channel transistor and the threshold voltage V _THP ≦ 0 of the p-channel transistor.

When VSS ′ is applied to the gate of the n-channel transistor 1302, the gate voltage becomes V _GS > 0 because VSS ′> VSS. Therefore, when | V _GS |> | V _THn |, the n-channel transistor 1302 is turned on. When the potential VSS ′ is applied to the gate of the p-channel transistor 1301, the gate voltage becomes V _GS <0 because VSS ′ <VDD, and the p-channel transistor 1301 is turned on.

Therefore, depending on the values of VSS, VSS ′, and V _THn , both the p-channel transistor 1301 and the n-channel transistor 1302 are turned on, and therefore, unlike the case shown in FIG. The potential of the output signal OUT does not become VDD.

The potential of the output signal OUT is determined by the current flowing through each transistor. In FIG. 14 (B), the the V _GS of the n-channel transistor and V _GSn, if the V _GS of the p-channel transistor and _{V GSp, | V GSn | <} | V GSp | So each transistor characteristics and channel If there is no difference in the ratio between the width W and the channel length L, the potential of the output signal OUT is closer to VDD than VSS. However, depending on the mobility of each TFT, the threshold voltage, the ratio of the channel width to the channel length, and the like, the potential of the output signal OUT may be closer to VSS than VDD. In this case, the operation of the digital circuit is not normal, and there is a high possibility of malfunction. This can cause a malfunction of a digital circuit provided in a subsequent stage in a chain.

  As described above, in the inverter illustrated in FIG. 13A, when the binary potentials VDD ′ and VSS ′ of the input signal IN satisfy VDD ′ ≧ VDD and VSS ′ ≦ VSS, respectively, the desired potential is changed. Thus, it can be said that the inverter operates normally. However, if the binary potentials VDD 'and VSS' of the input signal IN are VDD '<VDD and VSS'> VSS, respectively, an output signal OUT having a desired potential cannot be obtained and the inverter does not operate normally. There is.

  This applies not only to the inverter but also to other digital circuits. That is, if the binary potential of the input signal is out of the predetermined range, the circuit element of the digital circuit malfunctions, so that the output signal OUT having the desired potential cannot be obtained, and the digital circuit operates normally. Does not work.

  The potential of the input signal supplied from the preceding circuit or wiring is not necessarily high enough to allow the digital circuit to operate normally. In this case, normal operation of the digital circuit can be ensured by adjusting the potential of the input signal with the level shifter. However, in general, the level shifter operates in conjunction with each other such that another circuit element operates only when one circuit element operates within the level shifter, so that the potential of the output signal falls or The rise is slow, which tends to hinder high-speed operation of the semiconductor device.

  Further, when the power supply voltage is small, the current is small and it is difficult to turn on the power supply, so that it is difficult to operate at high speed. Conversely, when the power supply voltage is increased to operate at high speed, the power consumption increases.

  Further, since the n-channel transistor 1302 and the p-channel transistor 1301 are turned on at the same time and a short-circuit current flows, there is a problem that current consumption increases.

  In order to solve the above-mentioned problem, in a level shifter circuit having a first input inverter and a second output inverter, a first inverter is switched from a first inverter to a second inverter by a capacitor (capacitance element) and bias means. It has been proposed to convert the DC level of an input signal. (See Patent Document 1). However, in this circuit, the DC level conversion capacitor connected between the gate of each transistor constituting the second inverter and the output of the first inverter always has the high level power supply potential or the low level power supply potential by the bias means. To the extent that the charging and discharging of these capacitors adversely affect the dynamic characteristics of the circuit (that is, lower the circuit operating speed), or the power consumption associated with the charging and discharging of these capacitors cannot be ignored. The problem arises that the size becomes larger. In addition, when there is a variation in the threshold value of the transistor, it is difficult to match the capacitance of each capacitor to the corresponding transistor, and therefore, the voltage across the DC level conversion capacitor must match the threshold value of the corresponding transistor. Therefore, a problem may occur that the transistor cannot be accurately turned on and off.

JP-A-9-172667

  In view of the above problems, an object of the present invention is to propose a digital circuit that can operate normally regardless of a binary potential of an input signal.

  According to the present invention, a potential difference between a potential of a signal actually input to a digital circuit and a potential at which the digital circuit can operate normally is stored in advance, and the potential difference is added to the actually input signal. After that, by providing a correction means for inputting to each circuit element in the digital circuit, the digital circuit operates normally.

  The correction means turns off the n-channel transistor when the low potential of the input signal is supplied, and turns off the p-channel transistor when the high potential of the input signal is supplied. it can. As a result, the digital circuit can operate normally.

  FIG. 1A shows a structure of a digital circuit of the present invention. The digital circuit 100 includes a correction unit 101 for correcting the potential of the input signal IN, and one or more circuit elements 102 whose operations are controlled by the input signal corrected by the correction unit 101. Then, the potential of the output signal OUT is controlled according to the operation of the circuit element.

  FIG. 1B schematically shows a first configuration of the correction means 101 included in the digital circuit of the present invention. The correcting means 101 of the first configuration has a capacitor 123 for correcting one of the high potential side and the low potential side of the input signal.

  Further, a switch 130 that controls supply of the power supply potential 1 to the first electrode of the capacitor 123 and a switch 131 that controls supply of the power supply potential 2 to the second electrode of the capacitor 123 are provided. Further, a switch 132 for controlling the supply of the potential of the input signal IN to the first electrode of the capacitor 123 is provided. Then, the second electrode of the capacitor 123 is connected to the output terminal 140.

  Note that when correcting the high-potential side of the input signal IN, power supply potential 1 ≦ power supply potential 2 is satisfied. When correcting the potential on the low potential side of the input signal IN, power supply potential 1 ≧ power supply potential 2 is satisfied.

  By controlling the switches 130 and 131, the capacitor 123 can store and hold the potential difference between the power supply potential 1 and the power supply potential 2.

  When the potential of the input signal IN is given to the first electrode of the capacitor 123 by controlling the switch 132, the potential difference held in the capacitor 123 is added to the potential of the input signal IN, and Input to the circuit element 102.

  Therefore, by controlling the potential difference between the power supply potential 1 and the power supply potential 2 to a desired magnitude, the height of the potential given to the circuit element 102 can be controlled, and the circuit element 102 and thus the digital circuit 100 operate normally. Can be done.

  Normal operation means that the potential of the output terminal when the input signal IN is on the low voltage side is substantially equal to the potential of the output terminal when the input signal IN is equal to VSS, and the input signal IN is high. This refers to the case where the potential of the output terminal when the potential is on the potential side is substantially equal to the output when the input signal IN is VDD. Note that even if the output is not necessarily equal to VSS or VDD, it can be considered that the digital circuit provided in the subsequent stage is operating normally unless a malfunction occurs.

  FIG. 1C schematically shows a second configuration of the correction means 101 included in the digital circuit of the present invention. The correction means 101 of the second configuration corresponds to a means for performing correction by substituting the power supply potential 1 of FIG. 1B with the potential of the input signal. Specifically, the correction means 101 of the second configuration has a capacitance element 103 for correcting the potential of the input signal IN.

  Note that, when correcting the potential on the high potential side of the input signal IN, the potential on the high potential side of the input signal IN ≦ the power supply potential. When correcting the potential on the low potential side of the input signal IN, the potential on the low potential side of the input signal IN ≧ the power supply potential.

  The potential difference between one of the high potential side and the low potential side of the input signal IN and the power supply potential is stored in the capacitor 103 in advance. The supply of the power supply potential to the capacitor 103 is controlled by the switch 108.

  With the above structure, the potential difference held in the capacitor 103 is added to the potential of the input signal IN and input to the subsequent circuit element 102.

  Therefore, by controlling the potential difference between the potential of the input signal IN and the power supply potential to a desired magnitude, the height of the potential applied to the circuit element 102 can be controlled, and the circuit element 102 and thus the digital circuit 100 can be normally operated. Can work.

  In the case where the circuit element 102 includes a transistor and a corrected input signal is input to the gate of the transistor, a state in which a capacitor for storing the gate capacitance of the transistor and a potential difference is connected in series become. Therefore, the combined capacitance obtained by connecting the capacitance element for storing the gate capacitance of the transistor and the potential difference in series is smaller than the capacitance value of the gate capacitance of the transistor alone. Therefore, a delay in operation of the transistor due to the gate capacitance can be prevented and the operation speed can be increased. Further, since a transistor which is one of the circuit elements malfunctions and is turned on when it should be turned off, an increase in current consumption due to leakage current can be prevented.

  Note that the operation of initializing the electric charge held in the capacitor and the operation of storing the potential difference to be corrected impede the normal operation of the digital circuit because the electric charge stored in each capacitor leaks. It is better to do it again before it ends.

  Further, although a switch is used in the present invention, other elements can be substituted. For example, a transistor may be used as a switch. In this case, the polarity of the transistor used as the switch may be either n-type or p-type.

  In the present invention, the switch may be an electrical switch or a mechanical switch. Anything can be used as long as it can control the current flow. It may be a transistor, a diode, or a logic circuit combining them. Therefore, when a transistor is used as a switch, the transistor operates as a simple switch, and there is no particular limitation on the polarity (conductivity type) of the transistor. However, in the case where it is desirable that the off-state current be small, it is preferable to use a transistor having the polarity with the small off-state current. As a transistor with small off-state current, there is a transistor provided with an LDD region. In the case where the transistor operated as a switch operates in a state in which the source terminal potential is close to the low potential side power supply (Vss, Vgnd, 0 V, or the like), the n-channel type is used. When operating near a side power supply (such as Vdd), it is desirable to use a p-channel type. This is because the absolute value of the gate-source voltage can be increased, and the switch can easily operate. Note that a CMOS switch may be used by using both the n-channel type and the p-channel type.

  Further, the position of the switch does not necessarily have to be provided at the position shown in FIG. 1, and if the circuit can perform the above-described operation, the position at which the switch is provided can be appropriately determined by the designer. In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, another element (for example, another element or a switch) that enables electrical connection therebetween may be arranged. Depending on the case, the number of switches may be increased or decreased.

  According to the present invention, with the above structure, a digital circuit can operate normally regardless of the potential of an input signal.

  In the case where the circuit element includes a transistor and the corrected input signal is input to the gate of the transistor, a state in which the gate capacitance of the transistor and the first or second capacitance element are connected in series become. Therefore, the capacitance value of the combined capacitance obtained by connecting the gate capacitance of the transistor and the first capacitance element or the second capacitance element in series is smaller than the case where the gate capacitance of the transistor is used alone. Therefore, delay in operation of the transistor due to gate capacitance can be prevented.

(Embodiment 1)
In this embodiment, a specific structure and operation of an inverter which is one of digital circuits of the present invention will be described.

  FIG. 2 shows a configuration of the inverter according to the present embodiment. 201 corresponds to a correction unit, and 202 is a circuit element group.

  The correction means 201 includes a first capacitive element 203, a second capacitive element 204, three switches 205 to 207 for controlling supply of a potential to the first capacitive element 203, and a second capacitive element 204. And three switches 208 to 210 for controlling the supply of potential to the switch.

The switch 205 controls supply of a potential of an input signal to a first electrode included in the first capacitor 203. The switch 206 controls the supply of the high potential side power supply potential V _H to the first electrode of the first capacitor 203. The switch 207 controls supply of the power supply potential VDD to the second electrode included in the first capacitor 203.

The switch 208 controls supply of a potential of an input signal to a first electrode included in the second capacitor 204. The switch 209 controls supply of the low potential side power supply potential _VL to the first electrode included in the second capacitor 204. The switch 210 controls supply of the power supply potential VSS to the second electrode included in the second capacitor 204.

  Note that although this embodiment mode shows the mode in which the power supply potential VDD is supplied to the second electrode included in the first capacitor 203 by the switch 207, the present invention is not limited to this. The potential supplied to the second electrode included in the first capacitor 203 may be a potential other than the power supply potential VDD, and the supplied potential may be appropriately adjusted in accordance with the potential of an input signal. . Similarly, the power supply potential VSS is supplied to the second electrode of the second capacitor 204 by the switch 210; however, the present invention is not limited to this. The potential supplied to the second electrode included in the second capacitor 204 may be a potential other than the power supply potential VSS, and the supplied potential may be appropriately adjusted in accordance with the potential of an input signal. .

  The circuit element group 202 includes one p-channel transistor 211 and one n-channel transistor 212. A power supply potential VDD is supplied to a first terminal (here, a source) of the p-channel transistor 211, and a power supply potential VSS is supplied to a first terminal (here, a source) of the n-channel transistor 212. I have. A second terminal (here, drain) of the p-channel transistor 211 and a second terminal (here, drain) of the n-channel transistor 212 are connected to each other, and the second terminal of these two transistors is connected to each other. The potential is supplied to a subsequent circuit as the potential of the output signal OUT.

  The second electrode of the first capacitor 203 is connected to the gate of the p-channel transistor 211, and the second electrode of the second capacitor 204 is connected to the gate of the n-channel transistor 212. I have.

Note that VDD> VSS, _VH > _VL , VDD> _VH , and _VL > VSS. It is desirable that the power supply potential V _H is set so as to be close to the potential on the high potential side of the input signal in the normal operation, and to be lower than the potential if possible. Thus, when a high-potential-side potential is supplied, the p-channel transistor 211 is easily turned off. Further, it is desirable that the power supply potential V _L is set so as to be close to the potential on the low potential side of the input signal in the normal operation and to be higher than the potential if possible. Thus, when a low potential is supplied, the n-channel transistor 212 is easily turned off. In this embodiment, it is assumed that the high potential side of the input signal is equal to the power supply potential _VH, and the low potential side of the input signal is equal to the power supply potential _VL . The V _H -V _L> V _THn, made to be V _L -V _H <V _THp.

In this embodiment, the operation is described on the assumption that the threshold voltages of the p-channel transistor 211 and the n-channel transistor 212 included in the circuit element group 202 are 0. It is not always 0. In this case, for example, _assuming that the threshold voltage of the p-channel transistor 211 is V _THp , V _H is set to be higher than the potential on the high potential side of the input signal during normal operation by | V _THp | minutes or more. Is desirable. Further, for example, when the threshold voltage of the n-channel transistor 212 is V _THn , it is desirable that _VL is set to be lower than the potential on the low potential side of the input signal by | V _THn | . By doing so, it is possible to maximize | V _GS | to obtain a higher on-current when turning on the p-channel transistor 211 or the n-channel transistor 212 while preventing the transistor from becoming normally on. it can.

  Next, the operation of the inverter shown in FIG. 2 will be described with reference to FIG. The operation of the digital circuit of the present invention is classified into an operation of storing a potential difference to be corrected and a normal operation of performing the original function of the digital circuit.

First, an operation of storing a potential difference will be described with reference to FIG. The potential difference to be stored differs between the first capacitor 203 and the second capacitor 204. The first capacitor 203 stores a potential difference between the power supply potential VDD and the high-potential power supply potential V _H, and the second capacitor 204 stores a potential difference between the power supply potential VSS and the low-potential power supply potential _VL .

Specifically, turning OFF the switch 205 as shown in FIG. 3 (A), and turns on the switch 206 and 207, provide a power supply potential V _H to the first electrode of the first capacitor 203, a second electrode To the power supply potential VDD. Then, charge is accumulated in the first capacitor 203 by the power supply potential V _H and the power supply potential VDD.

Further, the switch 208 is turned off and the switches 209 and 210 are turned on, so that the power supply potential _VL is applied to the first electrode of the second capacitor 204 and the power supply potential VSS is applied to the second electrode. Then, electric charge is accumulated in the second capacitor 204 by the power supply potential _VL and the power supply potential VSS.

Next, as shown in FIG. 3B, when the switches 205, 206, and 207 are turned off, the accumulated charge is held in the first capacitor 203, and the potential between the power supply potential VDD and the power supply potential _VH is changed. the potential difference between (for serial and Vc ₁₎ is stored. Similarly, by turning OFF the switch 208, 209, 210, the accumulated charge is held in the second capacitor 204, a potential difference (Vc ₂ between the power supply potential VSS and the power supply potential V _L serial Is stored.

  Next, the correction of the potential of the input signal based on the stored potential difference and the normal operation performed based on the corrected potential will be described.

Operation in the case where the potential of the input signal IN is on the high potential side (V _{H in} this embodiment) will be described with reference to FIG.

In a normal operation, the switches 206, 207, 209, and 210 are always off, and the switches 205 and 208 are on. The potential V _{H of the} input signal is supplied to the first electrode of the first capacitor 203 and the first electrode of the second capacitor 204 through the switches 205 and 208.

The potential difference between the two electrodes of each of the first capacitor 203 and the second capacitor 204 is always constant in accordance with the law of conservation of electric charge. Therefore, when the potential V _H is applied to the first electrode, the potential of the second electrode of the first capacitor 203 is kept at the height obtained by adding the potential difference Vc ₁ to the potential V _H. Here, since the potential difference Vc ₁ = power supply potential VDD−power supply potential V _H , the potential of the second electrode of the first capacitor 203 is VDD. The potential VDD of the second electrode is applied to the gate of the p-channel transistor 211, and the p-channel transistor 211 is turned off because the gate voltage becomes 0.

On the other hand, the potential of the second electrode of the second capacitor 204 when the potential V _H is supplied to the first electrode, the potential difference Vc ₂ is maintained at a height that is added to the potential V _H. Here, since the potential difference Vc ₂ = the power supply potential VSS−the power supply potential _VL , the potential of the second electrode of the second capacitor 204 is V _H + VSS− _VL . Therefore, the gate voltage of the n-channel transistor 212 becomes _VH - _VL , and is turned on when _VH - _VL > _VTHn .

Therefore, when the potential of the input signal IN is V _H, it is supplied to the subsequent circuit power supply potential VSS as the potential of the output signal.

Next, an operation in the case where the potential of the input signal IN is on the low potential side (V _{L in} this embodiment) is described with reference to FIG.

As described above, in the normal operation, the switches 206, 207, 209, and 210 are off, and the switches 205 and 208 are on. The potential _{VL of the} input signal is supplied to the first electrode of the first capacitor 203 and the first electrode of the second capacitor 204 via the switches 205 and 208.

The potential difference between the two electrodes of each of the first capacitor 203 and the second capacitor 204 is always constant in accordance with the law of conservation of electric charge. The potential of the second electrode of the first capacitor 203 when the potential V _L is supplied to the first electrode, the potential difference Vc ₁ is maintained at a height that is added to the potential V _L. Here, since the potential difference Vc ₁ = power supply potential VDD−power supply potential V _H , the potential of the second electrode of the first capacitor 203 becomes _VL + VDD−V _H. Therefore, the gate voltage of the p-channel transistor 211 becomes _VL - _VH , and is turned on when _VL - _VH < _VTHp .

On the other hand, the potential of the second electrode of the second capacitor 204, the potential V _L to the first electrode is applied, a potential difference Vc ₂ is maintained at a height that is added to the potential V _L. Here, since the potential difference Vc ₂ = power supply potential VSS−power supply potential _VL , the potential of the second electrode of the second capacitor 204 is VSS. The potential VSS of the second electrode is applied to the gate of the n-channel transistor 212, and the n-channel transistor 212 is turned off because the gate voltage becomes 0.

Therefore, when the potential of the input signal IN is _VL , the power supply potential VDD is supplied to the subsequent circuit as the potential of the output signal.

According to the present invention, the potential difference V _C1 and V _C2 can be simultaneously obtained regardless of the potential of the input signal.

Note that in this embodiment, the supply of the power supply potential VSS or VDD to the second electrode of the capacitor is controlled by the switch 207 or 210; however, the present invention is not limited to this structure. The supply of the power supply potential V _H ′ different from the power supply potential VDD to the second electrode of the first capacitor 203 may be controlled by the switch 207. Further, the supply of the power supply potential V _L ′ different from the power supply potential VSS to the second electrode of the second capacitor 204 may be controlled by the switch 210. In this case, the high potential side of the V _H of an input signal 'when', a low potential side potential V _L 'and', and _{V H '' + V L '} -V L -VSS> V THn, also V _L '' + V _H 'and -V _H -VDD <V _{THp. Further, V L '' + V L} ' is preferably a -V _L -VSS ≦ V _THn, also V _H' '+ V _H' is desirably -V _H -VDD ≧ V _THp.

Note that when the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switch 207 or 210, compared to the case where a potential _VL 'or _VH ' different from the power supply potential VSS or VDD is supplied. In addition, the number of wirings for supplying a power supply potential can be reduced.

(Embodiment 2)
In this embodiment, a structure of an inverter which is one of the digital circuits of the present invention, which is different from that in Embodiment 1, will be described.

  FIG. 5 shows a configuration of the inverter according to the present embodiment. Reference numeral 301 denotes a correction unit, and reference numeral 302 denotes a circuit element group.

  The correction means 301 includes a first capacitor 303, a second capacitor 304, a switch 305 for controlling the supply of the power supply potential VDD to the first capacitor 303, and a switch 305 for controlling the second capacitor 304. A switch 306 for controlling the supply of the power supply potential VSS.

  Note that although this embodiment mode shows the mode in which the power supply potential VDD is supplied to the second electrode included in the first capacitor 303 by the switch 305, the present invention is not limited to this. The potential supplied to the second electrode included in the first capacitor 303 may be a potential other than the power supply potential VDD, and the supplied potential may be adjusted as appropriate in accordance with the potential of the input signal. . Similarly, the power supply potential VSS is supplied to the second electrode of the second capacitor 304 by the switch 306; however, the present invention is not limited to this. The potential supplied to the second electrode included in the second capacitor 304 may be a potential other than the power supply potential VSS, and the potential to be supplied may be appropriately adjusted in accordance with the potential of an input signal. .

The circuit element group 302 includes one p-channel transistor 311 and one n-channel transistor 312. A power supply potential VDD is supplied to a first terminal (here, a source) of the p-channel transistor 311, and a power supply potential VSS is supplied to a first terminal (here, a source) of the n-channel transistor 312. I have. A second terminal (here, drain) of the p-channel transistor 311 and a second terminal (here, drain) of the n-channel transistor 312 are connected to each other, and the potential of the second terminal of these two transistors is used. Is supplied to a subsequent circuit as the potential of the output signal OUT. Note that VDD> VSS. Also, if VSS is connected to the n-channel transistor 312 and the switch 306, the high potential side of the V _H of the input signal, when the low potential side potential was set to V _L, V _H -V _L > V _THn , _VL− V _H <V _THp .

  The second electrode of the first capacitor 303 is connected to the gate of the p-channel transistor 311, and the second electrode of the second capacitor 304 is connected to the gate of the n-channel transistor 312. I have.

  Next, the operation of the inverter shown in FIG. 5 will be described with reference to FIG. The operation of the inverter shown in FIG. 6 is also classified into an operation of storing the potential difference to be corrected and a normal operation of performing the original function of the digital circuit. However, in the inverter of this embodiment, the supply of the power supply potential to each capacitor is not performed simultaneously by the first capacitor and the second capacitor, but is performed sequentially.

First, an operation of storing a potential difference in the first capacitor 303 will be described with reference to FIG. As illustrated in FIG. 6A, the switch 305 is turned on and the switch 306 is turned off, so that the high potential side V _H of the input signal IN is supplied to the first electrode of the first capacitor 303. With the above structure, electric charge is accumulated in the first capacitor 303 by the potential V _H of the input signal IN and the power supply potential VDD. Then, the switch 305 is turned off, the electric charge accumulated in the first capacitor 303 is held, and the potential difference (referred to as Vc ₁ ) between the power supply potential VDD and the potential V _H on the high potential side of the input signal is reduced. It is memorized.

Next, an operation of storing a potential difference in the second capacitor 304 is described with reference to FIG. In FIG. 6B, the switch 305 is turned off and the switch 306 is turned on, so that the low potential side potential _VL of the input signal IN is supplied to the first electrode of the second capacitor 304. With the above structure, charge is accumulated in the second capacitor 304 by the potential _VL of the input signal IN and the power supply potential VSS. Then, the switch 306 is turned off, the electric charge accumulated in the second capacitor 304 is held, and the potential difference between the power supply potential VSS and the potential _VL on the low potential side of the input signal (hereinafter referred to as Vc ₂ ) is obtained. It is memorized.

  Note that charge accumulation in the first capacitor 303 and the second capacitor 304 may be performed first.

  Next, the correction of the potential of the input signal based on the stored potential difference and the normal operation performed based on the corrected potential will be described. As shown in FIG. 6C, in the case of the normal operation, the switches 305 and 306 are always turned off.

The potential difference between the two electrodes of each of the first capacitor 303 and the second capacitor 304 is always constant in accordance with the law of conservation of electric charge. Therefore, when the potential V _H is applied to the first electrode, the potential of the second electrode of the first capacitor 303 is kept at the height obtained by adding the potential difference Vc ₁ to the potential V _H. Here, since the potential difference Vc ₁ = power supply potential VDD−potential V _H on the higher potential side of the input signal, the potential of the second electrode of the first capacitor 303 is VDD. The potential VDD of the second electrode is supplied to the gate of the p-channel transistor 311. Since the gate voltage of the p-channel transistor 311 becomes 0, the p-channel transistor 311 is turned off.

On the other hand, the potential of the second electrode of the second capacitor 304 when the potential V _H is supplied to the first electrode, the potential difference Vc ₂ is maintained at a height that is added to the potential V _H. Here, since the potential difference Vc ₂ = the power supply potential VSS−the potential _VL on the low potential side of the input signal, the potential of the second electrode of the second capacitor 304 is V _H + VSS− _VL . Therefore, the n-channel transistor 312 is turned on because the gate voltage becomes _VH - _VL and _VH - _VL > _VTHn .

Therefore, when the potential of the input signal IN is V _H, it is supplied to the subsequent circuit power supply potential VSS as the potential of the output signal.

If the potential of the input signal IN is at the potential V _L on the low potential side, the potential V _L of the input signal applied to the first electrode of the first electrode, the second capacitor 304 of the first capacitor 303 Can be

The potential difference between the two electrodes of each of the first capacitor 303 and the second capacitor 304 is always constant in accordance with the law of conservation of electric charge. The potential of the second electrode of the first capacitor 303 when the potential V _L is supplied to the first electrode, the potential difference Vc ₁ is maintained at a height that is added to the potential V _L. Here, since the potential difference Vc _{1 is} equal to the power supply potential VDD−the potential V _H on the high potential side of the input signal, the potential of the second electrode of the first capacitor 303 is V _L + VDD−V _H. Therefore, the p-channel transistor 311 is turned on because the gate voltage becomes _VL - _VH and _VL - _VH < _VTHp .

On the other hand, the potential of the second electrode of the second capacitor 304, the potential V _L to the first electrode is applied, a potential difference Vc ₂ is maintained at a height that is added to the potential V _L. Here, since the potential difference Vc ₂ = the power supply potential VSS−the potential _VL on the low potential side of the input signal, the potential of the second electrode of the second capacitor 304 is VSS. The potential VSS of the second electrode is applied to the gate of the n-channel transistor 312, and the n-channel transistor 312 is turned off because the gate voltage becomes 0.

Therefore, when the potential of the input signal IN is _VL , the power supply potential VDD is supplied to the subsequent circuit as the potential of the output signal.

  According to the present invention, with the above structure, a digital circuit can operate normally regardless of the potential of an input signal. Further, the number of switches used for the correction means can be reduced as compared with the digital circuit shown in FIG. 2, and the effect of the present invention can be obtained with a simpler configuration.

Note that in this embodiment, the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switch 305 or 306; however, the present invention is not limited to this structure. The supply of the power supply potential V _H ′ different from the power supply potential VDD to the second electrode of the first capacitor 303 may be controlled by the switch 305. Further, supply of a power supply potential V _L ′ different from the power supply potential VSS to the second electrode of the second capacitor 304 may be controlled by the switch 306. In this case, V _H + V _L 'and -V _L -VSS> V _THn, also V _L + V _H' and -V _H -VDD <V _THp. Further, V _L 'is preferably a -VSS ≦ V _THn, also V _H' is desirably -VDD ≧ V _THp.

Note that the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switch 305 or 306, as compared to the case where a potential _VL 'or _VH ' different from the power supply potential VSS or VDD is supplied. In addition, the number of wirings for supplying a power supply potential can be reduced.

Conversely, when the potential _VL 'or _VH ' different from the power supply potential VSS or VDD is supplied, the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switch 305 or 306. Thus, the potential difference stored in each capacitor can be appropriately set in accordance with the threshold values of the p-channel transistor 311 and the n-channel transistor 312. In this embodiment mode, the operation has been described assuming that the threshold voltages of the p-channel transistor 311 and the n-channel transistor 312 included in the circuit element group 302 are 0. However, in an actual circuit, the threshold value is 0. Not always. In this case, for example, _assuming that the threshold voltage of the p-channel transistor 311 is V _THp , V _H ′ is higher than the potential V _H on the high potential side of the input signal during normal operation by | V _THp | minutes or more. It is desirable to set. Further, for example, when the threshold voltage of the n-channel transistor 312 is V _THn , the _VL is set to be lower than the potential _VL on the low potential side of the input signal during normal operation by | V _THn | minutes or more. desirable. With the above structure, the input signal can be corrected in accordance with the threshold value of each transistor, and the operation of the digital circuit can be made more reliable.

(Embodiment 3)
In this embodiment, a configuration of a NAND which is one of digital circuits of the present invention will be described.

  The NAND of the present embodiment illustrated in FIG. 7 includes a first correction unit 401, a second correction unit 402, and a circuit element group 403.

  The first correction unit 401 includes a first capacitance element 404, a second capacitance element 405, a switch 406 for controlling supply of a power supply potential VDD to the first capacitance element 404, and a second capacitance element. And a switch 407 for controlling the supply of the power supply potential VSS to the switch 405.

  The second correction unit 402 includes a third capacitor 411, a fourth capacitor 412, a switch 413 that controls supply of a power supply potential VDD to the third capacitor 411, A switch 414 for controlling the supply of the power supply potential VSS to the element 412.

  The circuit element group 403 includes two p-channel transistors 420 and 421 and two n-channel transistors 422 and 423. A power supply potential VDD is supplied to a first terminal (here, a source) of the p-channel transistor 420 and a first terminal (here, a source) of the p-channel transistor 421. The second terminal (here, the drain) of the p-channel transistor 420 and the second terminal (here, the drain) of the p-channel transistor 421 are connected to each other. Further, a power supply potential VSS is supplied to a first terminal (here, a source) of the n-channel transistor 422. Further, a first terminal (here, source) of the n-channel transistor 423 is connected to a second terminal (here, drain) of the n-channel transistor 422. The second terminal (here, the drain) of the n-channel transistor 423 is connected to the second terminals of the p-channel transistors 420 and 421. Note that the potential of the second terminal of the n-channel transistor 423 and the potential of the second terminal of the p-channel transistors 420 and 421 are supplied to a subsequent circuit as the potential of the output signal OUT.

  The second electrode of the first capacitor 404 is connected to the gate of the p-channel transistor 420. The second electrode of the second capacitor 405 is connected to the gate of the n-channel transistor 422. The second electrode of the third capacitor 411 is connected to the gate of the p-channel transistor 421. The second electrode of the fourth capacitor 412 is connected to the gate of the n-channel transistor 423.

A first electrode of the first capacitor 404, a first electrode of the second capacitor 405, the potential of the input signal IN ₁ is inputted. Further, a first electrode of the third capacitor 411, the first electrode of the fourth capacitor element 412, the potential of the input signal IN ₂ is input.

Note that VDD> VSS. The potential on the high potential side of the input signal is V _H , the potential on the low potential side is V _L , the threshold voltages of the p-channel transistors ₄₂₀ and 421 are V _THp, and the threshold voltages of the n-channel transistors 422 and 423 are V when the _{THn, V H -V L> V} THn, made to be V _L -V _H <V _THp.

  The operation of the NAND shown in FIG. 7 is also classified into an operation of storing a potential difference to be corrected and a normal operation of performing the original function of the digital circuit. However, in the NAND of this embodiment, the supply of the power supply potential to each capacitor is not performed simultaneously by the first capacitor 404 and the second capacitor 405, but is performed sequentially, and the third capacitor 411 is supplied. And the fourth capacitor 412 are performed not sequentially but simultaneously.

When the potential difference is stored in the first capacitor 404, the switch 406 is turned on and the switch 407 is turned off, and the high potential V _H of the input signal IN _{1 is} applied to the first electrode of the first capacitor 404. give. Then, after the charge is sufficiently accumulated, the switch 406 is turned off, and the charge accumulated in the first capacitor 404 is held. When the potential difference is stored in the second capacitor 405, the switch 407 is turned on and the switch 406 is turned off, and the potential V on the low potential side of the input signal IN _{1 is} applied to the first electrode of the second capacitor 405. Give _L. Then, after the charges are sufficiently accumulated, the switch 407 is turned off, and the charges accumulated in the second capacitor 405 are held.

When storing a potential difference into the third capacitor 411, turning on the switch 413 and turning OFF the switch 414, the third first electrode to the high potential side of the input signal IN ₂ potential V _H of the capacitor 411 give. After the charge is sufficiently accumulated, the switch 413 is turned off, and the charge accumulated in the third capacitor 411 is held. Also, when storing a potential difference in the fourth capacitive element 412, turns on the switch 414 and turning OFF the switch 413, the potential of the first low-potential side of the input to the electrode signal IN ₂ of the fourth capacitor element 412 V Give _L. Then, after the charge is sufficiently accumulated, the switch 414 is turned off, and the charge accumulated in the fourth capacitor 412 is held.

  Then, during normal operation, the potential of the input signal is corrected based on the stored potential difference. During normal operation, the switches 406, 407, 413, and 414 are always off.

  According to the present invention, with the above structure, a digital circuit can operate normally regardless of the potential of an input signal.

Note that in this embodiment, the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switches 406, 407, 413, and 414; however, the present invention is not limited to this structure. The supply of the power supply potential V _H1 ′ different from the power supply potential VDD to the second electrode of the first capacitor 404 may be controlled by the switch 406. Further, supply of the power supply potential V _L1 ′ different from the power supply potential VSS to the second electrode of the second capacitor 405 may be controlled by the switch 407. In this case, V _H + V _L1 'and -V _L -VSS> V _THn, also V _L + V _H1' and -V _H -VDD <V _THp. Furthermore, it is desirable that V _L1 ′ −VSS ≦ V _THn , and it is desirable that V _H1 ′ −VDD ≧ V _THp .

The supply of the power supply potential V _H2 ′ different from the power supply potential VDD to the second electrode of the third capacitor 411 may be controlled by the switch 413. Further, supply of a power supply potential V _L2 ′ different from the power supply potential VSS to the second electrode of the fourth capacitor 412 may be controlled by the switch 414. In this case, V _H + V _L2 'and -V _L -VSS> V _THn, also V _L + V _H2' and -V _H -VDD <V _THp. Furthermore, it is desirable that V _L2 ′ −VSS ≦ V _THn and that V _H2 ′ −VDD ≧ V _THp is desirable.

  Note that when the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switches 406, 407, 413, and 414, the power supply potential is different from the case where a potential different from the power supply potential VSS or VDD is supplied. Can be reduced in the number of wirings for supplying the power.

On the other hand, when a potential different from the power supply potential VSS or VDD is supplied, each of the switches 406, 407, 413, and 414 controls the supply of the power supply potential VSS or VDD to the second electrode. The potential difference stored in the capacitor can be set as appropriate in accordance with the threshold value of each of the transistors 420 to 423. For example, assuming that the threshold voltages of the p-channel transistors 420 and ₄₂₁ are V _THp , V _H1 ′ or V _H2 ′ is higher than the potential V _H on the high potential side of the input signal during normal operation by | V _THp | minutes or more. It is desirable to set so that For example, if the threshold voltage of the n-channel transistors 421 and 423 is V _THn , V _L1 ′ or V _L2 ′ is lower than the potential V _L on the low potential side of the input signal during normal operation by | V _THn | It is desirable to set so that With the above structure, the input signal can be corrected in accordance with the threshold value of each transistor, and the operation of the digital circuit can be made more reliable.

  Note that in this embodiment, the case where the second structure illustrated in FIG. 1C is used as in FIG. 5 is described; however, the first structure illustrated in FIG. You can also.

  Further, although the case of the NAND is described in this embodiment, the present invention can be similarly applied to various logic circuits such as a NOR and a transmission gate.

(Embodiment 4)
In this embodiment, a configuration of a clocked inverter which is one of digital circuits of the present invention will be described.

  The clocked inverter of this embodiment illustrated in FIG. 8A includes a correction unit 501 and a circuit element group 502.

  The correction means 501 includes a first capacitor 503, a second capacitor 504, a switch 505 for controlling the supply of the power supply potential VDD to the first capacitor 503, and a switch 505 for the second capacitor 504. A switch 506 for controlling the supply of the power supply potential VSS.

  The circuit element group 502 includes two p-channel transistors 520 and 521 and two n-channel transistors 522 and 523. A power supply potential VDD is supplied to a first terminal (here, a source) of the p-channel transistor 520. The second terminal (here, the drain) of the p-channel transistor 520 and the first terminal (here, the source) of the p-channel transistor 521 are connected to each other. In addition, a power supply potential VSS is supplied to a first terminal (here, a source) of the n-channel transistor 523. A first terminal (here, source) of the n-channel transistor 522 is connected to a second terminal (here, drain) of the n-channel transistor 523. The second terminal (here, the drain) of the n-channel transistor 522 is connected to the second terminal (here, the drain) of the p-channel transistor 521. Note that the potential of the second terminal of the n-channel transistor 522 and the potential of the second terminal of the p-channel transistor 521 are supplied to a subsequent circuit as the potential of the output signal OUT.

  The second electrode of the first capacitor 503 is connected to the gate of the p-channel transistor 520. The second electrode of the second capacitor 504 is connected to the gate of the n-channel transistor 523.

  The potential of the input signal IN is input to the first electrode of the first capacitor 503 and the first electrode of the second capacitor 504. Then, the clock signal CK is input to the gate of the p-channel transistor 521, and the inverted clock signal CKb corresponding to the inverted signal of the clock signal is input to the gate of the n-channel transistor 522.

Note that VDD> VSS. Further, when the potential on the high potential side of the input signal is V _H , the potential on the low potential side is V _L , the threshold voltage of the p-channel transistor 520 is V _THp, and the threshold voltage of the n-channel transistor 523 is V _{THn. a, V H -V L> V THn} , made to be V _L -V _H <V _THp.

  Similarly to the first to third embodiments, the operation of the clocked inverter shown in FIG. 8A is divided into an operation of storing a potential difference to be corrected and a normal operation of performing the original function of the digital circuit. You. However, in the clocked inverter of this embodiment, the supply of the power supply potential to each capacitor is not performed simultaneously by the first capacitor 503 and the second capacitor 504, but is performed sequentially.

When the potential difference is stored in the first capacitor 503, the switch 505 is turned on and the switch 506 is turned off, so that the high potential V _H of the input signal IN is supplied to the first electrode of the first capacitor 503. . After the charge is sufficiently accumulated, the switch 505 is turned off, and the charge accumulated in the first capacitor 503 is held. When the potential difference is stored in the second capacitor 504, the switch 506 is turned on and the switch 505 is turned off, and the potential V _L on the low potential side of the input signal IN is applied to the first electrode of the second capacitor 504. give. After the charge is sufficiently accumulated, the switch 506 is turned off, and the charge accumulated in the second capacitor 504 is held.

  Then, during normal operation, the potential of the input signal is corrected based on the stored potential difference. During normal operation, the switches 505 and 506 are always turned off.

  According to the present invention, with the above structure, a digital circuit can operate normally regardless of the potential of an input signal.

  Note that the connection between the p-channel transistor 521 and the p-channel transistor 520 is not necessarily limited to the structure illustrated in FIG. For example, the p-channel transistor 521 may be connected so that supply of the power supply potential VDD to the source of the p-channel transistor 520 is controlled.

  Similarly, the connection between the n-channel transistor 522 and the n-channel transistor 523 is not necessarily limited to the structure illustrated in FIG. For example, the n-channel transistor 522 may be connected so that supply of the power supply potential VSS to the source of the n-channel transistor 523 is controlled.

  Next, a clocked inverter having a structure different from that in FIG. The clocked inverter of this embodiment illustrated in FIG. 8B is different from the clocked inverter illustrated in FIG. 8A in the connection configuration of the correction unit 501 and the circuit element group 502.

  Specifically, the clock signal CK is applied to the first electrode of the first capacitor 503, and the inverted clock signal CKb corresponding to the inverted signal of the clock signal is applied to the first electrode of the second capacitor 504. Is entered. The potential of the input signal IN is input to the gate of the p-channel transistor 541 and the gate of the n-channel transistor 542.

  Then, as in the case of FIG. 8A, the operation is distinguished into an operation of storing a potential difference to be corrected and a normal operation of performing the original function of the digital circuit. However, in the clocked inverter of this embodiment, the supply of the power supply potential to each capacitor may be performed sequentially or simultaneously.

When the potential difference is stored in the first capacitor 503, the switch 505 is turned on and the switch 506 is turned off, and the high potential V _H of the clock signal CK is applied to the first electrode of the first capacitor 503. . After the charge is sufficiently accumulated, the switch 505 is turned off, and the charge accumulated in the first capacitor 503 is held. Also, when storing a potential difference into the second capacitor 504, turning on the switch 506 and turning OFF the switch 505, the low potential side V _L of the inverted clock signal CKb to the first electrode of the second capacitor 504 Apply potential. After the charge is sufficiently accumulated, the switch 506 is turned off, and the charge accumulated in the second capacitor 504 is held.

  Then, during normal operation, the potential of the input signal is corrected based on the stored potential difference. During normal operation, the switches 505 and 506 are always turned off.

  According to the present invention, with the above structure, a digital circuit can operate normally regardless of the potential of an input signal.

Note that in this embodiment mode, the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switches 505 and 506; however, the present invention is not limited to this structure. The supply of the power supply potential V _H ′ different from the power supply potential VDD to the second electrode of the first capacitor 503 may be controlled by the switch 505. Further, supply of a power supply potential V _L ′ different from the power supply potential VSS to the second electrode of the second capacitor 504 may be controlled by the switch 506. In this case, V _H + V _L 'and -V _L -VSS> V _THn, also V _L + V _H' and -V _H -VDD <V _THp. Further, V _L 'is preferably a -VSS ≦ V _THn, also V _H' is desirably -VDD ≧ V _THp.

  Note that when the supply of the power supply potential VSS or VDD to the second electrode is controlled by the switches 505 and 506, the power supply potential is supplied as compared with the case where a power supply potential different from the power supply potential VSS or VDD is supplied. Can be reduced.

Conversely, when a potential different from the power supply potential VSS or VDD is supplied, storage in each capacitor element is smaller than when supply of the power supply potential VSS or VDD to the second electrode is controlled by the switches 505 and 506. The potential difference to be set can be appropriately set in accordance with the threshold values of the transistors 540 and 543. For example, _assuming that the threshold voltage of the p-channel transistor 540 is V _THp , V _H ′ is set to be higher than the potential V _H on the high potential side of the input signal during normal operation by | V _THp | minutes or more. desirable. Further, for example, when the threshold voltage of the n-channel transistor 543 is V _THn , V _L ′ is set to be lower than the potential V _L on the low potential side of the input signal during normal operation by | V _THn | or more. Is desirable. With the above structure, the input signal can be corrected in accordance with the threshold value of each transistor, and the operation of the digital circuit can be made more reliable.

  Note that FIG. 8A and FIG. 8B may be combined.

  In the present invention, there is no limitation on a kind of a transistor which can be applied, and the transistor is formed using a thin film transistor (TFT) using a non-single-crystal semiconductor film represented by amorphous silicon or polycrystalline silicon, a semiconductor substrate, or an SOI substrate. MOS transistors, junction transistors, bipolar transistors, transistors using organic semiconductors and carbon nanotubes, and other transistors can be used. There is no limitation on the type of substrate on which the transistor is provided, and the transistor can be provided over a single crystal substrate, an SOI substrate, a glass substrate, or the like.

  The transistor used in the digital circuit of the present invention may be a transistor formed using single crystal silicon, a transistor using SOI, polycrystalline silicon, semi-amorphous silicon Silicon) or a thin film transistor using amorphous silicon. Further, a transistor using an organic semiconductor or a transistor using a carbon nanotube may be used.

  Note that in this embodiment, the case where the second structure illustrated in FIG. 1C is used as in FIG. 5 is described; however, the first structure illustrated in FIG. You can also.

(Embodiment 5)
In this embodiment, in the inverter of the present invention illustrated in FIG. 2, the potential supplied to the second electrode included in the first capacitor 203 is set to a potential other than the power supply potential VDD, and the second capacitor A mode in which the potential supplied to the second electrode included in the element 204 is set to a potential other than the power supply potential VSS is described.

FIG. 16A illustrates a configuration of the inverter of this embodiment. Those already shown in FIG. 2 are denoted by the same reference numerals. In FIG. 16A, charge of the threshold voltage of the p-channel transistor 211 is accumulated in the first capacitor 203, and the charge of the threshold voltage of the n-channel transistor 212 is stored in the second capacitor 204. The value of each power supply voltage is optimized so that charges are accumulated. In this embodiment mode, the potential supplied to the first electrode of the first capacitor 203 by the switch 206 is VDD, and the potential supplied to the second electrode of the first capacitor 203 by the switch 207 is VDD. − | V _THp |. The potential supplied to the first electrode of the second capacitor 204 by the switch 209 is VSS, and the potential supplied to the second electrode of the second capacitor 204 by the switch 210 is VSS + | V _THn | And

  The operation of the inverter illustrated in FIG. 16A is described with reference to FIGS. 16B to 16D.

  First, charge is accumulated in the first capacitor 203 and the second capacitor 204. In this embodiment mode, the potential of the second electrode of the first capacitor 203 and the potential of the source of the p-channel transistor 211 can be individually controlled. The source potential of the n-channel transistor 212 can be controlled individually. Therefore, charge accumulation in the first capacitor 203 and the second capacitor 204 can be performed in parallel.

  First, as shown in FIG. 16B, by turning on the switches 206, 207, 209, and 210 and turning off the switches 205 and 208, the threshold voltage of the p-channel transistor 211 is stored in the first capacitor 203. Then, the threshold voltage of the n-channel transistor 212 is stored in the second capacitor 204. Then, by turning off the switches 206, 207, 209, and 210, the accumulated charge is held in the first capacitor 203 and the second capacitor 204.

  Next, the correction of the potential of the input signal based on the stored potential difference and the normal operation performed based on the corrected potential will be described.

  A case where the potential of the input signal IN is the same as the power supply potential VDD is described with reference to FIG. In a normal operation, the switches 206, 207, 209, and 210 are always off, and the switches 205 and 208 are on. The potential of the input signal is supplied to the first electrode of the first capacitor 203 and the first electrode of the second capacitor 204 via the switches 205 and 208.

Since the first capacitor 203 holds the threshold voltage − | V _THp |, the potential of the second electrode of the first capacitor 203 becomes VDD− | V _THp |. Therefore, the p-channel transistor 211 is turned off because its gate voltage V _GSp = − | V _THp |.

On the other hand, since the threshold voltage | V _THn | is held in the second capacitor 204, the potential of the second electrode of the second capacitor 204 is VDD + | V _THn |. Therefore, the n-channel transistor 212 is turned on because its gate voltage V _GSn = VDD−VSS + | V _THn |> | V _THn |.

  Therefore, when the potential of the input signal IN is VDD, the power supply potential VSS is supplied to the subsequent circuit as the potential of the output signal.

  A case where the potential of the input signal IN is the same as the power supply potential VSS is described with reference to FIG. As in the case of FIG. 16C, in a normal operation, the switches 206, 207, 209, and 210 are off, and the switches 205 and 208 are on. The potential of the input signal is supplied to the first electrode of the first capacitor 203 and the first electrode of the second capacitor 204 via the switches 205 and 208.

Since the first capacitor 203 holds the threshold voltage − | V _THp |, the potential of the second electrode of the first capacitor 203 is VSS− | V _THp |. Therefore, the p-channel transistor 211 is turned on because its gate voltage V _GSp = VSS−VDD− | V _THp | <− | V _THp |.

On the other hand, since the second capacitor 204 holds the threshold voltage | V _THn |, the potential of the second electrode of the second capacitor 204 becomes VSS + | V _THn |. Therefore, the n-channel transistor 212 turns off because its gate voltage V _GSn = | V _THn |.

  Therefore, when the potential of the input signal IN is VSS, the power supply potential VDD is supplied to the subsequent circuit as the potential of the output signal.

  In this embodiment, the operation speed of the transistor can be improved even when the power supply potential is not sufficiently higher than the absolute value of the threshold voltage of the transistor; therefore, power consumption of the digital circuit can be reduced. .

(Embodiment 6)
In this embodiment, in the inverter of the present invention illustrated in FIG. 5, the potential supplied to the second electrode included in the first capacitor 303 is set to a potential other than the power supply potential VDD, and the second capacitor A mode in which the potential supplied to the second electrode included in the element 304 is set to a potential other than the power supply potential VSS is described.

FIG. 17A illustrates a configuration of the inverter of this embodiment. Those already shown in FIG. 5 are denoted by the same reference numerals. In FIG. 17A, charge corresponding to the threshold voltage of the p-channel transistor 311 is accumulated in the first capacitor 303, and the charge corresponding to the threshold voltage of the n-channel transistor 312 is stored in the second capacitor 304. The value of each power supply voltage is optimized so that charges are accumulated. In this embodiment mode, the potential supplied to the second electrode of the first capacitor 303 by the switch 305 is set to VDD− | V _THp |. The potential supplied to the second electrode of the second capacitor 304 by the switch 306 is set to VSS + | V _THn |.

  The operation of the inverter shown in FIG. 17A will be described with reference to FIGS. 17B to 17D.

  First, charge is accumulated in the first capacitor 303 and the second capacitor 304.

  First, as shown in FIG. 17B, the switch 305 is turned on and the switch 306 is turned off. Then, by inputting VDD as an input signal, the threshold voltage of the p-channel transistor 311 is stored in the first capacitor 303. When the switch 305 is turned off, the accumulated charge is held in the first capacitor 303.

  Next, as shown in FIG. 17C, the switch 306 is turned on and the switch 305 is turned off. Then, the threshold voltage of the n-channel transistor 312 is stored in the second capacitor 304 by inputting VSS as an input signal. When the switch 306 is turned off, the accumulated charge is held in the second capacitor 304.

  Next, the correction of the potential of the input signal based on the stored potential difference and the normal operation performed based on the corrected potential will be described.

  The case where the potential of the input signal IN is the same as the power supply potential VDD is described with reference to FIG. In a normal operation, the switches 305 and 306 are always off. The potential of the input signal is supplied to a first electrode of the first capacitor 303 and a first electrode of the second capacitor 304.

Since the first capacitor 303 holds the threshold voltage − | V _THp |, the potential of the second electrode of the first capacitor 303 is VDD− | V _THp |. Therefore, the p-channel transistor 311 is turned off because its gate voltage V _GSp = − | V _THp |.

On the other hand, since the threshold voltage | V _THn | is held in the second capacitor 304, the potential of the second electrode of the second capacitor 304 is VDD + | V _THn |. Therefore, the n-channel transistor 312 is turned on because its gate voltage V _GSn = VDD−VSS + | V _THn |> | V _THn |.

  Therefore, when the potential of the input signal IN is VDD, the power supply potential VSS is supplied to the subsequent circuit as the potential of the output signal.

  Next, a case where the potential of the input signal IN is the same as the power supply potential VSS will be described. As in the case of FIG. 17C, the switches 305 and 306 are off in a normal operation. The potential of the input signal is supplied to a first electrode of the first capacitor 303 and a first electrode of the second capacitor 304.

Since the first capacitor 303 holds the threshold voltage − | V _THp |, the potential of the second electrode of the first capacitor 303 is VSS− | V _THp |. Therefore, the p-channel transistor 311 is turned on because its gate voltage V _GSp = VSS−VDD− | V _THp | <− | V _THp |.

On the other hand, since the threshold voltage | V _THn | is held in the second capacitor 304, the potential of the second electrode of the second capacitor 304 is VSS + | V _THn |. Therefore, the n-channel transistor 312 is turned off because its gate voltage V _GSn = | V _THn |.

  Therefore, when the potential of the input signal IN is VSS, the power supply potential VDD is supplied to the subsequent circuit as the potential of the output signal.

  In this embodiment, the operation speed of the transistor can be improved even when the power supply potential is not sufficiently higher than the absolute value of the threshold voltage of the transistor; therefore, power consumption of the digital circuit can be reduced. .

  Hereinafter, examples of the present invention will be described.

(Example 1)
Example 1 In this example, a configuration and driving of a clocked inverter in the case where the clocked inverter of the present invention is used for a signal line driver circuit of a semiconductor display device will be described.

  FIG. 9A shows a circuit diagram of a clocked inverter used in this embodiment. The clocked inverter illustrated in FIG. 9A corresponds to one in which a transistor is used for a switch of the clocked inverter illustrated in FIG.

  Note that in this embodiment, the case where the second structure illustrated in FIG. 1C is used as in FIG. 5 is described; however, the first structure illustrated in FIG. You can also.

  The clocked inverter illustrated in FIG. 9A includes a first capacitor 601, a second capacitor 602, p-channel transistors 603, 607, and 608, and n-channel transistors 604, 609, and 610. are doing.

  The first electrode of the first capacitor 601 and the first electrode of the second capacitor 602 are connected to each other, and are supplied with the potential of the input signal IN. The second electrode of the first capacitor 601 is connected to the gate of the p-channel transistor 607. Further, the second electrode of the second capacitor 602 is connected to the gate of the n-channel transistor 610.

  A power supply potential VDD is supplied to a first terminal of the p-channel transistor 603, and a second terminal is connected to a second electrode of the first capacitor 601. A power supply potential VSS is applied to a first terminal of the n-channel transistor 604, and a second terminal is connected to a second electrode of the second capacitor 602.

  A power supply potential VDD is supplied to a first terminal (the source here) of the p-channel transistor 607. The second terminal (here, the drain) of the p-channel transistor 607 and the first terminal (here, the source) of the p-channel transistor 608 are connected to each other. A power supply potential VSS is supplied to a first terminal (the source here) of the n-channel transistor 610. A first terminal (here, source) of the n-channel transistor 609 is connected to a second terminal (here, drain) of the n-channel transistor 610. Then, a second terminal (here, drain) of the n-channel transistor 609 is connected to a second terminal (here, drain) of the p-channel transistor 608. Note that the potential of the second terminal of the n-channel transistor 609 and the potential of the second terminal of the p-channel transistor 608 are supplied to a subsequent circuit as the potential of the output signal OUT.

  FIG. 9B illustrates the potential of the input signal IN, the period during which charge is accumulated in the second capacitor 602, the period during which charge is accumulated in the first capacitor 601, and the period during which normal operation is performed. 4 shows a timing chart of the potential of the gate of the transistor 603 and the potential of the gate of the n-channel transistor 604.

As illustrated in FIG. 9B, in the period in which the charge is stored in the second capacitor 602, the gate of the p-channel transistor 603 is supplied with a potential higher than a potential obtained by adding a threshold voltage to the power supply potential VDD, and is turned off. It becomes. The gate of the n-channel transistor 604 is supplied with a potential higher than the potential obtained by adding the threshold voltage to the power supply potential VSS, and is turned on. Then, the potential of the input signal IN is maintained at the potential _VL on the low voltage side.

  Then, when the charge is sufficiently accumulated in the second capacitor 602, a potential lower than the threshold voltage from the power supply potential VSS is applied to the gate of the n-channel transistor 604 and the gate is turned off, and the charge is stored in the second capacitor 602. Is held.

Next, in a period during which charge is accumulated in the first capacitor 601, the gate of the p-channel transistor 603 is supplied with a potential lower than a potential obtained by adding a threshold voltage to the power supply potential VDD, and is turned on. In addition, the n-channel transistor 604 is turned off when a potential lower than the potential obtained by adding the threshold voltage to the power supply potential VSS is applied to the gate. Then, the potential of the input signal IN is kept at the potential V _H on the high voltage side.

  When sufficient charge is accumulated in the second capacitor 602, a potential higher than the sum of the power supply potential VSS and the threshold voltage is applied to the gate of the p-channel transistor 604, and the second capacitor 602 is turned off. A state in which the electric charge is held in 602 is obtained.

  Note that in FIG. 9B, charge accumulation in the second capacitor 602 is performed before accumulation of charge in the first capacitor 601; That is, after the charge is stored in the first capacitor 601, the charge may be stored in the second capacitor 602.

  Then, in the normal operation period, the gate of the p-channel transistor 603 is supplied with a potential higher than a potential obtained by adding the threshold voltage to the power supply potential VDD, and is turned off. The n-channel transistor 604 is turned off when a potential lower than a potential obtained by adding the threshold voltage to the power supply potential VSS is applied to the gate.

  FIG. 10 shows a configuration of a signal line driving circuit using the clocked inverter of this embodiment. The signal line driving circuit of this embodiment includes a shift register 1001, a latch A1002, and a latch B1003. The latch A1002 and the latch B1003 have a plurality of stages of latches, and the clocked inverter of this embodiment is used for each latch.

  Specifically, as shown in FIG. 10, the latch of each stage included in the latch A 1002 of this embodiment includes a clocked inverter 1004 of this embodiment, a normal clocked inverter 1005, and two inverters 1006 and 1007. Have.

  It is assumed that a signal having the same amplitude as the power supply is input to the normal clocked inverter 1005 and the two inverters 1006 and 1007. Therefore, a normal circuit may be used. However, it is assumed that a small amplitude signal is input to the video signal, that is, the input signal of the clocked inverter 1004. Therefore, it is necessary to use the circuit of the present invention as shown in FIGS.

  In the case of the clocked inverter of this embodiment, the video signal corresponds to the input signal IN, and one of the timing signal supplied from the shift register and the signal whose polarity is inverted is connected to the gate of the p-channel transistor 608. The other is input to the gate of the n-channel transistor 609. The period for accumulating charges may be provided during the period when the latch A is not operating. For example, it may be provided in a flyback period or a lighting period in a time gray scale (a period in which the driver is not moving).

  Alternatively, the timing of accumulating charges may be controlled using a signal (sampling pulse) output from the shift register 1001. That is, charge may be accumulated using sampling pulses several rows earlier.

  FIG. 11 is a top view of the clocked inverters 1004 and 1005. Since the configurations of the clocked inverters 1004 and 1005 are almost the same, the configuration of the clocked inverter 1004 will be described as an example. Note that the components already shown in FIG. 9A are denoted by the same reference numerals.

  Reference numeral 1101 denotes a wiring to which an input signal IN is input, and 1102 denotes a wiring to which an output signal OUT is output. Reference numeral 1103 denotes a wiring to which a potential supplied to the gate of the n-channel transistor 609 is supplied, and reference numeral 1104 denotes a wiring to which a potential supplied to the gate of the p-channel transistor 608 is supplied. Reference numeral 1105 denotes a wiring to which a potential supplied to the gate of the n-channel transistor 604 is supplied. Reference numeral 1106 denotes a wiring to which a potential supplied to the gate of the p-channel transistor 603 is supplied.

  Reference numeral 1120 denotes a wiring to which the power supply potential VSS is supplied, and reference numeral 1121 denotes a wiring to which the power supply potential VDD is supplied.

  FIG. 12A is a cross-sectional view taken along the line A-A ′ in FIG. 11, and FIG.

  The wiring 1200 and the wiring 1201 are both connected to a wiring 1106, and the wiring 1200 is connected to a second terminal of the p-channel transistor 603 through a wiring 1220.

  The p-channel transistor 608 included in the clocked inverter 1004 includes a channel formation region 1207, impurity regions 1206 and 1208 corresponding to a first terminal or a second terminal, a gate electrode 1202 corresponding to a gate, a channel formation region A gate insulating film 1224 provided between the gate electrode 1207 and the gate electrode 1202 is provided.

  The p-channel transistor 607 included in the clocked inverter 1004 includes a channel formation region 1209, impurity regions 1208 and 1210 corresponding to a first terminal or a second terminal, a gate electrode 1203 corresponding to a gate, and a channel formation region A gate insulating film 1224 provided between the gate electrode 1209 and the gate electrode 1203 is provided.

  The p-channel transistor 607 included in the clocked inverter 1005 includes a channel formation region 1211, impurity regions 1210 and 1212 corresponding to a first terminal or a second terminal, a gate electrode 1204 corresponding to a gate, and a channel formation region A gate insulating film 1224 provided between the gate electrode 1211 and the gate electrode 1204 is provided.

  A p-channel transistor 608 included in the clocked inverter 1005 includes a channel formation region 1213, impurity regions 1212 and 1214 corresponding to a first terminal or a second terminal, a gate electrode 1205 corresponding to a gate, a channel formation region A gate insulating film 1224 provided between the gate electrode 1213 and the gate electrode 1205 is provided.

  Note that the p-channel transistor 608 included in the clocked inverter 1004 and the p-channel transistor 607 included in the clocked inverter 1004 share an impurity region 1208. The impurity region 1208 corresponds to a source in the p-channel transistor 608 included in the clocked inverter 1004, and corresponds to a drain in the p-channel transistor 607 included in the clocked inverter 1004.

  Further, the p-channel transistor 608 included in the clocked inverter 1005 and the p-channel transistor 607 included in the clocked inverter 1005 share an impurity region 1212. The impurity region 1212 corresponds to a source in the p-channel transistor 608 included in the clocked inverter 1005, and corresponds to a drain in the p-channel transistor 607 included in the clocked inverter 1005.

  Further, the p-channel transistor 607 included in the clocked inverter 1004 and the p-channel transistor 607 included in the clocked inverter 1005 share an impurity region 1210. Impurity region 1210 corresponds to a source in both transistors.

  A wiring 1215 is connected to the impurity region 1206. Further, a wiring 1217 is connected to the impurity region 1214. The wiring 1215 is connected to the drain of the n-channel transistor 609 included in the clocked inverter 1004.

  A gate electrode 1203 of a p-channel transistor 607 included in the clocked inverter 1004 is connected to a second terminal of the p-channel transistor 603 through a wiring 1221.

  The wiring 1223 is connected to the impurity region 1225 included in the semiconductor film 1226 of the first capacitor 601. A capacitor formed by overlapping the semiconductor film 1226 and the gate electrode 1203 with the gate insulating film 1224 interposed therebetween and the capacitor formed by overlapping the gate electrode 1203 and the wiring 1223 with the interlayer insulating film 1230 interposed therebetween. Together with the capacitive element corresponds to the first capacitive element 601.

  Thus, the capacitance element is formed as a MOS capacitance. However, the MOS capacitor has a very small capacitance value depending on the vertical relationship of the potential between one electrode and the other electrode. Therefore, by arranging two capacitors in parallel and reversing their polarities, electrode directions, and the like, they operate as capacitors regardless of the vertical relationship of potential.

  Note that the capacitor is formed large. This is because the voltage is divided by the capacitor 601 and the gate capacitance of the transistor 607 even when the voltage of the input signal IN is applied. For example, if the capacitance of the capacitor 601 is equal to the gate capacitance of the transistor 607, only half of the amplitude of the input signal IN is applied to the gate of the transistor 607. Therefore, the capacitor 601 needs to be large. As a reference, it is preferable that the capacitor 601 be formed with a size five times as large as the gate capacitance of the transistor 607. Note that the same applies to the relationship between the capacitor 602 and the transistor 610.

Note that the clocked inverter which is one of the digital circuits of the present invention is not limited to the structure shown in FIG. For example, a clocked inverter included in a flip-flop circuit included in the shift register 1001 may be used.
Also in this case, the present invention may be applied to a portion where a signal having a small amplitude is input to the input signal. Therefore, since the amplitude of the clock signal and its inverted signal is small in the shift register, the clocked inverter in FIG. 8A may be used. In this case, the shift register does not operate during the blanking period of the input video signal, and therefore, it is sufficient to accumulate charges during the period.

  Note that the clocked inverter which is one of the digital circuits of the present invention is not limited to the structure shown in FIG.

(Example 2)
Any semiconductor device using the digital circuit of the present invention for a driver circuit is included in the scope of the present invention. FIG. 15 shows an external view of a semiconductor display device which is one of the semiconductor devices of the present invention. The semiconductor display device illustrated in FIG. 15 includes a pixel portion 1503 provided with a plurality of pixels, a scan line driver circuit 1501 for selecting a pixel, and a signal line driver circuit 1502 for supplying a video signal to the selected pixel. Have. Various signals and a power supply potential used for driving the pixel portion 1503, the signal line driver circuit 1502, or the scan line driver circuit 1501 are supplied through the FPC 1504.

The semiconductor display device of the present invention includes a liquid crystal display device, a light emitting device having a light emitting element typified by an organic light emitting element in each pixel, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), and a FED (Field Emission).
Display) and other display devices having a circuit element using a semiconductor film in a drive circuit.

  The semiconductor device included in the category of the present invention includes, in addition to the semiconductor display device, an arithmetic circuit including an adder, an ALU (Arithmetic Logic Unit), a counter, a multiplier, a shifter, and the like, a flip-flop, a multiport RAM, There is a semiconductor integrated circuit having one or a plurality of storage circuits including a FIFO (First In First Out) circuit and the like and a control circuit including a PLA (Programmable Logic Array) and the like.

(Example 3)
Electronic devices using the semiconductor device of the present invention include a video camera, a digital camera, a goggle-type display (head-mounted display), a navigation system, a sound reproducing device (car audio, an audio component, etc.), a notebook personal computer, a game device, A portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), an image reproducing apparatus having a recording medium (specifically, a recording medium such as a digital versatile disc (DVD) is reproduced, and the image is reproduced. Device with a display capable of displaying). FIG. 18 shows specific examples of these electronic devices.

  FIG. 18A illustrates a display device including a housing 2001, a display portion 2002, a speaker portion 2003, and the like. The semiconductor device of the present invention can be used for the display portion 2002. The display device includes all display devices for displaying information such as for personal computers, for receiving TV broadcasts, and for displaying advertisements. The semiconductor device of the present invention can be used for the display portion 2002 and other signal processing circuits. Note that in the case where a light-emitting device is used for a display device, a polarizing plate may be provided in order to prevent an image from appearing like a mirror surface due to reflection of external light on an electrode of the light-emitting element.

  FIG. 18B illustrates a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The digital still camera of the present invention is completed by using the semiconductor device of the present invention for the display portion 2102 or other signal processing circuits.

  FIG. 18C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The notebook personal computer of the present invention is completed by using the semiconductor device of the present invention for the display portion 2203 or other signal processing circuits.

  FIG. 18D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The mobile computer of the present invention is completed by using the semiconductor device of the present invention for the display portion 2302 or another signal processing circuit.

  FIG. 18E illustrates a portable image reproducing device (specifically, a DVD reproducing device) including a recording medium, which includes a main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, and a recording medium (such as a DVD). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. The display portion A 2403 mainly displays image information, and the display portion B 2404 mainly displays character information. Note that the image reproducing device provided with the recording medium includes a home game machine and the like. The image reproducing device of the present invention is completed by using the semiconductor device of the present invention for the display portions A2403 and B2404 or other signal processing circuits.

  FIG. 18F illustrates a goggle-type display (head-mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The goggle-type display of the present invention is completed by using the semiconductor device of the present invention for the display portion 2502 or other signal processing circuits.

  FIG. 18G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, a voice input portion 2608, operation keys 2609, and the like. . The video camera of the present invention is completed by using the semiconductor device of the present invention for the display portion 2602 or other signal processing circuits.

  Here, FIG. 18H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a sound input portion 2704, a sound output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. Note that the display portion 2703 displays white characters on a black background, so that current consumption of the mobile phone can be suppressed. The mobile phone of the present invention is completed by using the semiconductor device of the present invention for the display portion 2703 or another signal processing circuit.

  As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in all fields. Further, the electronic apparatus of this embodiment may use any of the configurations shown in the first to ninth embodiments.

FIG. 2 illustrates a configuration of a digital circuit of the present invention. FIG. 2 is a diagram showing a first configuration of an inverter which is one of the digital circuits of the present invention. FIG. 3 is a view showing the operation of the inverter shown in FIG. 2. FIG. 3 is a view showing the operation of the inverter shown in FIG. 2. FIG. 5 is a diagram showing a second configuration of an inverter which is one of the digital circuits of the present invention. FIG. 6 is a diagram showing the operation of the inverter shown in FIG. 5. FIG. 4 is a diagram showing a second configuration of a NAND which is one of the digital circuits of the present invention. FIG. 3 is a diagram showing a second configuration of a clocked inverter which is one of the digital circuits of the present invention. 8A and 8B are an equivalent circuit diagram and a timing chart of the clocked inverter illustrated in FIG. FIG. 10 illustrates a configuration of a signal line driver circuit using the clocked inverter illustrated in FIG. 9. 10A is a top view of the clocked inverter illustrated in FIG. Sectional drawing of FIG. The figure which shows the structure and operation | movement of a general inverter. The figure which shows a mode that an inverter malfunctions when the electric potential of an input signal is not in a desired height. 1 is an external view of a semiconductor display device of the present invention. The figure which shows the operation | movement of the inverter of this invention. The figure which shows the operation | movement of the inverter of this invention. FIG. 13 is a diagram of an electronic device using the semiconductor device of the present invention.

Claims (7)

Correction means, having one or more circuit elements,
The correction means has a first capacitance element, a second capacitance element, a first switch, and a second switch,
A first electrode of the first capacitor and a first electrode of the second capacitor are connected to an input terminal;
Supply of a first potential to a second electrode of the first capacitor is controlled by the first switch,
Supply of a second potential to a second electrode of the second capacitor is controlled by the second switch,
A semiconductor device, wherein a potential of a second electrode of the first capacitor and a potential of a second electrode of the second capacitor are supplied to the one or more circuit elements. Correction means, having one or more circuit elements,
The correction means has a first capacitance element, a second capacitance element, a first switch, and a second switch,
A first electrode of the first capacitor and a first electrode of the second capacitor are connected to an input terminal;
Supply of a first potential to a second electrode of the first capacitor is controlled by the first switch,
Supply of a second potential to a second electrode of the second capacitor is controlled by the second switch,
A potential of a second electrode of the first capacitor is supplied to a gate of a first transistor included in the one or more circuit elements;
A potential of a second electrode of the second capacitor is supplied to a gate of a second transistor included in the one or more circuit elements;
The first potential is supplied to a source of the first transistor,
The semiconductor device, wherein the second potential is supplied to a source of the second transistor. Correction means, having one or more circuit elements,
The correction means has a first capacitance element, a second capacitance element, and first to sixth switches,
The supply of the potential of the input terminal to the first electrode of the first capacitor is controlled by the first switch,
The supply of the potential of the input terminal to the first electrode of the second capacitor is controlled by the second switch,
Supply of a first potential to a second electrode of the first capacitor is controlled by the third switch,
The fourth switch controls supply of a second potential to a second electrode of the second capacitor,
The fifth switch controls the supply of a third potential to the first electrode of the first capacitor,
The sixth switch controls supply of a fourth potential to a first electrode of the second capacitor,
A semiconductor device, wherein a potential of a second electrode of the first capacitor and a potential of a second electrode of the second capacitor are supplied to the one or more circuit elements. Correction means, having one or more circuit elements,
The correction means has a first capacitance element, a second capacitance element, and first to sixth switches,
The supply of the potential of the input terminal to the first electrode of the first capacitor is controlled by the first switch,
The supply of the potential of the input terminal to the first electrode of the second capacitor is controlled by the second switch,
Supply of a first potential to a second electrode of the first capacitor is controlled by the third switch,
The fourth switch controls supply of a second potential to a second electrode of the second capacitor,
The fifth switch controls the supply of a third potential to the first electrode of the first capacitor,
The sixth switch controls supply of a fourth potential to a first electrode of the second capacitor,
A potential of a second electrode of the first capacitor is supplied to a gate of a first transistor included in the one or more circuit elements;
A potential of a second electrode of the second capacitor is supplied to a gate of a second transistor included in the one or more circuit elements;
The first potential is supplied to a source of the first transistor,
The semiconductor device, wherein the second potential is supplied to a source of the second transistor. The high potential side of the input signal is supplied to the first electrode of the first capacitor, and the first switch is turned on to apply the first potential to the second electrode of the first capacitor. After the supply, the first switch is turned off to hold the charge accumulated in the first capacitor,
A low potential side of the input signal is supplied to a first electrode of the second capacitor, and a second switch is turned on to apply a second potential to the second electrode of the second capacitor. After the supply, the second switch is turned off to hold the charge accumulated in the second capacitor,
With the first switch and the second switch turned off, the first electrode of the first capacitor and the first electrode of the second capacitor are connected to the high potential side or low potential of the input signal. A semiconductor device which supplies a potential on a potential side and supplies potentials of a second electrode of the first capacitor and a second electrode of the second capacitor to one or more circuit elements. Drive method. In claim 5,
The method for driving a semiconductor device, wherein the first potential is higher than a high potential side of the input signal, and the second potential is lower than a high potential side of the input signal. An electronic apparatus comprising the semiconductor device according to claim 1.

Images