KR101079760B1 - Shift resistor and method for driving same - Google Patents

Abstract

In the present invention, the input portion of the inverter is the threshold potential of the inverter, and the CK signal is amplified by inputting the CK signal through the capacitive means at the input portion of the inverter, and the amplified CK signal is used for the shift register. In other words, by obtaining the threshold potential of the inverter, it is possible to provide a shift register which hardly affects the variation in transistor characteristics.

Description

SHIFT RESISTOR AND METHOD FOR DRIVING SAME

The present invention relates to an active matrix display device which inputs a video signal and performs video display. The present invention also relates to a shift register for generating sampling pulses for sequentially sampling a video signal.

In recent years, active matrix display devices, such as liquid crystal display devices and light emitting devices, have been developed due to an increase in demand for portable devices. In particular, techniques for forming a pixel and a driving circuit (hereinafter referred to as an internal circuit) integrally by using a transistor formed of a polycrystalline semiconductor (polysilicon) on an insulator have been actively developed. The internal circuit has a source signal line driver circuit, a gate signal line driver circuit, and the like, and controls pixels arranged in a matrix.

In addition, the internal circuit is connected to a control IC or the like (hereinafter referred to as an external circuit) via a flexible printed circuit board (FPC) or the like, and its operation is controlled.

In general, since the IC used for the external circuit is a single crystal, it operates at a voltage lower than the power supply voltage of the internal circuit. In the present state, the external circuit usually operates at a power supply voltage of 3.3V, while the internal circuit operates at a power supply voltage of about 10V. Therefore, in order to operate the shift register of the internal circuit with the clock (hereinafter referred to as CK) signal of the external circuit, it is necessary to amplify the CK signal to the same voltage as the power supply voltage of the internal circuit with a level shifter.

When amplifying the CK signal with an external circuit, problems such as an increase in components such as a level shifter IC and a power supply IC, and an increase in power consumption occur. In the internal circuit, if a level shifter for amplifying the CK signal is provided at the input portion of the FPC and supplied to the front end of the shift register, problems such as an increase in layout area, an increase in power consumption, and difficulty in high frequency operation are caused.

For this reason, a shift register that operates with a low voltage CK signal has been proposed. It is mentioned that the shift register of the present invention can operate sufficiently with a low power supply voltage and a low voltage input signal by providing a differential amplification type data transmission section (see Japanese Patent Laid-Open No. 11-184432, for example).

In the shift register including the differential amplifier type data transfer section, the shift register may malfunction when the transistor characteristics constituting the differential amplifier deviate from the intended characteristics. In polysilicon TFTs and the like that are not single crystals, non-uniformity of characteristics is a problem that cannot be ignored.

This invention is made | formed in view of the said problem, and makes it a subject to provide the low power consumption shift register which is hard to be affected by the characteristic nonuniformity of a transistor.

According to the present invention, the CK signal is amplified by inputting the CK signal through the capacitive means to the input unit of the inverter having acquired the threshold potential, and the amplified CK signal is used for the shift register. In other words, by acquiring the threshold potential of the inverter, it is possible to provide a shift register which hardly affects the characteristic unevenness of the transistor.

In addition, the level shifter for amplifying the CK signal is operated by a control signal generated using the output pulse of the shift register, so that the level shifter operates only for a short period in which the amplification of the CK signal is required. As a result, the level shifter of the CK signal can provide a shift register with a short period of time in which a through current flows and a low power consumption.

The structure of this invention is described below.

The shift register of the present invention is a shift register having a level shifter for amplifying the amplitude of a clock signal. The level shifter includes a capacitor means,

A second inverter including an input unit connected to a first electrode of the capacitor means, a first P-channel transistor, a second P-channel transistor, and an N-channel transistor, wherein the source of the first P-channel transistor and One of the drains is electrically connected to one of the source and the drain of the second P-channel transistor, and the other of the source and the drain of the second P-channel transistor is electrically connected to one of the source and the drain of the N-channel transistor. The second inverter having gates of the second P-channel transistor and the N-channel transistor electrically connected to an output of the first inverter,

Means for electrically connecting an input and an output of the first inverter;

First means for inputting a reference potential to the second electrode of the capacitor means;

Second means for inputting said clock signal to a second electrode of said capacitor means;

Third means for fixing the potential of the output of the level shifter,

And a fourth means for fixing the potential of the input portion of the inverter in the period in which the level shifter does not operate,

The control signal of the level shifter is generated from an output pulse of the shift register.

The reference potential is characterized by using the potentials of the H level and the L level of the clock signal.

The drive method of the shift register of the present invention has a level shifter for amplifying the amplitude of a clock signal. The level shifter includes a capacitor means,

An inverter having an input connected to the first electrode of the capacitor;

A switch provided between the input unit and the output unit of the inverter,

First means for inputting a reference potential to the second electrode of the capacitor means;

Second means for inputting a clock to a second electrode of the capacitor means;

Third means for fixing the potential of the output of the level shifter;

A drive method of a shift register having a fourth means for fixing a potential of an input portion of the inverter,

In the reset period, the switch is turned on, and the input part and the output part of the inverter are the threshold potentials of the inverter, whereby the first electrode of the capacitor means is the threshold potential, and the first means The second electrode of the capacitor means is the reference potential,

In the clock take-out period, the clock signal is input to the second electrode of the capacitor means by the second means, and according to the change of the potential from the reference potential, the H level or Outputs an L level corresponding to the input clock signal;

In a period in which the output of the inverter is not constant, the potential of the output of the level shifter is fixed by the third means,

In the period in which the level shifter is not operated, the potential of the input portion of the inverter is fixed by the fourth means,

The control signal of the level shifter is generated from an output pulse of the shift register.

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The present invention is very effective when the shift register is operated with a CK signal having an amplitude smaller than the power supply voltage by using a transistor having a large characteristic unevenness such as a polysilicon TFT. By using the shift register of the present invention, the influence of characteristic nonuniformity can be almost ignored. In addition, since the level shifter of the CK signal is controlled using a pulse generated from the shifter register and is operated only for a short period of time requiring the amplification of the CK signal, it is possible to provide a shift register with a short period of passage of the through current and a low power consumption.

1 is a diagram showing the first embodiment.
2 is a diagram showing the second embodiment.
3 is a diagram showing the third embodiment.
4 is a diagram showing a timing chart in the third embodiment.
5 is a diagram showing timing of control signals.
6 is a diagram showing a configuration of a shift register to which the present invention is applicable.
7 is a diagram illustrating a configuration example of the D-FF.
8 is a diagram showing an example of a method of generating a control signal in the present invention.
9 is a diagram showing an example of an electronic apparatus to which the present invention is applicable.
10 is a diagram showing the characteristics of the inverter.
11 is a diagram illustrating another configuration example of the output inverter.

Embodiments of the present invention will be described below.

Embodiment 1

1A shows a first configuration of a level shifter for amplifying the CK signal of the shift register of the present invention.

The level shifter of the present embodiment includes the CK take-out switch 1001, the reference switch 1002, the threshold set switch 1003, the capacitance means 1004, the correction inverter 1005, the potential fixing switch 1006, An output inverter 1007 has an output inverter 1007, which has a first P-type TFT 1008, a second P-type TFT 1009, and an N-type TFT 1010.

The CK take-out switch 1001 controls the on / off by the signal ② generated from the output pulse of the shift register and receives the CK signal. The reference switch 1002 is controlled on and off by the signal? Generated from the output pulse of the shift register, and receives the reference potential at the connection portion between the CK take-out switch 1001 and the capacitor 1004. The input part and the output part of the correction inverter 1005 are electrically connected through the threshold set switch 1003, and the on / off of the threshold set switch 1003 is controlled by the signal?. Here, the CK take-out switch 1001, the reference switch 1002, the threshold set switch 1003, and the potential fixing switch 1006 are turned on when the control signal is at the H level.

During the period when the level shifter does not operate, in order to prevent malfunction or through current of the correction inverter 1005, the input portion of the correction inverter 1005 is connected to the GND power supply via the potential fixing switch 1006. The potential fixing switch 1006 is controlled on / off by the signal ③ generated from the output pulse of the shift register. In the output inverter 1007, the first P-type TFT 1008 is controlled on / off by the signal? Generated from the output pulse of the shift register so as not to malfunction until the output of the CK signal is started.

Here, OUT is set so that the period during which the level shifter is not operated becomes the GND potential, and becomes the VDD potential when the H level of the CK signal is received. For this reason, in the period during which the level shifter does not operate, the input portion of the correction inverter 1005 is fixed at the GND potential. Further, the switch of the first P-type TFT 1008 is provided in the output inverter 1007 by controlling the output period of VDD in the first P-type TFT 1008, so that the output of the correction inverter 1005 is reduced. This is to prevent malfunctions when they are not constant.

In the period during which the level shifter does not operate, when the side where the input unit of the correction inverter 1005 is fixed to H level is logically fitted, the potential fixing switch 1006 is a P-type TFT, and the correction inverter 1005 The input is electrically connected to VDD. In addition, the output inverter 1007 is configured as shown, for example, at 1107 in FIG. 11, instead of the first P-type TFT 1008 that controls the output period of the VDD of the output inverter 1007. By controlling the output period of GND in the TFT lllO, it is possible to prevent the malfunction in the case where the output of the correction inverter 1005 is not constant in the reset period Tl. In FIG. 11, the same symbol is used for the same thing as FIG.

The timing chart of the level shifter of this embodiment is shown in FIG. 1 (b). An operation of amplifying the low voltage CK signal in the level shifter will be described with reference to Figs. As an example, the potential is specified and described. GND is 0V, VDD is 7V, H level of signals ①, ②, ③ and ④ is 7V, L level is 0V, H level of CK signal is 3V, L level is 0V, reference potential is 1.5 which is the mid potential of CK signal. Let V be.

First, the period Tl is a reset period. The signal 1 becomes H level (7V), and the reference switch 1002 and the threshold set switch 1003 are turned on. Node a becomes the reference potential (1.5V). Since the node b acts in a direction in which the potential of the node c is fed back so that the potential does not move, the node b becomes the threshold potential of the correction inverter 1005 (here, 3.5V). Here, the potential difference between both ends of the capacitive means 1004 is preserved.

Subsequently, it transfers to CK lead-out period T2, signal (2) turns into H level (7V), and CK take-out switch 1001 turns on. Since the CK signal is at the L level OV at the beginning of the T2 period, the potential of the node a goes from 1.5V to 0V. Since the potential difference across the capacitor means is maintained, node b changes by the voltage change of node a. Thus, node b drops from 3.5V to 1.5V.

10 shows the VIN-VOUT characteristics of a typical inverter. As shown in FIG. 10, when VIN fluctuates even slightly from the threshold to the upper or lower side, VOUT approaches VDD or GND largely.

Therefore, since node b was set at the threshold potential of correction inverter 1005 in the Tl period, node c reacts sensitively to change in node b. In this case, since the potential of the node b is falling, the node c approaches VDD largely. The output of OUT remains the GND (OV).

In the next T2 period, the CK signal changes from the L level OV to the H level 3V. As a result, the node a becomes 3V from 0V, and the node b rises to a potential of about 3.5 (threshold potential) + 1.5V. Thus, node c approaches GND. At this time, since the signal? Is at the L level OV, the OUT becomes VDD (7V).

At the end of the T2 period, the CK signal changes from the H level (3V) to the L level (0V). As a result, node a becomes 3V to 0V, and node b drops to a potential of about 3.5 (threshold potential) -1.5V. Thus, node c approaches VDD and OUT becomes GND (0V). In this way, as shown in Fig. 1 (b) OUT, a pulse that becomes the H level (7 V) by one half of the CK signal is generated.

After the amplification of the CK signal is completed, the signal ③ becomes H level (7V), the potential fixing switch 1006 is turned on, and the input portion of the correction inverter 1005 is fixed to GND (0V).

The reference potential is preferably an intermediate potential of the CK signal amplitude, but it does not need to be strictly an intermediate potential, it is different from the highest potential and the lowest potential of the CK signal, and also slightly fluctuates within a range that does not deviate from the amplitude of the CK signal. It is possible to let. This intermediate potential may be generated in an external circuit or in an internal circuit.

As in the present embodiment, even if the amplitude of the CK signal is small with respect to the power supply voltage, the CK signal can be amplified without being substantially influenced by the characteristic unevenness of the transistor. In the period during which the level shifter is not operated, the potential is fixed to prevent the malfunction and the penetration current to flow. Therefore, the power consumption can be reduced. Thus, the present invention is suitable for a shift register using a polysilicon TFT having a large variation in characteristics of a transistor.

Embodiment 2

2A shows a second configuration of the level shifter for amplifying the CK signal of the shift register of the present invention.

In Embodiment 1, an example of using the intermediate potential of the CK signal as the reference potential is shown. In Embodiment 2, the H level and the L level of the CK signal are used as the reference potential without using the intermediate potential, and the CK signal is amplified. Give an example.

The level shifter of the present embodiment includes a first CK take-out switch 2001 and a second CK take-out switch 2004, a first reference switch 2002, a second reference switch 2005, and H. It has a set capacity means 2003 and an L set capacity means 2006, a threshold set switch 2007, a correction inverter 2008, a potential fixing switch 2009, an output inverter 2010, and an output inverter ( 2010 includes a first P-type TFT 2011, a second P-type TFT 2012, and an N-type TFT 2013.

The level shifter of this embodiment divides the capacitance means connected to the input part of the correction inverter 2008 into two, the H set capacitance means 2003 and the L set capacitance means 2006. As shown in FIG. A first reference switch 2002 and a first CK take-out switch 2001 are connected to terminals opposite to the H set capacitance means 2003 connected to the correction inverter 2008, and the L set capacitance means ( A second reference switch 2005 and a second CK take-out switch 2004 are connected to the terminal opposite to 2006. Here, the capacitance of the H set capacitance means 2003 and the L set capacitance means 2006 are assumed to be equivalent.

In addition, the threshold setting switch 2007, the potential fixing switch 2009, and the output inverter 2010 are the threshold setting switch 2007 between the input part and the output part of the correction inverter 2008, as in the first embodiment. Is installed. The output inverter 2010 is connected to the output of the correction inverter 2008, and the first inverter TFT 2011 that controls the output period of the VDD is provided in the output inverter 2010. By controlling the output period of the VDD with the first P-type TFT 2011, it is possible to prevent malfunction when the output of the correction inverter 2008 is not constant. In addition, since the potential is fixed during the period when the level shifter does not operate, the input portion of the correction inverter is connected to GND via the potential fixing switch 2009.

In the period during which the level shifter does not operate, when the side where the input unit of the correction inverter 2008 is fixed to H level is logically fitted, the potential fixing switch 2009 is a P-type TFT, and the correction inverter 2008 The input is electrically connected to VDD. In addition, the first P-type TFT which controls the output period of the VDD of the output inverter 2010 by setting the output inverter 2010 to the structure as shown in 1107 of FIG. 11 similarly to Embodiment 1, for example. Instead of (2011), by controlling the output period of the GND with the N-type TFT (lllO), it is possible to prevent the malfunction when the output of the correction inverter 2008 is not constant in the reset period Tl. In FIG. 11, the same symbol is used for the same thing as FIG.

The timing chart of the level shifter of this embodiment is shown in FIG.2 (b). An operation of amplifying the low voltage CK signal in the level shifter of the present embodiment will be described with reference to FIGS. 2A and 2B. As an example, the potential is specified and described. GND is 0V, VDD is 7V, H level of signals ①, ②, ③ and ④ is 7V, L level is 0V, H level of CK signal is 3V, L level is 0V, reference potential is H level is 3V, L level Is 0V.

The timings of the control signals ①, ②, ③, ④ are the same as those in the first embodiment. First, in the reset period Tl, the first reference switch 2002 and the second reference switch 2005 are turned on so that the node e is at a potential of 3V and the node f is at 0V. The input unit of the correction inverter 2008 is turned on for the threshold setting switch 2007 to become the threshold potential of the correction inverter 2008. Here, the potential difference between the both ends of the capacitive means of the H set capacitor means 2003 and the L set capacitor means 2006 is preserved.

Subsequently, it transfers to CK take-out period T2, and the 1st CK take-out switch 2001 and the 2nd CK take-out switch 2004 turn on. First, since the CK signal is at the L level OV, the potential of the node e becomes from 3V to 0V, and the potential of the node f remains at 0V. Due to the change of the node e, the potential of the node g drops by about 1.5 V from the threshold potential of the correction inverter 2008. Subsequently, when the CK signal reaches the H level (3V), the potential of the node e becomes from 0V to 3V, and the potential of the node f becomes from 3V to OV. By the change of this node f, the potential of the node g becomes the electric potential which rose about 1.5V from the threshold electric potential of the correction inverter 2008. At the end of the T2 period, the CK signal becomes L level (0V), and the potential of the node g becomes a potential which is lowered by about 1.5V from the threshold potential of the correction inverter 2008. In this way, as shown in OUT of FIG. 2 (b), a pulse that becomes H level (7 V) by 1/2 cycle of the CK signal is generated.

As described above, the CK signal can be amplified using the H level and the L level of the CK signal without using the intermediate potential of the CK signal as the reference potential. Therefore, the number of power supplies can be reduced by using the H level power supply and the L level power supply of the CK signal without adding the power supply of the intermediate potential of the CK signal.

Embodiment 3

3 shows a third configuration of the level shifter for amplifying the CK signal of the shift register of the present invention.

In the first and second embodiments, the change in the potential from the threshold potential of the input portion of the inverter when the CK signal was received was about 1/2 of the CK signal amplitude, but in the third embodiment, the change was similar to the CK signal amplitude. An example can be shown.

The level shifter of the present embodiment includes the first and second CK drawing switches 3001 and 3008, the first and second reference switches 3002 and 3009, the first, second, third, fourth and the like. Fifth capacitive means 3003,3007,3010,3014,3015, first and second correction inverters 3005,3012, first and second threshold set switches 3004,3011, first and The second potential fixing switch 3006, 3013, the third correction inverter 3017, the third threshold setting switch 3016, the third potential fixing switch 3018, and the output inverter 3019. Have

The level shifter of this embodiment divides the capacitance means connected to the input part of the 3rd correction inverter 3017 into two, the 2nd capacitance means 3007 and the 4th capacitance means 3014. As shown in FIG. An output of the first correction inverter 3005 is connected to a terminal opposite to the second capacitance means 3007 connected to the third correction inverter 3017, and an input of the first correction inverter 3005 is connected to the first terminal. Is connected to the capacitive means 3003. The input portion and the output portion of the first correction inverter 3005 are electrically connected via the first threshold set switch 3004, and the input portion of the first correction inverter 3005 has a first potential fixing switch ( Connected to VDD via 3006). A first CK take-out switch 3001 and a first reference switch 3002 are connected to a terminal opposite to the first capacitance means 3003 connected to the first correction inverter 3005. The CK signal is received from the first CK take-out switch 3001 and the reference potential is received from the first reference switch 3002, respectively.

An output of the second correction inverter 3012 is connected to a terminal opposite to the fourth capacitance means 3014 connected to the third correction inverter 3017, and an input of the second correction inverter 3012 is connected to the third terminal. Is connected to the capacitive means 3010. The input portion and the output portion of the second correction inverter 3012 are electrically connected via the second threshold set switch 3011, and the input portion of the second correction inverter 3012 has a second potential fixing switch ( Connected to VDD via 3013). In addition, an input portion of the first correction inverter 3005 and an input portion of the second correction inverter 3012 are connected by the fifth capacitance means 3015. A second CK take-out switch 3008 and a second reference switch 3009 are connected to the terminal opposite to the second capacitance means 3010 connected to the second correction inverter 3012. The CK signal is received from the second CK signal extraction switch 3008 and the reference potential is received from the second reference switch 3009, respectively.

In addition, an input portion and an output portion of the third correction inverter 3017 are connected via a third threshold set switch 3016, and an input portion of the third correction inverter 3017 is connected to the third potential fixing switch. It is connected to GND via 3018. The output of the third correction inverter 3017 is connected to the output inverter 3019, and the output inverter 3019 is provided with a first P-type TFT 3020 for controlling the period for outputting VDD. Here, the capacitances of the first, second, third and fourth capacitance means are equal, and the capacitance of the fifth capacitance means is the capacitance of the first, second, third and fourth capacitance means. Let it be smaller enough.

In a period in which the level shifter does not operate, when the one in which the input unit of the third correction inverter 3017 is fixed at the H level is logically fitted, the potential fixing switch 3018 is a P-type TFT, The input of the corrected inverter 3017 is electrically connected to VDD. In addition, similarly to the first embodiment, the output inverter 3019 is configured as shown in, for example, 1107 in FIG. 11, so that the first P-type TFT (which controls the output period of the VDD of the output inverter 3019) ( Instead of 3020, by controlling the output period of the GND with the N-type TFT (lllO), it is possible to prevent the malfunction when the output of the third correction inverter 3017 is not constant in the reset period Tl. In FIG. 11, the same symbol is used for the same thing as FIG.

4, the timing chart of the level shifter of this embodiment is shown. 3 and 4, the operation of amplifying the low voltage CK signal in the level shifter of the present embodiment will be described. As an example, the potential is specified and described. GND is 0V, VDD is 7V, H level of signals ①, ②, ③ and ④ is 7V, L level is 0V, H level of CK signal is 3V, L level is 0V, reference potential is H level is 3V, L level Let this be 0V.

The timings of the control signals ①, ②, ③ and ④ are the same as those in the first and second embodiments. First, in the reset period Tl, the first and second reference switches 3002 and 3009 are turned on, and the node i is at a potential of 3V and the node j is at a potential of 0V. At the same time, the first, second and third threshold set switches 3004, 3011 and 3016 are turned on, and the input / output portions of the first, second and third correction inverters 3005, 3012 and 3017 are first And threshold voltages (set to 3.5V) of the second and third correction inverters 3005, 3012, and 3017. Here, the potential difference between both ends of the first, second, third, fourth and fifth capacitive means is preserved.

Subsequently, it transfers to CK take-out period T2, and the 1st and 2nd CK take-out switches 3001 and 3008 turn on. First, since the CK signal is at the H level (3V), the potential of the node i remains 3V, and the potential of the node j is from 0V to 3V. The change of node j causes the potential of node 1 to rise from 3.5V to about 3V, and node n becomes 3.5V to 0V. In addition, the potential of the node k is slightly pulled up by the fifth capacitive means 3015. As a result, the potential of the node m is also lowered from 3.5V to the GND direction. Therefore, the potential of the node o becomes GND (0 V) from 3.5 V, the node p becomes VDD (7 V), and OUT becomes GND (0 V). Subsequently, the CK signal changes to L level (0V) and H level (3V), and accordingly, each node can be appropriately changed as shown in FIG.

By using this configuration, the change in the potential from the threshold potential of the inverter with respect to the CK signal amplitude can be made approximately equal to the CK signal amplitude, and more stable operation can be expected. In addition, the number of power supplies can also be reduced by using the H level and the L level of the CK signal without using the intermediate potential of the CK signal as the reference potential.

In Embodiments 1, 2, and 3, the reference potential is input from the reference switch only in the reset period, but it is not necessary to turn on the reference switch only in this period. That is, at the end of the reset period, one electrode of the capacitor should be at the reference potential, and in the period when the level shifter does not operate, the reference switch is turned on and the reference switch is turned off before the CK drawing period starts. You may also

In addition, during the period in which the level shifter was not operated, the output of the output inverter was L level. This is because the setting requires a high level CK signal when the D-flip flop (D-FF) of the shift register is operated. That is, when the shift register is set to operate the D-FF of the shift register with the CK signal at the L level, the output of the output inverter when the level shifter does not operate becomes H level. The input portion of the correction inverter at this time may be connected to VDD via a potential fixing switch, and the output inverter may be provided with a switch on the N-type TFT so that the GND potential is output only when necessary.

Further, as a means of preventing malfunction when the output of the corrected inverter is not constant, the above embodiment has provided an example in which a switch is provided in the P-type TFT or the N-type TFT of the output inverter, but it does not necessarily need to be this method. For example, an analog switch may be provided after the correction inverter, and an incorrect level may not be output when the output of the correction inverter is not constant.

In addition, the CK drawing switch, the reference switch, the threshold setting switch, and the potential fixing switch may be an N-type TFT, a P-type TFT, or an N-type TFT and P according to the CK signal potential and power supply potential. It is good also as an analog switch using both types of TFTs. Each control signal may be appropriately generated, such as generating an inverted signal in accordance with the polarity of each switch.

In the above embodiment, the potential of the input unit of the correction inverter during the period in which the level shifter does not operate is said to be connected to the power supply via the potential fixing switch. However, the input of the correction inverter may be the power supply potential. The output and the input of the inverter may be connected in a loop via the clocked inverter. In addition, the input terminal of the correction inverter may be fixed to a desired potential at a terminal opposite to the capacitor means connected to the correction inverter so as to be a potential at which the through current does not flow.

Embodiment 4

Next, the timing of generating the control signals ①, ②, ③ and ④ of the level shifter from the output pulses of the shift register will be described with reference to FIG. 5 is a timing chart of signals necessary for generating a control signal of the level shifter of the Nth stage accompanying the D-flip flop D-FF of the Nth stage constituting the shift register. The output Q 5001 of the N-th stage D-FF, the inverted output Qb 5002 of the N-th stage D-FF, the output Q 5003 of the N-th stage D-FF, The inverted output Qb 5004 of the D-FF in the N-1 stage is shown.

In the reset period Tl, NAND of the output Q 5001 of the D-FF of the N-th stage and the inverted output Qb 5004 of the D-FF of the N-th stage in the period when the signal ① becomes H level. Can be generated by inverting the NAND output. In the drawing period T2 of the CK signal, the output Q 5003 of the D-FF of the N-th stage may be used in the period where the signal ② becomes H level. The potential fixing period T3 takes NOR of the output Q 5001 of the D-FF of the N-th stage and the output Q 5003 of the D-FF of the N-th stage in the period where the signal ③ becomes H level. Can be generated. As the signal ④ for controlling the VDD output of the output inverter, an inverted signal of the signal ② may be used.

However, the above description is an example in the case where there is no signal delay. In practice, it is necessary to generate a control signal with attention to the signal delay. In particular, starting the reset period after turning off the potential holding switch to prevent through current, starting the CK signal drawing period after the reset period ends to prevent the input reference potential from changing, It should be noted that the signal ④ of the VDD output control of the output inverter is turned on (L level) after the CK signal is started, and then the influence of noise is eliminated.

In Embodiment 4, an example of generating each control signal of the level shifter of the CK signal using the output of the D-FF at the N-2 stage and the D-FF at the N-1 stage has been described. It is not necessarily limited to this. The output of the N-stage D-FF may be used in the reset period, and the output of the N-stage D-FF may be used in the CK signal extraction period. In short, the output pulse of the shift register may be appropriately generated according to the purpose.

In this way, the control signal of the level shifter can be generated from the output pulse of the shift register.

(Example)

EMBODIMENT OF THE INVENTION Below, the Example of this invention is described.

The connection relationship between the D-FF and the level shifter in each stage when the shift register is configured by using the level shifters of Embodiments 1, 2, and 3 will be described.

Example 1

6 shows an example of the configuration of a shift register using the level shifter of the present invention.

The shift register is composed of a plurality of level shifters (LS) 6001 and a D-FF 6002. The input Nl of the level shifter of the Nth stage is connected to the output Q of the D-FF of the N-th stage, and the input N2 of the level shifter of the Nth stage is connected to the output Q of the D-FF of the N-1 stage. The output OUT of the level shifter of the Nth stage is connected to CK2 of the D-FF of the N-1 stage and CKl of the D-FF of the Nth stage. The output Q of the N-th stage D-FF is connected to the input IN of the N-th stage D-FF, and the output Q of the D-FF of the N-th stage is input IN of the D-FF of the N + 1 stage. Is connected to. The output OUT of the level shifter of the N + 1th stage is connected to CK2 of the D-FF of the Nth stage.

In this embodiment, an example in which the ratio of the number of stage shifters constituting the shift register and the number of flip flops corresponds to 1: 1 is given. However, the ratio of the number of stage shifters constituting the shift register to the number of flip flops is 1; : N (N may be 2 or more). The layout area, operating frequency, power consumption, and the like of the circuit may be appropriately selected.

[Example 2]

Next, the timing chart is shown in FIG. 7B for the configuration example of the D-FF 6002 in FIG. 7A.

The D-FF 6002 has a first clocked inverter 7001 and an inverter 7002 connected in series, and a second clocked inverter 7003 connected in loop form with the inverter. The first clocked inverter 7001 includes a first P-type TFT 7004, a second P-type TFT 7005, a first N-type TFT 7006, and a second N-type TFT connected in series. And a second clocked inverter 7003, a third P-type TFT 7008, a fourth P-type TFT 7009, and a third N-type TFT 7010 connected in series. And a fourth N-type TFT 7011.

The second N-type TFT 7007 and the third P-type TFT 7008 are controlled on / off by CKl, and the first P-type TFT 7004 and the fourth N-type TFT 7011 are On / off is controlled by CK2. The output IN of the front end D-FF is input to the gates of the second P-type TFT 7005 and the first N-type TFT 7006.

The operation of this embodiment will be described using the timing chart of FIG. 7 (b).

First, in the period Tl, a pulse is input to IN to become H level, the second P-type TFT 7005 is turned off, and the first N-type TFT 7006 is turned on. Subsequently, in the period T2, CKl becomes H level, the second N-type TFT 707 turns on, the node Qb becomes the GND potential, and the node Q becomes the VDD potential. Subsequently, in the period T3, CK2 becomes H level, and the fourth N-type TFT 7011 is turned on, and the node Qb is maintained at the GND potential. Further, in the period T4, CK2 is at the L level, the first P-type TFT 7004 is turned on, the fourth N-type TFT 7011 is turned off, the node Qb is at the VDD potential, and the node Q is at the GND potential. do.

In this embodiment, although the D-FF shown in Fig. 7A is used, it is needless to say that it is not necessarily limited to the flip-flop of this configuration.

Example 3

In the fourth embodiment, the timing of generating the control signal of the level shifter from the output pulse of the shift register has been described. However, in actual use, it is necessary to input to the level shifter in consideration of the delay of each control signal. The specific example is given.

8A shows an example of a circuit for generating control signals 1, 2, 3 and 4 of the level shifter in consideration of the delay from the output pulse of the shift register. 8 (b) shows the timing chart.

The generation of the control signal of the level shifter in the Nth stage will be described. First, the output Q of the N-th stage D-FF (N-2 Q) and the N-th stage of the D-FF output Q (N-1 Q) are inputted to the NOR 8001, and NOR ( Let the output of 8001) be the signal ③. When the output Q (N-2Q) of the D-FF in the N-th stage is at the H level, the signal ③ is at the L level. Next, the output Q of the N-th stage D-FF (N-2Q) and the N-th stage of the D-FF output Q (N-1 Q) are inverted by the first inverter 8002. Is inputted to the NAND 8003, and the output of the NAND 8003 is inverted by the second inverter 8004 to generate the signal?. Compared with the signal ③, since the signal ① has a delay as much as the second inverter 8004, the signal ① is directed to the L level, and then the signal ① is directed to the H level. In addition, when a plurality of inverters are added in series to the second inverter 8004, the timing at which the H level of the signal ③ and the H level of the signal ① overlap is completely eliminated and the through current can be eliminated.

Further, among the first P-type TFT 8005, the second P-type TFT 8006, and the N-type TFT 8007 connected in series, the second P-type TFT 8006 and the N-type TFT 8007 The inverted pulse of the output Q of the D-FF at the N-th stage is input to the gate electrode of N, and the signal? Is input to the gate electrode of the first P-type TFT 8005. The source electrode of the first P-type TFT 8005 is connected to VDD, the source electrode of the N-type TFT 8007 is connected to GND, and the second P-type TFT 8006 and the N-type TFT 8007 The drain electrode is connected, and the third inverter 8008, the fourth inverter 8009, the fifth inverter 8010, the sixth inverter 8011, and the seventh inverter 8012 are connected in series. have.

Since the signal ① is inputted to the gate electrode of the first P-type TFT 8005, the signal ① becomes L level, and then the input portion of the third inverter 8008 becomes H level. Further, the fourth inverter 8009 is inverted to generate the signal ②. As a result, the reset period and the CK drawing period do not overlap.

Further, the signal? Is generated via the fifth inverter 8010, the sixth inverter 8011, and the seventh inverter 8012. As a result, the output inverter enters the VDD output enabled state after the CK drawing period starts.

In the present embodiment, the configuration of FIG. 8A has been described, but needless to say, the configuration is not limited to this configuration. It may be appropriately configured in consideration of the delay time and the frequency of each control signal.

Example 4

The display device of the present invention can be used for the display portion of various electronic devices. In particular, it is preferable to use the display device of the present invention for a mobile device requiring low power consumption.

Specifically, the electronic device may include a portable information terminal (such as a mobile phone, a mobile computer, a portable game machine or an electronic book), a video camera, a digital camera, a goggle display, a display display, a navigation system, and the like. A specific example of these electronic devices is shown in FIG.

9A is a display display, and includes a case 9001, an audio output unit 9002, a display unit 9003, and the like. The display device of the present invention can be used for the display portion 9003. The display device includes all information display devices such as a PC, a TV broadcast reception, and an advertisement display.

9B is a mobile computer and includes a main body 9101, a stylus 9102, a display portion 9103, operation buttons 9104, an external interface 9305, and the like. The display device of the present invention can be used for the display portion 9103.

9C is a game machine and includes a main body 9201, a display portion 9202, operation buttons 9203, and the like. The display device of the present invention can be used for the display portion 9202.

9 (d) is a mobile phone and includes a main body 9301, a voice output section 9302, a voice input section 9303, a display section 9304, an operation switch 9305, an antenna 9906, and the like. The display device of the present invention can be used for the display portion 9304.

As described above, the application range of the display device of the present invention is extremely wide, and it can be used in electronic devices in all fields.

1001: CK take-out switch 1001: reference switch
1003: threshold set switch, 1004: capacity means
1005: compensation inverter 1006: potential fixing switch
1007: output inverter 1008: first P-type TFT
1009: second P-type TFT 1010: N-type TFT

Claims (10)

A shift register having a level shifter for amplifying the amplitude of a clock signal, wherein the level shifter includes:
Capacity means,
A first inverter having an input connected to a first electrode of the capacitor;
A second inverter comprising a first P-channel transistor, a second P-channel transistor, and an N-channel transistor, wherein one of the source and the drain of the first P-channel transistor is electrically connected to one of the source and the drain of the second P-channel transistor. A second one of the source and the drain of the second P-channel transistor is electrically connected to one of the source and the drain of the N-channel transistor, and each gate of the second P-channel transistor and the N-channel transistor is The second inverter electrically connected to an output of the first inverter,
Means for electrically connecting an input and an output of the first inverter;
First means for inputting a reference potential to the second electrode of the capacitor means;
Second means for inputting said clock signal to a second electrode of said capacitor means;
Third means for fixing the potential of the output of the level shifter,
And the control signal of the level shifter is generated from an output pulse of the shift register.
The method of claim 1,
And a potential at the H level or L level of the clock signal as the reference potential.
delete delete A personal computer having a display device, the display device comprising:
And a shift register having a level shifter for amplifying the amplitude of the clock signal, wherein the level shifter includes:
Capacity means,
A first inverter having an input connected to a first electrode of the capacitor;
A second inverter comprising a first P-channel transistor, a second P-channel transistor, and an N-channel transistor, wherein one of the source and the drain of the first P-channel transistor is electrically connected to one of the source and the drain of the second P-channel transistor. A second one of the source and the drain of the second P-channel transistor is electrically connected to one of the source and the drain of the N-channel transistor, and each gate of the second P-channel transistor and the N-channel transistor is The second inverter electrically connected to an output of the first inverter,
Means for electrically connecting an input and an output of the first inverter;
First means for inputting a reference potential to the second electrode of the capacitor means;
Second means for inputting said clock signal to a second electrode of said capacitor means;
Third means for fixing the potential of the output of the level shifter,
And the control signal of the level shifter is generated from an output pulse of the shift register.
A camera having a display device, the display device comprising:
And a shift register having a level shifter for amplifying the amplitude of the clock signal, wherein the level shifter includes:
Capacity means,
A first inverter having an input connected to a first electrode of the capacitor;
A second inverter comprising a first P-channel transistor, a second P-channel transistor, and an N-channel transistor, wherein one of the source and the drain of the first P-channel transistor is electrically connected to one of the source and the drain of the second P-channel transistor. A second one of the source and the drain of the second P-channel transistor is electrically connected to one of the source and the drain of the N-channel transistor, and each gate of the second P-channel transistor and the N-channel transistor is The second inverter electrically connected to an output of the first inverter,
Means for electrically connecting an input and an output of the first inverter;
First means for inputting a reference potential to the second electrode of the capacitor means;
Second means for inputting said clock signal to a second electrode of said capacitor means;
Third means for fixing the potential of the output of the level shifter,
And the control signal of the level shifter is generated from an output pulse of the shift register.
The method of claim 6,
Said camera is at least one of a digital camera and a video camera.
A mobile telephone having a display device, wherein the display device includes:
And a shift register having a level shifter for amplifying the amplitude of the clock signal, wherein the level shifter includes:
Capacity means,
A first inverter having an input connected to a first electrode of the capacitor;
A second inverter comprising a first P-channel transistor, a second P-channel transistor, and an N-channel transistor, wherein one of the source and the drain of the first P-channel transistor is electrically connected to one of the source and the drain of the second P-channel transistor. A second one of the source and the drain of the second P-channel transistor is electrically connected to one of the source and the drain of the N-channel transistor, and each gate of the second P-channel transistor and the N-channel transistor is The second inverter electrically connected to an output of the first inverter,
Means for electrically connecting an input and an output of the first inverter;
First means for inputting a reference potential to the second electrode of the capacitor means;
Second means for inputting said clock signal to a second electrode of said capacitor means;
Third means for fixing the potential of the output of the level shifter,
And the control signal of the level shifter is generated from an output pulse of the shift register.
A mobile computer having a display device, the display device comprising:
And a shift register having a level shifter for amplifying the amplitude of the clock signal, wherein the level shifter includes:
Capacity means,
A first inverter having an input connected to a first electrode of the capacitor;
A second inverter comprising a first P-channel transistor, a second P-channel transistor, and an N-channel transistor, wherein one of the source and the drain of the first P-channel transistor is electrically connected to one of the source and the drain of the second P-channel transistor. A second one of the source and the drain of the second P-channel transistor is electrically connected to one of the source and the drain of the N-channel transistor, and each gate of the second P-channel transistor and the N-channel transistor is The second inverter electrically connected to an output of the first inverter,
Means for electrically connecting an input and an output of the first inverter;
First means for inputting a reference potential to the second electrode of the capacitor means;
Second means for inputting said clock signal to a second electrode of said capacitor means;
Third means for fixing the potential of the output of the level shifter,
And the control signal of the level shifter is generated from an output pulse of the shift register.
A game machine having a display device, wherein the display device includes:
And a shift register having a level shifter for amplifying the amplitude of the clock signal, wherein the level shifter includes:
Capacity means,
A first inverter having an input connected to a first electrode of the capacitor;
A second inverter comprising a first P-channel transistor, a second P-channel transistor, and an N-channel transistor, wherein one of the source and the drain of the first P-channel transistor is electrically connected to one of the source and the drain of the second P-channel transistor. A second one of the source and the drain of the second P-channel transistor is electrically connected to one of the source and the drain of the N-channel transistor, and each gate of the second P-channel transistor and the N-channel transistor is The second inverter electrically connected to an output of the first inverter,
Means for electrically connecting an input and an output of the first inverter;
First means for inputting a reference potential to the second electrode of the capacitor means;
Second means for inputting said clock signal to a second electrode of said capacitor means;
Third means for fixing the potential of the output of the level shifter,
And the control signal of the level shifter is generated from an output pulse of the shift register.

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