CN110264936A - Gate driving circuit and display device - Google Patents
Gate driving circuit and display device Download PDFInfo
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- CN110264936A CN110264936A CN201910549933.9A CN201910549933A CN110264936A CN 110264936 A CN110264936 A CN 110264936A CN 201910549933 A CN201910549933 A CN 201910549933A CN 110264936 A CN110264936 A CN 110264936A
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- clock signal
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The present invention provides a kind of gate driving circuit and display device.Gate driving circuit includes multi-stage shift register unit, and the gate driving circuit further includes signal generating circuit；The signal generating circuit is used to generate displacement coherent signal, and output signal is provided to the shift register cell according to control signal；The output signal includes the displacement coherent signal；Alternatively, the output signal includes the control signal and the shift output signal.The present invention can reduce cost and show the power consumption of product.
Description
Technical field
The present invention relates to display actuation techniques field more particularly to a kind of gate driving circuit and display devices.
Background technique
GOA (Gate On Array, the gate driving circuit being arranged in array substrate) circuit is a kind of by gate driving
Circuit integration will be scanned in the technology on TFT (thin film transistor (TFT)) substrate, each GOA unit as a shift register cell
Signal successively passes to next stage shift register cell, opens TFT switch line by line, and the data-signal for completing pixel unit is defeated
Enter.
As shown in Figure 1, TCON (sequence controller) is provided to the clock of gate driving circuit in existing display device
The amplitude of the amplitude of signal, the amplitude of direct current noise reduction voltage signal and frame start signal is lower, so that the gate driving circuit
The gate drive signal of output is unable to complete the driving to the thin film transistor (TFT) of display area, needs in every level-one shift register
The rear end of unit carries out level conversion to above each signal using electrical level transferring chip, so that the amplitude of above each signal increases,
To realize normal gate driving.However increases electrical level transferring chip and increase certain cost, and from integrated circuit board just
The higher clock signal of output amplitude, direct current noise reduction voltage signal and frame start signal increase the power consumption of display product, and mesh
Preceding mobile display product needs to further decrease the power consumption of product to increase the cruising ability of battery.
Summary of the invention
The main purpose of the present invention is to provide a kind of gate driving circuit and display device, solution needs in the prior art
Level conversion is carried out to above each signal using electrical level transferring chip in the rear end of every level-one shift register cell, to increase
The problem of cost and the power consumption of display product.
In order to achieve the above object, the present invention provides a kind of gate driving circuit, including multi-stage shift register unit,
The gate driving circuit further includes signal generating circuit；
The signal generating circuit is used to generate displacement coherent signal, and output signal is provided to according to control signal
The shift register cell；
The output signal includes the displacement coherent signal；Alternatively, the output signal include the control signal and
The shift output signal.
When implementation, the control signal includes control clock signal, and the displacement coherent signal includes shift clock signal；
The signal generating circuit includes that clock signal generates sub-circuit；
The clock signal generates sub-circuit and is used to generate shift clock signal according to control clock signal, and described in control
The absolute value of the current potential of shift clock signal is greater than the absolute value of the current potential of the control clock signal, and by the shift clock
Signal is provided to the shift register cell.
When implementation, the control signal includes control clock signal, and the displacement coherent signal includes shift clock signal；
The signal generating circuit includes that clock signal generates sub-circuit；
The clock signal generates sub-circuit and is used to carry out reverse phase to the control clock signal, to obtain shift clock letter
Number, and the control clock signal and the shift clock signal are provided to the shift register cell.
When implementation, it includes that the first clock signal generates transistor and second clock signal that the clock signal, which generates sub-circuit,
Generate transistor；
The control electrode that first clock signal generates transistor accesses the control clock signal, the first clock letter
The first pole and the second clock signal for number generating transistor generate the second pole of transistor and are electrically connected, and first clock is believed
Number generate transistor the second pole be electrically connected with the first level terminal；The first pole that first clock signal generates transistor is used for
Export the shift clock signal；
The second clock signal generates the control electrode of transistor and the second clock signal generates the first of transistor
Pole is all electrically connected with second electrical level end.
When implementation, the control signal includes control initial signal, and the displacement coherent signal includes displacement initial signal；
The signal generating circuit includes that initial signal generates sub-circuit；
The initial signal generates sub-circuit and is used to carry out reverse phase to the control initial signal, and to the control after reverse phase
Initial signal carries out level conversion, to obtain the displacement initial signal, and the displacement initial signal is provided to described more
First order shift register cell in grade shift register cell.
When implementation, it includes that the first initial signal generates transistor and the second initial signal that the initial signal, which generates sub-circuit,
Generate transistor；
The control electrode that first initial signal generates transistor accesses the control initial signal, the first starting letter
The first pole and second initial signal for number generating transistor generate the second pole of transistor and be electrically connecteds, and described first originates and believe
Number generate transistor the second pole be electrically connected with the first level terminal；The first pole that first initial signal generates transistor is used for
Export the displacement initial signal；
Second initial signal generates the control electrode of transistor and second initial signal generates the first of transistor
Pole is all electrically connected with second electrical level end.
When implementation, the control signal includes control voltage signal, and the displacement coherent signal includes shift voltage signal；
The signal generating circuit includes that voltage signal generates sub-circuit；
The voltage signal generates sub-circuit and is used to generate shift voltage signal according to control voltage signal, and described in control
The absolute value of the current potential of shift voltage signal is greater than the absolute value of the current potential of the control voltage signal, and by the shift voltage
Signal is provided to the shift register cell.
When implementation, the control signal includes control voltage signal, and the displacement coherent signal includes shift voltage signal；
The signal generating circuit includes that voltage signal generates sub-circuit；
The voltage signal generates sub-circuit and is used to carry out reverse phase to the control voltage signal, to obtain shift voltage letter
Number, and the control voltage signal and the shift voltage signal are provided to the shift register cell.
When implementation, it includes that first voltage signal generates transistor and second voltage signal that the voltage signal, which generates sub-circuit,
Generate transistor；
The control electrode that the first voltage signal generates transistor accesses the control voltage signal, the first voltage letter
The first pole and the second voltage signal for number generating transistor generate the second pole of transistor and are electrically connected, and the first voltage is believed
Number generate transistor the second pole be electrically connected with the first level terminal；The first pole that the first voltage signal generates transistor is used for
Export the shift voltage signal；
The second voltage signal generates the control electrode of transistor and the second voltage signal generates the first of transistor
Pole is all electrically connected with second electrical level end.
The present invention also provides a kind of display devices, including above-mentioned gate driving circuit.
When implementation, display device of the present invention further includes sequence controller；
The sequence controller is used to provide the described control signal.
Compared with prior art, gate driving circuit of the present invention and display device use signal generating circuit, root
Displacement coherent signal is generated according to control signal, and output signal is provided to the shift register cell (output signal
Including the displacement coherent signal；Alternatively, the output signal includes the control signal and the shift output signal), lead to
Cross the front end setting signal generative circuit in shift register cell, it can control the grid of the shift register cell output
The current potential of pole driving signal is higher, and level conversion function is integrated in gate driving circuit by the embodiment of the present invention, in gate driving
The input terminal of circuit increases the signal generating circuit, can save the spending of electrical level transferring chip, reduces display product
Power consumption improves the competitiveness of display product.Also, the signal in gate driving circuit described in the embodiment of the present invention generates electricity
Road can also realize the function of phase inverter, only provide the clock signal and voltage signal of conventional design half quantity, can be realized
Gate driving.
Detailed description of the invention
Figure 1A is the structure chart of gate driving circuit described in the embodiment of the present invention；
Figure 1B is the structure chart of gate driving circuit described in another embodiment of the present invention；
Fig. 2 is the circuit diagram for the embodiment that clock signal generates sub-circuit；
Fig. 3 is the working timing figure for the embodiment that clock signal shown in Fig. 2 generates sub-circuit；
Fig. 4 is the circuit diagram for the embodiment that initial signal generates sub-circuit；
Fig. 5 is the working timing figure for the embodiment that initial signal shown in Fig. 4 generates sub-circuit；
Fig. 6 is the circuit diagram for the embodiment that voltage signal generates sub-circuit；
Fig. 7 is the working timing figure for the embodiment that voltage signal shown in fig. 6 generates sub-circuit；
Fig. 8 is the circuit diagram of the first specific embodiment of gate driving circuit of the present invention；
Fig. 9 is the working timing figure of the first specific embodiment of gate driving circuit of the present invention；
Figure 10 is the circuit diagram of the second specific embodiment of gate driving circuit of the present invention；
Figure 11 is the working timing figure of the second specific embodiment of gate driving circuit of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The transistor used in all embodiments of the invention all can be triode, thin film transistor (TFT) or field-effect tube or its
The identical device of his characteristic.In embodiments of the present invention, to distinguish the two poles of the earth of transistor in addition to control electrode, will wherein claim a pole
For the first pole, another pole is known as the second pole.
In practical operation, when the transistor is triode, the control electrode can be base stage, and first pole can
Think collector, second pole can be with emitter；Alternatively, the control electrode can be base stage, described first can be extremely hair
Emitter-base bandgap grading, second pole can be with collector.
In practical operation, when the transistor is thin film transistor (TFT) or field-effect tube, the control electrode can be grid
Pole, described first can be extremely drain electrode, and described second extremely can be source electrode；Alternatively, the control electrode can be grid, described the
One extremely can be source electrode, and described second can be extremely drain electrode.
Gate driving circuit described in the embodiment of the present invention, including multi-stage shift register unit, the gate driving electricity
Road further includes signal generating circuit；
The signal generating circuit is used to generate displacement coherent signal, and output signal is provided to according to control signal
The shift register cell；
The output signal includes the displacement coherent signal；Alternatively, the output signal include the control signal and
The shift output signal.
Gate driving circuit described in the embodiment of the present invention uses signal generating circuit, generates displacement phase according to control signal
OFF signal, and output signal is provided to the shift register cell (output signal includes the displacement coherent signal；
Alternatively, the output signal includes the control signal and the shift output signal), by before shift register cell
Hold setting signal generative circuit, it can the current potential for controlling the gate drive signal of the shift register cell output is higher,
Level conversion function is integrated in gate driving circuit by the embodiment of the present invention, increases the letter in the input terminal of gate driving circuit
Number generative circuit, can save the spending of electrical level transferring chip, while reducing PLG (Panel Line to Gate, grid are defeated
Enter signal lead) loss to voltage, the power consumption of display product is reduced, the competitiveness of display product is improved.Also, this hair
Signal generating circuit in gate driving circuit described in bright embodiment can also realize the function of phase inverter, only provide conventional set
The clock signal and voltage signal for counting half quantity, can be realized gate driving.
In embodiments of the present invention, the control signal is provided by sequence controller.The control signal for example can wrap
Control clock signal, control initial signal and control voltage signal are included, but not limited to this.
The function of electrical level transferring chip will be integrated in gate driving framework by the present invention, reduce cost and power consumption.
As shown in Figure 1A, gate driving circuit described in the embodiment of the present invention includes N grades of shift register cells and signal
Generative circuit 10；N is the integer greater than 2；
In figure 1A, it is first order shift register cell marked as S1, is second level shift LD marked as S2
Device unit is N grades of shift register cells marked as SN, is gate drive signal output end marked as Out, marked as
Input is input terminal, is reset terminal marked as Reset；
The signal generating circuit 10 is used to generate displacement coherent signal S0, and by the displacement according to control signal SC
Coherent signal S0 is provided to the shift register cell.
In the specific implementation, the signal generating circuit 10 can carry out level conversion to the control signal SC, with life
At displacement coherent signal S0, so that the absolute value of the current potential of the displacement coherent signal S0 is higher than the current potential of the control signal SC
Absolute value；
In the specific implementation, the signal generating circuit 10 can carry out reverse phase to the control signal SC and go forward side by side line level
Conversion shifts coherent signal S0 to generate, so that the absolute value of the current potential of the displacement coherent signal S0 is believed higher than the control
The absolute value of the current potential of number SC；
In the specific implementation, the signal generating circuit 10 can carry out reverse phase to the control signal SC, be moved with generating
Position coherent signal S0, so that the displacement coherent signal S0 and the control signal SC reverse phase.
As shown in Figure 1B, gate driving circuit described in the embodiment of the present invention includes N grades of shift register cells and signal
Generative circuit 10；N is the integer greater than 2；
In fig. ib, it is first order shift register cell marked as S1, is second level shift LD marked as S2
Device unit is N grades of shift register cells marked as SN, is gate drive signal output end marked as Out, marked as
Input is input terminal；
The signal generating circuit 10 is used to generate displacement coherent signal S0, and by the control according to control signal SC
Signal SC and the displacement coherent signal S0 are provided to the shift register cell.
In embodiments of the present invention, the gate drive signal output end and next stage of adjacent upper level shift register cell
The input terminal of shift register cell is electrically connected, the gate drive signal output end of adjacent next stage shift register cell with it is upper
The reset terminal of level-one shift register cell is electrically connected, and but not limited to this.
According to a kind of specific embodiment, the control signal may include control clock signal, the related letter of the displacement
Number include shift clock signal；The signal generating circuit includes that clock signal generates sub-circuit；
The clock signal generates sub-circuit and is used to generate shift clock signal according to control clock signal, and described in control
The absolute value of the current potential of shift clock signal is greater than the absolute value of the current potential of the control clock signal, and by the shift clock
Signal is provided to the shift register cell.
In the specific implementation, the control signal may include control clock signal, and the displacement coherent signal can wrap
Shift clock signal is included, signal generating circuit may include that clock signal generates sub-circuit, and the clock signal generates sub-circuit
The absolute value that the current potential of the shift clock signal can be controlled is greater than the absolute value of the current potential for controlling clock signal.
For example, the current potential of the control clock signal can be 3.3V when the control clock signal is high level, when
When the control clock signal is low level, the current potential of the control clock signal can be -3.3V；When the shift clock is believed
Number be high level when, the current potential of the shift clock signal can be 28V；When the shift clock signal is low level, institute
The current potential for stating shift clock signal can be -15V, and but not limited to this.
According to another specific embodiment, the control signal may include control clock signal, and the displacement is related
Signal includes shift clock signal；The signal generating circuit includes that clock signal generates sub-circuit；
The clock signal generates sub-circuit and is used to carry out reverse phase to the control clock signal, to obtain shift clock letter
Number, and the control clock signal and the shift clock signal are provided to the shift register cell.
In the specific implementation, the control signal may include control clock signal, and the displacement coherent signal can wrap
Shift clock signal is included, the clock signal generates sub-circuit and is used to carry out reverse phase to the control clock signal, to be moved
Bit clock signal.
For example, when the shift register cell needs two clock signals (the first clock signal and second clock signal)
When, when first clock signal and the second clock signal inversion, sequence controller can only provide the first clock signal,
Sub-circuit being generated by the clock signal, operated in anti-phase being carried out to first clock signal, second clock letter can be obtained
Number.
Specifically, it may include that the first clock signal generates transistor and second clock that the clock signal, which generates sub-circuit,
Signal generates transistor；
The control electrode that first clock signal generates transistor accesses the control clock signal, the first clock letter
The first pole and the second clock signal for number generating transistor generate the second pole of transistor and are electrically connected, and first clock is believed
Number generate transistor the second pole be electrically connected with the first level terminal；The first pole that first clock signal generates transistor is used for
Export the shift clock signal；
The second clock signal generates the control electrode of transistor and the second clock signal generates the first of transistor
Pole is all electrically connected with second electrical level end.
In the specific implementation, first level terminal can be low level end, and the second electrical level end can be high level
End, but not limited to this.
As shown in Fig. 2, the embodiment that the clock signal generates sub-circuit may include that the first clock signal generates crystalline substance
Body pipe M11 and second clock signal generate transistor M12；
Grid access the first control clock signal clk 1 of the first clock signal generation transistor M11, described first
The drain electrode that clock signal generates transistor M11 is electrically connected with the source electrode of second clock signal generation transistor M12, and described the
The source electrode that one clock signal generates transistor M11 is electrically connected with low level end；First clock signal generates transistor M11's
Drain electrode is for exporting the first shift clock signal CKo1；
The second clock signal generates the grid of transistor M12 and the second clock signal generates transistor M12's
Drain electrode is all electrically connected with high level end；
The low level end is used for input low level VGL, and the high level end is used for input high level VGH.
In the embodiment shown in Figure 2, the breadth length ratio of M11 needs the breadth length ratio greater than M12, in the preferred case, M11's
The ratio of breadth length ratio and the breadth length ratio of M12 can be greater than 2:1, can ensure when the current potential of CLK1 is high level, CKo1's
Current potential is low level.
In the embodiment shown in Figure 2, M11 and M12 is N-type TFT, and but not limited to this.
In embodiments of the present invention, VGL can be -6V, and VGH can be 28V, and but not limited to this.
As shown in figure 3, present invention clock signal as shown in Figure 2 generates the embodiment of sub-circuit at work,
In first time period t1, the current potential of CLK1 is -3.3V, and M12 is opened, and M11 shutdown, the current potential of CKo1 is VGH；
In second time period t2, the current potential of CLK1 is 3.3V, M11 and M12 opening, and the current potential of CKo1 is VGL.
Specifically, the control signal may include control initial signal, the displacement coherent signal may include displacement
Initial signal；The signal generating circuit may include that initial signal generates sub-circuit；
The initial signal generates sub-circuit and is used to carry out reverse phase to the control initial signal, and to the control after reverse phase
Initial signal carries out level conversion, to obtain the displacement initial signal, and the displacement initial signal is supplied to described more
First order shift register cell in grade shift register cell.
In the specific implementation, the signal generating circuit may include that initial signal generates sub-circuit, the initial signal
Reverse phase and level conversion can be carried out to the control initial signal by generating sub-circuit, to obtain displacement initial signal, and should
Displacement initial signal is supplied to the first order shift register cell that the gate driving circuit includes.
Specifically, it may include that the first initial signal generates transistor and the second starting that the initial signal, which generates sub-circuit,
Signal generates transistor；
The control electrode that first initial signal generates transistor accesses the control clock signal, the first starting letter
The first pole and second initial signal for number generating transistor generate the second pole of transistor and be electrically connecteds, and described first originates and believe
Number generate transistor the second pole be electrically connected with the first level terminal；The first pole that first initial signal generates transistor is used for
Export the shift clock signal；
Second initial signal generates the control electrode of transistor and second initial signal generates the first of transistor
Pole is all electrically connected with second electrical level end.
As shown in figure 4, the embodiment that the initial signal generates sub-circuit may include that the first initial signal generates crystalline substance
Body pipe M3 and the second initial signal generate transistor M4；
First initial signal generates the grid access control initial signal STV0 of transistor M3, the first starting letter
Number generate transistor M3 drain electrode with second initial signal generate transistor M4 source electrode be electrically connected, it is described first originate believe
Number generate transistor M3 source electrode be electrically connected with low level end；First initial signal generates the drain electrode of transistor M3 for defeated
Initial signal STV is shifted out；The low level end is used for input low level VGL；
Second initial signal generates the leakage of the grid and second initial signal generation transistor M4 of transistor M4
Pole is all electrically connected with high level end；The high level end is used for input high level VGH.
Initial signal shown in Fig. 4 generates in the embodiment of sub-circuit, and M3 and M4 are N-type TFT, but not
As limit.
In embodiments of the present invention, VGL can be -6V, and VGH can be 28V, and but not limited to this.
In the embodiment shown in fig. 4, the breadth length ratio of M3 needs the breadth length ratio greater than M4, in the preferred case, the width of M3
The long ratio than with the breadth length ratio of M4 can be greater than 2:1, can ensure when the current potential of STV0 is high level, the current potential of STV
For low level.
As shown in figure 5, initial signal as shown in Figure 4 generates the embodiment of sub-circuit at work,
In first time period t1, the current potential of STV0 is -3.3V, and M4 is opened, and M3 shutdown, the current potential of STV is VGH；
In second time period t2, the current potential of STV0 is+3.3V, M4 and M3 opening, and the current potential of STV is VGL.
According to a kind of specific embodiment, the control signal may include control voltage signal, the related letter of the displacement
Number include shift voltage signal；The signal generating circuit includes that voltage signal generates sub-circuit；
The voltage signal generates sub-circuit and is used to generate shift voltage signal according to control voltage signal, and described in control
The absolute value of the current potential of shift voltage signal is greater than the absolute value of the current potential of the control voltage signal.
In the specific implementation, the control signal may include control voltage signal, and the displacement coherent signal can wrap
Shift voltage signal is included, signal generating circuit may include that voltage signal generates sub-circuit, and the voltage signal generates sub-circuit
The absolute value that the current potential of the shift voltage signal can be controlled is greater than the absolute value of the current potential for controlling voltage signal, and will
The shift voltage signal is supplied to described and shift register cell.
For example, the current potential of the control voltage signal can be 3.3V when the control voltage signal is high level, when
When the control voltage signal is low level, the current potential of the control voltage signal can be -3.3V；When the shift voltage is believed
Number be high level when, the current potential of the shift voltage signal can be 28V；When the shift voltage signal is low level, institute
The current potential for stating shift voltage signal can be -15V, and but not limited to this.
According to another specific embodiment, the control signal includes control voltage signal, the displacement coherent signal
Including shift voltage signal；The signal generating circuit includes that voltage signal generates sub-circuit；
The voltage signal generates sub-circuit and is used to carry out reverse phase to the control voltage signal, to obtain shift voltage letter
Number, and the control voltage signal and the shift voltage signal are provided to the shift register cell.
In the specific implementation, the control signal may include control voltage signal, and the displacement coherent signal can wrap
Shift voltage signal is included, the voltage signal generates sub-circuit and is used to carry out reverse phase to the control voltage signal, to be moved
Position voltage signal.
For example, when the shift register cell needs two voltage signals (first voltage signal and second voltage signal)
When, when the first voltage signal and the second voltage signal inversion, sequence controller can only provide first voltage signal,
Sub-circuit being generated by the voltage signal, operated in anti-phase being carried out to the first voltage signal, second voltage letter can be obtained
Number.
Specifically, it includes that first voltage signal generates transistor and second voltage signal that the voltage signal, which generates sub-circuit,
Generate transistor；
The control electrode that the first voltage signal generates transistor accesses the control voltage signal, the first voltage letter
The first pole and the second voltage signal for number generating transistor generate the second pole of transistor and are electrically connected, and the first voltage is believed
Number generate transistor the second pole be electrically connected with the first level terminal；The first pole that the first voltage signal generates transistor is used for
Export the shift voltage signal；
The second voltage signal generates the control electrode of transistor and the second voltage signal generates the first of transistor
Pole is all electrically connected with second electrical level end.
As shown in fig. 6, the embodiment that the voltage signal generates sub-circuit may include that first voltage signal generates crystalline substance
Body pipe M61 and second voltage signal generate transistor M62；
The first voltage signal generates the first control of the grid access voltage signal VDDO0 of transistor M61, and described first
The drain electrode that voltage signal generates transistor M61 is electrically connected with the source electrode of second voltage signal generation transistor M62, and described the
The source electrode that one voltage signal generates transistor M61 is electrically connected with low level end；The first voltage signal generates transistor M61's
Drain electrode is for exporting the first shift voltage signal VDDO；
The second voltage signal generates the grid of transistor M62 and the second voltage signal generates transistor M62's
Drain electrode is all electrically connected with high level end；
The low level end is used for input low level VGL, and the high level end is used for input high level VGH.
In the embodiment shown in fig. 6, the breadth length ratio of M61 needs the breadth length ratio greater than M62, in the preferred case, M61's
The ratio of breadth length ratio and the breadth length ratio of M62 can be greater than 2:1, can ensure when the current potential of VDDO0 is high level, VDDO's
Current potential is low level.
In the embodiment shown in fig. 6, M61 and M62 is that (N-type Metal-oxide-semicondutor is brilliant for N-type TFT
Body pipe), but not limited to this.
In embodiments of the present invention, VGL can be -6V, and VGH can be 28V, and but not limited to this.
As shown in fig. 7, present invention voltage signal as shown in FIG. 6 generates the embodiment of sub-circuit at work,
It is 3.3V, M61 and M62 opening in the current potential of first voltage output stage t71, VDDO0, the current potential of VDDO is VGL；
It is -3.3V in the current potential of second voltage output stage t72, VDDO0, M62 is opened, M61 shutdown, and the current potential of VDDO is
VGH。
Illustrate gate driving circuit of the present invention below by two specific embodiments.
As shown in figure 8, the first specific embodiment of gate driving circuit of the present invention includes N grades of shift register lists
Member and signal generating circuit；N is the integer greater than 2；
In fig. 8, it is first order shift register cell marked as S1, is second level shift register marked as S2
Unit is N grades of shift register cells marked as SN, is gate drive signal output end marked as Out；Marked as
Input is input terminal；
The signal generating circuit includes that clock signal generates sub-circuit 81, initial signal generates sub-circuit 82 and voltage letter
Number generate sub-circuit 83, wherein
It includes that the first clock signal generates transistor M11, the life of second clock signal that the clock signal, which generates sub-circuit 81,
Transistor M13 is generated at transistor M12, third clock signal and the 4th clock signal generates transistor M14, wherein
Grid access the first control clock signal clk 1 of the first clock signal generation transistor M11, described first
The drain electrode that clock signal generates transistor M11 is electrically connected with the source electrode of second clock signal generation transistor M12, and described the
The source electrode that one clock signal generates transistor M11 is electrically connected with low level end；First clock signal generates transistor M11's
Drain electrode is for exporting the first shift clock signal CKo1 to the N grades of shift register cell；
The second clock signal generates the grid of transistor M12 and the second clock signal generates transistor M12's
Drain electrode is all electrically connected with high level end；
The third clock signal generates grid access the second control clock signal clk 2 of transistor M13, the third
The drain electrode that clock signal generates transistor M13 is electrically connected with the source electrode of the 4th clock signal generation transistor M14, and described the
The source electrode that three clock signals generate transistor M13 is electrically connected with low level end；The third clock signal generates transistor M13's
Drain electrode is for exporting the second shift clock signal CKo2 to the N grades of shift register cell；
4th clock signal generates the grid of transistor M14 and the 4th clock signal generates transistor M14's
Drain electrode is all electrically connected with high level end；
It includes that the first initial signal generates transistor M3 and the life of the second initial signal that the initial signal, which generates sub-circuit 82,
At transistor M4；
First initial signal generates the grid access control initial signal STV0 of transistor M3, the first starting letter
Number generate transistor M3 drain electrode with second initial signal generate transistor M4 source electrode be electrically connected, it is described first originate believe
Number generate transistor M3 source electrode be electrically connected with low level end；First initial signal generates the drain electrode of transistor M3 for defeated
The input terminal of shift clock signal STV to the first order shift register cell S1 out；The low level end is low for inputting
Level VGL；
Second initial signal generates the leakage of the grid and second initial signal generation transistor M4 of transistor M4
Pole is all electrically connected with high level end；The high level end is used for input high level VGH；
It includes that first voltage signal generates transistor M61, second voltage signal generates that the voltage signal, which generates sub-circuit,
Transistor M62, tertiary voltage signal generate transistor M63 and the 4th voltage signal generates transistor M64；
The first voltage signal generates the first control of the grid access voltage signal VDDO0 of transistor M61, and described first
The drain electrode that voltage signal generates transistor M61 is electrically connected with the source electrode of second voltage signal generation transistor M62, and described the
The source electrode that one voltage signal generates transistor M61 is electrically connected with low level end；The first voltage signal generates transistor M61's
Drain electrode is for exporting the first shift voltage signal VDDO to the N grades of shift register cell；
The second voltage signal generates the grid of transistor M62 and the second clock signal generates transistor M62's
Drain electrode is all electrically connected with high level end；
The tertiary voltage signal generates the second control of the grid access voltage signal VDDE0 of transistor M63, and described first
The drain electrode that voltage signal generates transistor M61 is electrically connected with the source electrode of the 4th voltage signal generation transistor M64, and described the
The source electrode that three voltage signals generate transistor M63 is electrically connected with low level end；The tertiary voltage signal generates transistor M63's
Drain electrode is for exporting the second shift voltage signal VDDE to the N grades of shift register cell；
4th voltage signal generates the grid of transistor M64 and the 4th voltage signal generates transistor M64's
Drain electrode is all electrically connected with high level end.
In the first specific embodiment of gate driving circuit of the present invention, all transistors are all N-type film
Transistor, but not limited to this.
In the first specific embodiment of gate driving circuit of the present invention,
The breadth length ratio of M11 needs the breadth length ratio greater than M12, in the preferred case, the breadth length ratio of M11 and the breadth length ratio of M12
Ratio can be greater than 2:1, can ensure when the current potential of CLK1 is as high level, the current potential of CKo1 is low level；
The breadth length ratio of M13 needs the breadth length ratio greater than M14, in the preferred case, the breadth length ratio of M13 and the breadth length ratio of M14
Ratio can be greater than 2:1, can ensure when the current potential of CLK2 is as high level, the current potential of CKo2 is low level；
The breadth length ratio of M3 needs the breadth length ratio greater than M4, in the preferred case, the ratio of the breadth length ratio of the breadth length ratio and M4 of M3
Value can be greater than 2:1, and can ensure when the current potential of STV0 is high level, the current potential of STV is low level；
The breadth length ratio of M61 needs the breadth length ratio greater than M62, in the preferred case, the breadth length ratio of M61 and the breadth length ratio of M62
Ratio can be greater than 2:1, can ensure when the current potential of VDDO0 is as high level, the current potential of VDDO is low level；
The breadth length ratio of M63 needs the breadth length ratio greater than M64, in the preferred case, the breadth length ratio of M63 and the breadth length ratio of M64
Ratio can be greater than 2:1, can ensure when the current potential of VDDE0 is as high level, the current potential of VDDE is low level；
Also, VGH can be+28V, and VGL can be -6V, and but not limited to this.
In embodiments of the present invention, VDDO and VDDE is direct current noise reduction voltage signal, and STV is frame start signal.
First specific embodiment of gate driving circuit of the present invention at work, as shown in figure 9,
In first time period t1, the current potential of CLK1 is -3.3V, and M12 is opened, and M11 shutdown, the current potential of CKo1 is VGH；CLK2
Current potential be that -3.3V, M14 and M13 are opened, the current potential of CKo2 is VGL；The current potential of STV0 is -3.3V, and M4 is opened, M3 shutdown,
The current potential of STV is VGH；
In second time period t2, the current potential of CLK1 is 3.3V, M11 and M12 opening, and the current potential of CKo1 is VGL；The electricity of CLK2
Position is -3.3V, and M14 is opened, and M13 shutdown, the current potential of CKo2 is VGH；The current potential of STV0 is+3.3V, M4 and M3 opening, STV's
Current potential is VGL；
It is 3.3V, M61 and M62 opening in the current potential of first voltage output stage t71, VDDO0, the current potential of VDDO is VGL；
The current potential of VDDE0 is -3.3V, and M64 is opened, and M6 shutdown, the current potential of VDD3 is VGH；
It is -3.3V in the current potential of second voltage output stage t72, VDDO0, M62 is opened, M61 shutdown, and the current potential of VDDO is
VGH；The current potential of VDDE0 is 3.3V, M64 and M63 opening, and the current potential of VDDE is VGL.
In the first specific embodiment of present invention gate driving circuit as shown in Figure 8, the signal generating circuit pair
It controls signal and carries out reverse phase and level conversion, generate displacement coherent signal, and the displacement coherent signal is provided to the shifting
Bit register unit.
As shown in Figure 10, the second specific embodiment of gate driving circuit of the present invention includes N grades of shift registers
Unit and signal generating circuit；N is the integer greater than 2；
It is first order shift register cell marked as S1 in Figure 10, is second level shift LD marked as S2
Device unit is N grades of shift register cells marked as SN, is gate drive signal output end marked as Out；Marked as
Input is input terminal；
The signal generating circuit includes that clock signal generates sub-circuit 81, initial signal generates sub-circuit 82 and voltage letter
Number generate sub-circuit 83, wherein
It includes that the first clock signal generates transistor M11 and the life of second clock signal that the clock signal, which generates sub-circuit 81,
At transistor M12, wherein
Grid access the first control clock signal clk 1 of the first clock signal generation transistor M11, described first
The drain electrode that clock signal generates transistor M11 is electrically connected with the source electrode of second clock signal generation transistor M12, and described the
The source electrode that one clock signal generates transistor M11 is electrically connected with low level end；First clock signal generates transistor M11's
Drain electrode is for exporting the first shift clock signal CKo1 to the N grades of shift register cell；And the N grades of shift register list
Member is respectively connected to the first control clock signal clk 1；
The second clock signal generates the grid of transistor M12 and the second clock signal generates transistor M12's
Drain electrode is all electrically connected with high level end；
It includes that the first initial signal generates transistor M3 and the life of the second initial signal that the initial signal, which generates sub-circuit 82,
At transistor M4；
First initial signal generates the grid access control initial signal STV0 of transistor M3, the first starting letter
Number generate transistor M3 drain electrode with second initial signal generate transistor M4 source electrode be electrically connected, it is described first originate believe
Number generate transistor M3 source electrode be electrically connected with low level end；First initial signal generates the drain electrode of transistor M3 for defeated
The input terminal of shift clock signal STV to the first order shift register cell S1 out；The low level end is low for inputting
Level VGL；
Second initial signal generates the leakage of the grid and second initial signal generation transistor M4 of transistor M4
Pole is all electrically connected with high level end；The high level end is used for input high level VGH；
It includes that first voltage signal generates transistor M61 and the generation of second voltage signal that the voltage signal, which generates sub-circuit,
Transistor M62；
The first voltage signal generates the first control of the grid access voltage signal VDDO0 of transistor M61, and described first
The drain electrode that voltage signal generates transistor M61 is electrically connected with the source electrode of second voltage signal generation transistor M62, and described the
The source electrode that one voltage signal generates transistor M61 is electrically connected with low level end；The first voltage signal generates transistor M61's
Drain electrode is for exporting the first shift voltage signal VDDO to the N grades of shift register cell；The N grades of shift register cell
Access the first control voltage signal VDD0；
The second voltage signal generates the grid of transistor M62 and the second clock signal generates transistor M62's
Drain electrode is all electrically connected with high level end；
In the second specific embodiment of gate driving circuit of the present invention, all transistors are all N-type film
Transistor, but not limited to this.
In the second specific embodiment of gate driving circuit of the present invention,
The breadth length ratio of M11 needs the breadth length ratio greater than M12, in the preferred case, the breadth length ratio of M11 and the breadth length ratio of M12
Ratio can be greater than 2:1, can ensure when the current potential of CLK1 is as high level, the current potential of CKo1 is low level；
The breadth length ratio of M3 needs the breadth length ratio greater than M4, in the preferred case, the ratio of the breadth length ratio of the breadth length ratio and M4 of M3
Value can be greater than 2:1, and can ensure when the current potential of STV0 is high level, the current potential of STV is low level；
The breadth length ratio of M61 needs the breadth length ratio greater than M62, in the preferred case, the breadth length ratio of M61 and the breadth length ratio of M62
Ratio can be greater than 2:1, can ensure when the current potential of VDDO0 is as high level, the current potential of VDDO is low level；
Also, VGH can be+28V, and VGL can be -6V, and but not limited to this.
Second specific embodiment of gate driving circuit of the present invention at work, as shown in figure 11,
In first time period t1, the current potential of CLK1 is -6V, and M12 is opened, and M11 shutdown, the current potential of CKo1 is VGH；STV0's
Current potential is -3.3V, and M4 is opened, and M3 shutdown, the current potential of STV is VGH；
In second time period t2, the current potential of CLK1 is 28V, M11 and M12 opening, and the current potential of CKo1 is VGL；The electricity of STV0
Position is that+3.3V, M4 and M3 are opened, and the current potential of STV is VGL；
It is 28V, M61 and M62 opening in the current potential of first voltage output stage t71, VDDO0, the current potential of VDDO is VGL；
It is -6V in the current potential of second voltage output stage t72, VDDO0, M62 is opened, M61 shutdown, and the current potential of VDDO is
VGH。
In the second specific embodiment of present invention gate driving circuit as shown in Figure 10, the signal generating circuit pair
Control initial signal carries out reverse phase and goes forward side by side line level conversion, generates displacement initial signal, and the displacement initial signal is provided
To first order shift register cell；The signal generating circuit carries out reverse phase to control clock signal, obtains shift clock letter
Number, and the control clock signal and shift clock signal are all provided to the shift register cell；The signal generates
Circuit carries out reverse phase to control voltage signal, obtains shift voltage signal, and the control voltage signal and shift voltage are believed
Number it is all provided to the shift register cell, so as to reduce the output channel quantity of sequence controller.
Display device described in the embodiment of the present invention includes above-mentioned gate driving circuit.
In the specific implementation, display device described in the embodiment of the present invention further includes sequence controller；
The sequence controller is used to provide the described control signal.
The embodiment of the present invention increases a small number of thin film transistor (TFT)s on the basis of sequence controller and gate driving circuit
It realizes level conversion function, while being able to achieve the function of phase inverter, advantageously reduce the output channel quantity of sequence controller.
Display device provided by the embodiment of the present invention can be mobile phone, tablet computer, television set, display, notebook
Any products or components having a display function such as computer, Digital Frame, navigator.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (11)
1. a kind of gate driving circuit, including multi-stage shift register unit, which is characterized in that the gate driving circuit also wraps
Include signal generating circuit；
The signal generating circuit is used to generate displacement coherent signal according to control signal, and output signal is provided to described
Shift register cell；
The output signal includes the displacement coherent signal；Alternatively, the output signal includes the control signal and described
Shift output signal.
2. gate driving circuit as described in claim 1, which is characterized in that the control signal includes control clock signal,
The displacement coherent signal includes shift clock signal；The signal generating circuit includes that clock signal generates sub-circuit；
The clock signal generates sub-circuit and is used to generate shift clock signal according to control clock signal, and controls the displacement
The absolute value of the current potential of clock signal is greater than the absolute value of the current potential of the control clock signal, and by the shift clock signal
It is provided to the shift register cell.
3. gate driving circuit as described in claim 1, which is characterized in that the control signal includes control clock signal,
The displacement coherent signal includes shift clock signal；The signal generating circuit includes that clock signal generates sub-circuit；
The clock signal generates sub-circuit and is used to carry out reverse phase to the control clock signal, to obtain shift clock signal,
And the control clock signal and the shift clock signal are provided to the shift register cell.
4. gate driving circuit as claimed in claim 2 or claim 3, which is characterized in that the clock signal generates sub-circuit and includes
First clock signal generates transistor and second clock signal generates transistor；
The control electrode that first clock signal generates transistor accesses the control clock signal, and first clock signal is raw
It is electrically connected at the first pole of transistor with the second pole that the second clock signal generates transistor, first clock signal is raw
It is electrically connected at the second pole of transistor with the first level terminal；First clock signal generates the first pole of transistor for exporting
The shift clock signal；
The second clock signal generates the control electrode of transistor and the second clock signal generates the first pole of transistor all
It is electrically connected with second electrical level end.
5. gate driving circuit as described in claim 1, which is characterized in that the control signal includes control initial signal,
The displacement coherent signal includes displacement initial signal；The signal generating circuit includes that initial signal generates sub-circuit；
The initial signal generates sub-circuit and is used to carry out the control initial signal reverse phase, and originates to the control after reverse phase
Signal carries out level conversion, to obtain the displacement initial signal, and the displacement initial signal is provided to the multistage shifting
First order shift register cell in bit register unit.
6. gate driving circuit as claimed in claim 5, which is characterized in that it includes first that the initial signal, which generates sub-circuit,
Initial signal generates transistor and the second initial signal generates transistor；
The control electrode that first initial signal generates transistor accesses the control initial signal, and first initial signal is raw
It is electrically connected at the first pole of transistor with the second pole that second initial signal generates transistor, first initial signal is raw
It is electrically connected at the second pole of transistor with the first level terminal；First initial signal generates the first pole of transistor for exporting
The displacement initial signal；
Second initial signal generates the control electrode of transistor and second initial signal generates the first pole of transistor all
It is electrically connected with second electrical level end.
7. gate driving circuit as described in claim 1, which is characterized in that the control signal includes control voltage signal,
The displacement coherent signal includes shift voltage signal；The signal generating circuit includes that voltage signal generates sub-circuit；
The voltage signal generates sub-circuit and is used to generate shift voltage signal according to control voltage signal, and controls the displacement
The absolute value of the current potential of voltage signal is greater than the absolute value of the current potential of the control voltage signal, and by the shift voltage signal
It is provided to the shift register cell.
8. gate driving circuit as described in claim 1, which is characterized in that the control signal includes control voltage signal,
The displacement coherent signal includes shift voltage signal；The signal generating circuit includes that voltage signal generates sub-circuit；
The voltage signal generates sub-circuit and is used to carry out reverse phase to the control voltage signal, to obtain shift voltage signal,
And the control voltage signal and the shift voltage signal are provided to the shift register cell.
9. gate driving circuit as claimed in claim 7 or 8, which is characterized in that the voltage signal generates sub-circuit and includes
First voltage signal generates transistor and second voltage signal generates transistor；
The control electrode that the first voltage signal generates transistor accesses the control voltage signal, and the first voltage signal is raw
It is electrically connected at the first pole of transistor with the second pole that the second voltage signal generates transistor, the first voltage signal is raw
It is electrically connected at the second pole of transistor with the first level terminal；The first voltage signal generates the first pole of transistor for exporting
The shift voltage signal；
The second voltage signal generates the control electrode of transistor and the second voltage signal generates the first pole of transistor all
It is electrically connected with second electrical level end.
10. a kind of display device, which is characterized in that including the gate driving as described in any claim in claim 1 to 9
Circuit.
11. display device as claimed in claim 10, which is characterized in that further include sequence controller；
The sequence controller is used to provide the described control signal.
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| CN1256480A (en) * | 1998-11-04 | 2000-06-14 | 松下电器产业株式会社 | Operating circuit and built-in drive circuit for liquid crystal display panel using the operating circuit |
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