KR950009728A - BiCMOS semiconductor memory device - Google Patents

Abstract

The level converting circuit comprises a MOS transistor Q3 which receives an input signal at a gate, a MOS transistor Q1 which is conducted in accordance with a reference voltage (Vref) and an input signal, and a MOS transistor constituting a current mirror in which the current from the transistor Q1 functions as a current mirror current source. The thinners Q2 and Q4, and the capacitance element Cs which transfers an input signal to the gates of the current mirror transistors Q2 and Q4 by capacitive coupling, are included.

Transistor Q3 charges output node NB to the level of power supply potential Vcc, and transistor Q4 discharges output node NB to the level of second power source potential Vee.

When the input signal is at a high level, the gate potentials of the transistors Q2 and Q4 rise rapidly by capacitive coupling. By reducing the amount of current supplied by the transistors Q1 and Q2, a level change circuit that operates at a high speed with a small current consumption can be realized.

When this level change circuit is applied to a semiconductor memory device, it is possible to obtain a semiconductor memory device which operates at a high speed while having a low current consumption.

The semiconductor memory device also includes a bit line load circuit, a redundant repairing circuit, and an internal power supply voltage conversion circuit for realizing low power consumption.

Description

BiCMOS semiconductor memory device

Since this is an open matter, no full text was included.

1 is a view schematically showing the overall structure of a semiconductor memory device according to the present invention;

2 is a view showing a specific structure of a level conversion circuit according to the present invention.

Claims (73)

A signal input node (NA; NA1); A first switching element (Q2; MQ2), in which one conductive electrode node and a control electrode node are connected to each other, and connected according to a potential level of an input signal applied to the input node; A signal output node NB; A second switching element (Q4; MQ4) connected to a control electrode node of the first switching element and driving the signal output node to a predetermined potential level; And a capacitor (Cs) for transferring the input signal to the control electrodes of the first and second switching devices by capacitive coupling. The semiconductor circuit according to claim 1, further comprising a third switching element (Q1) provided between said signal input node and said one conducting electrode node and receiving a predetermined reference potential at a control electrode node. The semiconductor circuit according to claim 1, further comprising a third switching element (Q1) connected between said output node and a node receiving another power supply potential, and a control electrode node connected to said input node. The method of claim 1, wherein the capacitor Cs is formed between the first conductive layer 52 and the second conductive layer 53, and the first and second conductive layers, respectively, connected to the input node. And a third conductive layer (54) connected to an electrode node and said one conducting electrode node of said first switching element. The semiconductor circuit according to claim 1, further comprising clamping elements (Q6; PQ2) for clamping the potential of the control electrode node of the first switching element to a predetermined potential level. 6. A semiconductor circuit according to claim 5, wherein the clamping elements (Q6; PQ2) are bipolar transistors (Q6) operating in an emitter follower manner to transfer a reference potential to the control electrode node of the first transistor element. According to claim 1, (a) has a threshold voltage to be turned on and receives a reference voltage through the resistance element (R) to the control electrode node and a conductive terminal has a potential lower than the potential of the control electrode node by the threshold voltage A transistor element Q6 to be transferred to the control electrode node of the first switching element, and (b) another capacitor element Cc connected between the input node and the control electrode of the transistor element Q6. The semiconductor circuit which has further. The semiconductor circuit according to claim 1, wherein said first switching element (Q2) and said second switching element (Q4) constitute a current mirror circuit. 2. The apparatus of claim 1, further comprising: another signal input node (NA2) for receiving another input signal complementary to the input signal; And a third switching element (MQ3) for supplying current to the second switching element in response to the another input signal. A semiconductor circuit according to claim 1, further comprising latch / amplification means (IV, Q5; IVA, IVB) for amplifying and latching the potential of the output node. A signal input node NA; A signal output node NB; A switching element (QA; QB) having a control electrode node and driving the output node to a level of a power potential according to the potential of the control electrode node; A capacitor (CA; CB) provided between the signal input node and a control electrode node of the switching element; And a potential holding means (RA; RB) for maintaining the control electrode node of the switching element at a predetermined potential level. The method of claim 11, wherein the switching element (QA) has a threshold voltage for turning on, one conducting electrode node is connected to receive the power potential and the other conducting electrode node is connected to the signal output node A semiconductor circuit comprising an insulated gate transistor, wherein the potential holding means RA includes an element for maintaining a voltage between the control electrode node and the one conductive electrode node of the switching element at the threshold voltage; . 12. The apparatus of claim 11, further comprising: another switching element (QB) QA having a control electrode node and transferring another power supply potential to the signal output node in response to a potential of the control electrode node; A potential holding means (RB) RA for holding the potential of the control electrode node of the element at a predetermined potential and another capacitor connected between the signal input node and the control electrode node of the another switching element; A semiconductor circuit further comprising (RB; RA). The method of claim 13, wherein the switching device QB has a threshold voltage for turning on, and one conducting electrode node is connected to receive the another power potential, and another conducting electrode node is connected to the signal. An insulated gate transistor connected to an output node, wherein said another potential holding means RB applies a potential equal to the sum of said threshold voltage and said another power supply potential of said another switching element. A semiconductor circuit comprising an element (RB; RA). A first signal input node (/ IN1, IN1); Second signal input nodes IN2 and IN2; Signal output nodes D1, D2; D3, D4; A connecting OR logic gate receiving a potential of the first and second signal input nodes; A first transistor element Q2 conducting in response to the potential level of the output of the connected OR logic gate; And a second transistor (Q4) or the like connected to the first transistor in a current mirror form to drive the signal output node at a level of a power potential. The capacitor Cs of claim 15, wherein the control electrode nodes of the first and second transistors Q2 and Q4 are capacitively coupled to the output nodes of the connection OR logic gates D1, D2; D3 and D4. The semiconductor circuit further having. 16. The device of claim 15, wherein the connected OR logic gates (D1, D2; D3, D4) comprise a first diode (D1; D3) with an anode connected to the first signal input, and an anode with the second signal. And a second diode (D2; D4) connected to an input and having a cathode of the first diode and a cathode of the second diode connected to each other. 17. The capacitor of claim 16, wherein the capacitor Cs is formed on the first conductive layer 65 connected to the control electrode nodes of the first and second transistors Q2 and Q4, and on the first conductive layer. And a second conductive layer (64) formed at and connected to a signal output node of said connection OR logic gates (D1, D2; D3, D4). 18. The n-type impurity region according to claim 17, wherein the first diode D1 is an anode of the first p-type impurity region 61 formed on the surface of the semiconductor body region 60. And (63) as a cathode, wherein the second diode (D2) includes a p-type impurity region formed on the surface of the semiconductor body as an anode and the n-type impurity region as a cathode. 16. The third transistor device of claim 15, further comprising a third transistor device having a control electrode node connected between an output node of the connection OR logic gates D3 and D4 and the first transistor element Q1, and having a predetermined reference potential. A semiconductor circuit further having (Q1). The method of claim 15, wherein the third signal input node (IN1) receiving the input signal complementary to the input signal applied to the first input node (IN1) and one conductive electrode node to receive another power potential. A third transistor element PQ1 connected to another conducting electrode node connected to the first transistor element, a control electrode node receiving an input signal applied to the third signal input node, and applied to the second input node; The fourth signal input node IN2 receiving an input signal complementary to the input signal, and one conductive electrode node are connected to receive another power potential, and the other conductive terminal is connected to the first transistor element Q1. And a fourth transistor (PQ2) connected to a control electrode node to receive an input signal applied to the fourth signal input node. 16. The display device of claim 15, further comprising: a third transistor element (PQ3; PQ5) connected in response to an input signal applied to the first signal input node (/ IN, IN1), and the second signal input node (/ IN2; A fourth transistor element (PQ4; PQ6) conducted in response to an input signal applied to IN2), and a semiconductor further having another power supply potential delivered when both the third and fourth transistor elements are conducted; Circuit. A circuit for generating a reference voltage used in the level converting circuit 65 for converting the logic amplitude of an input signal, wherein the level converting circuit 65 is turned on in response to a first level potential of the input signal to generate a signal output node ( A first transistor element Q2 for driving Out to a level of a first power supply potential, and a second transistor element Q1 that is connected when the input signal is at a potential of a second level while receiving the reference voltage from a control electrode node; And a driving stage (Q3, Q4) for operating the output node to the second power potential level by operating in the form of a current mirror to be in communication with the second transistor (Q1), the first transistor element ( A third transistor element MP1 provided corresponding to Q2) and conducting when receiving the first level potential from a control electrode to supply current from the first power supply potential supply node; and corresponding to the second transistor element. Is provided by A fourth transistor element MP2 receiving the second level potential at the conductive electrode node, receiving the reference voltage at the control electrode node, and supplying a current from the one conductive electrode node to the other conductive electrode node; Means (OP) for maintaining a constant ratio of currents supplied from the third and fourth transistor elements, and means for generating the reference voltage according to currents supplied from the third and fourth transistor elements. And a means (OP, R1, R2) for generating the reference voltage. 24. The apparatus of claim 23, wherein the means for generating the reference voltage (OP, R1, R2) comprises: current / voltage converting means (R1, R2) for converting current supplied from the third and fourth transistor elements into voltage; And differential amplifying means (OP) for differentially amplifying the voltage converted by said current / voltage converting means to generate said reference voltage. 25. The device of claim 24, wherein the current / voltage converting means (R1, R2) are connected between the fourth transistor element (MP2) and the second power supply potential supply node and the applied voltage is applied to the negative input of the differential amplifying means. A second resistance element connected between the applied first resistance element R2, the third transistor MP1 and the second power supply potential supply node, and the applied voltage being applied to the positive input of the differential amplification means; A semiconductor circuit comprising (R1). 25. The method of claim 24, wherein the first transistor element (Q2) is the first transistor (transconductance) β1, the second transistor element (Q1) is the second transistor (β2) The third transistor element (MP1) is a third And a fourth transistor element (MP2) having a fourth transconductance β4, wherein β1 / β2 = β3 / β4. A circuit for generating a reference voltage used in the level converting circuit 65 for converting the logic amplitude of an input signal, wherein the level converting circuit 65 is turned on in response to the first level shift of the input signal to produce a signal output node. A first transistor element (Q2) for driving N to a first power potential level, a second transistor element (Q1) receiving the reference voltage from a control electrode node and conducting when the input signal is at a second level potential; And a driving stage (Q3, Q4) for driving the signal output node to the second power potential level by operating in the form of a current mirror when the second transistor is conductive, and receives the first level potential from the control electrode node. A third transistor element DQ2 for supplying current from the first power potential supply node; Mirror current is generated by 'reflecting' the current supplied from the third transistor element DQ2 in the form of a current mirror, and the ratio of the mirror current and the current supplied by the third transistor is the second transistor element Q1. Current mirror means (DQ3, DQ4) corresponding to a ratio of the current supplied by the first transistor element (Q2) and the current supplied by the first transistor element (Q2); And a means (DQ1; DQ1, BP1, MN1) for converting the mirror current into a voltage to generate the reference voltage. 28. The current mirror means of claim 27, wherein the conversion means DQ1 (DQ1, BP1, MN1) receives the second level potential at one conductive electrode node and a control electrode node and the other conductive electrode node are interconnected to each other. A semiconductor circuit comprising a fourth transistor element (DQ1) for supplying current to (DQ3, DQ4). 29. The method of claim 28, wherein the first transistor element (Q2) is a first transistor conductance β1, the second transistor element (Q1) is a second transistor conductance β2, the third transistor element (DQ2) is a third transistor conductance. and? 4, wherein the fourth transistor (DQ1) has a fourth transconductance? 4 and is? 1 /? 2-? 3 /? 4. 28. The device of claim 27, wherein the means for conversion (DQ1; DQ1, BP1, MN1) are resistor connected to provide current to the current mirror means (DQ3, DQ4) for generating the mirror current from a first power supply potential supply node. A fifth transistor device BP1 having a fourth transistor DQ1 and a threshold voltage for turning on, and transferring the voltage lower than the voltage generated by the fourth transistor device by the threshold voltage to generate the reference voltage; Semiconductor circuit comprising a. Reference potential generating means (80) for generating a reference potential; current generation means (RQ6) for generating a current in accordance with the reference potential; Current mirror means (PR2; PR1) for generating a mirror current flowing in the current mirror form from the current generated by the current generating means from the first power potential supply node (Vcc) to the second power potential supply node (Vee) and ; Reference voltage generating means (RN1) for generating a reference voltage from the mirror current; And a means (MP3; RN2) for adjusting the reference voltage in inverse proportion to the change in the second power source potential. 32. The method of claim 31, wherein the current mirror means (RP2, PR1) are (a) a first transistor element (PR2) and (b) the diode is connected between the first power supply potential supply node and the current generation means (RQ6) And a second transistor element RP1 connected to the first transistor element RP2 in the form of a current mirror to generate the mirror current, wherein the adjusting means MP3; RN1 is arranged in parallel with the first transistor element. And a third transistor element (MP3) connected to and receiving a second power supply potential at a control electrode node. 33. The semiconductor circuit according to claim 32, wherein the conductivity of the first transistor element (RP2) and the third transistor element is the same. The method of claim 31, wherein the reference voltage generating means (RN1) is commonly connected to one conducting electrode node and the control node node output node (ND3) for generating the reference voltage, the other conducting electrode node is A second transistor element having a first transistor element connected to receive a two power potential, and the means for adjustment (MP3; RN2) is connected in parallel with the first transistor element to receive the first power potential at a control electrode node; A semiconductor circuit having (RN2). 32. The semiconductor circuit according to claim 31, wherein said current generating means (RN6) comprises a bipolar transistor (RQ6) receiving said reference voltage at a base electrode node. A resistance element RR20, one end of which is glued to the first potential potential supply node; Current source means (RQ2, RQ1, RQ3, RQ4, RR1-RR6) provided with the other end (ND2) of the resistance element between a second power supply potential supply node and determining the amount of current flowing through the resistance element; An output transistor (RQ10) for generating a reference voltage (VREF1) by transferring a potential of the other end of the resistance element in the form of an emitter follower; And a reference voltage generating circuit (80) having means (MP4, RR21) or the like for adjusting the potential of the other end of the resistance element in inverse proportion to the change of the second power source potential. 37. The method of claim 36, wherein the means for adjusting (MP4, RR21) includes a variable resistance means (MP4) connected in parallel with the resistance element (RR20) and receives the second power potential at the control electrode node, A semiconductor circuit comprising a transistor element (MP4) whose conductance changes in inverse proportion to a change in power supply potential. Normal decoding means for generating a signal for decoding the address signal and selecting a memory cell designated by the address signal when the address signal designates a total memory cell in a memory array including a plurality of memory cells; When the address signal designates a bad memory cell in the memory array, a signal is generated which decodes the address signal to select a spare memory cell for replacement with the bad memory cell and has the same number of logic gates as the normal decode means. A circuit for decoding an address signal having a preliminary decoding means (260) having a logical gate structure different from the number of logical stages. 39. The apparatus of claim 38, wherein the address signal consists of a plurality of bits and the conventional decode means 250 comprises a multi-bit logic gate which receives at the input a predetermined combination of the plurality of bits, wherein the preliminary decode Means (260) comprising input stage inverters (261a to 261c) provided at the input stages corresponding to the plurality of bits. 39. The apparatus according to claim 38, further comprising predecoding means (18) for predecoding an address signal corresponding to an externally applied address signal to apply a predecoded signal as said address signal to said normal and reserved decoding means (250,260). Semiconductor circuit. A transistor device pair (PM, NM) and the transistor according to claim 31, wherein said conventional decode means (250) comprises an inverter (253) at its output stage and said inverter (253) is usually turned on and off complementary to each other. A semiconductor circuit comprising a fusible conductor (Fu) connected between one of a pair of elements and a power supply potential supply node. 39. The apparatus of claim 38, further comprising activation means (270; 285) programmed to generate an activation signal when a bad memory cell is present in the memory array, wherein the preliminary decode means (260) uses the address signal as an input signal, and And an inverter (261aa-261cd) for receiving the activation signal as one operating power potential at an input terminal. Means for generating a spare memory cell use instruction signal indicating that the spare memory cell is usable as a spare decode circuit for replacing the designated defective memory cell with a spare memory cell when the diver address signal designates a defective memory cell ( 272; 285); A plurality of logic gates 261aa-261cd receiving each bit of the address signal; Extra activation means (271; 285) for supplying an operating power supply potential to each of said plurality of logic gates in response to said preliminary memory cell use instruction signal; A logic gate (262; 263; 262a; 262b; 263) of a next stage receiving an output signal of a logic gate selected from the plurality of logic gates through an input signal line; And a fuse element (F00 to F13, F0 to E3; F00a to F13a) provided between each output of said plurality of logic gates and an input signal line of said next logic gate. 44. The semiconductor circuit according to claim 43, wherein the plurality of logic gates (261aa to 261cd) comprise inverters. 44. The logic gate of claim 43 wherein the plurality of logic gates 261aa-261cd are grouped into groups corresponding to each bit of the address signal, and the next logic gates 262, 263; 262a, 263 are (a). First logic gates 262 and 262a receiving the outputs of the first and second groups of the plurality of logic gates on the first and second conductor lines 274, 275; 274a and 275a, respectively; b) an output of the first logical gate and an output of a third group of the plurality of logic gates are received through a corresponding fuse element to a third conductor line, wherein the first to third conductor lines are connected to the input signal line; And a second logic gate (263; 263a) constituting the semiconductor circuit. 45. The logic gate of claim 43, wherein the output of the logic gates 261aa-2611cd of the plurality of logic gates receives the next logic gate 263b of another stage and the output of the corresponding logic gate of the logic gate 261aa-2611cd. A semiconductor circuit further having another fuse element F00b-F13b provided corresponding to the angles of the plurality of logic gates for selectively transferring to a logic gate. A circuit for controlling activation and deactivation of a predetermined circuit, comprising: first and second fuse elements FAa, FBa to FAc, FBc; FCa, FDa, FCb, FDb; 450a, 450b; First setting means (451a, 452) for detecting a break in one of the first and second fuse elements and setting the predetermined circuit in an active or inactive state according to a detection result; Second setting means 451b, 452 for detecting simultaneous connection or simultaneous disconnection of the first and second fuse elements and setting the predetermined circuit to a state different from that set by the first setting means according to a detection result; Activating control circuit. A circuit for controlling activation and deactivation of a predetermined circuit, comprising: first fuse elements 450a and 450b; First detection elements (451a; 462a) for detecting whether the fuse is cut; A second fuse device (450b; 460b) provided separately from the first fuse device; Second detection elements (451b; 462b) for detecting whether the second fuse device is cut off; And a logic gate (452,453; 463a-468a, 463b-468b) logic gates for controlling the activation or deactivation of the predetermined circuit in response to the outputs of the first and second detection elements. 49. The gate controller of claim 48, wherein the logic gates 452, 453; 463a-468a, 463b-468b detect that the outputs of the first and second detection elements are equal in logic. , 465b to 468b). 49. The method of claim 48, wherein the logic gates (452, 453; 463a to 468b) invert the output of the first detection device (462a) and the output of the second detection device (462b). A second inverter 463b for inverting the signal, a first transistor element 465a for receiving the output of the first detection element at the control electrode node, and a control electrode node receiving the output of the second detection element, A second transistor element 465b connected between a first power supply node and an output node receiving one power potential in series with a transistor element, and a third transistor element receiving the output of the first detection element at a control electrode node. 466a and a fourth transistor element 466b connected between the output node and a second power node subjected to another power potential in series with the third transistor element while receiving the output of the second inverter at a control electrode node. And the output of the second inverter to the control electrode. Is a fifth transistor element 467b and a sixth transistor element 467a which receives the output of the first inverter at a control electrode node and is connected between the first power node and the output node in series with the fifth transistor element. And a seventh transistor element 468a receiving the output of the first inverter at a control electrode node, and an output node in series with the seventh transistor element receiving the output of the second detection element at a control electrode node. And an eighth transistor element (468b) connected between said second power supply node. Bit line pairs 155a and 155b connecting memory cells of one column; A pair of transistor elements (241, 242) in which a first conductive node and a control electrode node are cross coupled to each other and the first conductive node is connected to different bit lines of the pair of bit lines; And a device (243) for supplying a potential lower than a power supply potential to another conducting node of each of the pair of transistor elements. A semiconductor memory device for inputting and outputting multibit data, comprising: a first data bus (LDB1; LWB1) provided corresponding to a first data bit of the multibit data; A second data bus (LDB2; LWB2) provided corresponding to the second data bits of the multi-bit data generator; A plurality of bit line pairs B11 to B22 including a specific bit line pair B21 and to which memory cells of one column are connected to each other; Column decode means (6) for decoding an address signal and generating a column select signal for simultaneously designating a pair of bit lines to be connected in parallel to said first and second data buses in said plurality of bit line pairs; First gate means (421a, 421b) connected in response to a first column selection signal from a first output node of said column decode means to couple said particular pair of bit lines to said first data bus; Conducted in response to a second column selection signal from a second output node of the column decode means, connecting the particular bit line pair to the second data bus and generating only one of the first and second gate means. Second gate means (420a, 420b) set to operate in response to the selected column selection signal; Load means for each bit line of the specific bit line pair to raise a potential to a power potential when the first and second column select signals are in an inactive state indicating an unselected state; A semiconductor memory device provided in series with the particular bit line pair and having first and second switching elements 424a and 424b respectively connected in response to an inactive state of the first and second column select signals; . 53. The method of claim 52, wherein the load means (422a, 422b, 423a, 423b; 422a, 422b, 423a, 423b, 25d, 425b, 426a, 426b) delivers a power potential in response to an inactive first column selection signal. A first transistor element 423a, a second transistor element 423b that transmits a power potential in response to an inactive first column selection signal, and a first transistor element in response to an inactive second column selection signal A third transistor element 422a for transmitting the power potential to one bit line through the second transistor element 422a, and a fourth transistor element 422b for transferring the power potential to the other bit line in response to the inactive second column selection signal. And a semiconductor memory device. The fifth transistor element 426a of claim 53, wherein the load means 422a, 422b, 423a, 423b, 425a, 425b, 426a, 426b transfer a power potential in response to an inactive second column selection signal. ), A sixth transistor element 425a which transfers the power potential received from the fifth transistor to one bit line in response to the inactive first column selection signal, and in response to the inactive second column selection signal. A seventh transistor element 426b which transfers a power potential, and an eighth transistor element 425b which transfers a power potential received from the seventh transistor element to another bit line in response to an inactive first column selection signal; And a semiconductor memory device further comprising. 53. The method of claim 52, wherein the specific bit line pair B21 and each of the other bit line pairs B11 to B20 and B22 have a smaller current driving capability than the first and second switching elements 424a and 424b. And a switching element (427) for shorting bit lines of corresponding bit line pairs in response to corresponding column selection signals in an inactive state. 54. The method of claim 53, wherein the current driving is smaller than the first to fourth transistor elements 422a and 423b for each of the specific bit line pair B21 and each of the other bit line pairs B11 to B20 and B22. And a transistor element (426a, 426b) capable of bringing the bit lines of the corresponding bit line pair to the power potential in response to a corresponding column selection signal in an inactive state. Bit line pairs 155a and 155b for connecting one column of memory cells; Recording means (170) for generating a recording gate selection signal for selecting the bit line pair in response to a column selection signal at the time of data writing; A write gate (151) for connecting the bit line pair to write data buses (163a, 163b) in response to the write gate selection signal; A read gate (152) for connecting the bit line pair to a read data bus (164a, 164b) in response to the column select signal; A write driver (33) which remains active for a predetermined time and transfers complementary write data to the write data bus when the column select signal is activated even after the write gate select signal is deactivated at the time of data writing; And precharge means (162a, 162b) for supplying a high potential to a low potential bus line of said read data bus in response to said write gate selection signal deactivation and said write data. 58. The method of claim 57, wherein the precharge means (162a, 162b) is turned on in response to a control signal and the first transistor element (188a) reacts with a potential on one bus line of the write data bus and And a second transistor element 188b connected in series between a power supply node supplying a high potential and a bus line of the read data bus, and a third transistor element turned on in response to the control signal. 189a, and a fourth that is turned on in response to the potential of the other busline of the write data bus and the third and fourth transistor elements are connected in series between the power supply node and another busline of the read data bus. A semiconductor memory device including a transistor element 189b and the like. 58. The apparatus according to claim 57, further comprising: decoding means (25.6) for decoding the applied address signal to generate said column selection signal with a first delay time, and a second shorter than said first delay time in response to a recording mode designation signal. A recording control means 190 for generating a write enable signal for a predetermined time after the delay time, and a third delay time longer than the first and second delay times in response to the second write enable signal being active. Means (31) for activating the write driver (33) with the fourth delay time shorter than the third delay time in response to the write enable signal being inactive; A pulse generator 191 for generating a one-shot pulse signal having a predetermined activation time in response to the enable signal being active, and said one short pulse being active In response to activating the recording means 170, and a semiconductor memory device having an additional means (192) for enabling the pre-charging means (162a, 162b) in response to inde the one-shot pulse is inactive. 58. The apparatus according to claim 57, further comprising: recording control means (190) for generating a write enable signal with a first delay in response to a recording mode designation signal, and in response to the recording enable signal being active; Means (31,192) for activating recording means (170) and for activating the precharge means (162a, 162b) in response to the write enable signal being inactive; and for the recording means in response to the write enable signal. And a means (31) for activating the write driver (33) after activation. Level determining means (901 to 909) having a plurality of comparison reference voltage levels for determining the potential level of the input signal; Means (910-913) for generating an operation mode designation signal for designating a predetermined operation mode in accordance with the output of the level determining means; And a mode setting means (36) for setting the internal circuit to the designated operation mode in response to the operation mode designation signal. 62. The apparatus according to claim 61, wherein the level determining circuits are provided in correspondence with the plurality of voltage drop elements 902 and 903 connected in series to sequentially drop the voltage level of the input signal, and the plurality of voltage drop means. And a plurality of comparators (904 to 909) including a first comparator for comparing an output of the voltage drop element with a different reference voltage and comparing an input signal with a predetermined reference voltage. 63. The semiconductor memory device according to claim 62, wherein each of the plurality of cascaded comparators includes emitter coupling logic, and a common emitter of emitter coupling logic (904 to 909) is coupled to the next transistor element. 62. The N voltage drop device (902, 903) according to claim 61, wherein the level determining means (901 to 909) is connected in series between the first node (930) and the second node (2) receiving the input signal when N is an integer. And (N + 1) first transistors 904, 906, and 908 provided between the corresponding first node 930 and the output nodes of the plurality of voltage drop elements and receiving a signal of a corresponding node from a control electrode and connected in series with each other. ), Which is provided corresponding to the (N + 1) first transistors, receives a different reference voltage from each control node, and a lower conducting node of the first transistor is connected to one conducting node of the corresponding second transistor. And (N + 1) second transistors (905,907,909). 65. The device of claim 64, wherein the means for generating (910-913) are provided corresponding to the first transistor provided for the first node and the (N + 1) second transistors and further conducting corresponding transistors. A memory device on a peninsula comprising (N + 2) third transistor elements (910-913) for generating signals corresponding to the potentials of the nodes. First comparing means (650) for comparing an input signal with a first reference voltage; Second comparing means 660 for comparing the input signal with a second reference voltage; First operation mode designation signal generating means (36) for generating a first operation mode designation signal in response to an output of said first and second comparing means; Mode detection means (750) which is activated in response to the first operation mode designation signal to detect the potential level of the second input signal and generate a mode detection signal in accordance with the detection result; And a mode switching means (770) for setting an internal circuit to an operation mode designated by the mode detection signal in response to the mode detection signal. 67. The semiconductor memory device according to claim 66, wherein said first device; means (650) comprises means (701-715) for activating said second comparing means in response to said input signal. 67. The apparatus of claim 66, wherein the first comparing means 650 generates the second comparing means 660 and the first operation mode designating signal generating means 36 when the internal input signal is higher than the first reference voltage. Semiconductor memory device to activate. 68. The semiconductor memory device according to claim 67, comprising means (726 to 730) for generating a complementary signal according to a result of comparing said input signal with said second reference voltage when said second comparing means (660) is activated. 63. The apparatus of claim 62, further comprising: step-down means (760) which is activated in response to the mode detection signal to step down the power supply voltage according to the potential level of the second input signal; And a power supply voltage switching means (770) for selectively passing the output of the step-down means and the power supply voltage in response to the mode detection signal. 71. The apparatus of claim 70, wherein the second input signal consists of a plurality of bits (x2, x3) and the step-down means are provided corresponding to the plurality of bits, each of different currents in response to the corresponding bits. A plurality of current elements 813, 815, 818, 820 causing a flow, a current adding means 821 for flowing a current corresponding to the sum of the currents generated by the plurality of current elements, and the current adding means And a converter (822, 826) for converting current into voltage. 71. The semiconductor memory device according to claim 70, further comprising a plurality of memory cells (MC) each including a flip-flop having a power supply node (775) for receiving a voltage from the power supply voltage switching means (770). A semiconductor memory device comprising a plurality of static type memory cells MC arranged in rows and columns and operable in a test mode for testing hold voltages of the plurality of memory cells, wherein A plurality of word lines WL disposed corresponding to the rows of the memory cells and respectively connecting the memory cells of the corresponding rows; Means (12) for responding to a test mode designation signal for designating said test mode for holding said plurality of word lines in a mode non-selected state; Means 750 including means 760 and 770 for changing a level of voltage applied to power nodes of a plurality of memory cells in response to the test mode designation signal and for selecting a plurality of predetermined voltage levels in response to an external control signal; 76, 770 and the like. ※ Note: The disclosure is based on the initial application.