JPWO2023026383A5 - - Google Patents
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- JPWO2023026383A5 JPWO2023026383A5 JP2023543539A JP2023543539A JPWO2023026383A5 JP WO2023026383 A5 JPWO2023026383 A5 JP WO2023026383A5 JP 2023543539 A JP2023543539 A JP 2023543539A JP 2023543539 A JP2023543539 A JP 2023543539A JP WO2023026383 A5 JPWO2023026383 A5 JP WO2023026383A5
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- transition
- output terminal
- input terminal
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2021/031085 WO2023026383A1 (ja) | 2021-08-25 | 2021-08-25 | 半導体集積回路装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2023026383A1 JPWO2023026383A1 (https=) | 2023-03-02 |
| JPWO2023026383A5 true JPWO2023026383A5 (https=) | 2024-05-17 |
| JP7709075B2 JP7709075B2 (ja) | 2025-07-16 |
Family
ID=85321906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023543539A Active JP7709075B2 (ja) | 2021-08-25 | 2021-08-25 | 半導体集積回路装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12499963B2 (https=) |
| JP (1) | JP7709075B2 (https=) |
| WO (1) | WO2023026383A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20240162895A1 (en) * | 2022-11-16 | 2024-05-16 | International Business Machines Corporation | Competing path ring-oscillator for direct measurement of a latch timing window parameters |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2748865B2 (ja) * | 1994-09-27 | 1998-05-13 | 日本電気株式会社 | 出力回路 |
| JP2001101870A (ja) * | 1999-09-30 | 2001-04-13 | Fujitsu Ltd | 半導体集積回路 |
| JP2002009601A (ja) * | 2000-06-27 | 2002-01-11 | Fujitsu Ltd | 半導体集積回路および半導体集積回路の初期化方法 |
| JP3939208B2 (ja) * | 2002-06-24 | 2007-07-04 | 富士通株式会社 | 出力パルスサイクルを短くできるパルス発生回路 |
| JP2008219232A (ja) * | 2007-03-01 | 2008-09-18 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
| JP5200506B2 (ja) * | 2007-11-28 | 2013-06-05 | 富士通セミコンダクター株式会社 | メモリ装置 |
| JP2010073282A (ja) * | 2008-09-19 | 2010-04-02 | Nec Electronics Corp | 半導体装置、半導体装置の設計方法 |
| JP5987503B2 (ja) * | 2012-07-02 | 2016-09-07 | 株式会社ソシオネクスト | リング発振器及び半導体装置 |
| JP6217087B2 (ja) | 2013-01-31 | 2017-10-25 | 株式会社ソシオネクスト | リング発振器及び半導体装置 |
| US10964379B2 (en) * | 2018-11-07 | 2021-03-30 | Arm Limited | Ring oscillator based bitcell delay monitor |
-
2021
- 2021-08-25 WO PCT/JP2021/031085 patent/WO2023026383A1/ja not_active Ceased
- 2021-08-25 JP JP2023543539A patent/JP7709075B2/ja active Active
-
2024
- 2024-02-22 US US18/584,725 patent/US12499963B2/en active Active
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