JPWO2020241775A1 - - Google Patents

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Publication number
JPWO2020241775A1
JPWO2020241775A1 JP2021522875A JP2021522875A JPWO2020241775A1 JP WO2020241775 A1 JPWO2020241775 A1 JP WO2020241775A1 JP 2021522875 A JP2021522875 A JP 2021522875A JP 2021522875 A JP2021522875 A JP 2021522875A JP WO2020241775 A1 JPWO2020241775 A1 JP WO2020241775A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021522875A
Other languages
Japanese (ja)
Other versions
JP7307161B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2020241775A1 publication Critical patent/JPWO2020241775A1/ja
Priority to JP2023107470A priority Critical patent/JP7610654B2/ja
Application granted granted Critical
Publication of JP7307161B2 publication Critical patent/JP7307161B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/184—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components inserted in holes through the PCBs and wherein terminals of the components are connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2021522875A 2019-05-29 2020-05-28 電子素子実装用基板、電子装置、および電子モジュール Active JP7307161B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023107470A JP7610654B2 (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019100404 2019-05-29
JP2019100404 2019-05-29
PCT/JP2020/021181 WO2020241775A1 (ja) 2019-05-29 2020-05-28 電子素子実装用基板、電子装置、および電子モジュール

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023107470A Division JP7610654B2 (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Publications (2)

Publication Number Publication Date
JPWO2020241775A1 true JPWO2020241775A1 (enExample) 2020-12-03
JP7307161B2 JP7307161B2 (ja) 2023-07-11

Family

ID=73552185

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2021522875A Active JP7307161B2 (ja) 2019-05-29 2020-05-28 電子素子実装用基板、電子装置、および電子モジュール
JP2023107470A Active JP7610654B2 (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2023107470A Active JP7610654B2 (ja) 2019-05-29 2023-06-29 電子素子実装用基板、電子装置、および電子モジュール

Country Status (4)

Country Link
US (1) US12144114B2 (enExample)
JP (2) JP7307161B2 (enExample)
CN (1) CN113875000A (enExample)
WO (1) WO2020241775A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202539314A (zh) * 2024-01-31 2025-10-01 日商京瓷股份有限公司 配線基板及半導體裝置
WO2025183114A1 (ja) * 2024-02-29 2025-09-04 京セラ株式会社 配線基板および半導体デバイス

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273455A (ja) * 1994-03-30 1995-10-20 Oki Electric Ind Co Ltd 多層セラミック基板及びその製造方法
WO2002074029A1 (fr) * 2001-03-14 2002-09-19 Ibiden Co., Ltd. Carte de circuits imprimes multicouche
JP2004111769A (ja) * 2002-09-20 2004-04-08 Kyocera Corp 電子部品搭載用基板
JP2005072503A (ja) * 2003-08-27 2005-03-17 Kyocera Corp 配線基板およびそれを用いた電子装置
JP2006269692A (ja) * 2005-03-23 2006-10-05 Tdk Corp 多層セラミック基板及びその製造方法
JP2017050391A (ja) * 2015-09-01 2017-03-09 株式会社デンソー 多層基板およびその製造方法
JP2019079987A (ja) * 2017-10-26 2019-05-23 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140621B1 (enExample) * 1971-02-10 1976-11-05
JPS5122060A (ja) * 1974-08-19 1976-02-21 Fujitsu Ltd Tasopurintoban
JPH0717166Y2 (ja) 1988-06-28 1995-04-19 株式会社フジクラ 多層フレキシブルプリント配線板
JP2958492B2 (ja) 1990-03-30 1999-10-06 京セラ株式会社 多層配線回路基板の製造方法
JPH0685457A (ja) 1992-08-31 1994-03-25 Kyocera Corp セラミック多層回路基板及びその製造方法
JP3441318B2 (ja) 1996-11-25 2003-09-02 京セラ株式会社 半導体装置
JP2005150552A (ja) * 2003-11-18 2005-06-09 Ngk Spark Plug Co Ltd 配線基板の製造方法
EP2129201B1 (en) * 2007-03-01 2017-04-12 Murata Manufacturing Co. Ltd. Multilayer wiring substrate
JP5294828B2 (ja) * 2008-01-28 2013-09-18 京セラ株式会社 積層基板
WO2012121141A1 (ja) * 2011-03-07 2012-09-13 株式会社村田製作所 セラミック多層基板およびその製造方法
JP5835282B2 (ja) * 2013-07-04 2015-12-24 株式会社村田製作所 多層配線基板の製造方法およびプローブカードの製造方法並びに多層配線基板およびプローブカード
JP2017123377A (ja) * 2016-01-05 2017-07-13 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
JP6832630B2 (ja) 2016-03-28 2021-02-24 富士通インターコネクトテクノロジーズ株式会社 配線基板の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273455A (ja) * 1994-03-30 1995-10-20 Oki Electric Ind Co Ltd 多層セラミック基板及びその製造方法
WO2002074029A1 (fr) * 2001-03-14 2002-09-19 Ibiden Co., Ltd. Carte de circuits imprimes multicouche
JP2004111769A (ja) * 2002-09-20 2004-04-08 Kyocera Corp 電子部品搭載用基板
JP2005072503A (ja) * 2003-08-27 2005-03-17 Kyocera Corp 配線基板およびそれを用いた電子装置
JP2006269692A (ja) * 2005-03-23 2006-10-05 Tdk Corp 多層セラミック基板及びその製造方法
JP2017050391A (ja) * 2015-09-01 2017-03-09 株式会社デンソー 多層基板およびその製造方法
JP2019079987A (ja) * 2017-10-26 2019-05-23 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

Also Published As

Publication number Publication date
CN113875000A (zh) 2021-12-31
JP2023126865A (ja) 2023-09-12
JP7610654B2 (ja) 2025-01-08
US12144114B2 (en) 2024-11-12
WO2020241775A1 (ja) 2020-12-03
JP7307161B2 (ja) 2023-07-11
US20220361333A1 (en) 2022-11-10

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