JPWO2020179874A1 - - Google Patents

Info

Publication number
JPWO2020179874A1
JPWO2020179874A1 JP2021503650A JP2021503650A JPWO2020179874A1 JP WO2020179874 A1 JPWO2020179874 A1 JP WO2020179874A1 JP 2021503650 A JP2021503650 A JP 2021503650A JP 2021503650 A JP2021503650 A JP 2021503650A JP WO2020179874 A1 JPWO2020179874 A1 JP WO2020179874A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2021503650A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2020179874A1 publication Critical patent/JPWO2020179874A1/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/091—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts by printing or stamping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2021503650A 2019-03-06 2020-03-05 Withdrawn JPWO2020179874A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019040656 2019-03-06
PCT/JP2020/009472 WO2020179874A1 (ja) 2019-03-06 2020-03-05 電子部品装置を製造する方法

Publications (1)

Publication Number Publication Date
JPWO2020179874A1 true JPWO2020179874A1 (https=) 2020-09-10

Family

ID=72337164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021503650A Withdrawn JPWO2020179874A1 (https=) 2019-03-06 2020-03-05

Country Status (4)

Country Link
US (1) US12315760B2 (https=)
JP (1) JPWO2020179874A1 (https=)
TW (1) TWI857019B (https=)
WO (1) WO2020179874A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7714905B2 (ja) * 2021-04-23 2025-07-30 株式会社レゾナック 再配線層を形成する方法、及び、半導体パッケージを製造する方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000059645A1 (en) * 1999-04-01 2000-10-12 Ormet Corporation Methods to produce robust multilayer circuitry for electronic packaging
JP2001513946A (ja) * 1997-03-06 2001-09-04 オアメット コーポレイション 垂直相互接続電子集成体とこれに有用な組成物
JP2005093767A (ja) * 2003-09-18 2005-04-07 Matsushita Electric Ind Co Ltd 回路基板の製造方法および回路基板
JP2005203614A (ja) * 2004-01-16 2005-07-28 Sony Corp 半導体装置の製造方法、半導体装置、電子部品、半導体チップおよびパッケージ基板
JP2010103517A (ja) * 2008-09-29 2010-05-06 Hitachi Chem Co Ltd 半導体素子搭載用パッケージ基板とその製法及び半導体パッケージ
US20130009319A1 (en) * 2011-07-07 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Methods for Forming Through Vias
US20150279805A1 (en) * 2014-03-28 2015-10-01 Omkar G. Karhade Novel method and materials for warpage thermal and interconnect solutions
US20150279804A1 (en) * 2014-03-28 2015-10-01 Nachiket R. Raravikar Lps solder paste based low cost fine pitch pop interconnect solutions
JP2015530705A (ja) * 2012-08-09 2015-10-15 オーメット サーキッツ インク 非共晶はんだ合金を含む電気伝導性組成物
JP2016510169A (ja) * 2013-02-15 2016-04-04 オーメット サーキッツ インク 多層電子基体ｚ軸内部接続構造物
WO2018105125A1 (ja) * 2016-12-09 2018-06-14 日立化成株式会社 組成物、接着剤、焼結体、接合体及び接合体の製造方法
US20180366410A1 (en) * 2017-06-20 2018-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages and methods of forming the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002033562A (ja) * 2000-07-19 2002-01-31 Sony Corp 絶縁層及び接続孔の形成方法、配線構造の形成方法、並びにこれらの方法の実施に使用する型材及びその製造方法
KR101214746B1 (ko) * 2008-09-03 2012-12-21 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP6203493B2 (ja) 2009-11-05 2017-09-27 オーメット サーキッツ インク 冶金ネットワーク組成物の調製およびその使用方法
CN103404239B (zh) * 2011-02-15 2015-11-25 株式会社村田制作所 多层配线基板及其制造方法
JP5884477B2 (ja) 2011-12-27 2016-03-15 日立化成株式会社 半導体装置の製造方法、それにより得られる半導体装置及びそれに用いる熱硬化性樹脂組成物
JP6819599B2 (ja) * 2015-09-25 2021-01-27 大日本印刷株式会社 実装部品、配線基板、電子装置、およびその製造方法
JP2017108046A (ja) * 2015-12-11 2017-06-15 ルネサスエレクトロニクス株式会社 半導体装置
CN106384745B (zh) * 2016-11-16 2019-01-08 京东方科技集团股份有限公司 显示基板的制备方法
US10485091B2 (en) * 2016-11-29 2019-11-19 Nxp Usa, Inc. Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof
WO2018173764A1 (ja) * 2017-03-21 2018-09-27 富士フイルム株式会社 積層デバイス、積層体および積層デバイスの製造方法
US20200273830A1 (en) * 2019-02-27 2020-08-27 Nepes Co., Ltd. Semiconductor device and method for manufacturing the same

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001513946A (ja) * 1997-03-06 2001-09-04 オアメット コーポレイション 垂直相互接続電子集成体とこれに有用な組成物
WO2000059645A1 (en) * 1999-04-01 2000-10-12 Ormet Corporation Methods to produce robust multilayer circuitry for electronic packaging
JP2005093767A (ja) * 2003-09-18 2005-04-07 Matsushita Electric Ind Co Ltd 回路基板の製造方法および回路基板
JP2005203614A (ja) * 2004-01-16 2005-07-28 Sony Corp 半導体装置の製造方法、半導体装置、電子部品、半導体チップおよびパッケージ基板
JP2010103517A (ja) * 2008-09-29 2010-05-06 Hitachi Chem Co Ltd 半導体素子搭載用パッケージ基板とその製法及び半導体パッケージ
US20130009319A1 (en) * 2011-07-07 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Methods for Forming Through Vias
JP2015530705A (ja) * 2012-08-09 2015-10-15 オーメット サーキッツ インク 非共晶はんだ合金を含む電気伝導性組成物
JP2016510169A (ja) * 2013-02-15 2016-04-04 オーメット サーキッツ インク 多層電子基体ｚ軸内部接続構造物
US20150279805A1 (en) * 2014-03-28 2015-10-01 Omkar G. Karhade Novel method and materials for warpage thermal and interconnect solutions
US20150279804A1 (en) * 2014-03-28 2015-10-01 Nachiket R. Raravikar Lps solder paste based low cost fine pitch pop interconnect solutions
WO2018105125A1 (ja) * 2016-12-09 2018-06-14 日立化成株式会社 組成物、接着剤、焼結体、接合体及び接合体の製造方法
US20180366410A1 (en) * 2017-06-20 2018-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages and methods of forming the same

Also Published As

Publication number Publication date
US12315760B2 (en) 2025-05-27
WO2020179874A1 (ja) 2020-09-10
US20220148914A1 (en) 2022-05-12
TW202044955A (zh) 2020-12-01
TWI857019B (zh) 2024-10-01

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