JPWO2018216621A1 - Manufacturing method of semiconductor device and expanding tape - Google Patents

Abstract

A method of manufacturing a semiconductor device including a tape expanding step of expanding the interval between the individualized semiconductor chips 2 fixed on the expanding tape 1 and extending from 100 μm or less to 300 μm or more by stretching the expanding tape 1 while heating. The expanded tape 1 used, wherein the tensile stress at the heating temperature in the tape expanding step is 10 MPa or less, and the tensile stress at room temperature is 5 MPa or more higher than the tensile stress at the heating temperature.

Description

  The present invention relates to a method for manufacturing a semiconductor device and an expandable tape.

2. Description of the Related Art In recent years, as semiconductor devices have become smaller, more sophisticated, and more highly integrated, the number of pins in the semiconductor, the density thereof, and the pitch of wiring have been reduced. Therefore, a fragile layer such as a low-K layer for the purpose of miniaturizing a pin or a wiring or lowering the dielectric constant is applied, and accordingly, a technology for increasing reliability is required.
Against this background, a wafer level package (WLP) technology capable of achieving high reliability and high production has been developed.
The WLP technique is characterized in that assembling is performed in a wafer state, and the wafer is diced in the final step by dicing. It is a technology that enables high production and high reliability because it is assembled (sealed) at a wafer level.
In the WLP technology, a rewiring layer is formed by forming a rewiring pattern with polyimide, copper wiring, etc. on an insulating film on the circuit surface of a semiconductor chip, and metal pads, solder balls, etc. are mounted on the rewiring and connected. Construct bumps for terminals.
The WLP includes a semiconductor package having a package area similar to that of a semiconductor chip, such as a WLCSP (Wafer Level Chip Scale Package) or an FI-WLP (Fan In Wafer Level Package), and a FO-WLP (Fan Out Wafer Level Package). There is a semiconductor package in which the package area is larger than the semiconductor chip area and the terminals can be extended to the outside of the chip. Since such semiconductor packages are rapidly becoming smaller and thinner, after sealing at the wafer level to protect the periphery of the semiconductor chip in order to ensure reliability, a rewiring layer is formed, and the package is formed. Each individual piece is performed.
The reliability is ensured by performing such sealing at the wafer level and subsequent handling such as secondary mounting. Also, in the field of mounting single-function semiconductors such as discrete semiconductors, for the purpose of reducing stress applied to cracks or pads around semiconductor chips at the time of handling, after sealing at the wafer level to protect the semiconductor chip periphery, Each package is singulated and the process proceeds to the next step (SMT process, etc.). Many discrete semiconductors are smaller than the system LCI, and five- or six-surface sealing of the semiconductor chip is particularly required to protect the semiconductor chip at a higher level.

  By the way, in order to seal the side surfaces of the semiconductor chips, it is necessary to widen the intervals between the semiconductor chips after manufacturing the semiconductor chips by dividing the wafer into individual pieces. As a method of increasing the interval between semiconductor chips, a method including a rearrangement step of rearranging individualized semiconductor chips obtained by dicing a semiconductor wafer on a carrier or the like has been proposed (for example, see Non-Patent Documents). 1).

Kang Chen et al., "Innovative Wafer Level Packaging Manufacturing with FlexLine," 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

  However, since the number of semiconductor chips for each wafer increases due to the miniaturization of the semiconductor chips, it has been a problem to lengthen the rearrangement process of rearranging the semiconductor chips using a mounter, a flip chip bonder, or the like. In addition, the chip may be damaged when the chip is mounted in the rearrangement process due to the thinning of the semiconductor chip or the like.

  In view of the above circumstances, the present invention provides a method of manufacturing a semiconductor device which can be reduced in time as compared with a conventional process having a rearrangement step, and causes less damage to a chip, and an expanded tape applicable to the manufacturing method. The purpose is to provide.

As a result of intensive studies, the present inventors have found that the above-mentioned problems can be solved by the inventions described in the following [1] to [9].
[1] A method of manufacturing a semiconductor device including a tape expanding step of extending the interval between individualized semiconductor chips fixed on the expand tape from 100 μm or less to 300 μm or more by stretching the expand tape while heating. Expanding tape used for
An expanded tape having a tensile stress at a heating temperature of a tape expanding step of 10 MPa or less and a tensile stress at a room temperature of 5 MPa or more higher than the tensile stress at the heating temperature.
[2] A method of manufacturing a semiconductor device includes a tension holding step of holding a tension of an expanded expanded tape, a transfer step of transferring a semiconductor chip on the expanded tape holding the tension to a carrier, and a transfer step of transferring the semiconductor chip on the carrier. The expanding tape according to [1], further comprising: a peeling step of peeling the expanding tape from the semiconductor chip.
[3] The expanded tape according to [1] or [2], having a base layer and an adhesive layer.
[4] The expanded tape according to [3], wherein the adhesive layer is composed of an ultraviolet-curable adhesive.
[5] By stretching the expanded tape according to any one of [1] to [4] while heating, the interval between the singulated semiconductor chips fixed on the expanded tape is set to 100 μm or less to 300 μm. A method for manufacturing a semiconductor device, comprising a tape expanding step for expanding the above.
[6] A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first A step of preparing an expanding tape and a plurality of semiconductor chips having a surface opposite to the circuit surface fixed on the expanding tape;
A 2A step of extending the interval between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A third A step of maintaining the tension of the stretched expanded tape,
A fourth A step of transferring the circuit surfaces of the plurality of semiconductor chips onto the carrier so that the circuit surfaces are fixed;
A 5A step of peeling the expanding tape from the plurality of semiconductor chips,
A 6A step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7A step of separating the carrier from the plurality of semiconductor chips sealed by the sealing material,
A method for manufacturing a semiconductor device comprising:
[7] A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first B step of preparing an expanding tape and a plurality of semiconductor chips having a circuit surface fixed on the expanding tape;
A second B step of extending the interval between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A 3B step of maintaining the tension of the stretched expanded tape,
A 4B step of transferring the plurality of semiconductor chips onto the carrier such that the surface opposite to the circuit surface is fixed;
A 5B step of peeling the expanding tape from the plurality of semiconductor chips,
A 6B step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A method for manufacturing a semiconductor device comprising:
[8] A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first C step of preparing an expanding tape and a plurality of semiconductor chips having a surface opposite to a circuit surface fixed on the expanding tape;
A 2C step of extending a gap between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A 3C step of maintaining the tension of the expanded expanded tape,
A 4C step of transferring the circuit surfaces of the plurality of semiconductor chips onto the carrier so that the circuit surfaces are fixed;
A 5C step of peeling the expanding tape from the plurality of semiconductor chips,
A 6C step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7C step of separating the carrier from the plurality of semiconductor chips sealed by the sealing material;
A method of manufacturing a semiconductor device, comprising an 8C step of dividing a plurality of semiconductor chips sealed by a sealing material into individual semiconductor chips to form a plurality of semiconductor packages.
[9] A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first D step of preparing an expanding tape and a plurality of semiconductor chips having a circuit surface fixed on the expanding tape;
A 2D step of extending the interval between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A 3D step of maintaining the tension of the stretched expanded tape,
A 4D step of transferring a surface of the plurality of semiconductor chips to the carrier such that the surface opposite to the circuit surface is fixed;
A 5D step of peeling the expand tape from the plurality of semiconductor chips,
A 6D step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7D step of polishing the sealing material to expose the pad,
An 8D step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material,
A method of manufacturing a semiconductor device, comprising: a ninth step (D) of dividing a plurality of semiconductor chips sealed by a sealing material into individual semiconductor chips to form a plurality of semiconductor packages.

  According to the present invention, it is possible to provide a method of manufacturing a semiconductor device which can be performed in a shorter time as compared with a conventional process having a rearrangement step and which causes less damage to a chip, and an expanded tape applicable to the manufacturing method. be able to.

FIG. 9 is a schematic cross-sectional view for explaining one embodiment of the first to fourth steps in the first method for manufacturing a semiconductor device. FIG. 9 is a schematic cross-sectional view for explaining one embodiment of Steps 5A to 7A in the method for manufacturing a first semiconductor device. It is a schematic cross section for explaining one Embodiment of the 8Ath process and the 9th Ath process in a manufacturing method of the 1st semiconductor device. It is a schematic cross section for explaining one Embodiment of the 1Bth process-the 4Bth process in a manufacturing method of the 2nd semiconductor device. It is a schematic cross section for explaining one Embodiment of the 5Bth process-the 8Bth process in a manufacturing method of the 2nd semiconductor device. It is a schematic cross section for explaining other embodiments of the 7Bth process and the 8Bth process in the manufacturing method of the 2nd semiconductor device. It is a schematic cross section for explaining one Embodiment of the 9B process and the 10B process in a manufacturing method of the 2nd semiconductor device. It is a schematic cross section for explaining one Embodiment of the 1C process-the 4C process in a manufacturing method of the 3rd semiconductor device. It is a schematic cross section for explaining one Embodiment of the 5Cth process-the 8Cth process in a manufacturing method of the 3rd semiconductor device. FIG. 16 is a schematic cross-sectional view for explaining another embodiment of the fourth to eighth steps in the third semiconductor device manufacturing method. It is a schematic cross section for explaining one Embodiment of the 1D process-the 4D process in the manufacturing method of the 4th semiconductor device. It is a schematic cross section for explaining one Embodiment of the 5Dth process-the 9th Dth process in a manufacturing method of the 4th semiconductor device. It is a schematic cross section for explaining other embodiments of the 7D process and the 8D process in the manufacturing method of the 4th semiconductor device. It is a schematic cross section for explaining one Embodiment of the manufacturing method of the 5th semiconductor device. It is a schematic cross section for explaining other embodiments of the manufacturing method of the 5th semiconductor device.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, the same or corresponding parts have the same reference characters allotted, and overlapping description will be omitted. Unless otherwise specified, the positional relationship such as up, down, left, and right is based on the positional relationship shown in the drawings. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

(Method of Manufacturing Semiconductor Device)
[Method of Manufacturing First Semiconductor Device]
The first method for manufacturing a semiconductor device according to the present embodiment includes:
A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first A step of preparing an expanding tape and a plurality of semiconductor chips having a surface opposite to the circuit surface fixed on the expanding tape;
A 2A step of extending the interval between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A third A step of maintaining the tension of the stretched expanded tape,
A fourth A step of transferring the circuit surfaces of the plurality of semiconductor chips onto the carrier so that the circuit surfaces are fixed;
A 5A step of peeling the expanding tape from the plurality of semiconductor chips,
A 6A step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7A step of separating the carrier from the plurality of semiconductor chips sealed by the sealing material,
Forming a rewiring layer having a rewiring pattern from pads of a plurality of semiconductor chips sealed with a sealing material, and connecting terminal pads connected to the semiconductor chip by the rewiring pattern outside the region of the semiconductor chip An 8A step of providing
A ninth step (A) of dividing the semiconductor chip and the connection terminal pads connected thereto into a group to form a plurality of semiconductor packages;
Is provided.

  According to the first method for manufacturing a semiconductor device of the present embodiment, it is possible to manufacture a semiconductor package (FO-WLP) in which the package area is larger than the semiconductor chip area and the terminals can be extended to the outside of the chip. Become.

  The FO-WLP is spreading because it can be used in applications having a larger number of terminals than the chip area. In addition, for a flip chip BGA in which a semiconductor chip and a package substrate are connected by solder bumps or the like and solder balls are mounted on the package substrate, FO-WLP connects the semiconductor chip to a rewiring layer, and a metal pad ( Connection terminals) are provided and solder balls are mounted. For this reason, the FO-WLP contributes to downsizing and thinning of the package, and furthermore, the wiring length is shortened, so that high-speed transmission (high functionality) and cost reduction without the package substrate can be achieved.

  In FO-WLP, after dicing a semiconductor wafer, pads for connection terminals are formed outside the semiconductor chip via a redistribution layer, so that it is necessary to increase the interval between the semiconductor chips. As a method for widening the interval between semiconductor chips, a method including a rearrangement step of rearranging individualized semiconductor chips obtained by dicing a semiconductor wafer on a carrier or the like has been conventionally proposed (for example, Non-Patent Document 1). Reference 1).

  However, since the number of semiconductor chips for each wafer increases due to the miniaturization of the semiconductor chips, it has been a problem to lengthen the rearrangement process of rearranging the semiconductor chips using a mounter, a flip chip bonder, or the like. In addition, the chip may be damaged when the chip is mounted in the rearrangement process due to the thinning of the semiconductor chip or the like. On the other hand, according to the first method for manufacturing a semiconductor device of the present embodiment, these problems can be solved.

  Hereinafter, the first to ninth steps A to 9A will be described with reference to FIGS. FIG. 1 is a schematic sectional view for explaining one embodiment of the first to fourth A steps, and FIG. 2 is a schematic sectional view for explaining one embodiment of the fifth to seventh A steps. FIG. 3 is a schematic cross-sectional view for explaining one embodiment of the steps 8A and 9A.

First, in a first A step, an expanding tape 1 and a plurality of semiconductor chips 2 fixed on the expanding tape 1 are prepared. The expandable tape 1 has an adhesive layer 1a and a base film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface on which pads (circuits) 3 are provided, and a surface opposite to the circuit surface is fixed to the expandable tape 1 (FIG. 1A). Note that the plurality of semiconductor chips 2 are arranged at intervals.
In the second A step, the interval between the plurality of semiconductor chips 2 fixed on the expand tape 1 is increased by stretching the expand tape 1 (FIG. 1B).
In the 3A step, the stretched expanded tape 1 is fixed by using the fixing jig 4 to maintain the tension of the expanded tape 1 (FIG. 1C).
In the fourth A step, the circuit surfaces of the plurality of semiconductor chips 2 are transferred onto the carrier 5 so as to be fixed (FIG. 1D). At the time of transfer, the pad 3 may be embedded in the carrier 5 (FIG. 1D), and only the pad 3 is in contact with the carrier 5 and a gap is provided between the circuit surface of the semiconductor chip 2 and the carrier 5. May be present (not shown).
In the 5A step, the expanding tape 1 is peeled from the plurality of semiconductor chips 2 (FIG. 2A).
In the 6A step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (FIG. 2B). When the pad 3 is embedded in the carrier 5 and the circuit surface of the semiconductor chip 2 is in contact with the carrier 5, the circuit surface is not sealed, and the surface opposite to the circuit surface and the four side surfaces of the semiconductor chip are not sealed. Are sealed (FIG. 2B). On the other hand, if there is a sufficient gap between the circuit surface of the semiconductor chip 2 and the carrier 5 to allow the sealing material 6 to flow, the circuit surface is also sealed, and all six surfaces of the semiconductor chip are sealed. Stopped (not shown).
In the 7A step, the carrier 5 is separated from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 2C).
FIG. 3A is an enlarged view of FIG. 2C.
In step 8A, a rewiring layer 8 having a rewiring pattern 7 is formed from the pads 3 of the plurality of semiconductor chips 2 sealed with the sealing material 6, and the rewiring pattern is formed outside the region of the semiconductor chip 2. 7, connection terminal pads 9 connected to the semiconductor chip 2 are provided (FIG. 3B).
In the ninth step (A), the semiconductor chip 2 and the connection terminal pads 9 connected to the semiconductor chip 2 are singulated as a group to form a plurality of semiconductor packages 10 (FIG. 3C).
Hereinafter, each step will be described in detail.

<Step 1A>
There is no particular limitation on the method of preparing the expanding tape and the plurality of semiconductor chips fixed on the expanding tape. For example, it can be manufactured by laminating a semiconductor wafer on a dicing tape or the like, dicing with a blade or a laser to obtain a plurality of individualized semiconductor chips, and then transferring these to an expand tape.
Dicing may be performed by forming a brittle layer with a laser and expanding the layer. In addition, from the viewpoint of improving productivity by omitting the above-described transfer, a semiconductor wafer may be directly laminated on an expand tape and the semiconductor wafer may be diced by the above-described method.

  From the viewpoints of productivity improvement and cost reduction, the initial semiconductor chip interval (the interval between semiconductor chips before the second A step) is preferably narrow, preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less. . In the cutting of the wear by dicing, the wider the chip interval, the more the semiconductor wafer is wasted. Therefore, from the viewpoint of cost reduction, it is preferable that the width is narrow as described above. In order to prevent stress on the semiconductor chips when increasing the chip interval, the initial semiconductor chip interval is preferably 10 μm or more. If the diameter is smaller than 10 μm, the expanded tape area between a plurality of semiconductor chips is small, so that it is difficult to spread.

  The kind of the pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip. Even if the bump (projection electrode) such as a copper bump or a solder bump is used, Ni / Au A relatively flat metal pad such as a plating pad may be used.

<Step 2A>
By stretching the expand tape, the interval between the plurality of semiconductor chips is increased.

  As a method for stretching the expandable tape, for example, there are a push-up method and a tension method. In the push-up method, after the expand tape is fixed, the expand tape is stretched by raising the stage having a predetermined shape. The pulling method is a method in which the expand tape is stretched by fixing the expand tape and then pulling the expand tape in a predetermined direction in parallel with the installed expand tape surface. The push-up method is preferable because the space between the semiconductor chips can be uniformly extended and the required (occupied) device area is small and compact.

Stretching conditions may be appropriately set according to the characteristics of the expanding tape. For example, when the push-up method is adopted, the push-up amount (tensile amount) is preferably from 10 mm to 500 mm, and more preferably from 10 mm to 300 mm. If it is 10 mm or more, the interval between a plurality of semiconductor chips tends to be widened, and if it is 500 mm or less, scattering or misalignment of the semiconductor chips hardly occurs.
The temperature may be appropriately set according to the properties of the expanding tape, and may be, for example, 10 ° C to 200 ° C, 10 ° C to 150 ° C, or 20 ° C to 100 ° C. When the temperature is 10 ° C. or more, the expandable tape is easily stretched, and when the temperature is 200 ° C. or less, the semiconductor chip is displaced due to distortion or sagging due to thermal expansion or low elasticity of the expandable tape (between the expandable tape and the semiconductor chip). Peeling), scattering of the semiconductor chip and the like are unlikely to occur.
The push-up speed may be appropriately set according to the characteristics of the expanding tape, but may be, for example, 0.1 mm / sec to 500 mm / sec, or 0.1 mm / sec to 300 mm / sec, or 0.1 mm / sec to 200 mm / sec. It may be seconds. When it is 0.1 mm / sec or more, productivity is improved. If the speed is 500 mm / sec or less, peeling between the semiconductor chip and the expandable tape is less likely to occur.

  The interval between the plurality of semiconductor chips after the second A step is preferably 500 μm or more to secure a space necessary for providing a rewiring pattern and connection terminal pads outside the region of the semiconductor chip. Since the total number of redistribution layers increases in a high-density and highly functional semiconductor package, it is necessary to provide connection terminal pads outside the semiconductor chip. Therefore, it is preferable that the interval between the semiconductor chips is wide. From the above viewpoint, the interval between the plurality of semiconductor chips after the second A step is more preferably equal to or greater than 1 mm, and still more preferably equal to or greater than 2 mm. The upper limit is not particularly limited, but may be 5 mm or less.

<Step 3A>
In order to prevent the stretched expanded tape from returning to the original state, the tension of the expanded tape is maintained.

  There is no particular limitation on the method of holding the tension of the expanding tape as long as the tension is held and the interval between the semiconductor chips does not return to the original. For example, there are a method of fixing using a fixing jig such as a grip ring (manufactured by Technovision Co., Ltd.) and a method of heating and shrinking the outer peripheral portion of the expanded tape (heat shrink) to maintain the tension.

<Step 4A>
Transfer (laminate) so that the circuit surfaces of the plurality of semiconductor chips are fixed to the carrier. The lamination method is not particularly limited, but a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, or the like can be employed.

  Laminating conditions may be appropriately set depending on the physical properties and characteristics of the expand tape, the semiconductor chip, and the carrier. For example, in the case of a roll laminator, the temperature may be from room temperature (25 ° C) to 200 ° C, preferably from room temperature (25 ° C) to 150 ° C, more preferably from room temperature (25 ° C) to 100 ° C. When the temperature is equal to or higher than room temperature, the semiconductor chip is easily transferred (laminated) to a carrier. When the temperature is equal to or lower than 200 ° C., the semiconductor tape is displaced due to distortion or sagging due to thermal expansion or low elasticity of the expanding tape (expansion tape and semiconductor chip). Separation between semiconductor chips), scattering of the semiconductor chip, and the like. The temperature condition of a diaphragm type laminator is the same as that of the above-described roll laminator. The pressing time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, more preferably 5 seconds to 100 seconds. When the time is 5 seconds or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the time is 300 seconds or less, the productivity is improved. The pressure may be from 0.1 MPa to 3 MPa, preferably from 0.1 MPa to 2 MPa, more preferably from 0.1 MPa to 1 MPa. When the pressure is 0.1 MPa or more, the semiconductor chip is easily transferred (laminated) to a carrier, and when the pressure is 2 MPa or less, damage to the semiconductor chip is reduced.

<Step 5A>
The expanding tape is peeled (removed) from the plurality of semiconductor chips.

  When peeling the expanding tape, the adhesive force between the expanding tape and the carrier, the expanding tape and the semiconductor chip, and the semiconductor chip and the carrier should be adjusted so that the semiconductor chip transferred on the carrier does not shift or peel off from the carrier. It is necessary to set appropriately. For example, it is preferable that the adhesion between the expand tape and the semiconductor chip is equal to or smaller than the adhesion between the semiconductor chip and the carrier.

  A UV curing function may be imparted to the expand tape or the carrier surface, and setting may be made such that the adhesion (adhesion) is increased or decreased by irradiating UV. In this case, the expand tape is removed after UV irradiation (the UV irradiation step is added). For example, after expanding the adhesive tape (adhesive force) of the expanding tape by irradiating UV after the third A step, the expanding tape can be laminated on a carrier and the expanded tape can be peeled from the semiconductor chip. As a result, stress on the semiconductor chip is reduced, and transfer can be performed smoothly without displacement.

<Step 6A>
A plurality of semiconductor chips on the carrier are sealed with a sealing material.

  The sealing method is not particularly limited, and examples thereof include a compression mold (a sealing material is a liquid material, a solid material, a granule material, a film material, etc.) and a transfer mold (a sealing material is a liquid material, a solid material, a granule material). , A film material, etc.), and lamination of a film-like sealing material.

  After the step 6A, a heat treatment step including post cure may be added from the viewpoint of adjusting the properties of the sealing material. It is necessary to peel off the carrier after the step 6A or after the additional heat treatment step. When peeling, a heat treatment, a UV treatment step, or the like may be added. It is necessary to set the adhesion of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier can be peeled off without damaging the semiconductor chip and the encapsulant after the above steps.

<Step 7A>
The carrier is separated from the plurality of semiconductor chips sealed with the sealing material. Before peeling the carrier, a step of making the carrier peel easily by applying a chemical or mechanical change to the carrier surface layer in contact with the sealing material surface by heat treatment or UV irradiation may be introduced.

  By transferring the semiconductor chip from the expand tape to the carrier in the fourth step to the seventh step, a risk to heat resistance in a heating step such as a sealing step can be reduced. For example, if the semiconductor chip is sealed (without using a carrier) in a state where the semiconductor chip is present on the expandable tape, the semiconductor chip may be displaced or scattered due to the deformation or thermal expansion of the expandable expandable tape. May occur. When the displacement or chip scattering occurs, the productivity is reduced and the cost is increased. Therefore, it is necessary to transfer the semiconductor chip to the carrier.

<Step 8A>
Forming a rewiring layer having a rewiring pattern from pads of a plurality of semiconductor chips sealed with a sealing material, and connecting terminal pads connected to the semiconductor chip by the rewiring pattern outside the region of the semiconductor chip Is provided. In a semiconductor chip in which the density and the function have been advanced, the terminal interval is narrow. Therefore, a rewiring layer is formed, and a bump for the bump is widened by providing a connection terminal pad outside a region of the semiconductor chip ( FO-WLP). As a result, reliability such as a reduction in stress applied to the bump, an improvement in insulation, and an improvement in connection reliability are improved. This step can be performed by a conventionally known method.

<Step 9A>
A plurality of semiconductor packages are formed by dividing the semiconductor chip and the connection terminal pads connected thereto into one group. In the case of dicing with a blade, it is necessary to set the interval between the semiconductor chips in the second A step in consideration of the blade width (portion to be cut off). This step can be performed by a conventionally known method.

  When the thickness of the semiconductor package is reduced for the purpose of downsizing and thinning, a back grinding step (a step of shaving the sealing material on the back surface side of the circuit surface of the semiconductor chip to reduce the thickness) may be introduced. The back grinding step can be introduced, for example, after the 6A step, after the 7A step, or after the 8A step.

  Next, the materials used in each step will be described.

(Expanded tape)
The expandable tape that can be used in the first method for manufacturing a semiconductor device is not particularly limited as long as the expandable tape has a stretchability that can increase the interval between a plurality of semiconductor chips. It is preferable that the chip interval between MD and TD after the second A step (after the gap between the semiconductor chips is widened) is uniform, but after the sixth A step (after the sealing), the semiconductor chip and the connection terminals connected thereto are connected. When the dicing is possible without damage to the semiconductor chip when the pads are divided into groups (unless the blade damages the semiconductor chip), the width of MD and TD is not uniform. Is also good. At the time of dicing, the dicing interval width of MD and TD may not be the same. However, the MD lines and the TD lines are preferably uniform.

  The expand tape may have a multi-layer structure such as a base film (base layer) that greatly contributes to stretchability, an adhesive layer that controls adhesive strength, and the like.

  The base film is not particularly limited as long as it has stretchability and stability for maintaining the interval between the semiconductor chips after the tension holding step (step 3A).

  The base film is a polyester film such as a polyethylene terephthalate film; a polytetrafluoroethylene film, a polyethylene film, a polypropylene film, a polymethylpentene film, a polyvinyl acetate film, and an α-olefin such as poly-4-methylpentene-1. Various plastic films such as a homopolymer, a copolymer thereof, and a polyolefin-based film containing an ionomer of the homopolymer or the copolymer; a polyvinyl chloride film; a polyimide film; and a urethane resin film may be used. The base film is not limited to a single-layer film, and may be a multilayer film obtained by combining two or more plastic films or two or more plastic films of the same type.

  The base film is preferably a polyolefin film or a urethane resin film from the viewpoint of stretchability. The base film may contain various additives such as an anti-blocking agent, if necessary.

  The thickness of the base film may be appropriately set as needed, but is preferably 50 μm to 500 μm. If the thickness is less than 50 μm, the stretchability decreases, and if the thickness is more than 500 μm, inconveniences such as easy generation of distortion and deterioration in handling properties occur.

The thickness of the base film is appropriately selected within a range that does not impair workability. However, when a high-energy ray (especially, ultraviolet ray) curable adhesive is used as the adhesive constituting the adhesive layer, it is necessary to have a thickness that does not hinder the transmission of the high-energy ray. From such a viewpoint, the thickness of the base film may be usually from 10 to 500 µm, preferably from 50 to 400 µm, more preferably from 70 to 300 µm.
When the substrate layer is composed of a plurality of substrate films, it is preferable to adjust the thickness of the entire substrate layer to be within the above range. The base film may be chemically or physically subjected to a surface treatment, if necessary, in order to improve the adhesion to the adhesive layer. Examples of the surface treatment include a corona treatment, a chromic acid treatment, an ozone exposure, a flame exposure, a high piezoelectric shock exposure, and an ionizing radiation treatment.

  The pressure-sensitive adhesive layer is not particularly limited as long as the pressure-sensitive adhesive force can be controlled (set so that the semiconductor chip is not displaced or scattered in each process).

The pressure-sensitive adhesive layer preferably has a pressure-sensitive adhesive property at room temperature and is preferably composed of a pressure-sensitive adhesive component having an adhesive force to a semiconductor chip. Examples of the base resin of the adhesive component constituting the adhesive layer include acrylic resin, synthetic rubber, natural rubber, and polyimide resin.
From the viewpoint of reducing the adhesive residue of the pressure-sensitive adhesive component, the base resin preferably has a functional group (such as a hydroxyl group or a carboxyl group) that can react with other additives. As the adhesive component, a resin which is cured by high energy rays such as ultraviolet rays and radiation, or by heat may be used. When such a curable resin is used, the adhesive strength can be reduced by curing the resin. Further, in order to adjust the adhesive strength, the adhesive component may include a crosslinking agent capable of performing a crosslinking reaction with the functional group of the base resin. The crosslinking agent preferably has at least one functional group selected from the group consisting of an epoxy group, an isocyanate group, an aziridine group, and a melanin group. These crosslinking agents may be used alone or in combination of two or more.
When the reaction rate is low, a catalyst such as an amine or tin may be used as necessary. In addition, in order to adjust the adhesive properties, the adhesive component may appropriately contain optional components such as a rosin-based resin, a tackifier such as a terpene resin, and various surfactants.

  The thickness of the adhesive layer is usually 1 to 100 μm, preferably 2 to 50 μm, and more preferably 5 to 40 μm. By setting the thickness of the adhesive layer to 1 μm or more, a sufficient adhesive force with the semiconductor chip can be secured. Therefore, scattering of the semiconductor chip is suppressed in the second A step (extending the interval between the semiconductor chips). It becomes easier. On the other hand, even if the thickness exceeds 100 μm, there is no advantage in characteristics and it becomes uneconomical.

  When the pressure-sensitive adhesive layer is 10 μm or more, the base film is not damaged (cut, etc.) even when the semiconductor wafer is diced on an expand tape without using a dicing tape. The step of dicing the semiconductor wafer and transferring (sticking) it to the expanding tape can be omitted.

(Method of manufacturing expanded tape)
Expanding tapes can be manufactured according to techniques well known in the art. For example, it can be manufactured according to the following method. By coating a varnish containing an adhesive component and a solvent on the protective film by knife coating, roll coating, spray coating, gravure coating, bar coating, curtain coating, etc., and removing the solvent Form an adhesive layer. Specifically, it is preferable to perform heating at 50 to 200 ° C. for 0.1 to 90 minutes. If the generation of voids or the adjustment of viscosity in each step is not affected, it is preferable that the organic solvent is volatilized to 1.5% or less.
The produced protective film with an adhesive layer and the substrate film are laminated under a temperature condition of room temperature to 60 ° C so that the adhesive layer and the substrate film face each other.

  The expandable tape (base film or base film + adhesive layer) is used after peeling off the protective film.

Examples of the protective film include A-63 (manufactured by Teijin Dupont Film Co., Ltd., release agent: modified silicone), A-31 (manufactured by Teijin Dupont Film Co., release agent: Pt-based silicone), etc. Is mentioned.
The thickness of the protective film is appropriately selected within a range that does not impair workability, and is usually preferably 100 μm or less from an economic viewpoint. The thickness of the protective film is preferably from 10 to 75 μm, more preferably from 25 to 50 μm. If the thickness of the protective film is 10 μm or more, problems such as breakage of the film during the production of the expanded tape are unlikely to occur. Further, when the thickness of the protective film is 75 μm or less, the protective film can be easily peeled when using the expand tape.

(Carrier)
The carrier is particularly limited as long as it can withstand the temperature and pressure at the time of transfer (the chip is not damaged and the chip interval does not change), and can withstand the temperature and pressure at the time of sealing in the 6A step. There is no. For example, when the sealing temperature is 100 to 200 ° C., it is preferable to have heat resistance enough to withstand the temperature range. Further, the coefficient of thermal expansion is preferably 100 ppm / ° C. or less, more preferably 50 ppm / ° C. or less, and even more preferably 20 ppm / ° C. or less. If the coefficient of thermal expansion is large, problems such as displacement of the semiconductor chip occur. Further, the thermal expansion coefficient is preferably 3 ppm / ° C. or more, since distortion or warpage occurs if the thermal expansion coefficient is smaller than that of the semiconductor chip.

  The material of the carrier is not particularly limited, and examples thereof include silicon (wafer), glass, a plate of SUS, iron, Cu, or the like, and a glass epoxy substrate.

  The thickness of the carrier may be from 100 μm to 5000 μm, preferably from 100 μm to 4000 μm, more preferably from 100 μm to 3000 μm. When the thickness is 100 μm or more, the handleability is improved. Even if it is thick, it is not possible to expect a remarkable improvement in handleability, and it is sufficient if the thickness is 5000 μm or less in consideration of economy.

  The carrier may consist of multiple layers. In addition to the above-described layer that is responsible for heat resistance and handleability, there may be a layer in which an adhesive layer or a temporary fixing material is laminated from the viewpoint of imparting control of adhesion. The adhesion may be appropriately set in consideration of the adhesion of the semiconductor chip or the expanding tape. The thickness is not particularly limited, but may be, for example, 1 μm to 300 μm, and preferably 1 μm to 200 μm. When the thickness is 1 μm or more, a sufficient adhesive force with the semiconductor chip can be secured. On the other hand, even if the thickness exceeds 300 μm, there is no advantage in characteristics and it becomes uneconomical.

(Sealing material (mold material))
The sealing method is not particularly limited, and examples thereof include a compression mold (a sealing material is a liquid material, a solid material, a granule material, a film material, etc.) and a transfer mold (a sealing material is a liquid material, a solid material, a granule material). , A film material, etc.), and lamination of a film-like sealing material.

  The sealing material shape, characteristics, and sealing conditions may be set as appropriate for each of the above-described sealing methods. The sealing material shape, characteristics, and sealing conditions need to be set appropriately so that the semiconductor chip on the carrier does not move or peel during the sealing, and the semiconductor chip is not damaged.

  For example, the sealing temperature is preferably from 80C to 220C, more preferably from 90C to 210C, and still more preferably from 100C to 200C. When the sealing temperature is 80 ° C. or higher, insufficient filling around the semiconductor chip can be sufficiently suppressed. When the sealing temperature is 220 ° C. or lower, it is possible to prevent unfilling due to premature curing of the sealing material, an increase in the amount of warpage after sealing, and the like.

  After the sealing step (Step 6A), a heat treatment step including post-curing may be added from the viewpoint of adjusting the physical properties of the sealing material. In the case of post cure, the curing time is 100 ° C. to 200 ° C., 10 minutes to 5 hours, and is set according to the curing characteristics of the sealing material. When a heat treatment step for the purpose of suppressing warpage is required, the post-curing may be further performed at a lower temperature (200 ° C. or less) for 10 minutes to 3 hours.

[Method of Manufacturing Second Semiconductor Device]
The method for manufacturing the second semiconductor device according to the present embodiment includes:
A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first B step of preparing an expanding tape and a plurality of semiconductor chips having a circuit surface fixed on the expanding tape;
A second B step of extending the interval between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A 3B step of maintaining the tension of the stretched expanded tape,
A 4B step of transferring the surface of the plurality of semiconductor chips to the carrier so that the surface opposite to the circuit surface is fixed;
A 5B step of peeling the expanding tape from the plurality of semiconductor chips,
A 6B step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7B step of polishing the sealing material to expose the pad,
An 8B step of separating the carrier from the plurality of semiconductor chips sealed by the sealing material,
Forming a rewiring layer having a rewiring pattern from pads of a plurality of semiconductor chips sealed with a sealing material, and connecting terminal pads connected to the semiconductor chip by the rewiring pattern outside the region of the semiconductor chip A 9B step of providing
A 10B step of dividing the semiconductor chip and the connection terminal pads connected thereto into a group to form a plurality of semiconductor packages;
Is provided.

  According to the second method for manufacturing a semiconductor device of the present embodiment, it is possible to manufacture a semiconductor package (FO-WLP) in which the package area is larger than the semiconductor chip area and the terminals can be extended to the outside of the chip. Become. According to the second method for manufacturing a semiconductor device of the present embodiment, similarly to the first method for manufacturing a semiconductor device of the present embodiment, it is possible to solve the problem in the conventional FO-WLP manufacturing method.

  Steps 1B to 10B described above will be described with reference to FIGS. FIG. 4 is a schematic cross-sectional view for explaining one embodiment of the first to fourth steps B, and FIG. 5 is a schematic cross-sectional view for explaining one embodiment of the fifth to eighth steps B. FIG. 6 is a schematic cross-sectional view for explaining another embodiment of the steps 7B and 8B, and FIG. 7 is a schematic view for explaining one embodiment of the steps 9B and 10B. It is sectional drawing.

First, in a first B step, an expanding tape 1 and a plurality of semiconductor chips 2 fixed on the expanding tape 1 are prepared. The expandable tape 1 has an adhesive layer 1a and a base film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface on which pads (circuits) 3 are provided, and the circuit surface is fixed to the expanding tape 1 (FIG. 4A). Note that the plurality of semiconductor chips 2 are arranged at intervals. Further, at the time of fixing, the pad 3 may be embedded in the expanding tape 1.
In the second B step, the interval between the plurality of semiconductor chips 2 fixed on the expand tape 1 is increased by stretching the expand tape 1 (FIG. 4B).
In the 3B step, the tension of the expanded tape 1 is maintained by fixing the stretched expanded tape 1 using the fixing jig 4 (FIG. 4C).
In the 4B step, the transfer is performed on the carrier 5 such that the surfaces of the plurality of semiconductor chips 2 opposite to the circuit surfaces are fixed (FIG. 4D).
In the 5B step, the expanding tape 1 is peeled from the plurality of semiconductor chips 2 (FIG. 5A).
In the 6B step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (FIG. 5B). At this time, since the surface of the semiconductor chip 2 opposite to the circuit surface is in contact with the carrier 5, this surface is not sealed, and a total of five circuit surfaces and four side surfaces of the semiconductor chip 2 are sealed. .
In a 7B step, the pad 3 is exposed by polishing the sealing material 6.
In step 8B, the carrier 5 is separated from the plurality of semiconductor chips 2 sealed with the sealing material 6.
Note that the order of the steps 7B and 8B can be interchanged. That is, after the sealing material 6 is polished to expose the pad 3 (FIG. 5C), the carrier 5 may be peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 5C). 5 (d)), after peeling the carrier 5 from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 6 (a)), the sealing material 6 is polished to expose the pad 3. Good (FIG. 6B).
FIG. 7A is an enlarged view of FIG. 5D or FIG. 6B.
In the 9B step, a rewiring layer 8 having a rewiring pattern 7 is formed from the pads 3 of the plurality of semiconductor chips 2 sealed with the sealing material 6, and the rewiring pattern 8 is formed outside the region of the semiconductor chip 2. 7, connection terminal pads 9 connected to the semiconductor chip 2 are provided (FIG. 7B).
In the 10B step, the semiconductor chip 2 and the connection terminal pads 9 connected to the semiconductor chip 2 are singulated as a group to form a plurality of semiconductor packages 10 (FIG. 7C).

  Steps 1B to 6B can be performed in the same manner as steps 1A to 6A, and steps 8B to 10B can be performed in steps 7B to 10B, respectively. It can be carried out in the same manner as in Step 9B. In a 7B step, the pad is exposed by polishing the sealing material. Polishing can be performed using a conventionally known polishing apparatus or the like. Note that when sealing can be performed in a state where the pads on the circuit surface are exposed in the step 6B, the step 7B is not necessarily provided.

  Further, as the material used in each step, the same material as that used in the first method for manufacturing a semiconductor device can be used, but the carrier 5 protects the surface opposite to the circuit surface of the semiconductor chip. In view of the above, a carrier having a layer formed by coating a material capable of protecting a sealing material and a chip on a layer bearing the above-described heat resistance and handleability, spin coating, laminating, or the like may be used as a carrier. Good.

[Third Semiconductor Device Manufacturing Method]
The third method for manufacturing a semiconductor device according to the present embodiment includes:
A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first C step of preparing an expanding tape and a plurality of semiconductor chips having a surface opposite to a circuit surface fixed on the expanding tape;
A 2C step of extending a gap between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A 3C step of maintaining the tension of the expanded expanded tape,
A 4C step of transferring the circuit surfaces of the plurality of semiconductor chips onto the carrier so that the circuit surfaces are fixed;
A 5C step of peeling the expanding tape from the plurality of semiconductor chips,
A 6C step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7C step of separating the carrier from the plurality of semiconductor chips sealed by the sealing material;
An 8C step of dividing the plurality of semiconductor chips sealed by the sealing material into individual semiconductor chips and forming a plurality of semiconductor packages;
Is provided.

  Hereinafter, the first to eighth steps C to 8C will be described with reference to FIGS. FIG. 8 is a schematic cross-sectional view for explaining one embodiment of the first to fourth C steps, and FIG. 9 is a schematic cross-sectional view for explaining one embodiment of the fifth to eighth C steps. FIG. 10 is a schematic cross-sectional view for explaining another embodiment of the fourth to eighth steps.

First, in a first C step, an expanding tape 1 and a plurality of semiconductor chips 2 fixed on the expanding tape 1 are prepared. The expandable tape 1 has an adhesive layer 1a and a base film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface on which pads (circuits) 3 are provided, and a surface opposite to the circuit surface is fixed to the expanding tape 1 (FIG. 8A). Note that the plurality of semiconductor chips 2 are arranged at intervals.
In the second C step, the interval between the plurality of semiconductor chips 2 fixed on the expand tape 1 is increased by stretching the expand tape 1 (FIG. 8B).
In the 3C step, the stretched expanded tape 1 is fixed using the fixing jig 4 to maintain the tension of the expanded tape 1 (FIG. 8C).
In the 4C step, the transfer is performed on the carrier 5 so that the circuit surfaces of the plurality of semiconductor chips 2 are fixed. At the time of transfer, the pad 3 may be completely embedded in the carrier 5 and the circuit surface of the semiconductor chip 2 may be in contact with the carrier 5 (FIG. 8D), and only a part of the pad 3 may be used. It may be embedded in the carrier 5 or only the end face of the pad 3 may be in contact with the carrier 5, and a gap may exist between the circuit surface of the semiconductor chip 2 and the carrier 5 (FIG. 10A).
In the 5C step, the expanding tape 1 is peeled off from the plurality of semiconductor chips 2 (FIG. 9A or FIG. 10B).
In the 6C step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6. When the circuit surface of the semiconductor chip 2 comes into contact with the carrier 5 after the step 5C (FIG. 9A), the circuit surface is not sealed, and the surface on the opposite side to the circuit surface of the semiconductor chip 2 and 4 A total of five side surfaces are sealed (FIG. 9B). On the other hand, if there is a sufficient gap between the circuit surface of the semiconductor chip 2 and the carrier 5 after the step 5C to allow the sealing material 6 to flow in (FIG. 10B), the circuit surface is also sealed. Then, all six surfaces of the semiconductor chip 2 are sealed (FIG. 10C).
In the 7C step, the carrier 5 is separated from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 9C or FIG. 10D).
In the 8C step, the plurality of semiconductor chips 2 sealed by the sealing material 6 are divided into individual semiconductor chips 2 to form a plurality of semiconductor packages 10 (FIG. 9D or FIG. 10E). ).
Hereinafter, each step will be described in detail.

<Step 1C>
There is no particular limitation on the method of preparing the expanding tape and the plurality of semiconductor chips fixed on the expanding tape. For example, it can be manufactured by laminating a semiconductor wafer on a dicing tape or the like, dicing with a blade or a laser to obtain a plurality of individualized semiconductor chips, and then transferring these to an expand tape.
Dicing may be performed by forming a brittle layer with a laser and expanding the layer. In addition, from the viewpoint of improving productivity by omitting the above-described transfer, a semiconductor wafer may be directly laminated on an expand tape and the semiconductor wafer may be diced by the above-described method.

  From the viewpoints of productivity improvement and cost reduction, the initial semiconductor chip interval (semiconductor chip interval before the second C step) is preferably small, preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less. . In the cutting of the wear by dicing, the wider the chip interval, the more the semiconductor wafer is wasted. Therefore, from the viewpoint of cost reduction, it is preferable that the width is narrow as described above. In order to prevent stress on the semiconductor chips when increasing the chip interval, the initial semiconductor chip interval is preferably 10 μm or more. If the diameter is smaller than 10 μm, the expanded tape area between a plurality of semiconductor chips is small, so that it is difficult to spread.

  The kind of the pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip. Even if the bump (projection electrode) such as a copper bump or a solder bump is used, Ni / Au A relatively flat metal pad such as a plating pad may be used.

<Step 2C>
By stretching the expand tape, the interval between the plurality of semiconductor chips is increased.

  As a method for stretching the expandable tape, for example, there are a push-up method and a tension method. In the push-up method, after the expand tape is fixed, the expand tape is stretched by raising the stage having a predetermined shape. The pulling method is a method in which the expand tape is stretched by fixing the expand tape and then pulling the expand tape in a predetermined direction in parallel with the installed expand tape surface. The push-up method is preferable because the space between the semiconductor chips can be uniformly extended and the required (occupied) device area is small and compact.

Stretching conditions may be appropriately set according to the characteristics of the expanding tape. For example, when the push-up method is adopted, the push-up amount (tensile amount) is preferably from 10 mm to 500 mm, and more preferably from 10 mm to 300 mm. If it is 10 mm or more, the interval between a plurality of semiconductor chips tends to be widened, and if it is 500 mm or less, scattering or misalignment of the semiconductor chips hardly occurs.
The temperature may be appropriately set according to the properties of the expanding tape, and may be, for example, 10 ° C to 200 ° C, 10 ° C to 150 ° C, or 20 ° C to 100 ° C. When the temperature is 10 ° C. or more, the expandable tape is easily stretched, and when the temperature is 200 ° C. or less, the semiconductor chip is displaced due to distortion or sagging due to thermal expansion or low elasticity of the expandable tape (between the expandable tape and the semiconductor chip). Peeling), scattering of the semiconductor chip and the like are unlikely to occur.
The push-up speed may be appropriately set according to the characteristics of the expanding tape, but may be, for example, 0.1 mm / sec to 500 mm / sec, or 0.1 mm / sec to 300 mm / sec, or 0.1 mm / sec to 200 mm / sec. It may be seconds. When it is 0.1 mm / sec or more, productivity is improved. If the speed is 500 mm / sec or less, peeling between the semiconductor chip and the expandable tape is less likely to occur.

  The interval between the plurality of semiconductor chips after the second C step is preferably 300 μm or more from the viewpoint of more surely protecting the side surfaces of the semiconductor chip with the sealing material in the sealing step (sixth C step). From the viewpoint of handleability, the interval between the plurality of semiconductor chips after the second C step is more preferably equal to or greater than 500 μm, and still more preferably equal to or greater than 1 mm. The upper limit is not particularly limited, but may be 5 mm or less.

<Step 3C>
In order to prevent the stretched expanded tape from returning to the original state, the tension of the expanded tape is maintained.

  There is no particular limitation on the method of holding the tension of the expanding tape as long as the tension is held and the interval between the semiconductor chips does not return to the original. For example, there are a method of fixing using a fixing jig such as a grip ring (manufactured by Technovision Co., Ltd.) and a method of heating and shrinking the outer peripheral portion of the expanded tape (heat shrink) to maintain the tension.

<Step 4C>
Transfer (laminate) so that the circuit surfaces of the plurality of semiconductor chips are fixed to the carrier. The lamination method is not particularly limited, but a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, or the like can be employed.

  Laminating conditions may be appropriately set depending on the physical properties and characteristics of the expand tape, the semiconductor chip, and the carrier. For example, in the case of a roll laminator, the temperature may be from room temperature (25 ° C) to 200 ° C, preferably from room temperature (25 ° C) to 150 ° C, more preferably from room temperature (25 ° C) to 100 ° C. If the temperature is higher than room temperature, the semiconductor chip is easily transferred (laminated) to the carrier. Peeling), scattering of the semiconductor chip and the like are unlikely to occur. The temperature condition of a diaphragm type laminator is the same as that of the above-described roll laminator. The pressing time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, more preferably 5 seconds to 100 seconds. When the time is 5 seconds or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the time is 300 seconds or less, the productivity is improved. The pressure may be from 0.1 MPa to 3 MPa, preferably from 0.1 MPa to 2 MPa, more preferably from 0.1 MPa to 1 MPa. When the pressure is 0.1 MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the pressure is 2 MPa or less, damage to the semiconductor chip is reduced.

<Step 5C>
The expanding tape is peeled (removed) from the plurality of semiconductor chips.

  When peeling the expanding tape, the adhesive force between the expanding tape and the carrier, the expanding tape and the semiconductor chip, and the semiconductor chip and the carrier should be adjusted so that the semiconductor chip transferred on the carrier does not shift or peel off from the carrier. It is necessary to set appropriately. For example, it is preferable that the adhesion between the expand tape and the semiconductor chip is equal to or smaller than the adhesion between the semiconductor chip and the carrier.

  A UV curing function may be imparted to the expand tape or the carrier surface, and setting may be made such that the adhesion (adhesion) is increased or decreased by irradiating UV. In this case, the expand tape is removed after UV irradiation (the UV irradiation step is added). For example, after expanding the adhesive tape (adhesive force) by irradiating UV after the 3C step, the expand tape can be laminated on a carrier, and the expanded tape can be peeled from the semiconductor chip. As a result, stress on the semiconductor chip is reduced, and transfer can be performed smoothly without displacement.

<Step 6C>
A plurality of semiconductor chips on the carrier are sealed with a sealing material.

  The sealing method is not particularly limited, and examples thereof include a compression mold (a sealing material is a liquid material, a solid material, a granule material, a film material, etc.) and a transfer mold (a sealing material is a liquid material, a solid material, a granule material). , A film material, etc.), and lamination of a film-like sealing material.

  After the 6C step, a heat treatment step including post cure may be added from the viewpoint of adjusting the properties of the sealing material. The carrier needs to be peeled off after the 6C step or after the additional heat treatment step. When peeling, a heat treatment, a UV treatment step, or the like may be added. It is necessary to set the adhesion of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier can be peeled off without damaging the semiconductor chip and the encapsulant after the above steps.

<Step 7C>
The carrier is separated from the plurality of semiconductor chips sealed with the sealing material. Before peeling the carrier, a step of making the carrier peel easily by applying a chemical or mechanical change to the carrier surface layer in contact with the sealing material surface by heat treatment or UV irradiation may be introduced.

  By transferring the semiconductor chip from the expanded tape to the carrier in the fourth to seventh steps, a risk to heat resistance in a heating step such as a sealing step can be reduced. For example, if the semiconductor chip is sealed (without using a carrier) in a state where the semiconductor chip is present on the expandable tape, the semiconductor chip may be displaced or scattered due to the deformation or thermal expansion of the expandable expandable tape. May occur. When the displacement or chip scattering occurs, the productivity is reduced and the cost is increased. Therefore, it is necessary to transfer the semiconductor chip to the carrier.

<Step 8C>
A plurality of semiconductor chips sealed with a sealing material are divided into individual semiconductor chips to form a plurality of semiconductor packages. This step can be performed by a conventionally known method.

  In the case of dicing with a blade, it is necessary to set the interval between the semiconductor chips in the second C step in consideration of the blade width (the portion that is not cut off). For example, when it is desired to leave a sealing material having a thickness of 50 μm on the side surface of the semiconductor chip, and when the dicing blade width is 250 μm, the expand tape is expanded so that the interval between the plurality of semiconductor chips after the 2C step becomes 350 μm. What is necessary is just to set the characteristic and the push-up condition (expanding condition).

  Although there is no particular limitation on the size of the semiconductor chip, it is preferably □ 20 mm or less, more preferably □ 15 mm or less, and still more preferably □ 10 mm or less, from the viewpoint of the size requiring protection with a sealing material.

  When the thickness of the semiconductor package is reduced for the purpose of downsizing and thinning, a back grinding step (a step of shaving the sealing material on the back surface side of the circuit surface of the semiconductor chip to reduce the thickness) may be introduced. The back grinding step can be introduced, for example, after the 6C step or the 7C step.

  In the step 6C, when the semiconductor chip is sealed so as to cover the circuit surface (six-surface sealing), a back grinding step (shaving the sealing material on the circuit surface side) of exposing the pad by back grinding is performed. May be introduced.

  Note that as a material used in each step, a material similar to the material used in the first method for manufacturing a semiconductor device can be used.

[Fourth Semiconductor Device Manufacturing Method]
The fourth method for manufacturing a semiconductor device according to the present embodiment includes:
A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first D step of preparing an expanding tape and a plurality of semiconductor chips having a circuit surface fixed on the expanding tape;
A 2D step of extending the interval between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A 3D step of maintaining the tension of the stretched expanded tape,
A 4D step of transferring a surface of the plurality of semiconductor chips to the carrier such that the surface opposite to the circuit surface is fixed;
A 5D step of peeling the expand tape from the plurality of semiconductor chips,
A 6D step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7D step of polishing the sealing material to expose the pad,
An 8D step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material,
A 9D step of dividing the plurality of semiconductor chips sealed by the sealing material into individual semiconductor chips and forming a plurality of semiconductor packages;
Is provided.

  Hereinafter, the above-described first to ninth steps will be described with reference to FIGS. FIG. 11 is a schematic cross-sectional view for explaining one embodiment of the first to fourth D steps, and FIG. 12 is a schematic cross-sectional view for explaining one embodiment of the fifth to ninth D steps. FIG. 13 is a schematic cross-sectional view for explaining another embodiment of the 7D step and the 8D step.

First, in a first D step, an expanding tape 1 and a plurality of semiconductor chips 2 fixed on the expanding tape 1 are prepared. The expandable tape 1 has an adhesive layer 1a and a base film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface on which pads (circuits) 3 are provided, and the circuit surface is fixed to the expandable tape 1 (FIG. 11A). Note that the plurality of semiconductor chips 2 are arranged at intervals. Further, at the time of fixing, the pad 3 may be embedded in the expanding tape 1.
In the 2D step, the interval between the plurality of semiconductor chips 2 fixed on the expand tape 1 is increased by stretching the expand tape 1 (FIG. 11B).
In the 3D step, the tension of the expanded tape 1 is maintained by fixing the stretched expanded tape 1 using the fixing jig 4 (FIG. 11C).
In the 4D step, the transfer is performed so that the surfaces of the plurality of semiconductor chips 2 opposite to the circuit surfaces are fixed to the carrier 5 (FIG. 11D).
In the 5D step, the expand tape 1 is peeled from the plurality of semiconductor chips 2 (FIG. 12A).
In the 6D step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (FIG. 12B). At this time, since the surface of the semiconductor chip 2 opposite to the circuit surface is in contact with the carrier 5, this surface is not sealed, and a total of five circuit surfaces and four side surfaces of the semiconductor chip 2 are sealed. .
In the 7D step, the pad 3 is exposed by polishing the sealing material 6.
In the 8D step, the carrier 5 is separated from the plurality of semiconductor chips 2 sealed with the sealing material 6.
Note that the order of the 7D step and the 8D step can be interchanged. That is, after the sealing material 6 is polished to expose the pad 3 (FIG. 12C), the carrier 5 may be peeled from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 12C). 12 (d)) After removing the carrier 5 from the plurality of semiconductor chips 2 sealed with the sealing material 6 (FIG. 13A), the sealing material 6 may be polished to expose the pad 3. Good (FIG. 13B).
In the ninth step D, the plurality of semiconductor chips 2 sealed by the sealing material 6 are separated into individual semiconductor chips 2 to form a plurality of semiconductor packages 10 (FIG. 12E).

  Note that the above-described first to sixth steps can be performed in the same manner as the first to sixth steps described above, and the eighth and ninth steps can be performed in the same manner as the above-described seventh and fifth steps, respectively. It can be carried out in the same manner as in Step 8C. In a 7D step, the pad is exposed by polishing the sealing material. Polishing can be performed using a conventionally known polishing apparatus or the like. Note that when sealing can be performed in the state where the pads on the circuit surface are exposed in the 6D step, the 7D step does not necessarily have to be provided.

  Further, as the material used in each step, the same material as that used in the first method for manufacturing a semiconductor device can be used, but the carrier 5 protects the surface opposite to the circuit surface of the semiconductor chip. In view of the above, a carrier having a layer formed by coating a material capable of protecting a sealing material and a chip on a layer bearing the above-described heat resistance and handleability, spin coating, laminating, or the like may be used as a carrier. Good.

[Fifth Semiconductor Device Manufacturing Method]
In the fifth method of manufacturing a semiconductor device according to the present embodiment, the interval between the singulated semiconductor chips fixed on the expand tape is increased from 100 μm or less to 300 μm or more by stretching the expand tape while heating. It has a tape expanding step for spreading. The method for manufacturing a semiconductor device according to the present embodiment includes a tension holding step of holding the tension of the expanded expand tape, a transfer step of transferring the semiconductor chip on the expanded tape where the tension is held to the carrier, and a transfer step of transferring the semiconductor chip on the carrier. Separating the expanded tape from the semiconductor chip. Hereinafter, each step will be described.

  FIG. 14 is a schematic cross-sectional view for explaining one embodiment of a fifth semiconductor device manufacturing method. FIG. 15 is a schematic cross-sectional view for explaining another embodiment of the fifth semiconductor device manufacturing method. It is sectional drawing.

First, an expanded tape 1 to which individualized semiconductor chips 2 are fixed is prepared (hereinafter, also referred to as a “preparation step”). The expandable tape 1 has an adhesive layer 1a and a base film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface on which pads (circuits) 3 are provided. The semiconductor chip 2 may have its surface opposite to the circuit surface fixed to the expanding tape 1 (FIG. 14A), or may have its circuit surface fixed to the expanding tape 1 (FIG. 15A). ).
In the tape expanding step, the spacing between the semiconductor chips 2 fixed on the expanding tape 1 is increased by stretching the expanding tape 1 while heating (FIG. 14B or FIG. 15B).
In the tension holding step, the tension of the expanded tape 1 is held by fixing the stretched expanded tape 1 using the fixing jig 4 (FIG. 14C or FIG. 15C).
In the transfer step, the semiconductor chip 2 is transferred to the carrier 5. In the preparation step, when the surface of the semiconductor chip 2 opposite to the circuit surface is fixed to the expand tape 1, the circuit surface is fixed to the carrier 5 by the above transfer (FIG. 14D). When the circuit surface is fixed to the expanding tape 1, the surface opposite to the circuit surface is fixed to the carrier 5 by the above transfer (FIG. 15D).
In the peeling step, the expanding tape 1 is peeled from the semiconductor chip 2 (FIG. 14E or FIG. 15E).
Hereinafter, each step will be described in detail.

<Preparation process>
There is no particular limitation on the method of preparing the expanded tape to which the singulated semiconductor chips are fixed. For example, it can be manufactured by laminating a semiconductor wafer on a dicing tape or the like, dicing with a blade or a laser to obtain a plurality of individualized semiconductor chips, and then transferring these to an expand tape.
Dicing may be performed by forming a brittle layer with a laser and expanding the layer. In addition, from the viewpoint of improving productivity by omitting the above-described transfer, a semiconductor wafer may be directly laminated on an expand tape and the semiconductor wafer may be diced by the above-described method.

  From the viewpoints of productivity improvement and cost reduction, the initial semiconductor chip interval (the interval between semiconductor chips before the tape expanding step) is preferably narrow, 100 μm or less, preferably 80 μm or less, and more preferably 60 μm or less. In the cutting of the wear by dicing, the wider the chip interval, the more the semiconductor wafer is wasted. Therefore, from the viewpoint of cost reduction, it is preferable that the width is narrow as described above. In order to prevent stress on the semiconductor chips when increasing the chip interval, the initial semiconductor chip interval is preferably 10 μm or more. If the diameter is smaller than 10 μm, the expanded tape area between a plurality of semiconductor chips is small, so that it is difficult to spread.

  The kind of the pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip. Even if the bump (projection electrode) such as a copper bump or a solder bump is used, Ni / Au A relatively flat metal pad such as a plating pad may be used.

<Tape expanding process>
By stretching the expand tape while heating, the intervals between the individualized semiconductor chips fixed on the expand tape are increased.

  As a method for stretching the expandable tape, for example, there are a push-up method and a tension method. In the push-up method, after the expand tape is fixed, the expand tape is stretched by raising the stage having a predetermined shape. The pulling method is a method in which the expand tape is stretched by fixing the expand tape and then pulling the expand tape in a predetermined direction in parallel with the installed expand tape surface. The push-up method is preferable because the space between the semiconductor chips can be uniformly extended and the required (occupied) device area is small and compact.

Stretching conditions may be appropriately set according to the characteristics of the expanding tape. For example, when the push-up method is adopted, the push-up amount (tensile amount) is preferably from 10 mm to 500 mm, and more preferably from 10 mm to 300 mm. If it is 10 mm or more, the interval between a plurality of semiconductor chips tends to be widened, and if it is 500 mm or less, scattering or misalignment of the semiconductor chips hardly occurs.
The heating temperature may be appropriately set according to the characteristics of the expanding tape, and is preferably, for example, 25 ° C to 200 ° C. The temperature is more preferably from 25C to 150C, and still more preferably from 30C to 100C. When the temperature is 25 ° C. or higher, the expandable tape is easily stretched, and when the temperature is 200 ° C. or lower, the semiconductor tape is displaced due to distortion or sagging due to thermal expansion or low elasticity of the expandable tape (between the expandable tape and the semiconductor chip). Peeling), scattering of the semiconductor chip and the like are unlikely to occur.
The push-up speed may be appropriately set according to the characteristics of the expanding tape, but may be, for example, 0.1 mm / sec to 500 mm / sec, or 0.1 mm / sec to 300 mm / sec, or 0.1 mm / sec to 200 mm / sec. It may be seconds. When it is 0.1 mm / sec or more, productivity is improved. If the speed is 500 mm / sec or less, peeling between the semiconductor chip and the expandable tape is less likely to occur.

The interval between the semiconductor chips after the tape expanding step may be 300 μm or more, but an appropriate interval can be selected according to the application.
In the FO-WLP application, the thickness is preferably 500 μm or more in order to secure a space required for providing a rewiring pattern and connection terminal pads outside the region of the semiconductor chip. Since the total number of redistribution layers increases in a high-density and highly functional semiconductor package, it is necessary to provide connection terminal pads outside the semiconductor chip. Therefore, it is preferable that the interval between the semiconductor chips is wide. From the above viewpoint, the interval between the plurality of semiconductor chips after the tape expanding step is preferably 1 mm or more, more preferably 2 mm or more.
In addition, in the FI-WLP application or the discrete semiconductor chip mounting application, the interval between the semiconductor chips after the tape expanding step is 300 μm or more from the viewpoint of more surely protecting the side surfaces of the semiconductor chip with a sealing material in the sealing step. . From the viewpoint of handleability, the interval between the plurality of semiconductor chips after the tape expanding step is preferably 500 μm or more, more preferably 1 mm.
The upper limit of the interval between the semiconductor chips after the tape expanding step is not particularly limited, but may be 5 mm or less.

<Tension holding process>
In order to prevent the stretched expanded tape from returning to the original state, the tension of the expanded tape is maintained.

  There is no particular limitation on the method of holding the tension of the expanding tape as long as the tension is held and the interval between the semiconductor chips does not return to the original. For example, there are a method of fixing using a fixing jig such as a grip ring (manufactured by Technovision Co., Ltd.) and a method of heating and shrinking the outer peripheral portion of the expanded tape (heat shrink) to maintain the tension.

<Transfer process>
Transfer (laminate) so that the semiconductor chip is fixed to the carrier. The lamination method is not particularly limited, but a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, or the like can be employed.

  Laminating conditions may be appropriately set depending on the physical properties and characteristics of the expand tape, the semiconductor chip, and the carrier. For example, in the case of a roll laminator, the temperature may be from room temperature (25 ° C) to 200 ° C, preferably from room temperature (25 ° C) to 150 ° C, more preferably from room temperature (25 ° C) to 100 ° C. If the temperature is higher than room temperature, the semiconductor chip is easily transferred (laminated) to the carrier. If the temperature is lower than 200 ° C., the semiconductor chip is displaced due to distortion or sagging due to thermal expansion or low elasticity of the expanding tape (between the expanding tape and the semiconductor chip). Peeling), scattering of the semiconductor chip and the like are unlikely to occur. The temperature condition of a diaphragm type laminator is the same as that of the above-described roll laminator. The pressing time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, more preferably 5 seconds to 100 seconds. When the time is 5 seconds or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the time is 300 seconds or less, the productivity is improved. The pressure may be from 0.1 MPa to 3 MPa, preferably from 0.1 MPa to 2 MPa, more preferably from 0.1 MPa to 1 MPa. When the pressure is 0.1 MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the pressure is 2 MPa or less, damage to the semiconductor chip is reduced.

  By transferring the semiconductor chip from the expand tape to the carrier, the risk of heat resistance in a heating step such as a sealing step described below can be reduced.

<Peeling step>
The expanding tape is peeled (removed) from the semiconductor chip.

  When peeling the expanding tape, the adhesive force between the expanding tape and the carrier, the expanding tape and the semiconductor chip, and the semiconductor chip and the carrier should be adjusted so that the semiconductor chip transferred on the carrier does not shift or peel off from the carrier. It is necessary to set appropriately. For example, it is preferable that the adhesion between the expand tape and the semiconductor chip is equal to or smaller than the adhesion between the semiconductor chip and the carrier.

  A UV (ultraviolet) curing function may be imparted to the expand tape or the carrier surface, and the adhesive force (adhesive force) may be set to rise or fall by irradiating UV. In this case, the expand tape is removed after UV irradiation (the UV irradiation step is added). For example, UV can be irradiated after the tension holding step to reduce the adhesion (adhesion) of the expanded tape, and then laminated on a carrier to peel the expanded tape from the semiconductor chip. As a result, stress on the semiconductor chip is reduced, and transfer can be performed smoothly without displacement.

<Sealing process>
The method for manufacturing a semiconductor device may further include a sealing step of sealing the semiconductor chip fixed on the carrier with a sealing material after the separation step (not shown). According to the method for manufacturing a semiconductor device of the present embodiment, since there is a sufficient space between the semiconductor chips, a total of five surfaces, namely, four sides of the semiconductor chip and a surface opposite to the surface not fixed to the carrier, are required. At least sealed. Further, according to the method of manufacturing a semiconductor device of the present embodiment, the semiconductor chips after the sealing step can be removed without the rearrangement step because the gap between the semiconductor chips can be sufficiently widened in the tape expanding step. Can be applied to

  Note that the sealing step may be a sealing step of sealing the semiconductor chip fixed on the expand tape with the sealing material after the tension holding step.

  The sealing method is not particularly limited, and examples thereof include a compression mold (a sealing material is a liquid material, a solid material, a granule material, a film material, etc.) and a transfer mold (a sealing material is a liquid material, a solid material, a granule material). , A film material, etc.), and lamination of a film-like sealing material.

  After the sealing step, a heat treatment step including post-curing may be added from the viewpoint of adjusting the properties of the sealing material. The carrier needs to be peeled off after the sealing step or after the additional heat treatment step. When peeling, a heat treatment, a UV treatment step, or the like may be added. It is necessary to set the adhesion of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier can be peeled off without damaging the semiconductor chip and the encapsulant after the above steps.

  When the thickness of the semiconductor package is reduced for the purpose of miniaturization and thinning, a back grinding step (a step of shaving the sealing material on the back surface side of the circuit surface of the semiconductor chip to reduce the thickness) may be introduced after the sealing step. Good.

  In the fifth method for manufacturing a semiconductor device, the same material as that used in the first method for manufacturing a semiconductor device can be used. It can be particularly preferably used. Note that the expand tape of the present embodiment can be manufactured by the same method as the expand tape manufacturing method in the first semiconductor device manufacturing method described above.

  The expanded tape of the present embodiment has a tensile stress of 10 MPa or less at the heating temperature (for example, 50 ° C.) in the above-described tape expanding step, and a tensile stress at room temperature (25 ° C.) of 5 MPa or more than the tensile stress at the heating temperature. high. The reason why the expanding tape of the present embodiment can be suitably applied to the above-described method for manufacturing a semiconductor device, particularly to the tape expanding step is not necessarily clear, but the present inventors consider as follows.

In the tape expanding process, it is the expansion of the expanding tape in the area where the semiconductor chips are fixed that contributes to increasing the interval between the semiconductor chips, and the expansion of the end portion of the expanding tape increases the interval between the semiconductor chips. Does not contribute. Here, in the tape expanding step, the expanding tape in the area where the semiconductor chip is fixed (the area of the stage) is heated, while the end portion of the expanding tape is not heated and is at room temperature. Further, when the expanded tape is heated, the tensile stress is reduced, and the expanded tape is more easily stretched as the tensile stress is smaller.
For this reason, the tensile stress of the expanded tape at the heating temperature in the tape expanding step is set to be smaller than the predetermined range, and the tensile stress at room temperature of the expanded tape is set to be higher than the predetermined value by more than the predetermined value at the heating temperature. Thereby, in the tape expanding step, the expansion of the expanding tape in the region where the semiconductor chip is fixed is sufficiently larger than the expansion of the end portion of the expanding tape, and the interval between the semiconductor chips can be further increased.

  The tensile stress at the above-mentioned heating temperature of the expanded tape is preferably 9 MPa or less, more preferably 8 MPa or less, in order to further increase the interval between the semiconductor chips after expansion.

  The tensile stress of the expanded tape at the heating temperature is not particularly limited, but is preferably 0.1 MPa or more. If it is less than 0.1 MPa, chip distortion or tape bending is likely to occur.

  The tensile stress at room temperature (25 ° C.) of the expanded tape is preferably higher than the tensile stress at the above-mentioned heating temperature by 6 MPa or more, more preferably higher by 7 MPa or more, in order to further increase the interval between the semiconductor chips after expansion. .

  The tensile stress is a value at a tensile strain of 1 (mm / mm) measured by a micro force tester (INSTRON 5948, manufactured by INSTRON). The tensile speed was 5 mm / sec.

  It is preferable that the chip interval between the MD and the TD after the tape expanding step is uniform. However, when the semiconductor chip and the connection terminal pads connected to the semiconductor chip are separated into a group after sealing, damage to the semiconductor chip may occur. As long as dicing is possible (without damaging the semiconductor chip), the width of MD and TD need not be uniform. At the time of dicing, the dicing interval width of MD and TD may not be the same. However, the MD lines and the TD lines are preferably uniform.

  The expand tape preferably has a plurality of layer structures such as a base film (base layer) that greatly contributes to stretchability and an adhesive layer that controls the adhesive strength.

  It is preferable that the base film has stretchability and stability to maintain the interval between the semiconductor chips after the tension holding step.

  The base film is a polyester film such as a polyethylene terephthalate film; a polytetrafluoroethylene film, a polyethylene film, a polypropylene film, a polymethylpentene film, a polyvinyl acetate film, and an α-olefin such as poly-4-methylpentene-1. Various plastic films such as a homopolymer, a copolymer thereof, and a polyolefin-based film containing an ionomer of the homopolymer or the copolymer; a polyvinyl chloride film; a polyimide film; and a urethane resin film may be used. The base film is not limited to a single-layer film, and may be a multilayer film obtained by combining two or more plastic films or two or more plastic films of the same type.

  The base film is preferably a polyolefin film or a urethane resin film from the viewpoint of stretchability. The base film may contain various additives such as an anti-blocking agent, if necessary.

  The thickness of the base film may be appropriately set as needed, but is preferably 50 μm to 500 μm. If the thickness is less than 50 μm, the stretchability decreases, and if the thickness is more than 500 μm, inconveniences such as easy generation of distortion and deterioration in handling properties occur.

The thickness of the base film is appropriately selected within a range that does not impair workability. However, when a high-energy ray (especially, ultraviolet ray) curable adhesive is used as the adhesive constituting the adhesive layer, it is necessary to have a thickness that does not hinder the transmission of the high-energy ray. From such a viewpoint, the thickness of the base film may be usually from 10 to 500 µm, preferably from 50 to 400 µm, more preferably from 70 to 300 µm.
When the substrate layer is composed of a plurality of substrate films, it is preferable to adjust the thickness of the entire substrate layer to be within the above range. The base film may be chemically or physically subjected to a surface treatment, if necessary, in order to improve the adhesion to the adhesive layer. Examples of the surface treatment include a corona treatment, a chromic acid treatment, an ozone exposure, a flame exposure, a high piezoelectric shock exposure, and an ionizing radiation treatment.

  The pressure-sensitive adhesive layer is not particularly limited as long as the pressure-sensitive adhesive force can be controlled (set so that the semiconductor chip is not displaced or scattered in each process).

The pressure-sensitive adhesive layer preferably has a pressure-sensitive adhesive property at room temperature and is preferably composed of a pressure-sensitive adhesive component having an adhesive force to a semiconductor chip. Examples of the base resin of the adhesive component constituting the adhesive layer include acrylic resin, synthetic rubber, natural rubber, and polyimide resin.
From the viewpoint of reducing the adhesive residue of the pressure-sensitive adhesive component, the base resin preferably has a functional group (a hydroxyl group, a carboxyl group, or the like) that can react with another additive. As the pressure-sensitive adhesive component, a resin that is cured by high energy rays such as ultraviolet rays and radiation (especially an ultraviolet-curable resin) or a resin that is cured by heat (a thermosetting resin) may be used. When such a curable resin is used, the adhesive strength can be reduced by curing the resin. In particular, a UV-curable pressure-sensitive adhesive containing a UV-curable resin is preferably used.

  Further, in order to adjust the adhesive strength, the adhesive component may include a crosslinking agent capable of performing a crosslinking reaction with the functional group of the base resin. The crosslinking agent preferably has at least one functional group selected from the group consisting of an epoxy group, an isocyanate group, an aziridine group, and a melanin group. These crosslinking agents may be used alone or in combination of two or more. When the reaction rate is low, a catalyst such as an amine or tin may be used as necessary. In addition, in order to adjust the adhesive properties, the adhesive may appropriately contain optional components such as a rosin-based resin, a tackifier such as a terpene resin, and various surfactants.

  The thickness of the adhesive layer is usually 1 to 100 μm, preferably 2 to 50 μm, and more preferably 5 to 40 μm. By setting the thickness of the adhesive layer to 1 μm or more, a sufficient adhesive force with the semiconductor chip can be ensured, so that scattering of the semiconductor chip in the tape expanding step can be easily suppressed. On the other hand, even if the thickness exceeds 100 μm, there is no advantage in characteristics and it becomes uneconomical.

  When the pressure-sensitive adhesive layer is 10 μm or more, the base film is not damaged (cut, etc.) even when the semiconductor wafer is diced on an expand tape without using a dicing tape. The step of dicing the wafer and transferring (sticking) it to the expanded tape can be omitted.

  Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited thereto.

(Preparation of acrylic resin solution)
In a 4000 ml autoclave equipped with a three-one motor, a stirring blade, and a nitrogen inlet tube, 1000 g of ethyl acetate, 650 g of 2-ethylhexyl acrylate, 350 g of 2-hydroxyethyl acrylate, and 3.0 g of azobisisobutyronitrile were blended, and then mixed. Then, nitrogen bubbling was performed at a flow rate of 100 ml / min for 60 minutes to dissolve dissolved oxygen in the system. The temperature was raised to 60 ° C. over 1 hour, and polymerization was performed for 4 hours after the temperature was raised. Thereafter, the temperature was raised to 90 ° C. over 1 hour, and further maintained at 90 ° C. for 1 hour, and then cooled to room temperature.
Next, 1000 g of ethyl acetate was added, and the mixture was stirred and diluted. To this were added 0.1 g of methoquinone as a polymerization inhibitor and 0.05 g of dioctyltin dilaurate as a urethanization catalyst, and then 100 g of 2-methacryloxyethyl isocyanate (Karenz MOI, manufactured by Showa Denko KK). After reacting at 70 ° C. for 6 hours, it was cooled to room temperature. Thereafter, ethyl acetate was added to adjust the nonvolatile content in the acrylic resin solution to 35% by mass to obtain an acrylic resin solution having a chain-polymerizable functional group.
When the acid value and the hydroxyl value of this resin were measured in accordance with JIS K0070, no acid value was detected, and the hydroxyl value was 121 mgKOH / g.
Further, the obtained acrylic resin solution was vacuum-dried at 60 ° C. overnight, and the obtained solid content was subjected to elemental analysis by a fully automatic elemental analyzer (VarioEL, manufactured by Elemental Corporation). When the content of 2-methacryloxyethyl isocyanate introduced into the acrylic resin was calculated from the measured nitrogen content, it was 0.59 mmol / g.
Further, using SD-8022 / DP-8020 / RI-8020 (manufactured by Tosoh Corporation), and using Gelpack GL-A150-S / GL-A160-S (manufactured by Hitachi Chemical Co., Ltd.) for the column, elution was performed. As a result of a GPC measurement using tetrahydrofuran for the liquid, the polystyrene equivalent weight average molecular weight was 420,000.

(Production of expanded tape)
To the acrylic resin solution (solid content: 100 parts by weight), 12.0 g of a polyfunctional isocyanate (Coronate L, 75% solid content, manufactured by Nippon Polyurethane Industry Co., Ltd.) was used as a crosslinking agent, and 12.0 g was used as a photoinitiator. 1.0 g of hydroxycyclohexyl phenyl ketone (Irgacure 184, manufactured by BASF) and ethyl acetate were further added so that the total solid content was 27% by mass, and the mixture was stirred uniformly for 10 minutes. Thereafter, the obtained solution was applied and dried on a protective film (surface release-treated polyethylene terephthalate, thickness 25 μm) to form an adhesive layer. At this time, two kinds of adhesive layers having a thickness of 10 μm or 30 μm when dried were prepared. Furthermore, the surface of the adhesive layer was laminated on a base film (thickness: 100 μm). Thereafter, the obtained two kinds of tapes were aged at 40 ° C. for 4 days. The tape having an adhesive layer of 10 μm was referred to as Expanded Tape A, and the tape having a thickness of 30 μm was referred to as Expanded Tape B.

In addition, as said base film, Himilan 1706 (made by Mitsui-Dupont Polychemical Co., Ltd., ionomer resin), ethylene / 1-hexene copolymer, butene / α-olefin copolymer, and Himilan 1706 are in this order. A laminated three-layer resin film was used.
The pressure-sensitive adhesive layer, the protective film and the substrate film were laminated with a roll laminator at 40 ° C. to form a protective film / adhesive layer / substrate film in this order. When used as an expand tape, the protective film was peeled off before use.

<Preparation of Individualized Semiconductor Chips on Expanded Tape (Step 1)>
(Evaluation sample A)
An 8-inch silicon wafer (250 μm thick) is laminated on a dicing tape at 40 ° C. using a wafer mounting device (DM-300-H, manufactured by JCM Co., Ltd.), and a dicing device (DFD6361) is sized with a blade to a size of 5 mm × 5 mm. (Manufactured by Disco Co., Ltd.). Thereafter, using a UV exposure machine (ML-320FSAT, manufactured by Mikasa Corporation), UV irradiation was performed at 300 mJ to reduce the adhesion of the dicing tape, and the semiconductor chips singulated into the expand tape A were laminated with a laminating apparatus (V130). Was transferred using Nikko Materials Co., Ltd. (under conditions of 40 ° C./0.5 MPa / 10 seconds) to produce Evaluation Sample A. The evaluation sample A from which the dicing tape was removed was fixed to a 12-inch dicing ring. At this time, the initial semiconductor chip interval was about 50 μm.

(Evaluation sample B)
An 8-inch silicon wafer (250 μm thickness) is laminated on the expanding tape B at 40 ° C. by using a wafer mounting device (DM-300-H, manufactured by JCM Corporation), and a dicing device (5 mm × 5 mm) is sized with a blade. The sample was diced using DFD6361 (manufactured by Disco Corporation) to prepare an evaluation sample B. Evaluation sample B was fixed to a 12-inch dicing ring. At this time, the initial semiconductor chip interval was about 50 μm.

(Evaluation sample C)
An 8-inch silicon wafer (250 μm thick) is laminated on a dicing tape at 40 ° C. using a wafer mounting device (DM-300-H, manufactured by JCM Co., Ltd.), and a dicing device (DFD6361) is sized with a blade to a size of 5 mm × 5 mm. And Disco Co., Ltd.) to produce Evaluation Sample C. At this time, the initial semiconductor chip interval was about 50 μm.

(Carrier)
A temporary fixing material was laminated on a 12-inch silicon wafer (original thickness: 775 μm) using a vacuum laminator (V130, manufactured by Nikko Materials Co., Ltd.), and then processed into a wafer to form a carrier. Laminating conditions were a diaphragm temperature of 80 ° C., a stage of 40 ° C., a time of 60 s, and a pressure of 0.5 MPa.

(Sealing material)
CEL-400ZHF-40WG (manufactured by Hitachi Chemical Co., Ltd.) was used as a sealing material.

(Examples 1 and 2)
<Step 2>
The evaluation samples A and B were set on a 12-inch expander (MX-5154FN, manufactured by Omiya Kogyo Co., Ltd.), and were pushed up at a pushing speed of 100 mm / sec and a temperature (stage temperature) of 50 ° C. for 1 second (pushing amount: 100 mm), and expanded. The tape was stretched. At this time, the chip spacing of the semiconductors was increased from about 50 μm initially to about 1 mm for both of the evaluation samples A and B.
<Step 3>
Evaluation samples A and B obtained by expanding the expand tape were fixed with a grip ring (GR-12, manufactured by Technovision Corporation) for a 12-inch expander to maintain the tension. Since Step 2 and Step 3 occur in an interlocked manner (a device that reaches the thrust of 100 mm and is fixed by the grip ring at the same time), Step 2 and Step 3 were completed in 1 second in total.
<Step 4>
After irradiating the UV to the evaluation samples A and B holding the tension (UV exposure machine ML-320FSAT, manufactured by Mikasa Co., Ltd.), the semiconductor chip is used as a carrier by using a vacuum laminator (V130, manufactured by Nikko Materials Co., Ltd.). The sides were laminated. Laminating conditions were a diaphragm temperature of 60 ° C., a stage temperature of 60 ° C., a pressure of 0.5 MPa, and 60 seconds.
<Step 5>
Only the expanded tape was peeled off from the evaluation samples A and B after lamination, and evaluation samples A ′ and B ′ in which semiconductor chips were arranged on a carrier (temporary fixing material) were produced. The evaluation samples A ′ and B ′ produced from the evaluation samples A and B were both good without scattering of the semiconductor chip or displacement. The expanding tape was peeled at room temperature (25 ° C.) for 10 seconds.
<Step 6 and Step 7>
The evaluation samples A ′ and B ′ were sealed with a sealing device (CPM1180, manufactured by TOWA Corporation) using the above sealing material. The sealing was performed with a 12-inch wafer size and a thickness of 350 μm. Granules were used as the shape of the sealing material. The method was performed by compression molding. The sealing conditions were 150 ° C./10 minutes / 37 tons. Thereafter, curing was performed at 150 ° C. for 1 hour. After curing, heat treatment was performed at 180 ° C. for 5 minutes to peel off the carrier, and the carrier was peeled off.

(Comparative Example 1)
The evaluation sample C was picked up from the dicing tape by a flip chip bonder (LFB2301, manufactured by Shinkawa Co., Ltd.) and relocated to the carrier. The pressure bonding time (rearrangement time) for one semiconductor chip having a size of 5 mm × 5 mm was 2 seconds including the pickup. Since the evaluation sample C has about 1250 semiconductor chips of 5 mm × 5 mm in size (calculated to be about 1256, but excluding peripheral chips which have a size of 5 mm × 5 mm or less during dicing). The placement took 2500 seconds. The distance between the semiconductor chips was 1 mm as in the case of the evaluation samples A and B. The sample rearranged on the carrier was designated as evaluation sample C ′.
The evaluation sample C ′ was sealed with a sealing device (CPM1180, manufactured by TOWA Corporation) using the above sealing material. The sealing was performed with a 12-inch wafer size and a thickness of 350 μm. Granules were used as the shape of the sealing material. The method was performed by compression molding. The sealing conditions were 150 ° C./10 minutes / 37 tons. Thereafter, curing was performed at 150 ° C. for 1 hour. After curing, heat treatment was performed at 180 ° C. for 5 minutes to peel off the carrier, and the carrier was peeled off.

(I) Method of Measuring Semiconductor Chip Interval The distance between semiconductor chips was measured with a microscope capable of measuring length (ECLIPSE-L, manufactured by Nikon Corporation). The measurement was performed at one point at the center and at four points at the periphery (one point at the top, bottom, left and right with the center at the center), for a total of five points. The semiconductor chip interval was an average value of five points.
(Ii) Evaluation of misalignment of semiconductor chip interval before and after the sealing step (step 6) The semiconductor chip interval before and after the sealing step was measured by the same method as (i). Five points were selected in the same manner as in (i), and the same points were measured before and after sealing. Samples in which the distance between the semiconductor chips at a total of five points fluctuated more than 10 μm before and after the sealing step were evaluated as NG, and those within 10 μm were evaluated as OK (good).

Table 1 summarizes the evaluation results of Examples 1 and 2 and Comparative Example 1.

  The manufacturing method (Examples 1 and 2) of the present invention has the same accuracy (evaluation of displacement) as compared with the conventional method (Comparative Example), and the productivity is remarkably improved.

  DESCRIPTION OF SYMBOLS 1 ... Expanded tape, 1a ... Adhesive layer, 1b ... Base film, 2 ... Semiconductor chip, 3 ... Pad (circuit), 4 ... Fixing jig, 5 ... Carrier, 6 ... Sealing material, 7 ... Rewiring pattern, 8 ... redistribution layer, 9 ... pad for connection terminal, 10 ... semiconductor package.

Claims (9)

It is used in a method of manufacturing a semiconductor device including a tape expanding step of expanding an interval between individualized semiconductor chips fixed on the expanding tape and extending from 100 μm or less to 300 μm or more by stretching the expanding tape while heating. An expanding tape,
An expanded tape having a tensile stress at the heating temperature of the tape expanding step of 10 MPa or less and a tensile stress at room temperature higher than the tensile stress at the heating temperature by 5 MPa or more.   A method of manufacturing the semiconductor device, wherein a tension holding step of holding a tension of the expanded tape that has been stretched, a transfer step of transferring the semiconductor chip on the expanded tape where the tension is held to a carrier, and a transfer to the carrier. The expanding tape according to claim 1, further comprising a peeling step of peeling the expanding tape from the semiconductor chip.   The expandable tape according to claim 1, further comprising a base layer and an adhesive layer.   The expandable tape according to claim 3, wherein the pressure-sensitive adhesive layer is formed of a UV-curable pressure-sensitive adhesive.   By stretching the expanded tape according to any one of claims 1 to 4 while heating, the interval between the singulated semiconductor chips fixed on the expanded tape is increased from 100 μm or less to 300 μm or more. A method for manufacturing a semiconductor device, comprising a tape expanding step. A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first A step of preparing an expandable tape and a plurality of the semiconductor chips having a surface opposite to the circuit surface fixed on the expandable tape;
2A step of extending the expand tape to increase the interval between the plurality of semiconductor chips fixed on the expand tape,
A third A step of maintaining the tension of the expanded tape that has been stretched,
A 4A step of transferring the circuit surfaces of the plurality of semiconductor chips onto a carrier so that the circuit surfaces are fixed;
A 5A step of peeling the expand tape from the plurality of semiconductor chips;
A 6A step of sealing the plurality of semiconductor chips on the carrier with a sealing material,
A 7A step of separating the carrier from the plurality of semiconductor chips sealed by the sealing material;
A method for manufacturing a semiconductor device comprising: A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first B step of preparing an expandable tape and a plurality of the semiconductor chips having the circuit surface fixed on the expandable tape;
A 2B step of extending the expand tape to increase the interval between the plurality of semiconductor chips fixed on the expand tape;
A 3B step of maintaining the tension of the expanded tape that has been stretched,
A 4B step of transferring the plurality of semiconductor chips onto a carrier such that a surface opposite to the circuit surface is fixed;
A 5B step of peeling the expanding tape from the plurality of semiconductor chips;
A 6B step of sealing the plurality of semiconductor chips on the carrier with a sealing material;
A method for manufacturing a semiconductor device comprising: A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first C step of preparing an expandable tape and a plurality of the semiconductor chips having a surface opposite to the circuit surface fixed on the expandable tape;
A 2C step of extending a distance between the plurality of semiconductor chips fixed on the expand tape by stretching the expand tape;
A 3C step of maintaining the tension of the expanded tape that has been stretched,
A 4C step of transferring the circuit surfaces of the plurality of semiconductor chips onto a carrier so that the circuit surfaces are fixed;
A 5C step of peeling the expand tape from the plurality of semiconductor chips;
A 6C step of sealing the plurality of semiconductor chips on the carrier with a sealing material;
A 7C step of separating the carrier from the plurality of semiconductor chips sealed by the sealing material;
A method of manufacturing a semiconductor device, comprising an 8C step of dividing a plurality of semiconductor chips sealed by the sealing material into individual semiconductor chips to form a plurality of semiconductor packages. A method for manufacturing a semiconductor device having a semiconductor chip provided with pads on a circuit surface,
A first D step of preparing an expanding tape and a plurality of the semiconductor chips having a circuit surface fixed on the expanding tape;
A 2D step of extending the expandable tape to increase the interval between the plurality of semiconductor chips fixed on the expandable tape,
A 3D step of maintaining the tension of the expanded tape that has been stretched,
A 4D step of transferring onto a carrier such that surfaces of the plurality of semiconductor chips opposite to the circuit surface are fixed;
A 5D step of peeling the expand tape from the plurality of semiconductor chips,
A 6D step of sealing the plurality of semiconductor chips on the carrier with a sealing material;
A 7D step of polishing the sealing material to expose the pad,
An 8D step of peeling the carrier from the plurality of semiconductor chips sealed by the sealing material;
A method for manufacturing a semiconductor device, comprising: a ninth step (D) of dividing a plurality of semiconductor chips sealed by the sealing material into individual semiconductor chips to form a plurality of semiconductor packages.

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