JPWO2018207583A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JPWO2018207583A1 JPWO2018207583A1 JP2019517540A JP2019517540A JPWO2018207583A1 JP WO2018207583 A1 JPWO2018207583 A1 JP WO2018207583A1 JP 2019517540 A JP2019517540 A JP 2019517540A JP 2019517540 A JP2019517540 A JP 2019517540A JP WO2018207583 A1 JPWO2018207583 A1 JP WO2018207583A1
- Authority
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- Japan
- Prior art keywords
- lead frame
- terminal portion
- ground terminal
- semiconductor device
- die attach
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Abstract
Description
実施の形態1.
まず本実施の形態の半導体装置の構成について、図1および図2を用いて説明する。図1は本実施の形態の半導体装置の概略平面図であり、図2は本実施の形態の半導体装置の、特に図1のII−II線に沿う部分の概略断面図である。なお図2に示される導電性材料などの一部の領域は、図1においては省略されている。また説明の便宜のため、各図においてX方向、Y方向、Z方向が導入されている。図1および図2を参照して、本実施の形態の半導体装置100は、リードフレーム1と、半導体素子2と、プラスチックモールド材料としてのモールド材料3とを主に備えている。
図12は第1の比較例の半導体装置の概略断面図である。図12を参照して、第1の比較例の半導体装置901において、本実施の形態の半導体装置100と同一の構成要素については同一の符号を付しその説明を繰り返さない。図12に示すように、第1の比較例においては、リードフレーム1が、ダイアタッチ部11と、信号端子部12とを含み、ダイアタッチ部11上に接合された半導体素子2の全体と、信号端子部12の一部が、モールド材料3に覆われ封止されている。信号端子部12の一部は、モールド材料3の最表面3aから平面視における外側へ突出するようにはみ出している。なお信号端子部12のZ方向上側のモールド材料3の最表面3aは、半導体装置100の導電性材料7に相当する上側金属ケース71に覆われており、信号端子部12のZ方向下側のモールド材料3の最表面3aは、半導体装置100の導電性材料7に相当する下側金属ケース72に覆われている。
本実施の形態の半導体装置は、基本的に実施の形態1の半導体装置100と同様の構成を有するため、詳細な説明を繰り返さない。本実施の形態においては実施の形態1と比較して、その製造方法において一部異なっている。以下では図14を用いて、本実施の形態の半導体装置の製造方法について説明する。
本実施の形態の半導体装置は、基本的に実施の形態1の半導体装置100と同様の構成を有するため、以下において半導体装置100と同一の構成要素については同一の符号を付しその説明を繰り返さない。ただし本実施の形態においては実施の形態1と比較して、その構成において一部異なっている。以下では図15を用いて、本実施の形態の半導体装置の、半導体装置100との構成上の差異について説明する。
本発明の半導体装置は、単一のリードフレームと、半導体素子と、モールド材料とを備えている。半導体素子はリードフレームの一方の主表面上に接合され、モールド材料はリードフレームの一方の主表面を覆い半導体素子を封止する。リードフレームは、ダイアタッチ部と、信号端子部と、接地端子部とを含み、ダイアタッチ部、信号端子部および接地端子部は一方の主表面に沿う方向に並ぶようにモールド材料の真下に配置される。リードフレームにおける互いに隣り合うダイアタッチ部と接地端子部との間および信号端子部と接地端子部との間には、リードフレームが貫通されるように除去された溝部が形成されている。
本発明の半導体装置の製造方法は、単一のリードフレームが準備される。互いに隣り合うダイアタッチ部と接地端子部との間および信号端子部と接地端子部との間に、リードフレームが貫通されるように除去された溝部が形成される。モールド材料によりリードフレームの一方の主表面が覆われ半導体素子が封止される。モールド材料は、ダイアタッチ部、信号端子部および接地端子部の真上に重なるように供給される。接地端子部は、モールド材料の平面視における外周部に配置される。
Claims (11)
- 単一のリードフレームと、
前記リードフレームの一方の主表面上に接合された半導体素子と、
前記リードフレームの前記一方の主表面を覆い前記半導体素子を封止するモールド材料とを備え、
前記リードフレームは、前記半導体素子が接合されたダイアタッチ部と、前記半導体素子と金属細線を介して電気的に接合された信号端子部と、接地電位に接続され前記モールド材料の平面視における外周部に配置された接地端子部とを含み、前記ダイアタッチ部、前記信号端子部および前記接地端子部は前記一方の主表面に沿う方向に並ぶように前記モールド材料の真下に配置され、
前記リードフレームにおける互いに隣り合う前記ダイアタッチ部と前記接地端子部との間および前記信号端子部と前記接地端子部との間には、前記リードフレームが貫通されるように除去された溝部が形成されている、半導体装置。 - 前記信号端子部は前記ダイアタッチ部の外側に、前記接地端子部は前記信号端子部の外側に、それぞれ配置される、請求項1に記載の半導体装置。
- 前記溝部は、前記リードフレームに重なるように接する前記モールド材料内に達するように形成される、請求項1または2に記載の半導体装置。
- 前記モールド材料の少なくとも一部を覆い、前記接地端子部の少なくとも第1の側面に接する導電性材料と、
前記ダイアタッチ部、前記信号端子部、前記接地端子部のそれぞれの前記一方の主表面と反対側の他方の主表面上に形成された被覆膜と、
前記ダイアタッチ部、前記信号端子部、前記接地端子部が前記溝部と接する第2の側面に形成された酸化被膜とをさらに備える、請求項1〜3のいずれか1項に記載の半導体装置。 - 前記溝部は第1の領域と、前記第1の領域以外の第2の領域とを含み、
前記第1の領域における前記一方の主表面に沿う方向の幅は、前記第2の領域における前記幅よりも大きくなるよう、前記溝部の前記第2の側面が外側に膨らんでいる、請求項4に記載の半導体装置。 - ダイアタッチ部と、信号端子部と、接地電位に接続される接地端子部とを含む単一のリードフレームを準備する工程と、
前記リードフレームの前記ダイアタッチ部に半導体素子を接合する工程と、
前記半導体素子と前記信号端子部とを金属細線を介して電気的に接合する工程と、
モールド材料により前記リードフレームの一方の主表面を覆い前記半導体素子を封止する工程と、
互いに隣り合う前記ダイアタッチ部と前記接地端子部との間および前記信号端子部と前記接地端子部との間に、前記リードフレームが貫通されるように除去された溝部を形成する工程とを備え、
前記封止する工程においては、前記モールド材料は、前記ダイアタッチ部、前記信号端子部および前記接地端子部の真上に重なるように供給され、
前記封止する工程においては、前記接地端子部は、前記モールド材料の平面視における外周部に配置される、半導体装置の製造方法。 - 前記リードフレームを準備する工程において、前記信号端子部は前記ダイアタッチ部の外側に、前記接地端子部は前記信号端子部の外側に、それぞれ形成される、請求項6に記載の半導体装置の製造方法。
- 前記溝部を形成する工程において、前記溝部は、前記リードフレームに重なるように接する前記モールド材料内に達するように形成される、請求項6または7に記載の半導体装置の製造方法。
- 前記モールド材料の少なくとも一部を覆い、前記接地端子部の少なくとも第1の側面に接する導電性材料を形成する工程と、
前記ダイアタッチ部、前記信号端子部、前記接地端子部のそれぞれの前記一方の主表面と反対側の他方の主表面上に被覆膜を形成する工程と、
前記ダイアタッチ部、前記信号端子部、前記接地端子部が前記溝部と接する第2の側面に酸化被膜を形成する工程とをさらに備える、請求項6〜8のいずれか1項に記載の半導体装置の製造方法。 - 前記導電性材料を形成する工程は、前記溝部を形成する工程の後になされる、請求項9に記載の半導体装置の製造方法。
- 前記溝部を形成する工程は、
前記溝部を形成すべき領域の前記他方の主表面上に形成された前記被覆膜を除去する工程と、
前記被覆膜が除去された状態で、前記リードフレームを薬液に浸漬することにより前記被覆膜が除去された領域と重なる前記リードフレームを除去する工程とを含み、
前記リードフレームを除去する工程により、前記被覆膜が除去された領域の幅よりも、前記リードフレームが除去された領域の幅が大きくなるように除去されることで、前記第2の側面が部分的に外側に膨らんだ前記溝部が形成される、請求項9または10に記載の半導体装置の製造方法。
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