JP6901197B2 - 半導体モジュール、及び半導体モジュールの製造方法 - Google Patents
半導体モジュール、及び半導体モジュールの製造方法 Download PDFInfo
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- JP6901197B2 JP6901197B2 JP2017093366A JP2017093366A JP6901197B2 JP 6901197 B2 JP6901197 B2 JP 6901197B2 JP 2017093366 A JP2017093366 A JP 2017093366A JP 2017093366 A JP2017093366 A JP 2017093366A JP 6901197 B2 JP6901197 B2 JP 6901197B2
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- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
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- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
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- 239000012299 nitrogen atmosphere Substances 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
Claims (5)
- 半導体チップと、
前記半導体チップの電極に接続されるボンディングワイヤと、
前記ボンディングワイヤの直下において前記ボンディングワイヤに接触する固化樹脂と、
を備え、
前記ボンディングワイヤの直下から延びる前記固化樹脂のボンディングワイヤの断面における横方向の厚さは、前記ボンディングワイヤの直径よりも小さい、半導体モジュール。 - さらに、前記半導体チップの入力側に搭載された入力整合回路と、前記半導体チップの出力側に搭載された出力整合回路と、のいずれか一方を少なくとも有し、
前記ボンディングワイヤは、前記半導体チップの第1の電極と前記入力整合回路を接続する第1のボンディングワイヤと、前記半導体チップの第2の電極と前記出力整合回路を接続する第2のボンディングワイヤと、を含み、
前記固化樹脂は、前記第1のボンディングワイヤに接触する第1の固化樹脂と、前記第2のボンディングワイヤに接触する第2の固化樹脂と、を含む、
請求項1に記載の半導体モジュール。 - 前記半導体チップを搭載するベースを更に備え、
前記固化樹脂は、前記ボンディングワイヤと前記ベースの間に介在する、
請求項1または請求項2に記載の半導体モジュール。 - ベースと、前記ベースの上に配置され前記ベースとの間に素子搭載領域を画定する側壁を有するハウジングとを備えた半導体モジュールの製造方法であって、
前記素子搭載領域に素子を搭載する工程と、
前記素子に対してワイヤボンディングを施す工程と、
前記素子搭載領域を、粘度1mPa・s以上且つ100mPa・s以下の固化樹脂で充填する工程と、
前記ワイヤボンディングで得られたボンディングワイヤの直下であって前記ベースと前記ボンディングワイヤの間に固化樹脂を形成する工程と、
を備える半導体モジュールの製造方法。 - 前記固化樹脂は、揮発成分を60%以上含むと共に、硬化成分を10%以上且つ40%以下含んでおり、
前記固化樹脂を形成する工程では、前記揮発成分を温度80℃以上且つ120℃以下の環境下で揮散させることによって、前記固化樹脂を形成する、
請求項4に記載の半導体モジュールの製造方法。
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JP6901197B2 true JP6901197B2 (ja) | 2021-07-14 |
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Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3235452B2 (ja) * | 1995-03-20 | 2001-12-04 | 松下電器産業株式会社 | 高周波集積回路装置 |
CN100570871C (zh) * | 2005-08-24 | 2009-12-16 | 富士通微电子株式会社 | 半导体器件及其制造方法 |
US20090032972A1 (en) * | 2007-03-30 | 2009-02-05 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2008251929A (ja) * | 2007-03-30 | 2008-10-16 | Toshiba Corp | 積層型半導体装置 |
JP5357667B2 (ja) * | 2009-08-24 | 2013-12-04 | 本田技研工業株式会社 | 電子装置の製造方法 |
JP5302147B2 (ja) * | 2009-09-14 | 2013-10-02 | 新日鉄住金化学株式会社 | 封止用エポキシ樹脂組成物および硬化物 |
JP2011228336A (ja) * | 2010-04-15 | 2011-11-10 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2013058606A (ja) * | 2011-09-08 | 2013-03-28 | Renesas Electronics Corp | 半導体装置の製造方法 |
WO2013145532A1 (ja) * | 2012-03-28 | 2013-10-03 | パナソニック株式会社 | 樹脂パッケージ |
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