JPWO2015008333A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2015008333A1 JPWO2015008333A1 JP2015527085A JP2015527085A JPWO2015008333A1 JP WO2015008333 A1 JPWO2015008333 A1 JP WO2015008333A1 JP 2015527085 A JP2015527085 A JP 2015527085A JP 2015527085 A JP2015527085 A JP 2015527085A JP WO2015008333 A1 JPWO2015008333 A1 JP WO2015008333A1
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 217
- 239000000758 substrate Substances 0.000 claims abstract description 208
- 239000011347 resin Substances 0.000 claims abstract description 47
- 229920005989 resin Polymers 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 40
- 238000000465 moulding Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 26
- 230000000052 comparative effect Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置10の平面図である。半導体装置10はモールド樹脂12を備えている。モールド樹脂12から第1端子14、第2端子16、第3端子18、及び制御端子20が外部に露出している。第1端子14に「P」と記載されているのは第1端子14が電源の正側(P側)に接続されるためである。第2端子16に「N」と記載されているのは第2端子16が電源の負側(N側)に接続されるためである。第3端子18に「U」と記載されているのは第3端子18がU相バスバーに接続されるためである。
本発明の実施の形態2に係る第1半導体装置と第2半導体装置は、実施の形態1に係る第1半導体装置(半導体装置10)と第2半導体装置(半導体装置50)との共通点が多いのでこれらとの相違点を中心に説明する。図13は、第1半導体装置である半導体装置100の樹脂内部を示す平面図である。半導体装置100は、図2の半導体装置10から第2ダイオード26を除去したものである。そのため、第2端子102の接続部102aは第1アノード電極24aにのみ接続されている。図14は、図13の半導体装置100の回路図である。
本発明の実施の形態3に係る第1半導体装置と第2半導体装置は、実施の形態1に係る第1半導体装置(半導体装置10)と第2半導体装置(半導体装置50)との共通点が多いので、これらとの相違点を中心に説明する。図18は、第1半導体装置である半導体装置120の樹脂内部を示す平面図である。半導体装置120は、図2の半導体装置から第2スイッチング素子32を除去したものである。そのため、第3端子122の接続部122bは第1基板21に電気的に接続され、接続部122aは第1エミッタ電極30aに電気的に接続されている。図19は、図18の半導体装置120の回路図である。
本発明の実施の形態4に係る半導体装置は、実施の形態1に係る半導体装置10との共通点が多いので、半導体装置10との相違点を中心に説明する。図23は、本発明の実施の形態4に係る半導体装置200の回路図である。半導体装置200は、容量が比較的小さいクランプダイオード202を備えている。クランプダイオード202のカソード電極は第1端子14に接続され、アノード電極は第3端子18に接続されている。
本発明の実施の形態5に係る半導体装置は、実施の形態1に係る半導体装置50との共通点が多いので、半導体装置50との相違点を中心に説明する。図25は、本発明の実施の形態5に係る半導体装置210の回路図である。半導体装置210は、容量が比較的小さいクランプダイオード212を備えている。クランプダイオード212のカソード電極は第3端子58に接続され、アノード電極は第2端子56に接続されている。
図27は、本発明の実施の形態6に係る半導体装置の斜視図である。半導体装置300は冷却器302を有している。冷却器302の主面302aには第1半導体装置304、306、308と第2半導体装置310、312、314が搭載されている。第1半導体装置304、306、308はそれぞれが実施の形態1に係る半導体装置10と同様の構成を有している。従って、第1半導体装置304は右側にP側に接続される第1端子14、中央にN側に接続される第2端子16、左側に負荷に接続される第3端子18を備えている。
Claims (10)
- 導電体で形成された第1基板と、
第1カソード電極と第1アノード電極を有し、前記第1カソード電極が前記第1基板に電気的に接続された第1ダイオードと、
導電体で形成された第2基板と、
第1エミッタ電極、第1コレクタ電極、及び第1ゲート電極を有し、前記第1コレクタ電極が前記第2基板に電気的に接続された第1スイッチング素子と、
第2エミッタ電極、第2コレクタ電極、及び第2ゲート電極を有し、前記第2コレクタ電極が前記第2基板に電気的に接続された第2スイッチング素子と、
前記第2基板に電気的に接続された第1端子と、
前記第1アノード電極に電気的に接続された第2端子と、
前記第1エミッタ電極、前記第2エミッタ電極、及び前記第1基板と電気的に接続された第3端子と、
前記第1端子、前記第2端子、及び前記第3端子の一部を外部に露出させつつ、前記第1基板、前記第1ダイオード、前記第2基板、前記第1スイッチング素子、及び前記第2スイッチング素子を覆うモールド樹脂と、を備えたことを特徴とする半導体装置。 - 第2カソード電極と第2アノード電極を有し、前記第2カソード電極が前記第1基板に電気的に接続され、前記第2アノード電極が前記第2端子に電気的に接続された第2ダイオードを備え、
前記モールド樹脂は、前記第2ダイオードを覆うことを特徴とする請求項1に記載の半導体装置。 - 導電体で形成された第1基板と、
第1カソード電極と第1アノード電極を有し、前記第1カソード電極が前記第1基板に電気的に接続された第1ダイオードと、
第2カソード電極と第2アノード電極を有し、前記第2カソード電極が前記第1基板に電気的に接続された第2ダイオードと、
導電体で形成された第2基板と、
第1エミッタ電極、第1コレクタ電極、及び第1ゲート電極を有し、前記第1コレクタ電極が前記第2基板に電気的に接続された第1スイッチング素子と、
前記第2基板に電気的に接続された第1端子と、
前記第1アノード電極、及び前記第2アノード電極に電気的に接続された第2端子と、
前記第1エミッタ電極、及び前記第1基板に電気的に接続された第3端子と、
前記第1端子、前記第2端子、及び前記第3端子の一部を外部に露出させつつ、前記第1基板、前記第1ダイオード、前記第2ダイオード、前記第2基板、及び前記第1スイッチング素子を覆うモールド樹脂と、を備えたことを特徴とする半導体装置。 - カソード電極とアノード電極を有し、前記カソード電極が前記第2基板に電気的に接続され、前記アノード電極が前記第3端子に電気的に接続されたクランプダイオードを備えたことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 導電体で形成された第1基板と、
第1カソード電極と第1アノード電極を有し、前記第1カソード電極が前記第1基板に電気的に接続された第1ダイオードと、
第2カソード電極と第2アノード電極を有し、前記第2カソード電極が前記第1基板に電気的に接続された第2ダイオードと、
導電体で形成された第2基板と、
第1エミッタ電極、第1コレクタ電極、及び第1ゲート電極を有し、前記第1コレクタ電極が前記第2基板に電気的に接続された第1スイッチング素子と、
前記第1基板と電気的に接続された第1端子と、
前記第1エミッタ電極に電気的に接続された第2端子と、
前記第2基板、前記第1アノード電極、及び前記第2アノード電極に電気的に接続された第3端子と、
前記第1端子、前記第2端子、及び前記第3端子の一部を外部に露出させつつ、前記第1基板、前記第1ダイオード、前記第2ダイオード、前記第2基板、及び前記第1スイッチング素子を覆うモールド樹脂と、を備えたことを特徴とする半導体装置。 - 第2エミッタ電極、第2コレクタ電極、及び第2ゲート電極を有し、前記第2エミッタ電極が前記第2端子に電気的に接続され、前記第2コレクタ電極が前記第2基板に電気的に接続された第2スイッチング素子を備え、
前記モールド樹脂は前記第2スイッチング素子を覆うことを特徴とする請求項5に記載の半導体装置。 - 導電体で形成された第1基板と、
第1カソード電極と第1アノード電極を有し、前記第1カソード電極が前記第1基板に電気的に接続された第1ダイオードと、
導電体で形成された第2基板と、
第1エミッタ電極、第1コレクタ電極、及び第1ゲート電極を有し、前記第1コレクタ電極が前記第2基板に電気的に接続された第1スイッチング素子と、
第2エミッタ電極、第2コレクタ電極、及び第2ゲート電極を有し、前記第2コレクタ電極が前記第2基板に電気的に接続された第2スイッチング素子と、
前記第1基板と電気的に接続された第1端子と、
前記第1エミッタ電極、及び前記第2エミッタ電極に電気的に接続された第2端子と、
前記第2基板、及び前記第1アノード電極に電気的に接続された第3端子と、
前記第1端子、前記第2端子、及び前記第3端子の一部を外部に露出させつつ、前記第1基板、前記第1ダイオード、前記第2基板、前記第1スイッチング素子、及び前記第2スイッチング素子を覆うモールド樹脂と、を備えたことを特徴とする半導体装置。 - カソード電極とアノード電極を有し、前記カソード電極が前記第2基板に電気的に接続され、前記アノード電極が前記第2端子に電気的に接続されたクランプダイオードを備えたことを特徴とする請求項5乃至7のいずれか1項に記載の半導体装置。
- 導電体で形成された第1基板と、
第1カソード電極と第1アノード電極を有し、前記第1カソード電極が前記第1基板に電気的に接続された第1ダイオードと、
導電体で形成された第2基板と、
第1エミッタ電極、第1コレクタ電極、及び第1ゲート電極を有し、前記第1コレクタ電極が前記第2基板に電気的に接続された第1スイッチング素子と、
第2エミッタ電極、第2コレクタ電極、及び第2ゲート電極を有し、前記第2コレクタ電極が前記第2基板に電気的に接続された第2スイッチング素子と、
前記第2基板に電気的に接続された第1端子と、
前記第1アノード電極に電気的に接続された第2端子と、
前記第1エミッタ電極、前記第2エミッタ電極、及び前記第1基板と電気的に接続された第3端子と、
前記第1端子、前記第2端子、及び前記第3端子の一部を外部に露出させつつ、前記第1基板、前記第1ダイオード、前記第2基板、前記第1スイッチング素子、及び前記第2スイッチング素子を覆うモールド樹脂と、を備えた第1半導体装置と、
導電体で形成された第3基板と、
第3カソード電極と第3アノード電極を有し、前記第3カソード電極が前記第3基板に電気的に接続された第3ダイオードと、
第4カソード電極と第4アノード電極を有し、前記第4カソード電極が前記第3基板に電気的に接続された第4ダイオードと、
導電体で形成された第4基板と、
第3エミッタ電極、第3コレクタ電極、及び第3ゲート電極を有し、前記第3コレクタ電極が前記第4基板に電気的に接続された第3スイッチング素子と、
前記第3基板と電気的に接続された第4端子と、
前記第3エミッタ電極に電気的に接続された第5端子と、
前記第4基板、前記第3アノード電極、及び前記第4アノード電極に電気的に接続された第6端子と、
前記第4端子、前記第5端子、及び前記第6端子の一部を外部に露出させつつ、前記第3基板、前記第3ダイオード、前記第4ダイオード、前記第4基板、及び前記第3スイッチング素子を覆うモールド樹脂と、を備えた第2半導体装置と、
前記第1半導体装置と前記第2半導体装置を搭載する冷却器と、を有し、
前記第1端子は前記第4端子と正対し、
前記第2端子は前記第5端子と正対し、
前記第3端子は前記第6端子と正対することを特徴とする半導体装置。 - 導電体で形成された第1基板と、
第1カソード電極と第1アノード電極を有し、前記第1カソード電極が前記第1基板に電気的に接続された第1ダイオードと、
第2カソード電極と第2アノード電極を有し、前記第2カソード電極が前記第1基板に電気的に接続された第2ダイオードと、
導電体で形成された第2基板と、
第1エミッタ電極、第1コレクタ電極、及び第1ゲート電極を有し、前記第1コレクタ電極が前記第2基板に電気的に接続された第1スイッチング素子と、
前記第2基板に電気的に接続された第1端子と、
前記第1アノード電極、及び前記第2アノード電極に電気的に接続された第2端子と、
前記第1エミッタ電極、及び前記第1基板に電気的に接続された第3端子と、
前記第1端子、前記第2端子、及び前記第3端子の一部を外部に露出させつつ、前記第1基板、前記第1ダイオード、前記第2ダイオード、前記第2基板、及び前記第1スイッチング素子を覆うモールド樹脂と、を備えた第1半導体装置と、
導電体で形成された第3基板と、
第3カソード電極と第3アノード電極を有し、前記第3カソード電極が前記第3基板に電気的に接続された第3ダイオードと、
導電体で形成された第4基板と、
第2エミッタ電極、第2コレクタ電極、及び第2ゲート電極を有し、前記第2コレクタ電極が前記第4基板に電気的に接続された第2スイッチング素子と、
第3エミッタ電極、第3コレクタ電極、及び第3ゲート電極を有し、前記第3コレクタ電極が前記第4基板に電気的に接続された第3スイッチング素子と、
前記第3基板と電気的に接続された第4端子と、
前記第2エミッタ電極、及び前記第3エミッタ電極に電気的に接続された第5端子と、
前記第4基板、及び前記第3アノード電極に電気的に接続された第6端子と、
前記第4端子、前記第5端子、及び前記第6端子の一部を外部に露出させつつ、前記第3基板、前記第3ダイオード、前記第4基板、前記第2スイッチング素子、及び前記第3スイッチング素子を覆うモールド樹脂と、を備えた第2半導体装置と、
前記第1半導体装置と前記第2半導体装置を搭載する冷却器と、を有し、
前記第1端子は前記第4端子と正対し、
前記第2端子は前記第5端子と正対し、
前記第3端子は前記第6端子と正対することを特徴とする半導体装置。
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US20160126168A1 (en) | 2016-05-05 |
DE112013007243B4 (de) | 2023-10-05 |
DE112013007243T5 (de) | 2016-04-07 |
JP5975177B2 (ja) | 2016-08-23 |
CN105393354B (zh) | 2018-05-25 |
US10224267B2 (en) | 2019-03-05 |
WO2015008333A1 (ja) | 2015-01-22 |
CN105393354A (zh) | 2016-03-09 |
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