JPWO2012144295A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
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- 239000000126 substance Substances 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
Description
実施の形態1では、ゲート配線部を2回屈曲させた半導体装置について説明する。図2および図3に示すように、インバータ回路のセルにおける半導体基板SUBの表面には、素子分離絶縁膜EBによって電気的に互いに絶縁された2つの素子形成領域PER,NER(活性領域)が規定されている。一方の素子形成領域PERでは、その表面から所定の深さにわたりNウェルNWが形成されている。他方の素子形成領域NERでは、その表面から所定の深さにわたりPウェルPWが形成されている。
実施の形態2では、ゲート配線部を1回屈曲させた半導体装置の第1の例について説明する。図7、図8および図9に示すように、ゲート配線部GHBは、第1ゲート電極部GEB1を含む第1ゲート配線部GHB1と、第2ゲート電極部GEB2を含む第2ゲート配線部GHB2とを備えている。
実施の形態3では、ゲート配線部を1回屈曲させた半導体装置の第2の例について説明する。
すでに述べたように、所定の寸法等をもってゲート電極部(ゲート配線部)が素子形成領域PERと素子形成領域NERとを横切るようにするためには、ゲート配線部を、素子形成領域PER(PER)から素子分離絶縁膜EB上へ向かって、所定の長さ分延在させる必要がある。ゲート配線部のパターン(形状)は、実質的にゲート配線本体のパターニングに依存する。ゲート配線本体は、たとえば、ポリシリコン膜等の上に写真製版処理によってレジストパターンを形成し、そのレジストパターンをマスクとしてポリシリコン膜等にエッチングを施すことによりパターニングされる。
Claims (7)
- 電源電位と接地電位との間に相補型スイッチング素子を直列に接続したインバータ回路を含む半導体装置であって、
主表面を有する半導体基板と、
前記半導体基板の表面上に形成され、第1の方向に平行に延在し、電源電位が印加される電源配線と、
前記半導体基板の表面上に形成され、前記電源配線に対して前記第1の方向と直交する第2の方向に距離を隔てて前記第1の方向に平行に延在し、接地電位が印加される接地配線と、
前記電源配線と前記接地配線とによって挟まれた前記半導体基板の領域において素子分離絶縁膜によってそれぞれ規定され、前記相補型スイッチング素子のための2つの素子形成領域と、
前記素子形成領域のそれぞれを横切るように形成されたゲート配線部と
を有し、
前記ゲート配線部は、
前記電源配線が配置されている側および前記接地配線が配置されている側の一方の側から他方の側へ前記第2の方向に平行に形成されて、前記素子形成領域内における所定の位置まで延在する第1ゲート配線部と、
前記第1ゲート配線部から前記他方の側へ、前記第2の方向に対して斜めに交差する第3の方向に平行に形成されて、前記素子形成領域と前記素子分離絶縁膜との境界として前記第1の方向に平行な境界を斜めに跨ぐように延在する第2ゲート配線部と
を備えた、半導体装置。 - 前記ゲート配線部は、前記第2ゲート配線部から前記他方の側へ、前記第2の方向に平行にさらに延在する第3ゲート配線部を含む、請求項1記載の半導体装置。
- 前記第2ゲート配線部は、前記他方の側へ、前記第3の方向に平行に前記素子分離絶縁膜上をさらに延在する、請求項1記載の半導体装置。
- 前記第1ゲート配線部に対して前記第2ゲート配線部のなす角度は10°〜80°である、請求項1記載の半導体装置。
- 前記第1ゲート配線部に対して前記第2ゲート配線部のなす角度は45°である、請求項4記載の半導体装置。
- 前記ゲート配線部は、互いに間隔を隔てて対向する両側面を有するゲート配線本体を含み、
前記ゲート配線本体は、前記一方の側の終端部および前記他方の側の終端部として、前記両側面に直交する終端面を有する、請求項1記載の半導体装置。 - 主表面を有する半導体基板と、
前記半導体基板において、素子分離絶縁膜によって規定された素子形成領域と、
前記素子形成領域を横切るように形成されたゲート配線部と
を有し、
前記ゲート配線部は、
前記素子形成領域と前記素子分離絶縁膜との境界に向かって前記境界が延在する方向と直交する方向に形成されて、前記素子形成領域内における所定の位置まで延在する第1ゲート配線部と、
前記第1ゲート配線部から屈曲して前記境界を斜めに跨ぐように延在する第2ゲート配線部と
を備えた、半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013510924A JP5711812B2 (ja) | 2011-04-20 | 2012-03-26 | 半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011093880 | 2011-04-20 | ||
JP2011093880 | 2011-04-20 | ||
JP2013510924A JP5711812B2 (ja) | 2011-04-20 | 2012-03-26 | 半導体装置 |
PCT/JP2012/057690 WO2012144295A1 (ja) | 2011-04-20 | 2012-03-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2012144295A1 true JPWO2012144295A1 (ja) | 2014-07-28 |
JP5711812B2 JP5711812B2 (ja) | 2015-05-07 |
Family
ID=47041413
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013510924A Expired - Fee Related JP5711812B2 (ja) | 2011-04-20 | 2012-03-26 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9054103B2 (ja) |
JP (1) | JP5711812B2 (ja) |
WO (1) | WO2012144295A1 (ja) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02170437A (ja) * | 1988-12-22 | 1990-07-02 | Fuji Electric Co Ltd | Mis型半導体装置の製造方法 |
JPH05198593A (ja) | 1992-01-22 | 1993-08-06 | Hitachi Ltd | パラメータ抽出方法 |
US5420447A (en) * | 1993-01-29 | 1995-05-30 | Sgs-Thomson Microelectronics, Inc. | Double buffer base gate array cell |
JP4301462B2 (ja) * | 1997-09-29 | 2009-07-22 | 川崎マイクロエレクトロニクス株式会社 | 電界効果トランジスタ |
JPH11330461A (ja) * | 1998-05-14 | 1999-11-30 | Nec Corp | 屈曲ゲート電極を有する半導体装置およびその製造方法 |
JP2009032788A (ja) * | 2007-07-25 | 2009-02-12 | Renesas Technology Corp | 半導体装置 |
-
2012
- 2012-03-26 US US14/112,926 patent/US9054103B2/en active Active
- 2012-03-26 WO PCT/JP2012/057690 patent/WO2012144295A1/ja active Application Filing
- 2012-03-26 JP JP2013510924A patent/JP5711812B2/ja not_active Expired - Fee Related
-
2015
- 2015-05-14 US US14/711,771 patent/US20150243735A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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US20140043063A1 (en) | 2014-02-13 |
WO2012144295A1 (ja) | 2012-10-26 |
US9054103B2 (en) | 2015-06-09 |
JP5711812B2 (ja) | 2015-05-07 |
US20150243735A1 (en) | 2015-08-27 |
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