JPWO2010073800A1 - Electronic parts and manufacturing method thereof - Google Patents

Electronic parts and manufacturing method thereof Download PDF

Info

Publication number
JPWO2010073800A1
JPWO2010073800A1 JP2010543960A JP2010543960A JPWO2010073800A1 JP WO2010073800 A1 JPWO2010073800 A1 JP WO2010073800A1 JP 2010543960 A JP2010543960 A JP 2010543960A JP 2010543960 A JP2010543960 A JP 2010543960A JP WO2010073800 A1 JPWO2010073800 A1 JP WO2010073800A1
Authority
JP
Japan
Prior art keywords
resin layer
pattern
manufacturing
electronic component
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010543960A
Other languages
Japanese (ja)
Other versions
JP5310743B2 (en
Inventor
水越　正孝
正孝 水越
石月　義克
義克 石月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2010543960A priority Critical patent/JP5310743B2/en
Publication of JPWO2010073800A1 publication Critical patent/JPWO2010073800A1/en
Application granted granted Critical
Publication of JP5310743B2 publication Critical patent/JP5310743B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4658—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0108—Transparent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0352—Differences between the conductors of different layers of a multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Abstract

【課題】電子部品とその製造方法において、従来よりも微細な導体パターンを形成すること。【解決手段】透明支持基材１１の上に樹脂層１３を形成する工程と、一方の主面１４ｘにパターン１４ｗが形成された導体プレート１４を樹脂層１３に押し当て、該樹脂層１３にパターン１４ｗを埋め込む工程と、樹脂層１３が現れるまで導体プレート１４の他方の主面１４ｙに対して研磨、CMP、又は切削を行い、パターン１４ｗを樹脂層１３に導体パターン１４ｚとして残す工程とを有する電子部品の製造方法による。【選択図】図１In an electronic component and a method for manufacturing the same, a conductor pattern finer than conventional ones is formed. A step of forming a resin layer 13 on a transparent support substrate 11, and a conductor plate 14 having a pattern 14w formed on one main surface 14x are pressed against the resin layer 13 to form a pattern on the resin layer 13. Electrons having a step of embedding 14w and a step of polishing, CMP, or cutting the other main surface 14y of the conductor plate 14 until the resin layer 13 appears, and leaving the pattern 14w as the conductor pattern 14z in the resin layer 13 Depends on the part manufacturing method. [Selection] Figure 1

Description

本発明は、電子部品とその製造方法に関する。   The present invention relates to an electronic component and a manufacturing method thereof.

LSI等の半導体素子は微細化の一途を辿っており、出荷される製品の中にはサブミクロンレベルの配線幅を有するものもある。   Semiconductor elements such as LSIs continue to be miniaturized, and some products shipped have sub-micron level wiring width.

これに対し、半導体素子を実装するための回路基板では、配線幅が最小でも１０数μm程度に留まっており、半導体素子と比べて２桁も大きな配線幅となっている。電子機器の高速度化や携帯機器の更なる小型化を実現するには、回路基板に半導体素子を高密度に実装しなければならず、そのためにも回路基板における配線幅の縮小化が望まれる。   On the other hand, in a circuit board for mounting a semiconductor element, the wiring width remains at least about a few tens of μm, and the wiring width is two orders of magnitude larger than that of the semiconductor element. In order to realize higher speed electronic devices and further miniaturization of portable devices, it is necessary to mount semiconductor elements on the circuit board at a high density, and for that purpose, it is desired to reduce the wiring width on the circuit board. .

回路基板における配線の形成方法としては、サブトラクト法、セミアディティブ法、及びインプリント法等が知られている。   As a method for forming wiring on a circuit board, a subtract method, a semi-additive method, an imprint method, and the like are known.

このうち、サブトラクト法は、レジストパターンをマスクにしながら導電膜をウエットエッチングすることにより配線を形成するものである。この方法では、エッチングが等方的に進行するため微細な配線の形成には不利であり、最小でも３５μm程度の配線幅しか実現できない。   Of these methods, the subtract method forms the wiring by wet etching the conductive film while using the resist pattern as a mask. This method is disadvantageous for the formation of fine wiring because etching proceeds isotropically, and only a wiring width of about 35 μm can be realized at a minimum.

また、セミアディティブ法では、絶縁層上にシード層を形成した後、その上にめっきレジストを形成し、シード層に給電を行いながらめっきレジストの開口内に電解めっきにより導電膜を形成する。そして、めっきレジストを除去した後にシード層をウエットエッチングすることにより、エッチングされずに残った導電膜よりなる配線が形成される。   In the semi-additive method, after a seed layer is formed on the insulating layer, a plating resist is formed thereon, and a conductive film is formed by electrolytic plating in the opening of the plating resist while supplying power to the seed layer. Then, after removing the plating resist, the seed layer is wet etched to form a wiring made of the conductive film remaining without being etched.

そのようなセミアディティブ法によれば、サブトラクト法と比較して配線幅を縮小することができる。但し、配線幅が５μm程度となると、安定した形状に配線を形成するのが困難になると共に、配線と下地との密着性が劣化する。そのため、セミアディティブ法は、幅が１０μmよりも広い配線の形成に使用されることが多い。   According to such a semi-additive method, the wiring width can be reduced as compared with the subtract method. However, when the wiring width is about 5 μm, it becomes difficult to form the wiring in a stable shape, and the adhesion between the wiring and the base deteriorates. For this reason, the semi-additive method is often used to form wiring having a width larger than 10 μm.

これに対し、インプリント法は、導体プレート（スタンパ）の表面の凹凸を樹脂層に印刻することにより、樹脂層に配線溝やホールを形成するものである。配線溝を形成した後は、配線溝にめっき法等により導電膜を形成し、樹脂層上の余分な導電膜をCMP(Chemical Mechanical Polishing)等により除去し、配線溝内に配線を形成する。   On the other hand, the imprint method is to form wiring grooves and holes in the resin layer by imprinting irregularities on the surface of the conductor plate (stamper) on the resin layer. After the wiring groove is formed, a conductive film is formed in the wiring groove by plating or the like, and an excess conductive film on the resin layer is removed by CMP (Chemical Mechanical Polishing) or the like to form a wiring in the wiring groove.

しかしながら、微細で複雑な形状の配線を形成する場合にインプリント法を用いると、樹脂層から導体プレートを剥離させるときに、樹脂層の一部が導体プレートに付着し、配線溝が欠損してしまうという問題がある。更に、導体プレートを何度も使用している間に、導体プレートに形成されている配線形状の凹凸が変形するという問題もインプリント法にはある。
特開２００７−３６２１７号公報 特開２００６−１００４６３号公報 特開２００５−５７２１号公報 特開２００６−３０３４３８号公報 特開２００８−８４９５８号公報 However, if the imprint method is used to form fine and complicated wiring, when the conductor plate is peeled from the resin layer, a part of the resin layer adheres to the conductor plate and the wiring groove is lost. There is a problem of end. Further, the imprint method also has a problem that the wiring pattern irregularities formed on the conductor plate are deformed while the conductor plate is used many times.
JP 2007-36217 A JP 2006-1000046 A JP 2005-5721 A JP 2006-303438 A JP 2008-84958 A

電子部品とその製造方法において、従来よりも微細な導体パターンを形成することを目的とする。   An object of the present invention is to form a finer conductor pattern than ever before in an electronic component and a method for manufacturing the same.

以下の開示の一観点によれば、下地の上に樹脂層を形成する工程と、一方の主面にパターンが形成された導体プレートを前記樹脂層に押し当て、該樹脂層に前記パターンを埋め込む工程と、前記樹脂層が現れるまで前記導体プレートの他方の主面に対して研磨、CMP、又は切削を行い、前記パターンを前記樹脂層に導体パターンとして残す工程とを有する電子部品の製造方法が提供される。   According to one aspect of the following disclosure, a step of forming a resin layer on a base, a conductor plate having a pattern formed on one main surface is pressed against the resin layer, and the pattern is embedded in the resin layer A method of manufacturing an electronic component, comprising: a step and a step of polishing, CMP, or cutting the other main surface of the conductor plate until the resin layer appears, and leaving the pattern as a conductor pattern on the resin layer. Provided.

また、その開示の他の観点によれば、導体プレートの一方の主面に形成されたパターンを、下地の電極パッドに接続する工程と、前記導体プレートと前記下地との間に樹脂を注入して樹脂層を形成する工程と、前記樹脂層が現れるまで前記導体プレートの他方の主面に対して研磨、CMP、又は切削を行い、前記パターンを前記樹脂層に導体パターンとして残す工程とを有する電子部品の製造方法が提供される。   According to another aspect of the disclosure, a step of connecting a pattern formed on one main surface of the conductor plate to an underlying electrode pad, and injecting resin between the conductor plate and the underlying Forming a resin layer, and polishing, CMP, or cutting the other main surface of the conductor plate until the resin layer appears, and leaving the pattern as a conductor pattern on the resin layer. An electronic component manufacturing method is provided.

そして、その開示の別の観点によれば、一方の主面に凹部が形成された複数の下地を並べる工程と、前記下地の各々の前記凹部に、導体プレートの一方の主面に形成されたパターンの突起を嵌入することにより、前記複数の下地を前記導体プレートにより繋ぐ工程と、前記複数の下地のそれぞれの主面上に樹脂層を形成する工程と、前記樹脂層が現れるまで前記導体プレートの他方の主面に対して研磨、CMP、又は切削を行い、前記パターンを前記樹脂層に導体パターンとして残す工程とを有する電子部品の製造方法が提供される。   According to another aspect of the disclosure, the step of arranging a plurality of bases having recesses formed on one main surface, and the recesses of each of the bases are formed on one main surface of the conductor plate. A step of connecting the plurality of bases by the conductor plate by inserting projections of a pattern; a step of forming a resin layer on each main surface of the plurality of bases; and the conductor plate until the resin layer appears. There is provided a method of manufacturing an electronic component including a step of polishing, CMP, or cutting the other main surface of the substrate and leaving the pattern as a conductor pattern on the resin layer.

また、その開示の更に他の観点によれば、下地と、前記下地の上に形成された電極パッドと、前記下地と前記電極パッドの上に形成された樹脂層と、前記電極パッドの上の前記樹脂層に埋め込まれた導体パターンとを有し前記導体パターンと前記電極パッドとが低融点金属を介して接合された電子部品が提供される。   According to still another aspect of the disclosure, a base, an electrode pad formed on the base, a resin layer formed on the base and the electrode pad, and the electrode pad An electronic component having a conductor pattern embedded in the resin layer and having the conductor pattern and the electrode pad bonded together via a low-melting point metal is provided.

そして、その開示の更に別の観点によれば、下地と、前記下地の上に形成された電極パッドと、前記下地と前記電極パッドの上に形成された樹脂層と、前記樹脂層に埋め込まれ、前記電極パッドに当接した突起を備えた導体パターンとを有し、前記突起の先端が、前記電極パッドの上面において横方向に潰れた電子部品が提供される。   According to still another aspect of the disclosure, a base, an electrode pad formed on the base, a resin layer formed on the base and the electrode pad, and embedded in the resin layer There is provided an electronic component having a conductor pattern provided with a protrusion abutting on the electrode pad, the tip of the protrusion being crushed laterally on the upper surface of the electrode pad.

図１（ａ）、（ｂ）は、第１実施形態に係る電子部品の製造途中の断面図（その１）である。1A and 1B are cross-sectional views (part 1) in the course of manufacturing the electronic component according to the first embodiment. 図２（ａ）、（ｂ）は、第１実施形態に係る電子部品の製造途中の断面図（その２）である。2A and 2B are cross-sectional views (part 2) in the course of manufacturing the electronic component according to the first embodiment. 図３（ａ）、（ｂ）は、第２実施形態に係る電子部品の製造途中の断面図（その１）である。3A and 3B are cross-sectional views (part 1) in the course of manufacturing the electronic component according to the second embodiment. 図４（ａ）、（ｂ）は、第２実施形態に係る電子部品の製造途中の断面図（その２）である。4A and 4B are cross-sectional views (part 2) in the middle of manufacturing the electronic component according to the second embodiment. 図５（ａ）、（ｂ）は、第３実施形態に係る電子部品の製造途中の断面図（その１）である。5A and 5B are cross-sectional views (part 1) in the course of manufacturing the electronic component according to the third embodiment. 図６（ａ）、（ｂ）は、第３実施形態に係る電子部品の製造途中の断面図（その２）である。6A and 6B are cross-sectional views (part 2) in the middle of manufacturing the electronic component according to the third embodiment. 図７は、第３実施形態に係る電子部品の製造途中の断面図（その３）である。FIG. 7: is sectional drawing (the 3) in the middle of manufacture of the electronic component which concerns on 3rd Embodiment. 図８（ａ）、（ｂ）は、第４実施形態に係る電子部品の製造途中の断面図（その１）である。8A and 8B are cross-sectional views (part 1) in the middle of manufacturing the electronic component according to the fourth embodiment. 図９（ａ）、（ｂ）は、第４実施形態に係る電子部品の製造途中の断面図（その２）である。9A and 9B are cross-sectional views (part 2) in the middle of manufacturing the electronic component according to the fourth embodiment. 図１０（ａ）、（ｂ）は、第４実施形態に係る電子部品の製造途中の断面図（その３）である。10A and 10B are cross-sectional views (part 3) in the middle of manufacturing the electronic component according to the fourth embodiment. 図１１（ａ）、（ｂ）は、第５実施形態に係る電子部品の製造途中の断面図（その１）である。11A and 11B are cross-sectional views (part 1) in the middle of manufacturing the electronic component according to the fifth embodiment. 図１２（ａ）、（ｂ）は、第５実施形態に係る電子部品の製造途中の断面図（その２）である。12A and 12B are cross-sectional views (part 2) in the middle of manufacturing the electronic component according to the fifth embodiment. 図１３（ａ）、（ｂ）は、第５実施形態に係る電子部品の製造途中の断面図（その３）である。FIGS. 13A and 13B are cross-sectional views (part 3) in the course of manufacturing the electronic component according to the fifth embodiment. 図１４（ａ）、（ｂ）は、第５実施形態に係る電子部品の製造途中の断面図（その４）である。14A and 14B are cross-sectional views (part 4) in the middle of manufacturing the electronic component according to the fifth embodiment. 図１５（ａ）、（ｂ）は、第５実施形態に係る電子部品の製造途中の断面図（その５）である。15A and 15B are cross-sectional views (part 5) in the middle of manufacturing the electronic component according to the fifth embodiment. 図１６（ａ）、（ｂ）は、第５実施形態に係る電子部品の製造途中の断面図（その６）である。FIGS. 16A and 16B are cross-sectional views (part 6) in the middle of manufacturing the electronic component according to the fifth embodiment. 図１７は、第６実施形態に係る電子部品の製造途中の断面図（その１）である。FIG. 17: is sectional drawing (the 1) in the middle of manufacture of the electronic component which concerns on 6th Embodiment. 図１８は、第６実施形態に係る電子部品の製造途中の断面図（その２）である。FIG. 18 is a cross-sectional view (part 2) in the middle of manufacturing the electronic component according to the sixth embodiment. 図１９は、第６実施形態に係る電子部品の製造途中の断面図（その３）である。FIG. 19 is a cross-sectional view (part 3) in the middle of manufacturing the electronic component according to the sixth embodiment. 図２０は、第６実施形態に係る電子部品の製造途中の断面図（その４）である。FIG. 20 is a cross-sectional view (part 4) in the middle of manufacturing the electronic component according to the sixth embodiment. 図２１（ａ）、（ｂ）は、第７実施形態に係る電子部品の製造途中の断面図（その１）である。21A and 21B are cross-sectional views (part 1) in the middle of manufacturing the electronic component according to the seventh embodiment. 図２２（ａ）、（ｂ）は、第７実施形態に係る電子部品の製造途中の断面図（その２）である。22A and 22B are cross-sectional views (part 2) in the middle of manufacturing the electronic component according to the seventh embodiment. 図２３（ａ）、（ｂ）は、第８実施形態に係る電子部品の製造途中の断面図（その１）である。23A and 23B are sectional views (part 1) in the middle of manufacturing the electronic component according to the eighth embodiment. 図２４（ａ）、（ｂ）は、第８実施形態に係る電子部品の製造途中の断面図（その２）である。24A and 24B are cross-sectional views (part 2) in the middle of manufacturing the electronic component according to the eighth embodiment. 図２５は、第８実施形態に係る電子部品の製造途中の断面図（その３）である。FIG. 25 is a cross-sectional view (part 3) in the middle of manufacturing the electronic component according to the eighth embodiment. 図２６（ａ）、（ｂ）は、第８実施形態に係る電子部品の別の製造方法について示す断面図である。FIGS. 26A and 26B are cross-sectional views illustrating another method for manufacturing an electronic component according to the eighth embodiment. 図２７は、第９実施形態に係る電子部品の製造途中の断面図（その１）である。FIG. 27 is a first cross-sectional view of the electronic component according to the ninth embodiment during manufacture. 図２８は、第９実施形態に係る電子部品の製造途中の断面図（その２）である。FIG. 28 is a cross-sectional view (No. 2) in the middle of manufacturing the electronic component according to the ninth embodiment. 図２９は、第９実施形態に係る電子部品の製造途中の断面図（その３）である。FIG. 29 is a cross-sectional view (part 3) in the middle of manufacturing the electronic component according to the ninth embodiment. 図３０は、第９実施形態に係る電子部品の製造途中の断面図（その４）である。FIG. 30 is a cross-sectional view (No. 4) in the middle of manufacturing the electronic component according to the ninth embodiment. 図３１は、第９実施形態に係る電子部品の製造途中の断面図（その５）である。FIG. 31 is a sectional view (part 5) in the middle of manufacturing the electronic component according to the ninth embodiment. 図３２は、第９実施形態に係る電子部品の製造途中の断面図（その６）である。FIG. 32 is a cross-sectional view (No. 6) in the middle of manufacturing the electronic component according to the ninth embodiment. 図３３は、第９実施形態に係る電子装置の拡大平面図である。FIG. 33 is an enlarged plan view of an electronic device according to the ninth embodiment. 図３４は、図３３のI−I線に沿う断面図である。34 is a cross-sectional view taken along the line II of FIG. 図３５は、比較例に係る電子装置の断面図である。FIG. 35 is a cross-sectional view of an electronic device according to a comparative example. 図３６（ａ）、（ｂ）は、第１０実施形態の第１例に係る導体プレートの型の製造途中の断面図（その１）である。FIGS. 36A and 36B are cross-sectional views (part 1) in the middle of manufacturing the conductor plate mold according to the first example of the tenth embodiment. 図３７（ａ）、（ｂ）は、第１０実施形態の第１例に係る導体プレートの型の製造途中の断面図（その２）である。FIGS. 37A and 37B are cross-sectional views (part 2) in the middle of manufacturing the conductor plate mold according to the first example of the tenth embodiment. 図３８（ａ）、（ｂ）は、第１０実施形態の第１例に係る導体プレートの型の製造途中の断面図（その３）である。FIGS. 38A and 38B are cross-sectional views (part 3) in the middle of manufacturing the conductor plate mold according to the first example of the tenth embodiment. 図３９（ａ）、（ｂ）は、第１０実施形態の第１例に係る導体プレートの型の製造途中の断面図（その４）である。FIGS. 39A and 39B are cross-sectional views (part 4) in the middle of the manufacture of the conductor plate mold according to the first example of the tenth embodiment. 図４０（ａ）、（ｂ）は、第１０実施形態の第１例に係る導体プレートの型の製造途中の断面図（その５）である。FIGS. 40A and 40B are cross-sectional views (part 5) in the middle of manufacturing the conductor plate mold according to the first example of the tenth embodiment. 図４１（ａ）、（ｂ）は、第１０実施形態の第２例に係る導体プレートの型の製造途中の断面図（その１）である。41 (a) and 41 (b) are cross-sectional views (part 1) in the middle of the manufacture of the conductor plate mold according to the second example of the tenth embodiment. 図４２（ａ）、（ｂ）は、第１０実施形態の第２例に係る導体プレートの型の製造途中の断面図（その２）である。FIGS. 42A and 42B are cross-sectional views (part 2) in the middle of manufacturing the conductor plate mold according to the second example of the tenth embodiment. 図４３は、第１０実施形態の第２例に係る導体プレートの型の製造途中の断面図（その３）である。FIG. 43 is a cross-sectional view (No. 3) in the middle of manufacturing the mold of the conductor plate according to the second example of the tenth embodiment. 図４４は、第１０実施形態の第３例に係る導体プレートの型の製造途中の断面図（その１）である。FIG. 44 is a cross-sectional view (part 1) of the conductor plate mold according to the third example of the tenth embodiment in the middle of manufacture. 図４５は、第１０実施形態の第３例に係る導体プレートの型の製造途中の断面図（その２）である。FIG. 45: is sectional drawing (the 2) in the middle of manufacture of the type | mold of the conductor plate which concerns on the 3rd example of 10th Embodiment. 図４６は、第１０実施形態の第３例に係る導体プレートの型の製造途中の断面図（その３）である。FIG. 46 is a cross-sectional view (No. 3) of the conductive plate mold according to the third example of the tenth embodiment in the middle of manufacture. 図４７は、第１０実施形態の第３例に係る導体プレートの型の製造途中の断面図（その４）である。FIG. 47 is a cross-sectional view (No. 4) of the conductor plate mold according to the third example of the tenth embodiment in the middle of manufacture. 図４８は、第１０実施形態の第３例に係る導体プレートの型の製造途中の断面図（その５）である。FIG. 48 is a cross-sectional view (No. 5) in the middle of manufacturing the conductor plate mold according to the third example of the tenth embodiment. 図４９（ａ）、（ｂ）は、第１１実施形態に係る導体プレートの製造途中の断面図（その１）である。49A and 49B are cross-sectional views (part 1) in the middle of manufacturing the conductor plate according to the eleventh embodiment. 図５０（ａ）、（ｂ）は、第１１実施形態に係る導体プレートの製造途中の断面図（その２）である。FIGS. 50A and 50B are cross-sectional views (part 2) in the middle of manufacturing the conductor plate according to the eleventh embodiment. 図５１（ａ）、（ｂ）は、第１１実施形態に係る導体プレートの製造途中の断面図（その３）である。51A and 51B are cross-sectional views (part 3) in the middle of manufacturing the conductor plate according to the eleventh embodiment. 図５２は、第１１実施形態に係る導体プレートを利用して作製した電子装置の拡大断面図である。FIG. 52 is an enlarged cross-sectional view of an electronic device manufactured using the conductor plate according to the eleventh embodiment.

以下に、添付図面を参照しながら、各実施形態について詳細に説明する。   Hereinafter, each embodiment will be described in detail with reference to the accompanying drawings.

（１）第１実施形態
図１〜図２は、本実施形態に係る電子部品の製造途中の断面図である。(1) 1st Embodiment FIGS. 1-2 is sectional drawing in the middle of manufacture of the electronic component which concerns on this embodiment.

本実施形態では、電子部品として回路基板を以下のようにして作製する。   In this embodiment, a circuit board is produced as an electronic component as follows.

まず、図１（ａ）に示すように、ガラス基板のような透明支持基板１１の上に接着層１２を形成する。その接着層１２としては、紫外線の照射によって接着力が低下するUVテープや、加熱によって接着力が低下する熱発泡粘着フィルム等を使用するのが好ましい。   First, as shown in FIG. 1A, an adhesive layer 12 is formed on a transparent support substrate 11 such as a glass substrate. As the adhesive layer 12, it is preferable to use a UV tape whose adhesive strength is reduced by irradiation of ultraviolet rays, a thermally foamed adhesive film whose adhesive strength is reduced by heating, or the like.

次いで、接着層１２の上に、熱硬化性樹脂又は熱可塑性樹脂を塗布し、これらの材料よりなる第１の樹脂層１３を例えば１０〜２０μm程度の厚さに形成する。但し、この厚さは、後述する導体プレートの凸パターンの高さに応じて設定されるものである。   Next, a thermosetting resin or a thermoplastic resin is applied on the adhesive layer 12, and the first resin layer 13 made of these materials is formed to a thickness of about 10 to 20 μm, for example. However, this thickness is set according to the height of the convex pattern of the conductor plate described later.

第１の樹脂層１３として使用し得る熱硬化性樹脂としては、例えば、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等がある。   Examples of the thermosetting resin that can be used as the first resin layer 13 include an epoxy resin, a silicone resin, a cyanate resin, a polyolefin resin, an acrylic resin, and benzocyclobutene.

これらの熱硬化性樹脂を使用する場合は、第１の樹脂層１３を形成した後に、加熱により第１の樹脂層１３を半硬化（Bステージ）の状態にするのが好ましい。   When these thermosetting resins are used, it is preferable that the first resin layer 13 is semi-cured (B stage) by heating after the first resin layer 13 is formed.

また、このように樹脂を塗布する代わりに、予め半硬化（Bステージ）の状態に形成したフィルムを第１の樹脂層１３として接着層１２上に貼り付けてもよい。   Further, instead of applying the resin in this way, a film formed in a semi-cured (B stage) state in advance may be pasted on the adhesive layer 12 as the first resin layer 13.

その後に、一方の主面１４ｘに凸パターン１４ｗが形成された第１の導体プレート１４を第１の樹脂層１３の上に配置し、透明支持基板１１と第１の導体プレート１４との位置合わせを行う。   Thereafter, the first conductive plate 14 having the convex pattern 14w formed on one main surface 14x is disposed on the first resin layer 13, and the transparent support substrate 11 and the first conductive plate 14 are aligned. I do.

第１の導体プレート１４の材料は特に限定されない。本実施形態では、配線抵抗の低減に有用な銅又は銅合金を第１の導体プレート１４の材料として使用する。   The material of the first conductor plate 14 is not particularly limited. In the present embodiment, copper or a copper alloy useful for reducing the wiring resistance is used as the material of the first conductor plate 14.

また、第１の導体プレート１４の凸パターン１４ｗは、図示のように高さの異なる二水準の第１及び第２の凸部１４ａ、１４ｂを有する。   Further, the convex pattern 14w of the first conductor plate 14 has two levels of first and second convex portions 14a and 14b having different heights as shown in the drawing.

次いで、図１（ｂ）に示すように、減圧雰囲気下において第１の樹脂層１３に第１の導体プレート１４を押し当て、第１の樹脂層１３に凸パターン１４ｗを埋め込む。   Next, as shown in FIG. 1B, the first conductive plate 14 is pressed against the first resin layer 13 in a reduced pressure atmosphere, and the convex pattern 14 w is embedded in the first resin layer 13.

このとき、上記のように第１の樹脂層１３を半硬化の状態としたので、第１の導体プレート１４を第１の樹脂層１３に押し当てるときに第１の樹脂層１３が流動し、第１の樹脂層１３に凸パターン１４ｗを隙間なく埋め込むことが可能となる。   At this time, since the first resin layer 13 is in a semi-cured state as described above, the first resin layer 13 flows when the first conductive plate 14 is pressed against the first resin layer 13, The convex pattern 14w can be embedded in the first resin layer 13 without a gap.

また、第１の樹脂層１３として熱可塑性樹脂を使用する場合には、第１の導体プレート１４の押し当てと同時に第１の樹脂層１３を加熱することにより、加熱によって軟化した第１の樹脂層１３に凸パターン１４ｗを容易に埋め込むことが可能となる。   When a thermoplastic resin is used as the first resin layer 13, the first resin softened by heating by heating the first resin layer 13 simultaneously with the pressing of the first conductor plate 14. The convex pattern 14w can be easily embedded in the layer 13.

更に、本工程を減圧雰囲気下において行うことにより、第１の樹脂層１３と第１の導体プレート１４との間に空気が入り込んでこれらの間に隙間が発生するのを防止できる。   Furthermore, by performing this step in a reduced-pressure atmosphere, it is possible to prevent air from entering between the first resin layer 13 and the first conductor plate 14 and generating a gap therebetween.

そして、このような凸パターン１４ｗの埋め込みにより、第１の凸部１４ａが第１の樹脂層１３の底面に到達する一方、第２の凸部１４ｂは第１の樹脂層１３の途中の深さまで埋め込まれる。   And by embedding such a convex pattern 14 w, the first convex portion 14 a reaches the bottom surface of the first resin layer 13, while the second convex portion 14 b reaches a depth in the middle of the first resin layer 13. Embedded.

その後、第１の樹脂層１３が熱硬化性樹脂の場合には加熱により第１の樹脂層１３を硬化する。そして、第１の樹脂層１３が熱可塑性樹脂の場合には、第１の樹脂層１３を冷却して硬化する。   Thereafter, when the first resin layer 13 is a thermosetting resin, the first resin layer 13 is cured by heating. When the first resin layer 13 is a thermoplastic resin, the first resin layer 13 is cooled and cured.

続いて、図２（ａ）に示すように、第１の樹脂層１３の表面が現れるまで第１の導体プレート１４の他方の主面１４ｙに対して研磨、CMP、又は切削を行うことで、凸パターン１４ｗを第１の樹脂層１３に第１の導体パターン１４ｚとして残す。なお、製造コストの低減という観点からすると、研磨やCMPよりもプロセスコストの安い切削により本工程を行うのが好ましい。また、切削には、研磨やCMPよりも高速で処理できるという利点もある。   Subsequently, as shown in FIG. 2A, by polishing, CMP, or cutting the other main surface 14y of the first conductor plate 14 until the surface of the first resin layer 13 appears, The convex pattern 14w is left in the first resin layer 13 as the first conductor pattern 14z. From the viewpoint of reducing the manufacturing cost, it is preferable to perform this step by cutting at a lower process cost than polishing or CMP. Cutting also has the advantage that it can be processed at higher speeds than polishing or CMP.

その後に、透明支持基板１１を介して接着層１２に紫外線を照射することにより接着層１２の接着力を低下させ、透明支持基板１１から第１の樹脂層１３を剥離する。なお、接着層１２として熱発泡フィルムを使用する場合には、加熱によって接着層１２の接着力を低下させればよい。そのような熱発泡フィルムとしては、熱硬化性の第１の樹脂層１３を熱硬化させるときの熱によって剥離性に影響が出ないものを選択するのが好ましい。   Thereafter, the adhesive layer 12 is irradiated with ultraviolet rays through the transparent support substrate 11 to reduce the adhesive force of the adhesive layer 12, and the first resin layer 13 is peeled from the transparent support substrate 11. In addition, what is necessary is just to reduce the adhesive force of the contact bonding layer 12 by heating, when using a thermally foamed film as the contact bonding layer 12. As such a thermally foamed film, it is preferable to select a film that does not affect the peelability by heat when the thermosetting first resin layer 13 is thermoset.

以上により、図２（ｂ）に示すように、第１の樹脂層１３内に第１の導体パターン１４ｚを形成してなる回路基板１０の基本構造が完成したことになる。   As described above, as shown in FIG. 2B, the basic structure of the circuit board 10 in which the first conductor pattern 14z is formed in the first resin layer 13 is completed.

その第１の導体パターン１４ｚのうち、第１の凸部１４ａ（図１（ｂ）参照）に相当する部分は導体プラグとして機能し、第２の凸部１４ｂに対応する部分は配線として機能する。   Of the first conductor pattern 14z, a portion corresponding to the first convex portion 14a (see FIG. 1B) functions as a conductor plug, and a portion corresponding to the second convex portion 14b functions as a wiring. .

ここまでの工程により、本実施形態に係る電子部品の製造方法の主要工程が終了したことになる。   With the steps so far, the main steps of the electronic component manufacturing method according to the present embodiment are completed.

上記した本実施形態によれば、第１の導体プレート１４の凸パターン１４ｗ自身を第１の導体パターン１４ｚとして利用するので、インプリント法のように第１の樹脂層１３から第１の導体プレート１４を剥離する必要がない。   According to the above-described embodiment, since the convex pattern 14w itself of the first conductor plate 14 is used as the first conductor pattern 14z, from the first resin layer 13 to the first conductor plate as in the imprint method. There is no need to peel 14.

そのため、第１の導体プレート１４の剥離時に第１の樹脂層１３の一部が欠損するというインプリント法の問題を克服することができ、最小の配線幅が１μm程度の微細な配線を高い歩留まりで形成することが可能となる。   Therefore, it is possible to overcome the problem of the imprint method in which a part of the first resin layer 13 is lost when the first conductor plate 14 is peeled off, and a fine wiring having a minimum wiring width of about 1 μm is obtained with a high yield. Can be formed.

しかも、第１の導体パターン１４ｚの形成にあたっては、めっき法により導電膜を形成したりフォトリソグラフィにより導電膜をパターニングしたりする工程が不要となるので、サブトラクト法やセミアディティブ法と比較して製造コストが安価になる。   In addition, the formation of the first conductor pattern 14z does not require a step of forming a conductive film by plating or patterning the conductive film by photolithography, so that it is manufactured in comparison with the subtractive method or the semi-additive method. Cost is low.

（２）第２実施形態
図３〜図４は、本実施形態に係る電子部品の製造途中の断面図である。なお、これらの図において第１実施形態で説明したのと同じ要素には第１実施形態におけるのと同じ符号を付し、以下ではその説明を省略する。(2) 2nd Embodiment FIGS. 3-4 is sectional drawing in the middle of manufacture of the electronic component which concerns on this embodiment. In these drawings, the same elements as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted below.

第１実施形態では、図２（ｂ）に示したように、一層の第１の導体パターン１４ｚを備えた回路基板１０を作製したが、本実施形態では以下のようにして二層の導体パターンが積層された回路基板を作製する。   In the first embodiment, as shown in FIG. 2B, the circuit board 10 including the first conductor pattern 14z of one layer is manufactured. In the present embodiment, the two-layer conductor pattern is formed as follows. A circuit board on which is stacked is manufactured.

その回路基板を作製するには、まず、第１実施形態で説明した図１（ａ）〜図２（ａ）の工程を行う。   In order to fabricate the circuit board, first, the steps shown in FIGS. 1A to 2A described in the first embodiment are performed.

次いで、図３（ａ）に示すように、第１の樹脂層１３と第１の導体パターン１４ｚのそれぞれの上に、熱硬化性の第２の樹脂層１７を形成する。そして、この第２の樹脂層１７を加熱することにより半硬化の状態とする。   Next, as shown in FIG. 3A, a thermosetting second resin layer 17 is formed on each of the first resin layer 13 and the first conductor pattern 14z. Then, the second resin layer 17 is heated to a semi-cured state.

なお、第２の樹脂層１７として使用し得る熱硬化性樹脂としては、第１実施形態で説明したように、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等がある。   The thermosetting resin that can be used as the second resin layer 17 includes, as described in the first embodiment, an epoxy resin, a silicone resin, a cyanate resin, a polyolefin resin, an acrylic resin, and There are benzocyclobutene and the like.

また、これらの熱硬化性樹脂に代えて、熱可塑性樹脂を使用してもよい。   Further, instead of these thermosetting resins, thermoplastic resins may be used.

その後に、一方の主面１８ｘに凸パターン１８ｗが形成された第２の導体プレート１８を第２の樹脂層１７の上方に配置し、透明支持基板１１と第２の導体プレート１８との位置合わせを行う。   Thereafter, the second conductor plate 18 having the convex pattern 18w formed on one main surface 18x is disposed above the second resin layer 17, and the transparent support substrate 11 and the second conductor plate 18 are aligned. I do.

その第２の導体プレート１８は、例えば銅や銅合金よりなり、配線形状の凸部１８ｃの他に、第１及び第２の突起１８ａ、１８ｂを有する。   The second conductor plate 18 is made of, for example, copper or a copper alloy, and includes first and second protrusions 18a and 18b in addition to the wiring-shaped convex portion 18c.

このうち、第１の突起１８ａは先の尖った錐状先端を有しているのに対し、第２の突起１８ｂの先端は平坦であり、その幅は第１の突起１８ａや凸部１８ｃといった凸パターン１８ｗの他の部位の幅よりも広く、例えば１００〜数１００μmの幅を有する。   Among these, the first protrusion 18a has a pointed cone-shaped tip, whereas the tip of the second protrusion 18b is flat, and the width thereof is such as the first protrusion 18a or the convex portion 18c. The width is wider than other portions of the convex pattern 18w, and has a width of, for example, 100 to several hundred μm.

次いで、図３（ｂ）に示すように、半硬化の状態にある第２の樹脂層１７に第２の導体プレート１８を押し当て、第２の樹脂層１７に凸パターン１８ｗを埋め込み、各突起１８ａ、１８ｂをその下の第１の導体パターン１４ｚに当接させる。   Next, as shown in FIG. 3B, the second conductive plate 18 is pressed against the second resin layer 17 in a semi-cured state, and the convex pattern 18w is embedded in the second resin layer 17, and each projection 18a and 18b are made to contact | abut to the 1st conductor pattern 14z under it.

このとき、点線円内に示すように、第１の突起１８ａは、下地の第１の導体パターン１４ｚと当接したことでその錐状先端が変形して基板横方向に広がる。そのように変形した錐状先端は、製造途中で導体プレート１８が第２の樹脂層１７から脱落するのを防止する機能を有すると共に、第１の導体パターン１４ｚと凸パターン１８ｗとの接触面積を拡大する機能を有する。   At this time, as shown in a dotted circle, the first protrusion 18a is in contact with the underlying first conductor pattern 14z, so that the cone-shaped tip is deformed and spreads in the lateral direction of the substrate. The deformed cone-shaped tip has a function of preventing the conductor plate 18 from falling off from the second resin layer 17 during the manufacturing process, and provides a contact area between the first conductor pattern 14z and the convex pattern 18w. Has the ability to expand.

一方、第２の突起１８ｂは、第１の突起１８ａよりも広い接触面積で下地の第１の導体パターン１４ｚや第１の樹脂層１３と当接することにより、凸パターン１８ｗが所要の深さ以上に過剰に第２の樹脂層１７に埋め込まれるのを阻止するように機能する。   On the other hand, the second protrusion 18b is in contact with the underlying first conductor pattern 14z and the first resin layer 13 with a wider contact area than the first protrusion 18a, so that the convex pattern 18w has a depth greater than a required depth. It functions to prevent the second resin layer 17 from being excessively embedded in the second resin layer 17.

その後に、第２の樹脂層１７を加熱して硬化させる。   Thereafter, the second resin layer 17 is heated and cured.

なお、第２の樹脂層１７の材料として熱可塑性樹脂を用いる場合には、加熱により第２の樹脂層１７を軟化させるのと同時に第２の樹脂層１７に凸パターン１８ｗを埋め込むのが好ましい。この場合は、凸パターン１８ｗを埋め込んだ後に第２の樹脂層１７を冷却して硬化させることになる。   When a thermoplastic resin is used as the material for the second resin layer 17, it is preferable to embed the convex pattern 18 w in the second resin layer 17 at the same time as the second resin layer 17 is softened by heating. In this case, after embedding the convex pattern 18w, the second resin layer 17 is cooled and cured.

続いて、図４（ａ）に示すように、第２の樹脂層１７の表面が現れるまで第２の導体プレート１８の他方の主面１８ｙに対して研磨、CMP、又は切削を行うことにより、凸パターン１８ｗを第２の樹脂層１７に第２の導体パターン１８ｚとして残す。   Subsequently, as shown in FIG. 4A, by polishing, CMP, or cutting the other main surface 18y of the second conductive plate 18 until the surface of the second resin layer 17 appears, The convex pattern 18w is left in the second resin layer 17 as the second conductor pattern 18z.

この後に、第１実施形態と同様に紫外線照射又は加熱により接着層１２の接着力を低下させ、透明支持基板１１から第１の樹脂層１３を剥離する。   Thereafter, as in the first embodiment, the adhesive force of the adhesive layer 12 is reduced by ultraviolet irradiation or heating, and the first resin layer 13 is peeled from the transparent support substrate 11.

これにより、図４（ｂ）に示すように、第１の導体パターン１４ｚと第２の導体パターン１８ｚとが積層された回路基板２０の基本構造が完成したことになる。   As a result, as shown in FIG. 4B, the basic structure of the circuit board 20 in which the first conductor pattern 14z and the second conductor pattern 18z are laminated is completed.

その回路基板２０では、既述の突起１８ａ、１８ｂが、上下の導体パターン１４ｚ、１８ｚ同士を電気的に接続する導体プラグとなる。また、凸部１８ｃは、第２の樹脂層１７に埋め込まれた配線となる。   In the circuit board 20, the above-described protrusions 18a and 18b serve as conductor plugs that electrically connect the upper and lower conductor patterns 14z and 18z. Further, the convex portion 18 c is a wiring embedded in the second resin layer 17.

以上説明した本実施形態によれば、樹脂層への凸パターンの埋め込みを二回行うことにより、微細な配線を上下に積層してなる回路基板２０を形成することが可能となる。   According to this embodiment described above, it is possible to form the circuit board 20 in which fine wirings are stacked one above the other by embedding the convex pattern in the resin layer twice.

また、図３（ｂ）に示したように、第１の突起１８ａの先端を錐状にしたので、該先端が第１の導体パターン１４ｚの上面に当接したときにその先端形状が潰れて横方向に広がり、第２の導体プレート１８が第２の樹脂層１７から抜け落ち難くなる。しかも、このように突起１８ａの先端が広がることで、第１の導体パターン１４ｚと第２の導体パターン１８ｚとの接触面積が増大し、各導体パターン１４ｚ、１８ｚ間のコンタクト抵抗を低減できる。   Further, as shown in FIG. 3B, since the tip of the first protrusion 18a is conical, the tip shape is crushed when the tip comes into contact with the upper surface of the first conductor pattern 14z. It spreads in the lateral direction, and the second conductor plate 18 is difficult to come off from the second resin layer 17. In addition, since the tips of the protrusions 18a expand in this way, the contact area between the first conductor pattern 14z and the second conductor pattern 18z increases, and the contact resistance between the conductor patterns 14z and 18z can be reduced.

更に、凸パターン１８ｗに第２の突起１８ｂを設けたので、第２の樹脂層１７に凸パターン１８ｗが過剰に埋め込まれるのを防止できる。   Further, since the second protrusion 18b is provided on the convex pattern 18w, it is possible to prevent the convex pattern 18w from being excessively embedded in the second resin layer 17.

特に、第２の突起１８ｂの幅を第１の突起１８ａや配線形状の凸部１８ｃよりも広くすることで、第１の突起１８ａが下地の第１の樹脂層１３等に沈み込み難くなり、凸パターン１８ｗの過剰な埋め込み防止の効果を得やすくなる。   In particular, by making the width of the second protrusion 18b wider than the first protrusion 18a and the wiring-shaped convex part 18c, the first protrusion 18a is unlikely to sink into the underlying first resin layer 13 or the like, It becomes easy to obtain the effect of preventing excessive embedding of the convex pattern 18w.

なお、このように第２の突起１８ｂの幅を広くすると、第２の突起１８ｂの電気抵抗が第１の突起１８ａや凸部１８ｃよりも小さくなるので、信号線よりも大電流が流れる電源線や接地線として第２の突起１８ｂを使用するのが好適である。   When the width of the second protrusion 18b is increased in this way, the electric resistance of the second protrusion 18b becomes smaller than that of the first protrusion 18a and the protrusion 18c, so that the power supply line through which a larger current flows than the signal line It is preferable to use the second protrusion 18b as a grounding wire.

また、上記では導体パターンの積層数を２層としたが、本実施形態はこれに限定されない。例えば、樹脂層１７を形成する工程（図３（ａ））、樹脂層１７に凸パターン１８ｗを埋め込む工程（図３（ｂ））、及び樹脂層１７に導体パターン１８ｚを残す工程（図４（ａ））を所要回数繰り返し、導体パターンの積層数を３層以上にしてもよい。   In the above description, the number of conductor patterns stacked is two, but the present embodiment is not limited to this. For example, a step of forming the resin layer 17 (FIG. 3A), a step of embedding the convex pattern 18w in the resin layer 17 (FIG. 3B), and a step of leaving the conductor pattern 18z in the resin layer 17 (FIG. 4B). a)) may be repeated a required number of times, and the number of conductor patterns stacked may be three or more.

（３）第３実施形態
図５〜図７は、本実施形態に係る電子部品の製造途中の断面図である。(3) Third Embodiment FIGS. 5 to 7 are cross-sectional views in the course of manufacturing an electronic component according to this embodiment.

第１、第２実施形態では導体プレートを利用して電子部品として回路基板を作製したが、本実施形態では、既に用意されている回路基板上に以下のように導体パターンを形成する。   In the first and second embodiments, a circuit board is manufactured as an electronic component using a conductor plate. In this embodiment, a conductor pattern is formed on a circuit board that has already been prepared as follows.

まず、図５（ａ）に示すように、樹脂基材３１の表面に例えば５〜１０μm程度の厚さの銅膜等よりなる電極パッド３２が形成された回路基板３０を用意する。   First, as shown in FIG. 5A, a circuit board 30 is prepared in which an electrode pad 32 made of a copper film or the like having a thickness of about 5 to 10 μm is formed on the surface of a resin base material 31.

なお、樹脂基材３１に代えて、絶縁層と配線層とが交互に複数形成されたビルドアップ基板を用いてもよい。   Instead of the resin base material 31, a build-up board in which a plurality of insulating layers and wiring layers are alternately formed may be used.

次いで、図５（ｂ）に示すように、回路基板３０の上に熱硬化性樹脂を塗布することにより、例えば１０〜２０μmの樹脂層３３を形成する。樹脂層３３の材料は特に限定されず、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等の熱硬化性樹脂を使用し得る。   Next, as shown in FIG. 5B, a thermosetting resin is applied on the circuit board 30 to form a resin layer 33 of 10 to 20 μm, for example. The material of the resin layer 33 is not particularly limited, and thermosetting resins such as epoxy resins, silicone resins, cyanate resins, polyolefin resins, acrylic resins, and benzocyclobutene can be used.

そして、樹脂層３３を形成した後に、樹脂層３３を加熱して半硬化の状態にする。   After the resin layer 33 is formed, the resin layer 33 is heated to a semi-cured state.

なお、樹脂層３３の材料として、上記の熱硬化性樹脂に代えて熱可塑性樹脂を使用してもよい。   In addition, as a material of the resin layer 33, a thermoplastic resin may be used instead of the thermosetting resin.

次いで、図６（ａ）に示すように、一方の主面３４ｘに凸パターン３４ｗが形成された導体プレート３４を樹脂層３３の上方に配置し、回路基板３０と導体プレート３４との位置合わせを行う。   Next, as shown in FIG. 6A, a conductor plate 34 having a convex pattern 34w formed on one main surface 34x is disposed above the resin layer 33, and the circuit board 30 and the conductor plate 34 are aligned. Do.

その凸パターン３４ｗは、第２実施形態と同様に、錐状先端を有する第１の突起３４ａと、先端が平坦な第２の突起３４ｂとを有する。   Similar to the second embodiment, the convex pattern 34w includes a first protrusion 34a having a conical tip and a second protrusion 34b having a flat tip.

また、導体プレート３４の材料としては、配線抵抗の低減に有用な銅や銅合金を用いるのが好ましい。   Further, as the material of the conductor plate 34, it is preferable to use copper or a copper alloy useful for reducing the wiring resistance.

そして、図６（ｂ）に示すように、半硬化の状態にある樹脂層３３に導体プレート３４を押し当て、樹脂層３３に凸パターン３４ｗを埋め込む。これにより、第１の突起３４ａが電極パッド３２に当接してその先端が変形し、樹脂層３３から導体プレート３４が脱落する危険性が低減されると共に、電極パッド３２と凸パターン３４ｗとの接触面積が拡大する。   Then, as shown in FIG. 6B, the conductor plate 34 is pressed against the semi-cured resin layer 33 and the convex pattern 34 w is embedded in the resin layer 33. As a result, the first protrusion 34a contacts the electrode pad 32 and the tip thereof is deformed, and the risk of the conductor plate 34 falling off from the resin layer 33 is reduced, and the contact between the electrode pad 32 and the convex pattern 34w is reduced. The area expands.

また、第２の突起３２ｂが下地の樹脂基材３１に当接することにより、導体プレート３４の過度な埋め込みが防止される。   Further, the second protrusion 32b abuts on the underlying resin base material 31 to prevent the conductor plate 34 from being excessively embedded.

その後に、樹脂層３３を加熱して硬化させる。   Thereafter, the resin layer 33 is heated and cured.

なお、樹脂層３３の材料として熱硬化性樹脂を利用する場合には、加熱により樹脂層３３を軟化させるのと同時に樹脂層３３に凸パターン３４ｗを埋め込み、その後に樹脂層３３を冷却して硬化させるのが好ましい。   When a thermosetting resin is used as the material of the resin layer 33, the resin layer 33 is softened by heating, and at the same time, the convex pattern 34w is embedded in the resin layer 33, and then the resin layer 33 is cooled and cured. It is preferable to do so.

続いて、図７に示すように、樹脂層３３の表面が現れるまで導体プレート３４の他方の主面３４ｙに対して研磨、CMP、又は切削を行うことにより、凸パターン３４ｗを樹脂層３３に導体パターン３４ｚとして残す。   Subsequently, as shown in FIG. 7, the other main surface 34y of the conductor plate 34 is polished, CMPed or cut until the surface of the resin layer 33 appears, whereby the convex pattern 34w is transferred to the resin layer 33 as a conductor. Leave as pattern 34z.

その導体パターン３４ｚのうち、第１の突起３４ａに対応する部分は導体プラグとして機能し、それ以外の部分は配線として機能する。   Of the conductor pattern 34z, a portion corresponding to the first protrusion 34a functions as a conductor plug, and the other portion functions as a wiring.

以上により、本実施形態に係る電子部品の製造工程の主要工程が終了したことになる。   Thus, the main process of the electronic component manufacturing process according to the present embodiment is completed.

上記した本実施形態によれば、樹脂層３３に埋め込まれた凸パターン３４ｗを導体パターン３４ｚとして利用するので、第１実施形態と同様の理由で樹脂基材３１上に微細な導体パターン３４ｚを形成することができる。   According to the above-described embodiment, since the convex pattern 34w embedded in the resin layer 33 is used as the conductor pattern 34z, a fine conductor pattern 34z is formed on the resin substrate 31 for the same reason as in the first embodiment. can do.

なお、上記では回路基板３０の上に樹脂層３３を形成したが、樹脂層３３を形成する下地はこれに限定されない。例えば、表面に電極パッド３２が設けられた半導体素子を樹脂基材３１の代わりに使用し、その半導体素子の上に樹脂層３３を形成してもよい。その場合、導体パターン３４ｚは、半導体素子上の再配線層として使用される。   Although the resin layer 33 is formed on the circuit board 30 in the above, the base on which the resin layer 33 is formed is not limited to this. For example, a semiconductor element having an electrode pad 32 on the surface may be used instead of the resin base material 31, and the resin layer 33 may be formed on the semiconductor element. In that case, the conductor pattern 34z is used as a redistribution layer on the semiconductor element.

（４）第４実施形態
本実施形態では、第３実施形態を変形し、以下のようにして電子部品として回路基板を作製する。(4) Fourth Embodiment In the present embodiment, the third embodiment is modified to produce a circuit board as an electronic component as follows.

図８〜図１０は、本実施形態に係る電子部品の製造途中の断面図である。なお、これらの図において第３実施形態で説明したのと同じ要素には第３実施形態と同じ符号を付し、以下ではその説明を省略する。   8-10 is sectional drawing in the middle of manufacture of the electronic component which concerns on this embodiment. In these drawings, the same elements as those described in the third embodiment are denoted by the same reference numerals as those in the third embodiment, and the description thereof is omitted below.

まず、図８（ａ）に示すように、ガラス基板等のように上面が平坦な基板３５の上にメタルマスク３６を配置する。   First, as shown in FIG. 8A, a metal mask 36 is disposed on a substrate 35 having a flat upper surface such as a glass substrate.

そのメタルマスク３６は、例えば厚さが２０〜１００μmのステンレス板またはニッケル板よりなり、直径が板厚と同程度の開口３６ａを有する。   The metal mask 36 is made of, for example, a stainless plate or nickel plate having a thickness of 20 to 100 μm, and has an opening 36a having a diameter that is approximately the same as the plate thickness.

次いで、図８（ｂ）に示すように、ジエチレングリコール等の有機溶媒中にSnのナノ粒子を分散させてなる低融点金属ペースト３８をメタルマスク３６上に供給した後、メタルマスク３６の表面に沿ってスキージ３７を移動させ、開口３６ａ下の基板３５に低融点金属ペースト３８を印刷する。   Next, as shown in FIG. 8B, a low melting point metal paste 38 in which Sn nanoparticles are dispersed in an organic solvent such as diethylene glycol is supplied onto the metal mask 36, and then along the surface of the metal mask 36. The squeegee 37 is moved to print the low melting point metal paste 38 on the substrate 35 below the opening 36a.

なお、低融点金属ペースト３８に含まれるナノ粒子はSn粒子に限定されず、Snの融点より低い２３０℃以下の融点の金属粒子であってもよい。そのような金属粒子としては、例えば、SnAg合金やSnBi合金の粒子がある。更に、Snの有機酸を含むペーストを低融点金属ペースト３８として使用してもよい。   The nanoparticles contained in the low melting point metal paste 38 are not limited to Sn particles, and may be metal particles having a melting point of 230 ° C. or lower which is lower than the melting point of Sn. Examples of such metal particles include SnAg alloy and SnBi alloy particles. Further, a paste containing Sn organic acid may be used as the low melting point metal paste 38.

続いて、図９（ａ）に示すように、第３実施形態で説明した導体プレート３４を基板３５に対向させる。そして、導体プレート３４を基板３５に向けて下降させることにより、導体プレート３４の第１の突起３４ａの先端部分に低融点金属ペースト３８を転写する。   Subsequently, as illustrated in FIG. 9A, the conductor plate 34 described in the third embodiment is opposed to the substrate 35. Then, by lowering the conductor plate 34 toward the substrate 35, the low melting point metal paste 38 is transferred to the tip portion of the first protrusion 34 a of the conductor plate 34.

そして、図９（ｂ）に示すように、導体プレート３４を１５０〜２５０℃程度の温度に加熱して低融点金属ペースト３８中の溶媒成分を蒸散させる。なお、導体プレート３４の加熱の仕方は特に限定されず、ホットプレートや炉を用いて導体プレート３４を加熱し得る。   And as shown in FIG.9 (b), the conductor plate 34 is heated to the temperature of about 150-250 degreeC, and the solvent component in the low melting metal paste 38 is evaporated. The method of heating the conductor plate 34 is not particularly limited, and the conductor plate 34 can be heated using a hot plate or a furnace.

その後、図１０（ａ）に示すように、第３実施形態に従って回路基板３０上に塗布された樹脂層３３に、上記の導体プレート３４の凸パターン３４ｗを埋め込む。   Thereafter, as shown in FIG. 10A, the convex pattern 34w of the conductor plate 34 is embedded in the resin layer 33 applied on the circuit board 30 according to the third embodiment.

そして、凸パターン３４ｗの埋め込みと同時、若しくは凸パターン３４ｗが電極パッド３２に当接した後に、低融点金属ペースト３８を加熱して溶融させ、この低融点金属ペースト３８を介して第１の突起と電極パッド３２とを接合する。   The low melting point metal paste 38 is heated and melted simultaneously with the embedding of the convex pattern 34 w or after the convex pattern 34 w comes into contact with the electrode pad 32, and the first protrusion and the first protrusion are formed via the low melting point metal paste 38. The electrode pad 32 is joined.

低融点金属ペースト３８の加熱方法は特に限定されないが、本実施形態ではホットプレート又は炉を用いて、２００〜２４０℃程度の温度に低融点金属ペースト３８を加熱する。   Although the heating method of the low melting metal paste 38 is not particularly limited, in the present embodiment, the low melting metal paste 38 is heated to a temperature of about 200 to 240 ° C. using a hot plate or a furnace.

なお、凸パターン３４ｗを埋め込むときの樹脂層３３の状態は特に限定されないが、樹脂層３３として熱硬化性樹脂を用いる場合には、事前の加熱によって半硬化となった樹脂層３３に凸パターン３４ｗを埋め込むのが好ましい。   The state of the resin layer 33 when embedding the convex pattern 34w is not particularly limited. However, when a thermosetting resin is used as the resin layer 33, the convex pattern 34w Is preferably embedded.

また、樹脂層３３として熱硬化性樹脂を用いる場合には、凸パターン３４ｗの埋め込みと同時に加熱により樹脂層３３を軟化させるのが好ましい。その場合、樹脂層３３を軟化させるための加熱が、低融点金属ペースト３８を溶融するための加熱を兼ねてもよい。   Moreover, when using a thermosetting resin as the resin layer 33, it is preferable to soften the resin layer 33 by heating simultaneously with embedding of the convex pattern 34w. In that case, the heating for softening the resin layer 33 may also serve as the heating for melting the low melting point metal paste 38.

そして、樹脂層３３を硬化させた後、図１０（ｂ）に示すように、樹脂層３３が現れるまで導体プレート３４の他方の主面３４ｙに対して研磨、CMP、又は切削を行い、凸パターン３４ｗを樹脂層３３に導体パターン３４ｚとして残す。   Then, after the resin layer 33 is cured, as shown in FIG. 10B, the other main surface 34y of the conductor plate 34 is polished, CMP, or cut until the resin layer 33 appears, and the convex pattern 34 w is left as a conductor pattern 34 z in the resin layer 33.

以上により、本実施形態に係る電子部品の製造工程の主要工程が終了したことになる。   Thus, the main process of the electronic component manufacturing process according to the present embodiment is completed.

上記した本実施形態によれば、図９（ｂ）に示したように、凸パターン３４ｗの先端に低融点金属ペースト３８を固着したので、その低融点金属ペースト３８によって凸パターン３４ｗと電極パッド３２との接合強度を増加させることができる。   According to the present embodiment described above, as shown in FIG. 9B, the low melting point metal paste 38 is fixed to the tip of the convex pattern 34w, so that the low melting point metal paste 38 and the convex pattern 34w and the electrode pad 32 are used. The bonding strength with can be increased.

更に、低融点金属ペースト３８によって凸パターン３４ｗと電極パッド３２との接触面積も拡大するので、これらの間の電気抵抗を低減することも可能となる。   Furthermore, since the contact area between the convex pattern 34w and the electrode pad 32 is increased by the low melting point metal paste 38, the electrical resistance between them can be reduced.

（５）第５実施形態
第１〜第４実施形態で説明したように、導体プレートの凸パターンを利用することにより微細な導体パターンを形成することができる。(5) Fifth Embodiment As described in the first to fourth embodiments, a fine conductor pattern can be formed by using the convex pattern of the conductor plate.

但し、微細な導体パターンが不要な層には、従来のサブトラクト法やセミアディティブ法により導体パターンを形成し得る。   However, a conductor pattern can be formed by a conventional subtracting method or semi-additive method in a layer that does not require a fine conductor pattern.

本実施形態では、そのような従来方法を併用しながら、回路基板上に半導体素子を実装してなるモジュールを電子部品として作製する。   In the present embodiment, a module formed by mounting a semiconductor element on a circuit board is manufactured as an electronic component while using such a conventional method in combination.

図１１〜図１６は、本実施形態に係る電子部品の製造途中の断面図である。なお、これらの図において、第１実施形態で説明したのと同じ要素には第１実施形態におけるのと同じ要素を付し、以下ではその説明を省略する。   11 to 16 are cross-sectional views of the electronic component according to the present embodiment during manufacture. In these drawings, the same elements as those described in the first embodiment are denoted by the same elements as those in the first embodiment, and the description thereof is omitted below.

この電子部品を作製するには、まず、第１実施形態で説明した図１（ａ）〜図２（ａ）の工程を行った後、図１１（ａ）に示すように、第１の樹脂層１３と第１の導体パターン１４ｚのそれぞれの上に、熱硬化性樹脂よりなる第２の樹脂層１７を形成する。   In order to manufacture this electronic component, first, after performing the steps of FIG. 1A to FIG. 2A described in the first embodiment, as shown in FIG. A second resin layer 17 made of a thermosetting resin is formed on each of the layer 13 and the first conductor pattern 14z.

その熱硬化性樹脂としては、例えば、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等がある。   Examples of the thermosetting resin include an epoxy resin, a silicone resin, a cyanate resin, a polyolefin resin, an acrylic resin, and benzocyclobutene.

なお、これらの熱硬化性樹脂に代えて、熱可塑性樹脂を使用してもよい。   A thermoplastic resin may be used instead of these thermosetting resins.

そして、第２の樹脂層１７を硬化した後に、図１１（ｂ）に示すように、第２の樹脂層１７にエキシマレーザ等のレーザ光を照射して、第１の導体パターン１４ｚが露出するホール１７ａを形成する。そのホール１７ａの直径は特に限定されないが、本実施形態では２０〜５０μm程度とする。   And after hardening the 2nd resin layer 17, as shown in FIG.11 (b), the 2nd resin layer 17 is irradiated with laser beams, such as an excimer laser, and the 1st conductor pattern 14z is exposed. Hole 17a is formed. The diameter of the hole 17a is not particularly limited, but in the present embodiment, it is about 20 to 50 μm.

次に、図１２（ａ）に示すように、ホール１７ａの内面と第２の樹脂層１７の上面に、スパッタ法により銅膜を０．１μm程度の厚さに形成し、その銅膜をシード層４０とする。   Next, as shown in FIG. 12A, a copper film is formed on the inner surface of the hole 17a and the upper surface of the second resin layer 17 to a thickness of about 0.1 μm by sputtering, and the copper film is seeded. Layer 40 is assumed.

なお、スパッタ法に代えて、無電解めっきによりそのシード層４０を形成してもよい。   Note that the seed layer 40 may be formed by electroless plating instead of the sputtering method.

その後に、図１２（ｂ）に示すように、シード層４０の上に液状のフォトレジスト４１を塗布し、それをベークして半硬化の状態とする。なお、このように液状のフォトレジストを用いるのではなく、フィルム状のフォトレジスト４１をシード層４０上に貼付するようにしてもよい。   Thereafter, as shown in FIG. 12B, a liquid photoresist 41 is applied on the seed layer 40, and is baked to be in a semi-cured state. Instead of using a liquid photoresist in this way, a film-like photoresist 41 may be stuck on the seed layer 40.

続いて、図１３（ａ）に示すように、フォトレジスト４１を露光、現像し、フォトレジスト４１に配線形状の窓４１ａを形成する。   Subsequently, as shown in FIG. 13A, the photoresist 41 is exposed and developed, and a wiring-shaped window 41 a is formed in the photoresist 41.

次に、図１３（ｂ）に示すように、シード層４０を給電層にしながら電解めっきを行うことにより、窓４１ａ内のシード層４０上に５〜３０μm程度の厚さの導電層４２を形成する。   Next, as shown in FIG. 13B, by performing electroplating while using the seed layer 40 as a power feeding layer, a conductive layer 42 having a thickness of about 5 to 30 μm is formed on the seed layer 40 in the window 41a. To do.

なお、電解めっきに代えて、蒸着法や印刷法により導電層４２を形成してもよい。このうち、印刷法を使用する場合は、銅等の導電性ナノ粒子を含有したナノペーストを窓４１ａ内のシード層４０上にインクジェット方式で印刷することで、導電層４２を形成し得る。   Note that the conductive layer 42 may be formed by vapor deposition or printing instead of electrolytic plating. Among these, when using a printing method, the conductive layer 42 can be formed by printing the nano paste containing conductive nanoparticles, such as copper, on the seed layer 40 in the window 41a by an inkjet method.

その後に、図１４（ａ）に示すようにフォトレジスト４１を除去する。   Thereafter, the photoresist 41 is removed as shown in FIG.

次に、図１４（ｂ）に示すように、エッチング液として過酸化水素に硫酸系の溶液を加えた薬液等を使用しながら、導電層４２が形成されていない部分のシード層４０をウエットエッチングして除去すると共に、エッチングされないシード層４０と導電層４２を第２の導体パターン４５とする。このような第２の導体パターン４５の形成方法はセミアディティブ法と呼ばれる。   Next, as shown in FIG. 14B, wet etching is performed on the seed layer 40 where the conductive layer 42 is not formed while using a chemical solution obtained by adding a sulfuric acid-based solution to hydrogen peroxide as the etching solution. The seed layer 40 and the conductive layer 42 that are not etched are used as the second conductor pattern 45. Such a method of forming the second conductor pattern 45 is called a semi-additive method.

ここまでの工程により、透明支持基板１１の上には、第１及び第２の樹脂層１３、１７と第１及び第２の導体パターン１４ｚ、４５とを有する回路基板４９が形成されたことになる。   Through the steps so far, the circuit board 49 having the first and second resin layers 13 and 17 and the first and second conductor patterns 14z and 45 is formed on the transparent support substrate 11. Become.

続いて、図１５（ａ）に示すように、第２の導体パターン４５の上に接着層４７を介して素子搭載用透明支持基板４６を貼付する。この素子搭載用透明支持基板４６は、ガラス基板のような透光性のであるのが好ましい。   Subsequently, as shown in FIG. 15A, an element mounting transparent support substrate 46 is pasted on the second conductor pattern 45 via an adhesive layer 47. The element mounting transparent support substrate 46 is preferably translucent like a glass substrate.

また、接着層４７としては、紫外線の照射によって接着力が低下するUVテープや、加熱によって接着力が低下する熱発泡粘着フィルム等を使用するのが好ましい。   Further, as the adhesive layer 47, it is preferable to use a UV tape whose adhesive strength is reduced by irradiation of ultraviolet rays, a thermally foamed adhesive film whose adhesive strength is reduced by heating, or the like.

そして、透明支持基板１１を通して接着層１２に紫外線を照射することにより接着層１２の接着力を低下させた後、図１５（ｂ）に示すように、第１の樹脂層１３から透明支持基板１１を剥離する。   Then, after reducing the adhesive force of the adhesive layer 12 by irradiating the adhesive layer 12 with ultraviolet rays through the transparent support substrate 11, as shown in FIG. 15B, the first resin layer 13 to the transparent support substrate 11 is used. To peel off.

なお、接着層１２として熱発泡粘着フィルムを使用する場合は、接着層１２を加熱してその接着力を低下させ、上記のように透明支持基板１１を剥離すればよい。   In addition, when using a heat foaming adhesive film as the contact bonding layer 12, the contact bonding layer 12 should be heated, the adhesive force may be reduced, and the transparent support substrate 11 may be peeled off as mentioned above.

このように透明支持基板１１を剥離することで、第１の樹脂層１３の底面に第１の導体パターン１４ｚが表出することになる。   By peeling off the transparent support substrate 11 in this way, the first conductor pattern 14z is exposed on the bottom surface of the first resin layer 13.

次に、図１６（ａ）に示すように、素子搭載用透明支持基板４６を下側にし、表出している第１の導体パターン１４ｚに半導体素子５１の外部接続端子５２を接合する。外部接続端子５２は、例えば金バンプよりなり、超音波接合によって第１の導体パターン１４ｚ上に接合される。   Next, as shown in FIG. 16A, the external mounting terminal 52 of the semiconductor element 51 is joined to the exposed first conductor pattern 14z with the element mounting transparent support substrate 46 facing down. The external connection terminal 52 is made of, for example, a gold bump, and is bonded onto the first conductor pattern 14z by ultrasonic bonding.

なお、このような超音波接合に代えて、低融点はんだや異方性導電フィルムを介して外部接続端子５２と第１の導体パターン１４ｚとを電気的に接続するようにしてもよい。   Instead of such ultrasonic bonding, the external connection terminal 52 and the first conductor pattern 14z may be electrically connected through a low melting point solder or an anisotropic conductive film.

また、素子搭載用透明支持基板４６により回路基板４９を支持しながら本工程を行うことにより、回路基板４９の撓みを抑えながらその上に半導体素子５１を接合でき、接合時の回路基板４９の操作性が向上する。   Further, by performing this step while supporting the circuit board 49 by the element mounting transparent support substrate 46, the semiconductor element 51 can be bonded to the circuit board 49 while suppressing the bending of the circuit board 49, and the operation of the circuit board 49 at the time of bonding is performed. Improves.

その後、図１６（ｂ）に示すように、素子搭載用透明支持基板４６を通した紫外線照射により接着層４７の接着力を弱めた後、回路基板４９から素子搭載用支持基板４６を剥離する。   Thereafter, as shown in FIG. 16B, after the adhesive force of the adhesive layer 47 is weakened by ultraviolet irradiation through the element mounting transparent support substrate 46, the element mounting support substrate 46 is peeled off from the circuit board 49.

なお、接着層４７として熱発泡フィルムを使用する場合には、加熱によって接着層４７の接着力を低下させればよい。   In the case where a thermally foamed film is used as the adhesive layer 47, the adhesive force of the adhesive layer 47 may be reduced by heating.

以上により、回路基板４９上に半導体素子５１を搭載してなるモジュールが完成した。   As described above, a module in which the semiconductor element 51 is mounted on the circuit board 49 is completed.

本実施形態によれば、回路基板４９のうち半導体素子５１に近い側の第１の導体パターン１４ｚを第１実施形態に従って形成したので、第１実施形態で説明した理由により第１の導体パターン１４ｚの幅を微細にすることができる。   According to the present embodiment, the first conductor pattern 14z on the side close to the semiconductor element 51 of the circuit board 49 is formed according to the first embodiment. Therefore, the first conductor pattern 14z is formed for the reason described in the first embodiment. Can be made fine.

また、半導体素子５１よりも離れており配線幅の微細化が不要な第２の導体パターン４５については、従来から手法が確立されているセミアディティブ法により形成することで、量産工場内にある既存の製造設備を活かしてモジュールを作製することが可能となる。   In addition, the second conductor pattern 45 that is farther away from the semiconductor element 51 and does not require a finer wiring width is formed by a semi-additive method in which a conventional method has been established. This makes it possible to produce modules using the manufacturing equipment.

なお、回路基板４９に搭載する素子は半導体素子５１に限定されず、任意の電子素子、例えばキャパシタや抵抗素子であってもよい。   The element mounted on the circuit board 49 is not limited to the semiconductor element 51, and may be any electronic element such as a capacitor or a resistance element.

（６）第６実施形態
本実施形態では、多層回路基板に半導体素子を搭載してなるモジュールを以下のようにして製造する。(6) Sixth Embodiment In this embodiment, a module in which a semiconductor element is mounted on a multilayer circuit board is manufactured as follows.

図１７〜図２０は、本実施形態に係る電子部品の製造途中の断面図である。   17-20 is sectional drawing in the middle of manufacture of the electronic component which concerns on this embodiment.

この電子部品を製造するには、まず、図１７に示すように、多層回路基板１１０を用意する。   In order to manufacture this electronic component, first, as shown in FIG. 17, a multilayer circuit board 110 is prepared.

その多層回路基板１１０は、複数の配線パターン９２〜９８と絶縁層９１とを交互に積層してなる。このうち、各配線パターン９２〜９８は例えば銅膜よりなり、絶縁層９１はエポキシ樹脂等よりなる。   The multilayer circuit board 110 is formed by alternately laminating a plurality of wiring patterns 92 to 98 and insulating layers 91. Among these, the wiring patterns 92 to 98 are made of, for example, a copper film, and the insulating layer 91 is made of an epoxy resin or the like.

そして、この多層回路基板１１０を貫通するようにスルーホール９１ｃが形成され、その内面に形成されたスルーホール内銅めっき膜１０２により、最下層の配線パターン９２と最上層の配線パターン９８とが電気的に接続される。   A through hole 91c is formed so as to penetrate through the multilayer circuit board 110, and the lowermost wiring pattern 92 and the uppermost wiring pattern 98 are electrically connected by a copper plating film 102 in the through hole formed on the inner surface thereof. Connected.

最上層の配線パターン９８は、絶縁層９１のビアホール９１ａの内面にも形成されており、このビアホール９１ａの形状を反映した凹部９８ａが配線パターン９８に形成される。   The uppermost wiring pattern 98 is also formed on the inner surface of the via hole 91a of the insulating layer 91, and a recess 98a reflecting the shape of the via hole 91a is formed in the wiring pattern 98.

本工程では、このようにして用意した多層回路基板１１０の最上層に熱硬化性の樹脂層１０３を形成する。   In this step, a thermosetting resin layer 103 is formed on the uppermost layer of the multilayer circuit board 110 thus prepared.

その樹脂層１０３として使用し得る熱硬化性樹脂としては、例えばエポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等がある。   Examples of thermosetting resins that can be used as the resin layer 103 include epoxy resins, silicone resins, cyanate resins, polyolefin resins, acrylic resins, and benzocyclobutene.

これらの熱硬化性樹脂を使用する場合は、樹脂層１０３を形成した後に、加熱により樹脂層１０３を半硬化の状態にするのが好ましい。   In the case of using these thermosetting resins, it is preferable that the resin layer 103 is semi-cured by heating after the resin layer 103 is formed.

なお、このような熱硬化性樹脂に代えて、熱可塑性樹脂を使用してもよい。   A thermoplastic resin may be used instead of such a thermosetting resin.

その後に、一方の主面１００ｘに凸パターン１００ｗが形成された導体プレート１００を樹脂層１０３の上方に配置し、多層回路基板１１０と導体プレート１００との位置合わせを行う。   Thereafter, the conductor plate 100 having the convex pattern 100w formed on one main surface 100x is disposed above the resin layer 103, and the multilayer circuit board 110 and the conductor plate 100 are aligned.

導体プレート１００は、例えば銅や銅合金よりなり、突起１００ａと配線形状の凸部１００ｃとを有する。このうち、突起１００ａは、図示のような先の尖った錐状先端を有していてもよい。   The conductor plate 100 is made of, for example, copper or a copper alloy, and includes a protrusion 100a and a wiring-shaped convex portion 100c. Among these, the protrusion 100a may have a pointed cone-shaped tip as illustrated.

次に、図１８に示すように、半硬化の状態にある樹脂層１０３に導体プレート１００を押し当て、樹脂層１０３に凸パターン１００ｗを埋め込み、突起１００ａを凹部９８ａに嵌入させ、突起１００ａを潰して凹部９８ａに密着させる。   Next, as shown in FIG. 18, the conductor plate 100 is pressed against the resin layer 103 in a semi-cured state, the convex pattern 100w is embedded in the resin layer 103, the protrusion 100a is inserted into the recess 98a, and the protrusion 100a is crushed. To close contact with the recess 98a.

その後に、樹脂層１０３を加熱して硬化させる。   Thereafter, the resin layer 103 is heated and cured.

なお、樹脂層１０３の材料として熱可塑性樹脂を用いる場合には、加熱により樹脂層１０３を軟化させるのと同時に樹脂層１０３に凸パターン１００ｗを埋め込むのが好ましい。この場合は、凸パターン１００ｗを埋め込んだ後に樹脂層１０３を冷却して硬化させることになる。   In the case where a thermoplastic resin is used as the material of the resin layer 103, it is preferable to embed the convex pattern 100w in the resin layer 103 at the same time as the resin layer 103 is softened by heating. In this case, after embedding the convex pattern 100w, the resin layer 103 is cooled and cured.

また、突起１００ａを凹部９８ａに嵌入させ、突起１００ａを潰して凹部９８ａに密着させた後、導体プレート１００と多層回路基板１１０との間に樹脂１０３を注入し、樹脂１０３を加熱により硬化させてもよい。   Further, the protrusion 100a is fitted into the recess 98a, and the protrusion 100a is crushed and brought into close contact with the recess 98a. Then, the resin 103 is injected between the conductor plate 100 and the multilayer circuit board 110, and the resin 103 is cured by heating. Also good.

続いて、図１９に示すように、樹脂層１０３の表面が現れるまで導体プレート１００の他方の主面１００ｙに対して研磨、CMP、切削、又は研削を行い、凸パターン１００ｗを樹脂層１０３に導体パターン１００ｚとして残す。   Subsequently, as shown in FIG. 19, polishing, CMP, cutting, or grinding is performed on the other main surface 100 y of the conductor plate 100 until the surface of the resin layer 103 appears, and the convex pattern 100 w is formed on the resin layer 103 as a conductor. Leave as pattern 100z.

その導体パターン１００ｚの平面レイアウトは特に限定されない。例えば、最上層の配線パターン９８のうち、グランドパターンとなるものの上方に導体パターン１００ｚを形成し、これら配線パターン９８と導体パターン１００ｚとをマイクロストリップ線路構造にしてもよい。   The planar layout of the conductor pattern 100z is not particularly limited. For example, the conductor pattern 100z may be formed above the uppermost wiring pattern 98 that becomes the ground pattern, and the wiring pattern 98 and the conductor pattern 100z may have a microstrip line structure.

その後に、図２０に示すように、樹脂層１０３に表出している導体パターン１００ｚに半導体素子１１５の外部接続端子１１６を接合する。外部接続端子１１６は、例えば金バンプよりなり、超音波接合によって導体パターン１００ｚ上に接合される。   Thereafter, as shown in FIG. 20, the external connection terminal 116 of the semiconductor element 115 is joined to the conductor pattern 100 z exposed on the resin layer 103. The external connection terminal 116 is made of, for example, a gold bump, and is bonded onto the conductor pattern 100z by ultrasonic bonding.

なお、このような超音波接合に代えて、低融点はんだや異方性導電フィルムを介して外部接続端子１１６と導体パターン１００ｚとを電気的に接続するようにしてもよい。   Instead of such ultrasonic bonding, the external connection terminal 116 and the conductor pattern 100z may be electrically connected via a low melting point solder or an anisotropic conductive film.

以上により、回路基板１１０上に半導体素子１１５を搭載してなるモジュールの基本構造が完成した。   As described above, the basic structure of the module in which the semiconductor element 115 is mounted on the circuit board 110 is completed.

上記した本実施形態では、導体プレート１００の凸パターン１００ｗを利用して導体パターン１００ｚを形成し、この導体パターン１００ｚにより半導体素子１１５と多層回路基板１００とを電気的に接続する。   In the present embodiment described above, the conductor pattern 100z is formed using the convex pattern 100w of the conductor plate 100, and the semiconductor element 115 and the multilayer circuit board 100 are electrically connected by this conductor pattern 100z.

これにより、半導体素子１１５の品種や世代によって外部接続端子１１６の配列が変更された場合でも、その配列に応じて導体パターン１００ｚと最上層の配線パターン９８のレイアウトを設計し直すのみで、多層回路基板１００上に半導体素子１１５を搭載できる。そのため、多層回路基板１００に大きな設計変更を行わなくても、多層回路基板１００に様々な半導体素子１１５を搭載できるようになる。   As a result, even when the arrangement of the external connection terminals 116 is changed depending on the type and generation of the semiconductor element 115, the multi-layer circuit can be obtained by simply redesigning the layout of the conductor pattern 100z and the uppermost wiring pattern 98 according to the arrangement. A semiconductor element 115 can be mounted on the substrate 100. Therefore, various semiconductor elements 115 can be mounted on the multilayer circuit board 100 without making a major design change to the multilayer circuit board 100.

なお、多層回路基板１００に搭載する素子は半導体素子１１５に限定されず、任意の電子素子、例えばキャパシタや抵抗素子であってもよい。   The element mounted on the multilayer circuit board 100 is not limited to the semiconductor element 115 and may be any electronic element such as a capacitor or a resistance element.

（７）第７実施形態
上記した第１〜第６実施形態では、樹脂層を形成する工程の後に当該樹脂層に導体プレートを押し当てる工程を行ったが、本実施形態ではこれらの工程の順序を以下のように逆にする。(7) Seventh Embodiment In the first to sixth embodiments described above, the step of pressing the conductor plate against the resin layer is performed after the step of forming the resin layer. In this embodiment, the order of these steps is performed. Is reversed as follows.

図２１〜図２２は、本実施形態に係る電子部品の製造途中の断面図である。   21 to 22 are cross-sectional views in the course of manufacturing the electronic component according to the present embodiment.

まず、図２１（ａ）に示すように、樹脂基材１２１の表面に例えば５〜１０μm程度の厚さの銅膜等よりなる電極パッド１２２が形成された回路基板１２０を用意する。   First, as shown in FIG. 21A, a circuit board 120 is prepared in which an electrode pad 122 made of, for example, a copper film having a thickness of about 5 to 10 μm is formed on the surface of a resin base 121.

なお、樹脂基材１２０に代えて、絶縁層と配線層とが交互に複数形成されたビルドアップ基板を用いてもよい。   Instead of the resin base material 120, a buildup substrate in which a plurality of insulating layers and wiring layers are alternately formed may be used.

そして、導体プレート１２４を回路基板１２０の上方に配置し、回路基板１２０と導体プレート１２４との位置合わせを行う。   Then, the conductor plate 124 is disposed above the circuit board 120 and the circuit board 120 and the conductor plate 124 are aligned.

その導体プレート１２４は、高さの異なる二水準の第１及び第２の凸部１２４ａ、１２４ｂが形成された凸パターン１２４ｗを一方の主面１２４ｘに有する。また、導体プレート１２４の材料としては、配線抵抗の低減に有用な銅や銅合金を用いるのが好ましい。   The conductor plate 124 has a convex pattern 124w formed with two levels of first and second convex portions 124a and 124b having different heights on one main surface 124x. Further, as the material of the conductor plate 124, it is preferable to use copper or copper alloy useful for reducing the wiring resistance.

ここで、凸パターン１２４ｗや電極パッド１２４の表面には自然酸化膜が形成されているので、本工程においてその自然酸化膜を除去しておくのが好ましい。自然酸化膜が厚さ１００nm程度の銅酸化膜である場合、酢酸等の有機酸やTMAH（水酸化テトラメチルアンモニウム）の希釈液に導体プレート１２４や電極パッド１２４の表面を曝すことで、その自然酸化膜を容易に除去することができる。   Here, since the natural oxide film is formed on the surface of the convex pattern 124w and the electrode pad 124, it is preferable to remove the natural oxide film in this step. When the natural oxide film is a copper oxide film having a thickness of about 100 nm, the surface of the conductor plate 124 or the electrode pad 124 is exposed to a dilute solution of organic acid such as acetic acid or TMAH (tetramethylammonium hydroxide). The oxide film can be easily removed.

次いで、図２１（ｂ）に示すように、窒素等の不活性ガスの雰囲気中において、導体プレート１２４と電極パッド１２２とを加熱しながら、電極パッド１２２に導体プレート１２４を押し当てる。   Next, as shown in FIG. 21B, the conductor plate 124 is pressed against the electrode pad 122 while heating the conductor plate 124 and the electrode pad 122 in an atmosphere of an inert gas such as nitrogen.

このときの加熱温度や押圧力は特に限定されないが、本実施形態では、加熱温度を２００℃、押圧力を数１００Pa、押圧時間を数１０分とする。導体パッド１２２や導体プレート１２４の表面の自然酸化膜が数nm以下になっている場合、このような条件を採用することで第１の凸部１２４ａと導体パッド１２２とが金属接合するようになる。   The heating temperature and pressing force at this time are not particularly limited, but in this embodiment, the heating temperature is 200 ° C., the pressing force is several hundred Pa, and the pressing time is several tens of minutes. When the natural oxide film on the surface of the conductor pad 122 or the conductor plate 124 is several nanometers or less, the first protrusion 124a and the conductor pad 122 are metal-bonded by adopting such conditions. .

また、本工程を上記のように不活性ガスの雰囲気中で行うことで、第１の凸部１２４ａや導体パッド１２２の表面に自然酸化膜が形成するのを抑制しつつ、第１の凸部１２４ａと導体パッド１２２とを金属接合させることができる。   Further, by performing this step in an inert gas atmosphere as described above, the first convex portion is suppressed while suppressing the formation of a natural oxide film on the surface of the first convex portion 124a and the conductor pad 122. 124a and the conductor pad 122 can be metal-bonded.

或いは、不活性ガスに代えて還元性ガスの雰囲気中で本工程を行ってもよい。これにより、更に良好な金属接合を得ることができる。そのような還元性ガスとしては、例えば、数１０ppm〜数%の濃度でギ酸（HCOOH）が混入した窒素ガスがある。   Alternatively, this step may be performed in an atmosphere of a reducing gas instead of the inert gas. Thereby, a further favorable metal joint can be obtained. An example of such a reducing gas is nitrogen gas mixed with formic acid (HCOOH) at a concentration of several tens of ppm to several percent.

続いて、図２２（ａ）に示すように、ノズル１２６から熱硬化性の樹脂を滴下し、毛細管現象を利用して導体プレート１２４と回路基板１２０との間に樹脂を隙間なく充填し、樹脂層１２３を形成する。   Subsequently, as shown in FIG. 22A, a thermosetting resin is dropped from the nozzle 126, and the resin is filled between the conductor plate 124 and the circuit board 120 using a capillary phenomenon without any gap. Layer 123 is formed.

樹脂層１２３の材料は特に限定されない。本実施形態では、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等のいずれかの材料で樹脂層１２３を形成し得る。   The material of the resin layer 123 is not particularly limited. In the present embodiment, the resin layer 123 can be formed of any material such as an epoxy resin, a silicone resin, a cyanate resin, a polyolefin resin, an acrylic resin, and benzocyclobutene.

その後に、樹脂１２３を加熱して硬化させる。   Thereafter, the resin 123 is heated and cured.

次に、図２２（ｂ）に示すように、樹脂層１２３の表面が現れるまで導体プレート１２４の他方の主面１２４ｙに対して研磨、CMP、又は切削を行うことにより、凸パターン１２４ｗを樹脂層１２３に導体パターン１２４ｚとして残す。   Next, as shown in FIG. 22 (b), the other main surface 124y of the conductor plate 124 is polished, CMPed or cut until the surface of the resin layer 123 appears, whereby the convex pattern 124w is formed into the resin layer. 123 is left as a conductor pattern 124z.

その導体パターン１２４ｚのうち、第１の突起１２４ａに対応する部分は導体プラグとして機能し、第２の突起１２４ｂに対応する部分は配線として機能する。   Of the conductor pattern 124z, a portion corresponding to the first protrusion 124a functions as a conductor plug, and a portion corresponding to the second protrusion 124b functions as a wiring.

以上により、本実施形態に係る電子部品の製造工程の主要工程が終了したことになる。   Thus, the main process of the electronic component manufacturing process according to the present embodiment is completed.

本実施形態によれば、樹脂層１２３の形成前に、図２１（ｂ）に示したように導体プレート１２４と電極パッド１２２とを金属接合させる。よって、導体プレート１２４と電極パッド１２２との間に樹脂層１２３が介在する余地がなくなり、導体プレート１２４と電極パッド１２２との接続の信頼性を向上させることが可能となる。   According to the present embodiment, before the resin layer 123 is formed, the conductor plate 124 and the electrode pad 122 are metal-bonded as shown in FIG. Therefore, there is no room for the resin layer 123 to intervene between the conductor plate 124 and the electrode pad 122, and the connection reliability between the conductor plate 124 and the electrode pad 122 can be improved.

（８）第８実施形態
本実施形態では、以下に説明するように、複数の回路基板を接続するのに導体プレートを使用する。(8) Eighth Embodiment In this embodiment, a conductor plate is used to connect a plurality of circuit boards, as will be described below.

図２３〜図２５は、本実施形態に係る電子部品の製造途中の断面図である。   23 to 25 are cross-sectional views in the course of manufacturing the electronic component according to the present embodiment.

まず、図２３（ａ）に示すように、下地として供せられる第１の回路基板１３１と第２の回路基板１３２を水平面内に並べて用意する。   First, as shown in FIG. 23A, a first circuit board 131 and a second circuit board 132 used as a base are prepared in a horizontal plane.

各回路基板１３１、１３２は、ビアホール１３０ａが形成された樹脂基材１３０を備えており、そのビアホール１３０ａの内面と樹脂基材１３０の上面に銅膜等をパターニングしてなる電極パッド１３８が形成される。   Each circuit board 131, 132 includes a resin base material 130 having a via hole 130a formed therein, and electrode pads 138 formed by patterning a copper film or the like on the inner surface of the via hole 130a and the upper surface of the resin base material 130 are formed. The

そして、これらの基板１３１、１３２の繋ぎ目に重なるように、一方の主面１４０ｘに凸パターン１４０ｗを備えた導体プレート１４０を配置する。凸パターン１４０ｗは、突起１４０ａと配線形状の凸部１４０ｃとを有し、各回路基板１３１、１３２との位置合わせによって突起１４０ａはビアホール１３０ａの上方に配される。   And the conductor plate 140 provided with the convex pattern 140w is arrange | positioned in one main surface 140x so that the joint of these board | substrates 131 and 132 may overlap. The convex pattern 140w has a protrusion 140a and a wiring-shaped protrusion 140c, and the protrusion 140a is arranged above the via hole 130a by alignment with the circuit boards 131 and 132.

なお、導体プレート１４０の材料は限定されないが、その材料として配線抵抗の低減に有用な銅や銅合金を用いるのが好ましい。   In addition, although the material of the conductor plate 140 is not limited, it is preferable to use copper or a copper alloy useful for reducing wiring resistance as the material.

次いで、図２３（ｂ）に示すように、ビアホール１３０ａを反映して各電極パッド１３８の表面に形成された凹部１３８ａに突起１４０ａを嵌入する。これにより、各回路基板１３１、１３２が導体プレート１４０によって機械的に結合される。   Next, as shown in FIG. 23B, the projection 140a is inserted into the recess 138a formed on the surface of each electrode pad 138 reflecting the via hole 130a. Thereby, the circuit boards 131 and 132 are mechanically coupled by the conductor plate 140.

次に、図２４（ａ）に示すように、毛細管現象を利用して、各回路基板１３１、１３２の各主面１３１ｘ、１３２ｘと導体プレート１４０との間の隙間に熱硬化性の樹脂を隙間なく充填し、樹脂層１３９を形成する。   Next, as shown in FIG. 24A, a thermosetting resin is formed in the gap between the main surfaces 131x and 132x of the circuit boards 131 and 132 and the conductor plate 140 by utilizing capillary action. The resin layer 139 is formed without filling.

その樹脂層１３９に使用し得る樹脂としては、例えば、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等がある。   Examples of resins that can be used for the resin layer 139 include epoxy resins, silicone resins, cyanate resins, polyolefin resins, acrylic resins, and benzocyclobutene.

その後、その樹脂層１３９を加熱して熱硬化させる。   Thereafter, the resin layer 139 is heated and cured.

ここで、図２４（ａ）の点線円内に示すように、樹脂層１３９の形成前に電極パッド１３８に突起１４０ａを押し当てて当該突起１４０ａの先端を横方向に潰しておくのが好ましい。このようにすると、樹脂層１３９から導体プレート１４０が抜け落ちようとするのを潰れた突起１４０ａによって阻止することができる。しかも、突起１４０ａの先端が潰れたことで、電極パッド１３８と突起１４０ａとの接触面積が増大し、突起１４０ａと電極パッド１３８とのコンタクト抵抗を低減できる。   Here, as shown in a dotted circle in FIG. 24A, it is preferable that the protrusion 140a is pressed against the electrode pad 138 and the tip of the protrusion 140a is crushed in the lateral direction before the resin layer 139 is formed. In this way, the conductor plate 140 can be prevented from falling out of the resin layer 139 by the crushed protrusion 140a. In addition, since the tip of the protrusion 140a is crushed, the contact area between the electrode pad 138 and the protrusion 140a increases, and the contact resistance between the protrusion 140a and the electrode pad 138 can be reduced.

続いて、図２４（ｂ）に示すように、樹脂層１３９の表面が現れるまで導体プレート１４０の他方の主面１４０ｙを砥石２３３で研磨し、凸パターン１４０ｗ（図２３（ａ）参照）を樹脂層１３９に導体パターン１４０ｚとして残す。なお、研磨に代えて、CMPや研削で本工程を行うようにしてもよい。   Subsequently, as shown in FIG. 24 (b), the other main surface 140y of the conductor plate 140 is polished with a grindstone 233 until the surface of the resin layer 139 appears, and the convex pattern 140w (see FIG. 23 (a)) is made of resin. The conductor pattern 140z is left on the layer 139. Note that this step may be performed by CMP or grinding instead of polishing.

その後に、図２５に示すように、上記の導体パターン１４０ｚに第１の半導体素子１５４をフリップチップ接続すると共に、各回路基板１３１、１３２の電極パッド１３８に第２〜第６の半導体素子１５２〜１５６をフリップチップ接続する。   Thereafter, as shown in FIG. 25, the first semiconductor element 154 is flip-chip connected to the conductor pattern 140z, and the second to sixth semiconductor elements 152 to the electrode pads 138 of the circuit boards 131 and 132, respectively. 156 is flip-chip connected.

このうち、第１の半導体素子１５１は、はんだバンプ等の第１の外部接続端子１５１ａにより導体パターン１４０ｚと電気的かつ機械的に接続される。また、第２〜第６の半導体素子１５２〜１５６は、はんだバンプ等の第２〜第６の外部接続端子１５２ａ〜１５６ａを介して電極パッド１３８と電気的かつ機械的に接続される。   Among these, the first semiconductor element 151 is electrically and mechanically connected to the conductor pattern 140z by a first external connection terminal 151a such as a solder bump. The second to sixth semiconductor elements 152 to 156 are electrically and mechanically connected to the electrode pad 138 through second to sixth external connection terminals 152a to 156a such as solder bumps.

以上により、本実施形態に係る電子部品１４９の基本構造が完成したことになる。   As described above, the basic structure of the electronic component 149 according to the present embodiment is completed.

上記した本実施形態によれば、図２４（ｂ）に示したように、導体プレート１４０を利用して形成された導体パターン１４０ｚと樹脂層１３９とにより二つの回路基板１３１、１３２が結合された新規な構造が得られる。これによれば、異種の回路基板１３１、１３２を繋げて様々な外形サイズの電子部品１４９を得ることができる。   According to the above-described embodiment, as shown in FIG. 24B, the two circuit boards 131 and 132 are coupled by the conductor pattern 140z formed using the conductor plate 140 and the resin layer 139. A new structure is obtained. According to this, electronic components 149 having various outer sizes can be obtained by connecting different types of circuit boards 131 and 132.

なお、上記では図２３（ｂ）のように各回路基板１３１、１３２を導体プレート１４０で繋いだ後に、図２４（ａ）のように樹脂層１３９を形成したが、本実施形態はこれに限定されない。   In the above description, the circuit boards 131 and 132 are connected by the conductor plate 140 as shown in FIG. 23B, and then the resin layer 139 is formed as shown in FIG. 24A. However, the present embodiment is not limited to this. Not.

図２６（ａ）、（ｂ）は、本実施形態に係る電子部品の別の製造方法について示す断面図である。   26A and 26B are cross-sectional views illustrating another method for manufacturing an electronic component according to this embodiment.

この例では、図２６（ａ）のように先に樹脂層１３９を形成し、その後に図２６（ｂ）のように樹脂層１３９に導体プレート１４０の凸パターン１４０ｗを埋め込む。このようにしても、異種の回路基板１３１、１３２を組み合わせて様々な外形サイズの電子部品１４９を得ることができる。   In this example, the resin layer 139 is formed first as shown in FIG. 26A, and then the convex pattern 140w of the conductor plate 140 is embedded in the resin layer 139 as shown in FIG. Even in this case, electronic components 149 having various outer sizes can be obtained by combining different types of circuit boards 131 and 132.

また、この場合も、点線円内に示すように、電極パッド１３８に突起１４０ａを押し当てて該突起１４０ａを横方向に潰すことで、樹脂層１３９から導体プレート１４０が抜け落ちるのを防止でき、突起１４０ａと電極パッド１３８とのコンタクト抵抗を低減できる。   Also in this case, as shown in the dotted circle, by pressing the protrusion 140a against the electrode pad 138 and crushing the protrusion 140a in the lateral direction, the conductor plate 140 can be prevented from falling off from the resin layer 139. The contact resistance between 140a and the electrode pad 138 can be reduced.

更に、繋げる回路基板１３１、１３２の個数も２個に限定されず、３個以上の回路基板を導体プレート１４０で繋げるようにしてもよい。   Furthermore, the number of circuit boards 131 and 132 to be connected is not limited to two, and three or more circuit boards may be connected by the conductor plate 140.

（９）第９実施形態
本実施形態では、導体プレートから得られた導体パターンと、半導体素子のはんだバンプとの接続信頼性を向上させ得る電子部品について説明する。(9) Ninth Embodiment In this embodiment, an electronic component that can improve the connection reliability between a conductor pattern obtained from a conductor plate and a solder bump of a semiconductor element will be described.

図２７〜図３２は、本実施形態に係る電子部品の製造途中の断面図である。なお、これらの図において、第６実施形態で説明したのと同じ要素には第６実施形態と同じ符号を付し、以下ではその説明を省略する。   27 to 32 are cross-sectional views in the middle of manufacturing the electronic component according to the present embodiment. In these drawings, the same elements as those described in the sixth embodiment are denoted by the same reference numerals as those in the sixth embodiment, and the description thereof is omitted below.

まず、図２７に示すように、多層回路基板１１０と導体プレート１００とを用意する。このうち、導体プレート１００は、一方の主面１００ｘに凸パターン１００ｗが形成されている。   First, as shown in FIG. 27, a multilayer circuit board 110 and a conductor plate 100 are prepared. Among these, the conductive plate 100 has a convex pattern 100w formed on one main surface 100x.

本実施形態では、その凸パターン１００ｚは、第６実施形態で説明した突起１００ａ（図１７参照）の他に、高さが異なる二水準の第１の凸部１００ｂと第２の凸部１００ｃとを有する。   In the present embodiment, the convex pattern 100z includes, in addition to the protrusion 100a (see FIG. 17) described in the sixth embodiment, two levels of the first convex portion 100b and the second convex portion 100c having different heights. Have

そして、突起１００ａがビアホール９１ａの上方に位置するように、導体プレート１００と多層回路基板１１０との位置合わせをする。   Then, the conductor plate 100 and the multilayer circuit board 110 are aligned so that the protrusion 100a is positioned above the via hole 91a.

次いで、図２８に示すように、ビアホール９１ａの形状を反映した配線パターン９８の凹部９８ａに突起１００ａを嵌入し、回路基板１１０に導体プレート１００を固定する。   Next, as shown in FIG. 28, the protrusion 100 a is inserted into the recess 98 a of the wiring pattern 98 reflecting the shape of the via hole 91 a, and the conductor plate 100 is fixed to the circuit board 110.

続いて、図２９に示すように、毛細管現象を利用して多層回路基板１１０と導体プレート１００との間の隙間に熱硬化性の樹脂を隙間なく充填し、樹脂層１０３を形成する。   Subsequently, as shown in FIG. 29, a capillary layer is used to fill the gap between the multilayer circuit board 110 and the conductor plate 100 with a thermosetting resin without any gap, thereby forming the resin layer 103.

樹脂層１０３の材料は特に限定されないが、本実施形態では、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等のいずれかの材料で樹脂層１０３を形成する。   The material of the resin layer 103 is not particularly limited, but in this embodiment, the resin layer 103 is made of any material such as an epoxy resin, a silicone resin, a cyanate resin, a polyolefin resin, an acrylic resin, and benzocyclobutene. Form.

その後に、樹脂層１０３を加熱して硬化する。   Thereafter, the resin layer 103 is heated and cured.

次に、図３０に示すように、樹脂層１０３の表面が現れるまで導体プレート１００の他方の主面１００ｙを砥石２３３で研磨し、凸パターン１００ｗを樹脂層１０３に導体パターン１００ｚとして残す。なお、研磨に代えて、CMPや研削で本工程を行うようにしてもよい。   Next, as shown in FIG. 30, the other main surface 100y of the conductor plate 100 is polished with a grindstone 233 until the surface of the resin layer 103 appears, and the convex pattern 100w is left as the conductor pattern 100z on the resin layer 103. Note that this step may be performed by CMP or grinding instead of polishing.

この後は、導体パターン１００ｚの上に半導体素子のはんだバンプを接合する工程に移るが、上記のように研磨を行った直後の研磨面は、溶融したはんだが濡れ広がりやすい状態となっている。よって、この状態で導体パターン１００ｚの上にはんだバンプを接合しようとすると、隣接する導体パターン１００ｚ同士が濡れ広がったはんだによって電気的にショートするおそれがある。また、このようにはんだが濡れ広がることで、導体パターン１００ｚにおいてはんだバンプが当接する部分のはんだ量が不足し、はんだバンプと導体パターン１００ｚとが電気的にオープンになるおそれもある。   Thereafter, the process proceeds to a step of joining the solder bumps of the semiconductor element on the conductor pattern 100z. The polished surface immediately after the polishing as described above is in a state in which the melted solder is easily spread. Therefore, when solder bumps are to be bonded onto the conductor pattern 100z in this state, there is a possibility that the adjacent conductor patterns 100z may be electrically short-circuited by the solder that has spread. In addition, when the solder spreads in this manner, the amount of solder at the portion where the solder bumps abut on the conductor pattern 100z is insufficient, and the solder bump and the conductor pattern 100z may be electrically opened.

そのようなはんだの濡れ広がりを防止すべく、次の工程では、図３１に示すように、樹脂層１０３と導体パターン１００ｚのそれぞれの上面を覆うように、熱硬化性樹脂の塗膜１１８を形成する。その熱硬化性樹脂の材料は特に限定されないが、後述の半導体素子と多層回路基板１１０との接着強度を高めるという観点から、接着性のある熱硬化性樹脂を採用するのが好ましい。そのような熱硬化性樹脂として、例えば、エポキシ系樹脂、シリコーン系樹脂、シアネート系樹脂、ポリオレフィン系樹脂、アクリル系樹脂、及びベンゾシクロブテン等がある。   In order to prevent the solder from spreading, in the next step, as shown in FIG. 31, a thermosetting resin coating 118 is formed so as to cover the upper surfaces of the resin layer 103 and the conductor pattern 100z. To do. The material of the thermosetting resin is not particularly limited, but it is preferable to employ an adhesive thermosetting resin from the viewpoint of increasing the adhesive strength between a semiconductor element and a multilayer circuit board 110 described later. Examples of such thermosetting resins include epoxy resins, silicone resins, cyanate resins, polyolefin resins, acrylic resins, and benzocyclobutene.

そして、この塗膜１１８が形成された状態で、多層回路基板１１０の上方に半導体素子１１５を用意し、多層回路基板１１０に向かってその半導体素子１１５を下ろす。その半導体素子１１５の主面には、はんだバンプ等の低融点金属を材料とする突起電極１１７が設けられる。   Then, with the coating film 118 formed, a semiconductor element 115 is prepared above the multilayer circuit board 110 and the semiconductor element 115 is lowered toward the multilayer circuit board 110. The main surface of the semiconductor element 115 is provided with a protruding electrode 117 made of a low melting point metal such as a solder bump.

このようにすると、図３２に示すように、突起電極１１７が塗膜１１８を押し退けて導体パターン１００ｚに当接する。   In this way, as shown in FIG. 32, the protruding electrode 117 pushes away the coating film 118 and comes into contact with the conductor pattern 100z.

そして、この状態で、塗膜１１８の硬化温度と突起電極１１７の融点の双方よりも高い温度に塗膜１１８と突起電極１１７を加熱する。これにより、溶融した突起電極１１７が横方向に広がるのを塗膜１１８で防止しつつ、塗膜１１８を熱硬化させることができる。   In this state, the coating film 118 and the protruding electrode 117 are heated to a temperature higher than both the curing temperature of the coating film 118 and the melting point of the protruding electrode 117. As a result, the coating film 118 can be thermally cured while preventing the melted protruding electrode 117 from spreading in the lateral direction.

その後に、塗膜１１８と突起電極１１７の加熱を停止することにより、溶融していた突起電極１１７を固化し、当該突起電極１１７を介して半導体素子１１５を多層回路基板１１０に電気的かつ機械的に接続する。   Thereafter, heating of the coating film 118 and the protruding electrode 117 is stopped to solidify the molten protruding electrode 117, and the semiconductor element 115 is electrically and mechanically connected to the multilayer circuit board 110 via the protruding electrode 117. Connect to.

以上により、本実施形態に係る電子部品１１９の基本構造が完成した。   Thus, the basic structure of the electronic component 119 according to this embodiment is completed.

上記のように、本実施形態では、溶融した突起電極１１７が濡れ広がるのを樹脂の塗膜１１８により防ぐことができるので、隣接する導体パターン１００ｚ同士がその突起電極１１７によって電気的にショートするのを防止できる。   As described above, in the present embodiment, the molten bump electrode 117 can be prevented from spreading by the resin coating film 118, so that the adjacent conductor patterns 100 z are electrically short-circuited by the bump electrode 117. Can be prevented.

しかも、突起電極１１７が濡れ広がらないことから、導体パターン１００ｚにおいて突起電極１１７が当接する部分のはんだ量不足を解消でき、突起電極１１７と導体パターン１００ｚとが電気的にオープンになる危険性を低減できる。   In addition, since the protruding electrode 117 does not wet and spread, it is possible to eliminate the shortage of solder in the portion of the conductive pattern 100z where the protruding electrode 117 abuts, thereby reducing the risk of the protruding electrode 117 and the conductive pattern 100z becoming electrically open. it can.

更に、その塗膜１１８は接着性を有しているため、塗膜１１８によって多層回路基板１１０と半導体素子１１５との機械的な接続強度を補強することができる。   Furthermore, since the coating film 118 has adhesiveness, the mechanical connection strength between the multilayer circuit board 110 and the semiconductor element 115 can be reinforced by the coating film 118.

ところで、図２７を参照して説明したように、導体パターン１００ｚの基となる凸パターン１００ｗは、高さの異なる第１の凸部１００ｂと第２の凸部１００ｃとを有する。そのような高さの相違に起因して、導体パターン１００ｚには以下のように厚さの異なる二種類の部分が形成されることになる。   By the way, as described with reference to FIG. 27, the convex pattern 100w that is the basis of the conductor pattern 100z includes the first convex portion 100b and the second convex portion 100c having different heights. Due to the difference in height, two types of portions having different thicknesses are formed in the conductor pattern 100z as follows.

図３３はこの電子装置１１９の拡大平面図であり、図３４は図３３のI−I線に沿う断面図である。   FIG. 33 is an enlarged plan view of the electronic device 119, and FIG. 34 is a cross-sectional view taken along the line II of FIG.

図３４に示されるように、導体パターン１００ｚは、第１の部分１００ｆと第２の部分１００ｅとを有する。このうち、第２の部分１００ｅは、凸パターン１００ｗの第１の凸部１００ｂに起因して形成されたものであって、第２の凸部１００ｃに起因して形成された第１の部分１００ｆよりも厚い。   As shown in FIG. 34, the conductor pattern 100z has a first portion 100f and a second portion 100e. Among these, the 2nd part 100e was formed resulting from the 1st convex part 100b of the convex pattern 100w, Comprising: The 1st part 100f formed resulting from the 2nd convex part 100c Thicker than.

本実施形態では、このような導体パターン１００ｚの第２の部分１００ｅ上に突起電極１１７が接合される。   In the present embodiment, the protruding electrode 117 is bonded onto the second portion 100e of the conductor pattern 100z.

突起電極１１７は、はんだ等の低融点金属を含んでいるため、その低融点金属と導体パターン１００ｚとの化合物よりなる化合物層１００ｇが第２の部分１００ｅに形成される。   Since the protruding electrode 117 includes a low melting point metal such as solder, a compound layer 100g made of a compound of the low melting point metal and the conductor pattern 100z is formed on the second portion 100e.

周囲の導体パターン１００ｚとは異なる結晶構造を有する化合物層１００ｇは、その形成過程で堆積が収縮し、化合物層１００ｇと周囲の導体パターン１００ｚとの間にクラックが形成され易い。   The compound layer 100g having a crystal structure different from that of the surrounding conductor pattern 100z shrinks in the formation process, and a crack is easily formed between the compound layer 100g and the surrounding conductor pattern 100z.

仮にそのようなクラックが形成されたとしても、そのクラックの形成部位は、突起電極１１７の直下にある第２の部分１００ｅである。第２の部分１００ｅは、第１の部分１００ｆよりも厚く形成されているので、仮にクラックが形成されたとしても、クラックによって第２の部分１００ｅが基板垂直方向に分断されることはなく、クラックによって導体パターン１００ｚが断線することはない。   Even if such a crack is formed, the formation site of the crack is the second portion 100e immediately below the protruding electrode 117. Since the second portion 100e is formed thicker than the first portion 100f, even if a crack is formed, the second portion 100e is not divided in the direction perpendicular to the substrate by the crack. Thus, the conductor pattern 100z is not disconnected.

一方、図３５は、比較例に係る電子装置の断面図である。   On the other hand, FIG. 35 is a cross-sectional view of an electronic device according to a comparative example.

この比較例では、導体パターン１００ｚに第２の部分１００ｅを形成せず、導体パターン１００ｚを上記の第１の部分１００ｆと同程度の薄さに形成している。   In this comparative example, the second portion 100e is not formed in the conductor pattern 100z, and the conductor pattern 100z is formed as thin as the first portion 100f.

この場合、化合物層１００ｇとその周囲の導体パターン１００ｚのそれぞれの結晶構造の違いに起因したクラックCが導体パターン１００ｚに形成される。本例に係る導体パターン１００ｚは、その全体が上記した第１の部分１００ｆと同程度に薄く形成されているため、クラックCが導体パターン１００ｚを基板垂直方向に横断し、導体パターン１００ｚが断線してしまう。   In this case, a crack C resulting from the difference in crystal structure between the compound layer 100g and the surrounding conductor pattern 100z is formed in the conductor pattern 100z. Since the conductor pattern 100z according to this example is formed as thin as the entire first portion 100f, the crack C crosses the conductor pattern 100z in the direction perpendicular to the substrate, and the conductor pattern 100z is disconnected. End up.

これに対し、本実施形態では上記のように膜厚が厚い第２の部分１００ｅを形成するので、このようなクラックに起因した導体パターン１００ｚの断線を防止できる。   In contrast, in the present embodiment, since the second portion 100e having a large film thickness is formed as described above, it is possible to prevent the conductor pattern 100z from being disconnected due to such a crack.

（１０）第１０実施形態
本実施形態では、第１〜第６実施形態で説明した導体プレートの型の作製方法について説明する。(10) Tenth Embodiment In this embodiment, a method for producing a conductor plate mold described in the first to sixth embodiments will be described.

・第１例
本例は、図１（ａ）に示したような高さの異なる二水準の凸部１４ａ、１４ｂを備えた導体プレート１４の型の作製方法に関する。-1st example This example is related with the production method of the type | mold of the conductor plate 14 provided with the bilevel convex part 14a, 14b from which height differs as shown to Fig.1 (a).

図３６〜図４０は、その導体プレートの型の製造途中の断面図である。   36 to 40 are cross-sectional views of the conductor plate mold in the middle of its manufacture.

その型を作製するには、まず、図３６（ａ）に示すように、シリコン基板７０の上側全面に第１のフォトレジスト７１を塗布し、それをベークして半硬化の状態とする。   In order to fabricate the mold, first, as shown in FIG. 36A, a first photoresist 71 is applied to the entire upper surface of the silicon substrate 70 and baked to be in a semi-cured state.

次に、図３６（ｂ）に示すように、クロム膜等の遮光膜よりなるマスクパターン（不図示）が形成された第１の露光マスク７２をシリコン基板７０の上方に配置する。そして、その第１の露光マスク７２を通じて露光光を第１のフォトレジスト７１に照射することにより、第１のフォトレジスト７１を露光する。   Next, as shown in FIG. 36B, a first exposure mask 72 on which a mask pattern (not shown) made of a light shielding film such as a chromium film is formed is disposed above the silicon substrate 70. Then, the first photoresist 71 is exposed by irradiating the first photoresist 71 with exposure light through the first exposure mask 72.

なお、このようにシリコン基板７０の上方に露光マスク７２を配置するのではなく、ステッパ等の露光装置を用いて第１のフォトレジスト７１を露光するようにしてもよい。   Instead of arranging the exposure mask 72 above the silicon substrate 70 in this way, the first photoresist 71 may be exposed using an exposure apparatus such as a stepper.

次いで、図３７（ａ）に示すように、第１のフォトレジスト７１を現像して窓７１ａを形成し、その窓７１ａを通じてシリコン基板７０をRIE(Reactive Ion Etching)によりドライエッチングして、シリコン基板７０に第１の溝７０ａを形成する。   Next, as shown in FIG. 37A, the first photoresist 71 is developed to form a window 71a, and the silicon substrate 70 is dry-etched by RIE (Reactive Ion Etching) through the window 71a. A first groove 70 a is formed in 70.

このドライエッチングの条件は特に限定されないが、本実施形態では、反応性ガスと不活性ガスとの混合ガスをエッチングガスとして使用する。このうち、反応性ガスとしては、F2、SF6、CF4、及びC4F8のいずれかのフッ素系ガスを使用し得る。或いは、Cl2又はH2を反応性ガスとして使用してもよい。また、不活性ガスとしては、例えばアルゴンガスがある。The dry etching conditions are not particularly limited, but in this embodiment, a mixed gas of a reactive gas and an inert gas is used as an etching gas. Among these, as the reactive gas, any fluorine-based gas of F 2 , SF 6 , CF 4 , and C 4 F 8 can be used. Alternatively, Cl 2 or H 2 may be used as the reactive gas. An example of the inert gas is argon gas.

なお、このようなドライエッチングに代えて、フッ酸又はKOH等のエッチング液を使用するウエットエッチングを行ってもよい。   Note that wet etching using an etchant such as hydrofluoric acid or KOH may be performed instead of such dry etching.

このエッチングを終了後、第１のフォトレジスト７１は除去される。   After this etching is finished, the first photoresist 71 is removed.

次に、図３７（ｂ）に示すように、シリコン基板７０の上側全面に第２のフォトレジスト７３を形成した後、この第２のフォトレジスト７３をベークして半硬化の状態にする。   Next, as shown in FIG. 37B, after the second photoresist 73 is formed on the entire upper surface of the silicon substrate 70, the second photoresist 73 is baked to be in a semi-cured state.

その後、図３８（ａ）に示すように、シリコン基板７０の上方に第２の露光マスク７４を配置し、その第２の露光マスク７４を通して第２のフォトレジスト７３に露光光を照射する。これにより、第２の露光マスク７４に形成されたクロム膜等の遮光膜よりなるマスクパターン（不図示）が第２のフォトレジスト７３に投影され、第２のフォトレジスト７３が露光されることになる。   Thereafter, as shown in FIG. 38A, a second exposure mask 74 is arranged above the silicon substrate 70, and the second photoresist 73 is irradiated with exposure light through the second exposure mask 74. As a result, a mask pattern (not shown) made of a light shielding film such as a chromium film formed on the second exposure mask 74 is projected onto the second photoresist 73, and the second photoresist 73 is exposed. Become.

なお、ステッパ等の露光装置を用いてこの露光を行ってもよい。   Note that this exposure may be performed using an exposure apparatus such as a stepper.

続いて、図３８（ｂ）に示すように、第２のフォトレジスト７３を現像して窓７３ａを形成し、その窓７３ａを通じてシリコン基板７０をRIEによりドライエッチングする。これにより、シリコン基板７０には、第１の溝７０ａよりも深い第２の溝７０ｂが形成される。   Subsequently, as shown in FIG. 38B, the second photoresist 73 is developed to form a window 73a, and the silicon substrate 70 is dry-etched by RIE through the window 73a. As a result, a second groove 70b deeper than the first groove 70a is formed in the silicon substrate 70.

このエッチングで使用されるエッチングガスは、第１の溝７０ａを形成するときと同様に、反応性ガスと不活性ガスとの混合ガスである。その反応性ガスとしては、F2、SF6、CF4、及びC4F8のいずれかのフッ素系ガス、或いはCl2又はH2が使用される。そして、不活性ガスとしては、例えばアルゴンガスが使用される。The etching gas used in this etching is a mixed gas of a reactive gas and an inert gas, as in the case of forming the first groove 70a. As the reactive gas, a fluorine-based gas of F 2 , SF 6 , CF 4 , and C 4 F 8 , Cl 2 or H 2 is used. For example, argon gas is used as the inert gas.

このエッチングを終了後、第２のフォトレジスト７３を除去することにより、図３９（ａ）に示すような母型７７が得られる。   After the etching is finished, the second photoresist 73 is removed, thereby obtaining a mother die 77 as shown in FIG.

次いで、図３９（ｂ）に示すように、第１及び第２の溝７０ａ、７０ｂを埋め込むように母型７７上に金属層を形成し、この金属層よりなる第１の子型７８を形成する。その金属層は、例えば、電解めっきにより形成されたニッケル層である。   Next, as shown in FIG. 39B, a metal layer is formed on the mother die 77 so as to fill the first and second grooves 70a and 70b, and a first child die 78 made of this metal layer is formed. To do. The metal layer is, for example, a nickel layer formed by electrolytic plating.

そして、母型７７から第１の子型７８を外した後、図４０（ａ）に示すように、樹脂によって第１の子型７８の型取りを行い、その樹脂よりなる第２の子型８０を得る。なお、樹脂で型取りをするのではなく、ニッケルの電鋳により第１の子型８０の型取りを行い、第２の子型を作製してもよい。   Then, after removing the first child mold 78 from the mother mold 77, as shown in FIG. 40 (a), the first child mold 78 is molded with resin, and the second child mold made of the resin is used. Get 80. Instead of molding with a resin, the first daughter mold 80 may be molded by electroforming nickel to produce a second daughter mold.

この後は、図４０（ｂ）に示すように、第１の子型７８から第２の子型８０を外す。   Thereafter, as shown in FIG. 40 (b), the second child mold 80 is removed from the first child mold 78.

以上により、導体プレート１４（図１（ａ）参照）を形成するための第２の子型８０が完成した。   Thus, the second child mold 80 for forming the conductor plate 14 (see FIG. 1A) was completed.

導体プレート１４の作製にあたっては、例えば第２の子型８０の表面に無電解銅めっきと電解銅めっきをこの順に行う。そして、これらのめっき膜を第２の子型８０から外すことにより、銅よりなる導体プレート１４を作製し得る。   In producing the conductor plate 14, for example, electroless copper plating and electrolytic copper plating are performed in this order on the surface of the second child mold 80. Then, by removing these plating films from the second child mold 80, the conductor plate 14 made of copper can be produced.

また、一つの第２の子型８０から複数の導体プレート１４を同じ形状及び同じ品質で作り出すことができ、導体プレート１４を安価に大量生産することができる。   Further, a plurality of conductor plates 14 can be produced from the same second child mold 80 with the same shape and the same quality, and the conductor plates 14 can be mass-produced at low cost.

・第２例
本例は、図６（ａ）に示したような錐状先端の突起３４ａを備えた導体プレート３４の型の作製方法に関する。Second Example This example relates to a method of manufacturing a mold of a conductor plate 34 having a conical tip protrusion 34a as shown in FIG.

図４１〜図４３は、その導体プレートの型の製造途中の断面図である。   41 to 43 are cross-sectional views of the conductor plate mold in the middle of its manufacture.

その型を作製するには、まず、第１例で説明した図３６（ａ）〜図３８（ｂ）の工程を行うことにより、図４１（ａ）に示すように、シリコン基板７０に第１及び第２の溝７０ａ、７０ｂが形成された状態にする。   In order to fabricate the mold, first, the steps of FIGS. 36A to 38B described in the first example are performed, so that the first is formed on the silicon substrate 70 as shown in FIG. The second grooves 70a and 70b are formed.

次いで、図４１（ｂ）に示すように、第２のフォトレジスト７３の上方に、開口８１ａを備えたメタルマスク８１を配置する。そして、その窓８１ａが第２のフォトレジスト７３の窓７３ａの上方に位置するように、シリコン基板７０とメタルマスク８１との位置合わせを行う。   Next, as shown in FIG. 41 (b), a metal mask 81 having an opening 81 a is disposed above the second photoresist 73. Then, the silicon substrate 70 and the metal mask 81 are aligned so that the window 81 a is positioned above the window 73 a of the second photoresist 73.

続いて、図４２（ａ）に示すように、メタルマスク８１の窓８１ａ下のシリコン基板７０をRIEによりドライエッチングする。   Subsequently, as shown in FIG. 42A, the silicon substrate 70 under the window 81a of the metal mask 81 is dry etched by RIE.

このドライエッチングでは、反応性ガスと不活性ガスとの混合ガスがエッチングガスとして使用される。このうち、反応性ガスとしては、F2、SF6、CF4、及びC4F8のいずれかのフッ素系ガスを使用し得る。或いは、Cl2又はH2を反応性ガスとして使用してもよい。また、不活性ガスとしては、例えばアルゴンガスがある。In this dry etching, a mixed gas of a reactive gas and an inert gas is used as an etching gas. Among these, as the reactive gas, any fluorine-based gas of F 2 , SF 6 , CF 4 , and C 4 F 8 can be used. Alternatively, Cl 2 or H 2 may be used as the reactive gas. An example of the inert gas is argon gas.

そして、このエッチングガスにおける反応性ガスの流量比を、第２の溝７０ｂを形成したときにおけるよりも低減することにより、反応ガスによる横方向のエッチング作用が弱まり、図示のように第２の溝７０ｂの底部をテーパ状にエッチングすることが可能となる。   Then, by reducing the flow rate ratio of the reactive gas in the etching gas as compared with the case where the second groove 70b is formed, the lateral etching action by the reactive gas is weakened, and the second groove as shown in the figure. It becomes possible to etch the bottom of 70b into a taper shape.

その後、図４２（ｂ）に示すように、第２のフォトレジスト７３を除去することにより母型８５が完成する。   Thereafter, as shown in FIG. 42B, the second photoresist 73 is removed to complete the mother die 85.

この後は、第１例で説明した図３９（ｂ）〜図４０（ｂ）の工程を行うことで、図４３に示すように、導体プレート３４（図６（ａ））を形成するための樹脂又は電鋳よりなる子型８６が完成する。   Thereafter, by performing the steps of FIGS. 39B to 40B described in the first example, as shown in FIG. 43, the conductor plate 34 (FIG. 6A) is formed. A child mold 86 made of resin or electroforming is completed.

導体プレート３４の作製にあたっては、子型８６の表面に無電解銅めっきと電解銅めっきをこの順に行う。そして、これらのめっき膜を子型８６から外すことにより、銅よりなる導体プレート３４を作製し得る。   In producing the conductor plate 34, electroless copper plating and electrolytic copper plating are performed on the surface of the child mold 86 in this order. Then, by removing these plating films from the child mold 86, the conductor plate 34 made of copper can be produced.

上記した子型８６の作製方法では、図４２（ａ）のエッチング工程において、第２の溝７０ｂを形成するときよりも反応性ガスの流量比を少なくすることにより、溝７０ｂの底面をテーパ状にすることができる。これにより、図４３に示した子型８６に、錐状先端の突起３４ａ（図６（ａ）参照）に対応した溝８６ａを形成することが可能となる。   In the manufacturing method of the above-described child mold 86, the bottom surface of the groove 70b is tapered by reducing the flow rate ratio of the reactive gas in the etching process of FIG. 42A compared with the case of forming the second groove 70b. Can be. This makes it possible to form a groove 86a corresponding to the conical tip protrusion 34a (see FIG. 6A) in the child mold 86 shown in FIG.

・第３例
本例では、二層のレジストパターンを利用することにより、図１（ａ）のような高さの異なる二水準の凸部１４ａ、１４ｂを備えた導体プレート１４の型を製造する。Third Example In this example, by using a two-layer resist pattern, a mold of a conductor plate 14 having two-level convex portions 14a and 14b having different heights as shown in FIG. 1A is manufactured. .

図４４〜図４８は、その導体プレートの型の製造途中の断面図である。   44 to 48 are cross-sectional views of the conductive plate mold in the middle of its manufacture.

まず最初に、図４４（ａ）に示すように、シリコン基板１５０の上にポジ型の第１のレジスト層１５１を形成し、その第１のレジスト層１５１をベークして半硬化の状態にする。   First, as shown in FIG. 44A, a positive first resist layer 151 is formed on a silicon substrate 150, and the first resist layer 151 is baked to be in a semi-cured state. .

次いで、その第１のレジスト層１５１の上に更にネガ型の第２のレジスト層１５２を形成し、その第２のレジスト層１５２をベークして半硬化の状態にする。   Next, a negative second resist layer 152 is formed on the first resist layer 151, and the second resist layer 152 is baked to be in a semi-cured state.

次に、図４４（ｂ）に示すように、遮光性の第１の露光マスク１５３の窓１５３ａを通じて露光光を第２のレジスト層１５２に照射し、第２のレジスト層１５２に感光部１５２ａを形成する。   Next, as shown in FIG. 44B, exposure light is irradiated to the second resist layer 152 through the window 153a of the light-shielding first exposure mask 153, and the photosensitive portion 152a is applied to the second resist layer 152. Form.

その後に、現像により感光部１５２ａ以外の部分の第２のレジスト層１５２を除去することにより、図４５（ａ）に示すように、第１のレジスト層１５１の上に上側レジストパターン１５２ｂを形成する。   Thereafter, by removing the second resist layer 152 at portions other than the photosensitive portion 152a by development, an upper resist pattern 152b is formed on the first resist layer 151 as shown in FIG. .

なお、この現像の際の現像液としては、未感光の第２のレジスト層１５２のみが溶解して第１のレジスト層１５１が溶解しない現像液が使用されるので、現像の後に第１のレジスト層１５１はシリコン基板１５０上に残存する。   Note that, as a developing solution at the time of development, a developing solution in which only the non-photosensitive second resist layer 152 is dissolved and the first resist layer 151 is not dissolved is used. The layer 151 remains on the silicon substrate 150.

次いで、図４５（ｂ）に示すように、遮光性の第２の露光マスク１５５の窓１５５ａを通じて露光光を第１のレジスト層１５１に照射して、第１のレジスト層１５１に感光部１５１ａを形成する。   Next, as shown in FIG. 45B, exposure light is irradiated to the first resist layer 151 through the window 155a of the light-shielding second exposure mask 155, and the photosensitive portion 151a is applied to the first resist layer 151. Form.

そして、現像により感光部１５１ａを除去することで、図４６（ａ）に示すような下部レジストパターン１５１ｂを形成する。この現像では、感光部１５１ａのみを選択的に除去する現像液を使用するので、現像によって上側レジストパターン１５２ｂが除去されることはない。   Then, by removing the photosensitive portion 151a by development, a lower resist pattern 151b as shown in FIG. 46A is formed. In this development, since a developer that selectively removes only the photosensitive portion 151a is used, the upper resist pattern 152b is not removed by the development.

続いて、図４６（ｂ）に示すように、各レジストパターン１５１ｂ、１５２ｂのそれぞれの上に金属層を形成し、この金属層よりなる母型１６０を形成する。その金属層は、例えば、電界めっきにより形成されたニッケル層である。   Subsequently, as shown in FIG. 46B, a metal layer is formed on each of the resist patterns 151b and 152b, and a matrix 160 made of the metal layer is formed. The metal layer is, for example, a nickel layer formed by electroplating.

そして、各レジストパターン１５１ｂ、１５２ｂのそれぞれをアッシングにより除去した後、図４７（ａ）に示すように、シリコン基板１５０から母型１６０を剥離する。   Then, after removing each of the resist patterns 151b and 152b by ashing, the mother die 160 is peeled from the silicon substrate 150 as shown in FIG.

次に、図４７（ｂ）に示すように、樹脂によって母型１６０の型取りを行い、その樹脂よりなる子型１６１を得る。なお、樹脂で型取りをするのではなく、ニッケルの電鋳により母型１６０の型取りを行うことで、子型１６１を作製してもよい。   Next, as shown in FIG. 47B, the mother die 160 is molded with a resin to obtain a child die 161 made of the resin. Instead of taking a mold with a resin, the child mold 161 may be produced by taking the mold 160 by electroforming nickel.

この後は、図４８に示すように、母型１６０から子型１６１を外す。   Thereafter, as shown in FIG. 48, the child die 161 is removed from the mother die 160.

以上により、導体プレート１４（図１（ａ）参照）を作製するための子型１６１が完成した。   Thus, the child die 161 for producing the conductor plate 14 (see FIG. 1A) was completed.

導体プレート１４を作製するには、例えば、子型１６１の表面に無電解銅めっきと電解銅めっきをこの順に行った後、これらのめっき膜を子型１６１から外し、銅よりなる導体プレート１４を作製し得る。   In order to produce the conductor plate 14, for example, after electroless copper plating and electrolytic copper plating are performed in this order on the surface of the child die 161, these plating films are removed from the child die 161, and the conductor plate 14 made of copper is removed. Can be made.

本例のように子型１６１を作製することで、その子型１６１から同一の品質の導体プレート１４を安価に大量生産することが可能となる。   By producing the child die 161 as in this example, it is possible to mass-produce the conductor plate 14 of the same quality from the child die 161 at a low cost.

（１１）第１１実施形態
本実施形態では、銅の拡散防止に有効な導体プレート１００の作製方法について説明する。(11) Eleventh Embodiment In this embodiment, a method for producing a conductive plate 100 effective for preventing copper diffusion will be described.

図４９〜図５１は、本例に係る導体プレートの製造途中の断面図である。   49 to 51 are cross-sectional views in the process of manufacturing the conductor plate according to this example.

まず最初に、図４９（ａ）に示すように、第１０実施形態の第３例に従って作製された子型１６１を用意する。なお、この子型１６１に代えて、第１０実施形態の第１例で作製した第２の子型８０や、第１０実施形態の第２例で作製した子型８６を用意してもよい。   First, as shown in FIG. 49A, a child die 161 manufactured according to the third example of the tenth embodiment is prepared. Instead of the child die 161, a second child die 80 produced in the first example of the tenth embodiment or a child die 86 produced in the second example of the tenth embodiment may be prepared.

次いで、図４９（ｂ）に示すように、その子型１６１の型面１６１ａにスパッタ法により銅拡散防止膜１７０として窒化チタン膜を１００nm程度の厚さに形成する。   Next, as shown in FIG. 49B, a titanium nitride film as a copper diffusion preventing film 170 is formed on the mold surface 161a of the child mold 161 to a thickness of about 100 nm by a sputtering method.

なお、銅拡散防止膜１７０は窒化チタン膜に限定されない。銅拡散防止膜１７０としては、窒化シリコン膜、チタン膜、タンタル膜、及び窒化タンタル膜のいずれかを形成し得る。   The copper diffusion prevention film 170 is not limited to the titanium nitride film. As the copper diffusion preventing film 170, any one of a silicon nitride film, a titanium film, a tantalum film, and a tantalum nitride film can be formed.

また、後で形成される導体プレート１００を子型１６１から剥離し易いようにするため、銅拡散防止膜１７０の形成前に、子型１６１の型面１６１ａに有機系の離型剤の層を数nmから１０nm程度の厚さに形成しておいてもよい。   Further, in order to facilitate peeling of the conductor plate 100 formed later from the child die 161, an organic mold release agent layer is formed on the die surface 161a of the child die 161 before the copper diffusion prevention film 170 is formed. It may be formed to a thickness of several nm to 10 nm.

そして、図５０（ａ）に示すように、銅拡散防止膜１７０の上にシード層１７１として厚さが約１００nmのチタン膜と厚さが約５００nmの銅膜とをこの順にスパッタ法により形成する。   Then, as shown in FIG. 50A, a titanium film having a thickness of about 100 nm and a copper film having a thickness of about 500 nm are formed in this order as a seed layer 171 on the copper diffusion prevention film 170 by a sputtering method. .

続いて、図５０（ｂ）に示すように、シード層１７１から給電を行い、該シード層１７１層の上に銅めっき層１７２を形成する。その銅めっき層１７２の厚さは限定されないが、本実施形態では子型１６１の上面から約１０μm以上の厚さに銅めっき層１７２を形成する。   Subsequently, as shown in FIG. 50B, power is supplied from the seed layer 171 to form a copper plating layer 172 on the seed layer 171 layer. Although the thickness of the copper plating layer 172 is not limited, in this embodiment, the copper plating layer 172 is formed to a thickness of about 10 μm or more from the upper surface of the child die 161.

この後に、子型１６１から銅めっき層１７２を剥離することにより、図５１に示すように、銅めっき層１７２、シード層１７１、及び銅拡散防止膜１７０を備えた導体プレート１００を得ることができる。   Thereafter, by peeling the copper plating layer 172 from the child die 161, the conductor plate 100 including the copper plating layer 172, the seed layer 171 and the copper diffusion prevention film 170 can be obtained as shown in FIG. .

なお、上記では図４９（ｂ）のように子型１６１の型面１６１ａ上に銅拡散防止膜１７０を形成したが、銅拡散防止膜１７０の形成方法はこれに限定されない。例えば、銅拡散防止膜１７０を形成しない状態で導体プレート１００を形成し、その導体プレート１００の完成後にその表面にスパッタ法で銅拡散防止膜１７０を形成するようにしてもよい。   In the above description, the copper diffusion prevention film 170 is formed on the mold surface 161a of the child mold 161 as shown in FIG. 49B, but the method of forming the copper diffusion prevention film 170 is not limited to this. For example, the conductor plate 100 may be formed without forming the copper diffusion prevention film 170, and the copper diffusion prevention film 170 may be formed on the surface of the conductor plate 100 by sputtering after the completion of the conductor plate 100.

図５２は、本実施形態に係る銅拡散防止膜１７０を備えた導体プレート１００を利用し、第９実施形態の図２７〜図３２に従って作製した電子部品の拡大断面図である。   FIG. 52 is an enlarged cross-sectional view of an electronic component manufactured according to FIGS. 27 to 32 of the ninth embodiment using the conductor plate 100 including the copper diffusion prevention film 170 according to the present embodiment.

図５２に示すように、上記のように導体プレート１００に銅拡散防止膜１７０を形成したことで、導体パターン１００ｚにも銅拡散防止膜１７０が形成される。これにより、導体パターン１００ｚの銅が樹脂層１０３内に拡散するのが防止され、隣接する導体パターン１００ｚ同士を樹脂層１０３によって良好に絶縁することが可能となる。
As shown in FIG. 52, by forming the copper diffusion prevention film 170 on the conductor plate 100 as described above, the copper diffusion prevention film 170 is also formed on the conductor pattern 100z. Thereby, the copper of the conductor pattern 100z is prevented from diffusing into the resin layer 103, and the adjacent conductor patterns 100z can be well insulated by the resin layer 103.

Claims (20)

下地の上に樹脂層を形成する工程と、
一方の主面にパターンが形成された導体プレートを前記樹脂層に押し当て、該樹脂層に前記パターンを埋め込む工程と、
前記樹脂層が現れるまで前記導体プレートの他方の主面に対して研磨、CMP(Chemical Mechanical Polishing)、又は切削を行い、前記パターンを前記樹脂層に導体パターンとして残す工程と、
を有することを特徴とする電子部品の製造方法。Forming a resin layer on the base;
Pressing a conductive plate having a pattern on one main surface against the resin layer, and embedding the pattern in the resin layer;
Polishing the other main surface of the conductor plate until the resin layer appears, CMP (Chemical Mechanical Polishing), or cutting, leaving the pattern as a conductor pattern on the resin layer;
A method for manufacturing an electronic component, comprising: 前記パターンは、前記下地に当接する突起を有することを特徴とする請求項１に記載の電子部品の製造方法。   The method of manufacturing an electronic component according to claim 1, wherein the pattern includes a protrusion that contacts the base. 前記突起は、前記下地に当接することにより形状が潰れる先端を有することを特徴とする請求項２に記載の電子部品の製造方法。   The method of manufacturing an electronic component according to claim 2, wherein the protrusion has a tip whose shape is crushed by contacting the base. 前記下地として、表面に電極パッドが形成された回路基板又は半導体素子を使用し、
前記樹脂層にパターンを埋め込む工程において、前記電極パッドに前記突起を当接させることを特徴とする請求項２又は請求項３に記載の電子部品の製造方法。As the base, using a circuit board or a semiconductor element having an electrode pad formed on the surface,
The method for manufacturing an electronic component according to claim 2, wherein, in the step of embedding a pattern in the resin layer, the protrusion is brought into contact with the electrode pad. 前記突起の先端に低融点金属を固着する工程と、
前記パターンが前記樹脂層に埋め込まれた状態で、前記低融点金属を加熱して溶融させ、前記低融点金属を介して前記突起と前記電極パッドとを接合する工程とを更に有することを特徴とする請求項４に記載の電子部品の製造方法。Fixing a low melting point metal to the tip of the protrusion;
A step of heating and melting the low melting point metal in a state where the pattern is embedded in the resin layer, and joining the protrusion and the electrode pad via the low melting point metal. The manufacturing method of the electronic component of Claim 4. 導体プレートの一方の主面に形成されたパターンを、下地の電極パッドに接続する工程と、
前記導体プレートと前記下地との間に樹脂を注入して樹脂層を形成する工程と、
前記樹脂層が現れるまで前記導体プレートの他方の主面に対して研磨、CMP、又は切削を行い、前記パターンを前記樹脂層に導体パターンとして残す工程と、
を有することを特徴とする電子部品の製造方法。Connecting the pattern formed on one main surface of the conductor plate to the underlying electrode pad;
Injecting resin between the conductor plate and the base to form a resin layer;
Polishing, CMP, or cutting the other main surface of the conductor plate until the resin layer appears, and leaving the pattern as a conductor pattern on the resin layer;
A method for manufacturing an electronic component, comprising: 前記パターンを前記電極パッドに接続する工程は、前記パターンを前記電極パッドに押し当てながら加熱することにより、前記パターンを金属接合により前記電極パッドに接続して行われることを特徴とする請求項６に記載の電子部品の製造方法。   7. The step of connecting the pattern to the electrode pad is performed by connecting the pattern to the electrode pad by metal bonding by heating while pressing the pattern against the electrode pad. The manufacturing method of the electronic component of description. 前記電極パッドの前記加熱は、不活性ガス又は還元性ガスの雰囲気中で行われることを特徴とする請求項７に記載の電子部品の製造方法。   The method for manufacturing an electronic component according to claim 7, wherein the heating of the electrode pad is performed in an atmosphere of an inert gas or a reducing gas. 前記パターンを前記電極パッドに接続する前に、該パターンと該電極パッドのそれぞれの表面の酸化膜を除去する工程を更に有することを特徴とする請求項６〜８のいずれか１項に記載の電子部品の製造方法。   9. The method according to claim 6, further comprising a step of removing an oxide film on a surface of each of the pattern and the electrode pad before connecting the pattern to the electrode pad. 10. Manufacturing method of electronic components. 前記樹脂層に前記導体パターンを残す工程において、第１の部分と、該第１の部分よりも厚い第２の部分とを前記導体パターンに形成し、
前記樹脂層に前記導体パターンを残した後に、前記導体パターンの前記第２の部分に突起電極を接合する工程を更に有することを特徴とする請求項１〜９のいずれか１項に記載の電子部品の製造方法。In the step of leaving the conductor pattern in the resin layer, a first portion and a second portion thicker than the first portion are formed in the conductor pattern,
The electron according to claim 1, further comprising a step of bonding a protruding electrode to the second portion of the conductor pattern after leaving the conductor pattern in the resin layer. A manufacturing method for parts. 前記樹脂層と前記導体パターンとを覆う樹脂の塗膜を形成する工程と、
前記塗膜に突起電極を押し込み、該突起電極を前記導体パターンに当接させる工程と、
前記突起電極を加熱して溶融することにより、該突起電極と前記導体パターンとを接合する工程とを更に有することを特徴とする請求項１〜９のいずれか１項に記載の電子部品の製造方法。Forming a resin coating film covering the resin layer and the conductor pattern;
Pressing the protruding electrode into the coating film, and contacting the protruding electrode with the conductor pattern;
The manufacturing of the electronic component according to any one of claims 1 to 9, further comprising a step of joining the protruding electrode and the conductor pattern by heating and melting the protruding electrode. Method. 前記突起電極は、低融点金属を含むことを特徴とする請求項１０又は請求項１１に記載の電子部品の製造方法。   The method of manufacturing an electronic component according to claim 10, wherein the protruding electrode includes a low melting point metal. 前記塗膜として熱硬化性樹脂の塗膜を形成し、
前記突起電極を加熱する工程において、前記塗膜を加熱して硬化させることを特徴とする請求項１１又は請求項１２に記載の電子部品の製造方法。Forming a thermosetting resin coating as the coating,
The method for manufacturing an electronic component according to claim 11, wherein in the step of heating the protruding electrode, the coating film is heated and cured. 一方の主面に凹部が形成された複数の下地を並べる工程と、
前記下地の各々の前記凹部に、導体プレートの一方の主面に形成されたパターンの突起を嵌入することにより、前記複数の下地を前記導体プレートにより繋ぐ工程と、
前記複数の下地のそれぞれの主面上に樹脂層を形成する工程と、
前記樹脂層が現れるまで前記導体プレートの他方の主面に対して研磨、CMP、又は切削を行い、前記パターンを前記樹脂層に導体パターンとして残す工程と、
を有することを特徴とする電子部品の製造方法。Arranging a plurality of bases having recesses formed on one main surface;
A step of connecting the plurality of bases by the conductor plate by inserting a projection of a pattern formed on one main surface of the conductor plate into each of the recesses of the base; and
Forming a resin layer on each main surface of the plurality of bases;
Polishing, CMP, or cutting the other main surface of the conductor plate until the resin layer appears, and leaving the pattern as a conductor pattern on the resin layer;
A method for manufacturing an electronic component, comprising: 前記樹脂層を形成する工程は、前記複数の下地を前記導体プレートにより繋いだ後に、前記複数の下地のそれぞれの前記主面と前記導体プレートとの間に樹脂を充填することにより行われることを特徴とする請求項１４に記載の電子部品の製造方法。   The step of forming the resin layer is performed by filling a resin between the main surface of each of the plurality of bases and the conductor plate after connecting the plurality of bases by the conductor plate. The method of manufacturing an electronic component according to claim 14, characterized in that: 前記樹脂層を形成する工程は、前記複数の下地を前記導体プレートにより繋ぐ前に行われ、
前記複数の下地を前記導体プレートにより繋ぐ工程は、前記樹脂層に前記導体プレートを押し当てて行われることを特徴とする請求項１４に記載の電子部品の製造方法。The step of forming the resin layer is performed before connecting the plurality of bases by the conductor plate,
The method of manufacturing an electronic component according to claim 14, wherein the step of connecting the plurality of bases by the conductor plate is performed by pressing the conductor plate against the resin layer. 前記突起は、前記電極パッドに当接することにより形状が潰れる先端を有することを特徴とする請求項１４〜１６のいずれか１項
に記載の電子部品の製造方法。The method of manufacturing an electronic component according to any one of claims 14 to 16, wherein the protrusion has a tip whose shape is crushed by contacting the electrode pad. 前記導体プレートの前記パターンは銅膜を有し、前記銅膜の上に銅拡散防止膜が形成されたことを特徴とする請求項１〜１７のいずれか１項に記載の電子部品の製造方法。   The method of manufacturing an electronic component according to claim 1, wherein the pattern of the conductor plate includes a copper film, and a copper diffusion prevention film is formed on the copper film. . 下地と、
前記下地の上に形成された電極パッドと、
前記下地と前記電極パッドの上に形成された樹脂層と、
前記電極パッドの上の前記樹脂層に埋め込まれた導体パターンとを有し、
前記導体パターンと前記電極パッドとが低融点金属を介して接合されたことを特徴とする電子部品。The groundwork,
An electrode pad formed on the base;
A resin layer formed on the base and the electrode pad;
A conductor pattern embedded in the resin layer on the electrode pad;
An electronic component, wherein the conductor pattern and the electrode pad are bonded via a low melting point metal. 下地と、
前記下地の上に形成された電極パッドと、
前記下地と前記電極パッドの上に形成された樹脂層と、
前記樹脂層に埋め込まれ、前記電極パッドに当接した突起を備えた導体パターンとを有し、
前記突起の先端が、前記電極パッドの上面において横方向に潰れたことを特徴とする電子部品。
The groundwork,
An electrode pad formed on the base;
A resin layer formed on the base and the electrode pad;
A conductor pattern with a protrusion embedded in the resin layer and in contact with the electrode pad;
An electronic component, wherein a tip of the protrusion is crushed laterally on an upper surface of the electrode pad.
JP2010543960A 2008-12-22 2009-10-15 Manufacturing method of electronic parts Expired - Fee Related JP5310743B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010543960A JP5310743B2 (en) 2008-12-22 2009-10-15 Manufacturing method of electronic parts

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008326143 2008-12-22
JP2008326143 2008-12-22
PCT/JP2009/067830 WO2010073800A1 (en) 2008-12-22 2009-10-15 Electronic component and method for manufacturing same
JP2010543960A JP5310743B2 (en) 2008-12-22 2009-10-15 Manufacturing method of electronic parts

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012236730A Division JP5585634B2 (en) 2008-12-22 2012-10-26 Electronic parts and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPWO2010073800A1 true JPWO2010073800A1 (en) 2012-06-14
JP5310743B2 JP5310743B2 (en) 2013-10-09

Family

ID=42287427

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2010543960A Expired - Fee Related JP5310743B2 (en) 2008-12-22 2009-10-15 Manufacturing method of electronic parts
JP2012236730A Expired - Fee Related JP5585634B2 (en) 2008-12-22 2012-10-26 Electronic parts and manufacturing method thereof

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012236730A Expired - Fee Related JP5585634B2 (en) 2008-12-22 2012-10-26 Electronic parts and manufacturing method thereof

Country Status (6)

Country Link
US (1) US8704106B2 (en)
EP (3) EP2384102A4 (en)
JP (2) JP5310743B2 (en)
KR (1) KR101230564B1 (en)
CN (1) CN102265714B (en)
WO (1) WO2010073800A1 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013211344A (en) * 2012-03-30 2013-10-10 Fujikura Ltd Multilayer wiring board manufacturing method
JP2014049580A (en) * 2012-08-31 2014-03-17 Murata Mfg Co Ltd Wiring board
JP5460897B1 (en) * 2013-01-17 2014-04-02 株式会社テムテック研究所 Method for manufacturing an electrode of a flat heating element
US9215798B2 (en) * 2013-03-05 2015-12-15 Eastman Kodak Company Imprinted multi-layer micro-structure method with multi-level stamp
US8895429B2 (en) * 2013-03-05 2014-11-25 Eastman Kodak Company Micro-channel structure with variable depths
EP3063464B1 (en) * 2013-09-24 2018-04-25 Philips Lighting Holding B.V. Lighting unit
JP2015109358A (en) * 2013-12-05 2015-06-11 デクセリアルズ株式会社 Method for manufacturing connection structure and anisotropic conductive film
JP6226069B2 (en) * 2014-05-30 2017-11-08 株式会社村田製作所 Manufacturing method of electronic parts
CN104597677B (en) * 2015-02-09 2017-05-31 合肥京东方光电科技有限公司 A kind of integrated circuit, first circuit structure and preparation method thereof
JP6457881B2 (en) * 2015-04-22 2019-01-23 新光電気工業株式会社 Wiring board and manufacturing method thereof
GB201613051D0 (en) 2016-07-28 2016-09-14 Landa Labs (2012) Ltd Applying an electrical conductor to a substrate
US11259417B2 (en) * 2018-03-14 2022-02-22 Lg Chem, Ltd. Embedded-type transparent electrode substrate and method for manufacturing same
US11791281B2 (en) * 2020-03-19 2023-10-17 Advanced Semiconductor Engineering, Inc. Package substrate and method for manufacturing the same
CN114643406B (en) * 2022-04-01 2023-09-01 哈焊国创(青岛)焊接工程创新中心有限公司 Friction micro-rivet welding method for light alloy and fiber reinforced composite material

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5651889A (en) * 1979-10-05 1981-05-09 Tokyo Shibaura Electric Co Method of manufacturing copperrcoated laminate board
US5374469A (en) * 1991-09-19 1994-12-20 Nitto Denko Corporation Flexible printed substrate
JPH0580530A (en) * 1991-09-24 1993-04-02 Hitachi Ltd Production of thin film pattern
JP3057130B2 (en) 1993-02-18 2000-06-26 三菱電機株式会社 Resin-sealed semiconductor package and method of manufacturing the same
JPH08264939A (en) * 1995-03-28 1996-10-11 Toshiba Corp Manufacture of printed wiring board
US6464510B1 (en) * 1999-05-24 2002-10-15 Anaren Microwave, Inc. Microwave circuit connector
TW512467B (en) 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
JP2002141637A (en) * 2000-11-02 2002-05-17 Multi:Kk Printed-wiring board and its manufacturing method
JP4129971B2 (en) 2000-12-01 2008-08-06 新光電気工業株式会社 Wiring board manufacturing method
US6518096B2 (en) * 2001-01-08 2003-02-11 Fujitsu Limited Interconnect assembly and Z-connection method for fine pitch substrates
JP3969192B2 (en) 2002-05-30 2007-09-05 株式会社デンソー Manufacturing method of multilayer wiring board
JP2004200247A (en) 2002-12-16 2004-07-15 Seiko Epson Corp Terminal, forming method therefor, semiconductor chip, semiconductor mounting substrate, electronic device and electronic apparatus
US7001662B2 (en) * 2003-03-28 2006-02-21 Matsushita Electric Industrial Co., Ltd. Transfer sheet and wiring board using the same, and method of manufacturing the same
US6853060B1 (en) * 2003-04-22 2005-02-08 Amkor Technology, Inc. Semiconductor package using a printed circuit board and a method of manufacturing the same
KR100604819B1 (en) 2003-06-12 2006-07-28 삼성전자주식회사 Flexible substrate for LDI package, manufacturing method thereof and semiconductor package using the same
JP4106438B2 (en) 2003-06-20 2008-06-25 独立行政法人産業技術総合研究所 Multilayer fine wiring interposer and manufacturing method thereof
US20050218491A1 (en) * 2004-03-31 2005-10-06 Alps Electric Co., Ltd. Circuit component module and method of manufacturing the same
JP4574288B2 (en) * 2004-04-09 2010-11-04 大日本印刷株式会社 Manufacturing method of rigid-flexible substrate
JP2006080424A (en) * 2004-09-13 2006-03-23 Matsushita Electric Ind Co Ltd Wiring board and its manufacturing method
JP2006100463A (en) 2004-09-29 2006-04-13 Ibiden Co Ltd Interlayer insulating layer for printed wiring board, printed wiring board and manufacturing method thereof
JP2006108211A (en) 2004-10-01 2006-04-20 North:Kk Wiring board, multilayered wiring circuit board using the board, and method of manufacturing the multilayered wiring circuit board
KR100632553B1 (en) 2005-04-20 2006-10-11 삼성전기주식회사 Method for manufacturing printed circuit board using imprinting process
KR20080017403A (en) * 2005-06-01 2008-02-26 미쓰이 긴조꾸 고교 가부시키가이샤 Mold for wiring substrate formation and process for producing the same, wiring substrate and process for producing the same, process for producing multilayered laminated wiring substrate and method for viahole formation
JP2006339365A (en) * 2005-06-01 2006-12-14 Mitsui Mining & Smelting Co Ltd Wiring board, its manufacturing method, manufacturing method of multilayer laminated wiring board and forming method of via hole
KR100688869B1 (en) 2005-07-22 2007-03-02 삼성전기주식회사 Method for fabricating printed circuit board using imprint process
CN101263752B (en) * 2005-09-20 2010-06-09 株式会社村田制作所 Method for manufacturing component incorporating module and component incorporating module
KR100797698B1 (en) * 2005-09-27 2008-01-23 삼성전기주식회사 Manufacturing method of high density printed circuit board
US7351784B2 (en) * 2005-09-30 2008-04-01 Intel Corporation Chip-packaging composition of resin and cycloaliphatic amine hardener
JP4058444B2 (en) * 2005-11-15 2008-03-12 Ｔｄｋ株式会社 Stamper, imprint method, and information recording medium manufacturing method
KR100733253B1 (en) * 2005-11-18 2007-06-27 삼성전기주식회사 High density printed circuit board and manufacturing method thereof
US7990165B2 (en) * 2006-04-21 2011-08-02 National Institute Of Advanced Industrial Science And Technology Contact probe and method of making the same
JP5187714B2 (en) 2006-07-11 2013-04-24 独立行政法人産業技術総合研究所 Semiconductor chip electrode connection structure
JP4783692B2 (en) * 2006-08-10 2011-09-28 新光電気工業株式会社 Capacitor-embedded substrate, manufacturing method thereof, and electronic component device
JP4105202B2 (en) 2006-09-26 2008-06-25 新光電気工業株式会社 Manufacturing method of semiconductor device
JP5091600B2 (en) * 2006-09-29 2012-12-05 三洋電機株式会社 Semiconductor module, semiconductor module manufacturing method, and portable device
CN101231963A (en) * 2006-09-29 2008-07-30 三洋电机株式会社 Semiconductor module, method for manufacturing the semiconductor module and portable device carrying the same
JP4073945B1 (en) 2007-01-12 2008-04-09 新光電気工業株式会社 Manufacturing method of multilayer wiring board
US7636215B2 (en) * 2007-01-19 2009-12-22 Tdk Corporation Magnetic recording medium, recording/reproducing apparatus, and method of manufacturing a magnetic recording medium
KR100811768B1 (en) 2007-04-23 2008-03-07 삼성전기주식회사 Manufacturing method of pcb
JP4317245B2 (en) * 2007-09-27 2009-08-19 新光電気工業株式会社 Electronic device and manufacturing method thereof
KR20090128680A (en) * 2008-06-11 2009-12-16 삼성전자주식회사 Master for manufacturing mold, mold for display device and manufacturing method thereof usign the same, and manufacturing method of display device using the same

Also Published As

Publication number Publication date
EP2421342A2 (en) 2012-02-22
US20110220397A1 (en) 2011-09-15
KR101230564B1 (en) 2013-02-07
JP5585634B2 (en) 2014-09-10
KR20110084525A (en) 2011-07-25
EP2421342B1 (en) 2013-09-11
JP5310743B2 (en) 2013-10-09
EP2421341A2 (en) 2012-02-22
EP2421341A3 (en) 2012-08-15
CN102265714B (en) 2014-05-14
WO2010073800A1 (en) 2010-07-01
EP2384102A4 (en) 2012-08-08
EP2384102A1 (en) 2011-11-02
EP2421341B1 (en) 2013-09-11
JP2013030809A (en) 2013-02-07
CN102265714A (en) 2011-11-30
US8704106B2 (en) 2014-04-22
EP2421342A3 (en) 2012-08-15

Similar Documents

Publication Publication Date Title
JP5585634B2 (en) Electronic parts and manufacturing method thereof
TWI499009B (en) Device packaging with substrates having embedded lines and metal defined pads
JP4052955B2 (en) Manufacturing method of semiconductor device
JP4146864B2 (en) WIRING BOARD AND MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
US9455219B2 (en) Wiring substrate and method of manufacturing the same
US8035202B2 (en) Electronic device having a wiring substrate
JP4980295B2 (en) Wiring substrate manufacturing method and semiconductor device manufacturing method
US20200135678A1 (en) Protrusion Bump Pads for Bond-on-Trace Processing
JP2006302929A (en) Salient electrode for connecting electronic component, electronic component packaging body using the same, and manufacturing method of salient electrode and electronic component packaging body
JP2009302476A (en) Semiconductor device, and method of manufacturing the same
KR20130063984A (en) Wiring board and method of manufacturing the same
JP5018270B2 (en) Semiconductor laminate and semiconductor device using the same
CN113228257A (en) Substrate for forming through-hole wiring, method for manufacturing the same, and semiconductor device mounting member
KR101009187B1 (en) A printed circuit board and a fabricating method of the same
JP2005243850A (en) Multilayer printed wiring board and its manufacturing method
JP2009147080A (en) Semiconductor device package and method of manufacturing the same
JP3350454B2 (en) Semiconductor integrated circuit device, method of manufacturing the same, and manufacturing apparatus
JP5392167B2 (en) Electronic parts and manufacturing method thereof
KR100942772B1 (en) Flip chip technology without solder resist and under-fill ink processes
JP2022023334A (en) Rewiring board, manufacturing method of semiconductor package board, and semiconductor package board
JP2020087982A (en) Via wiring forming substrate, via wiring forming substrate manufacturing method, and semiconductor chip mounting method
JP2012079956A (en) Semiconductor device and method for manufacturing the same
JP2000277652A (en) Semiconductor package

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120828

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121026

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130604

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130617

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees