JP2022023334A - Rewiring board, manufacturing method of semiconductor package board, and semiconductor package board - Google Patents

Abstract

To provide a rewiring board, a manufacturing method of a semiconductor package board, and a semiconductor package board that suppress open defects due to variations in the amount of solder and ensures connection reliability and mechanical strength even with a small amount of solder.SOLUTION: A rewiring board 10 includes a support 21, a peeling layer formed on one side of the support 21 and provided with a first reference plane S1, a wiring layer formed adjacent to the peeling layer and provided with a plurality of connection terminals, and a resin layer 25 formed on the side of the other surface of the support 21 and provided with a second reference plane S2 parallel to the first reference plane S1, and the end face of the connection terminal facing the support 21 has the same distance from the second reference plane S2, and after connecting a main board 1 and the rewiring board 10, the support 21 is deleted to obtain a more compact semiconductor package board 100.SELECTED DRAWING: Figure 2

Description

The present invention relates to a rewiring substrate, a method for manufacturing a semiconductor package substrate, and a semiconductor package substrate.

As the technology node of semiconductor chips advances year by year, narrower pitches between terminals of semiconductor chips are required, and finer and narrower pitches between terminals are also required for semiconductor package substrates on which semiconductor chips are mounted. Here, microbumps by solder connection are often used in the connection terminal structure between the semiconductor chip and the semiconductor package substrate (see Patent Documents 1 and 2).

Japanese Unexamined Patent Publication No. 2004-47510 Japanese Unexamined Patent Publication No. 2014-203963

According to the micro bumps disclosed in Patent Document 1 or 2, since the solder for connecting the semiconductor chips has a drum shape, if the terminals are lined up at a narrower pitch, the solder of the adjacent terminals is soldered. There is a problem that short circuits between them are likely to occur.
If the amount of solder is reduced in order to prevent this short circuit, the gap between the semiconductor chip and the semiconductor package substrate cannot be secured, which leads to deterioration of the injectability of the underfill resin. For this reason, a copper pillar is used in the terminal structure corresponding to the miniaturization of semiconductor chips to secure a gap so that underfill resin injection failure does not occur even with a small amount of solder.

However, if the amount of solder is reduced, the solder margin with respect to the variation in the copper pillars becomes narrower and smaller, which may lead to local open failure (connection failure). Further, when a thin copper pillar is used, the amount of solder arranged on the crown of the copper pillar having a smaller diameter is reduced. Since the solder layer is generally softer than the hardness of the IMC layer (Intermetallic layer) alloyed with solder, it has a function of absorbing mechanical impact, but it tends to become thinner as the melting time at high temperature becomes longer. There is a problem that the mechanical strength on the connection surface becomes weak due to this.

An object of the present invention is to provide a rewiring substrate, a method for manufacturing a semiconductor package substrate, and a semiconductor package substrate, which can suppress open defects due to variations in the amount of solder and can secure connection reliability and mechanical strength even with a small amount of solder. do.

In order to solve the above problems, one of the typical rewiring boards of the present invention is
With the support,
A peeling layer formed on one side of the support and provided with a first reference plane,
A wiring layer formed adjacent to the peeling layer and having a plurality of connection terminals,
It has a resin layer formed on the other side of the support and provided with a second reference plane parallel to the first reference plane.
The end faces of the connection terminals facing the support have the same distance from the second reference plane.

Further, in order to solve the above problems, one of the typical methods for manufacturing a semiconductor package substrate of the present invention is
A step of forming a release layer having a first reference plane on one side of the support, and
A step of forming a resin layer having a second reference plane parallel to the first reference plane on the other side of the support.
A step of laminating on the peeling layer to form a resin pattern layer having an opening, and
A step of forming a plurality of connection terminals in the opening of the resin pattern layer so that the inner end faces are in contact with the first reference plane.
A step of exposing the vicinity of the outer end face of the connection terminal by removing a part of the resin pattern layer.
The process of connecting the outer end surface of the connection terminal and the wiring terminal of the main board with solder,
The process of filling the underfill resin around the connected connection terminals,
The step of removing the support and the peeling layer, and
It has a step of removing the residue of the resin pattern layer.
Since it is difficult to directly specify the semiconductor package substrate of the present invention due to its structure or characteristics, the structure itself is specified by the method for manufacturing the structure, which is impossible or impractical. There are some circumstances.

According to the present invention, it is possible to provide a rewiring substrate, a method for manufacturing a semiconductor package substrate, and a semiconductor package substrate, which can suppress open defects due to variations in the amount of solder and ensure connection reliability and mechanical strength even with a small amount of solder. can.
Issues, configurations and effects other than those described above will be clarified by the following description of the embodiments.

FIG. 1 is a cross-sectional view of a main substrate according to the present embodiment. FIG. 2 is a cross-sectional view of the rewiring board according to the present embodiment. FIG. 3 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 4 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 8 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 9 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 11 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the rewiring substrate according to the present embodiment. FIG. 13 is a cross-sectional view showing a connection process between the rewiring board and the main board according to the present embodiment. FIG. 14 is a cross-sectional view showing a connection process between the rewiring board and the main board according to the present embodiment. FIG. 15 is a cross-sectional view showing a semiconductor package substrate according to this embodiment.

Embodiments of the present invention will be described below.

In the present disclosure, the term "plane" may refer not only to the surface of the plate-shaped member but also to the interface of the layer substantially parallel to the surface of the plate-shaped member for the layer contained in the plate-shaped member. Further, the "upper surface" and "lower surface" mean a plate-shaped member and a surface shown above or below in the drawing when the layer included in the plate-shaped member is illustrated.
Further, the "side surface" means a plate-shaped member or a portion of the layer included in the plate-shaped member and having a thickness of the surface or layer. Further, a part of the surface and the side surface may be collectively referred to as an "end".
Further, "upper" means a vertically upward direction when a plate-shaped member or a layer is placed horizontally. Further, the "upper" and the opposite "lower" may be referred to as "Z-axis direction", and the horizontal direction may be referred to as "X-axis direction" and "Y-axis direction".
Further, "planar shape" and "planar view" mean a shape when a surface or a layer is visually recognized from above. Further, the "cross-sectional shape" and "cross-sectional view" mean the shape when the plate-shaped member or the layer is cut in a specific direction and visually recognized from the horizontal direction.
Further, "central" means a central portion that is not a peripheral portion of a surface or layer. The "center direction" means a direction from the peripheral portion of the surface or layer toward the center in the planar shape of the surface or layer.

Further, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention describes the material, shape, structure, and arrangement of constituent parts. Etc. are not specified as the following. The technical idea of the present invention may be modified in various ways within the technical scope specified by the claims described in the claims.

The semiconductor package substrate of this embodiment is manufactured by manufacturing a main board and a rewiring board in a separate process, soldering the corresponding rewiring boards on the main board, and joining them by injecting an underfill resin.

The wiring scale of the rewiring board in this embodiment is L / S (wiring / space) = 0.5 μm / 0.5 μm to L / S = 10 μm / 10 μm (in other words, 0.5 μm ≦ L). (≦ 10 μm, 0.5 μm ≦ S ≦ 10 μm), the wiring scale of the main board is L / S = 10 μm / 10 μm or more, and the main board is made of an insulating resin material containing glass cloth to ensure rigidity. ..

Further, due to the characteristics of the insulating resin material containing glass cloth, the unevenness of the woven glass cloth fiber affects the surface of the insulating resin material. Therefore, generally, the above L / S = on the insulating resin material. It is difficult to realize a fine wiring scale of 0.5 μm / 0.5 μm to L / S = 10 μm / 10 μm, and an insulating resin containing glass cloth cannot be used as it is.
Therefore, in the present embodiment, in the manufacturing process of the rewiring board manufactured separately from the main board, the rewiring board is rigid throughout the process by forming the rewiring board (also referred to as an interposer) using a rigid support. This ensures ease of manufacture. Further, after connecting the main board and the rewiring board, the support is removed to obtain a more compact semiconductor package board.

The main substrate is manufactured by the same method as a flip-chip type semiconductor package substrate having an insulating resin material containing a general glass cloth as a core.

<Main board and its manufacturing method>
Hereinafter, an example of a method for manufacturing a main substrate will be described in detail.

(Formation of line pattern)
First, a through hole 11a is drilled at a predetermined position on an 800 μm glass epoxy substrate (core substrate) 11 with a drill having a diameter of 150 μm, and an electrolytic copper plating layer 12 is formed on the exposed surface of the glass epoxy substrate 11 by electrolytic copper plating. The electrolytic copper plating layer 12a is formed by electrolytically plating the inside of the through hole 11a. The front and back surfaces of the glass epoxy substrate 11 are electrically connected via the electrolytic copper plating layer 12a. If necessary, the electroless copper plating layer 12 and the electrolytic copper plating layer 12a are etched by a subtractive method to form a line pattern.

(Formation of interlayer insulating resin layer)
Next, as the interlayer insulating resin 13 of the main substrate, a resin (product name GX-T31) manufactured by Ajinomoto Fine-Techno Co., Ltd. having a thickness of 40 μm is vacuum-laminated on a copper line pattern. Further, using a UV laser device, holes 13a arranged in a matrix with an opening diameter of 70 μm and a pitch of adjacent holes of 150 μm are opened by aligning with the line pattern of the underlying copper.

(Copper wiring formation of interlayer insulating resin)
Further, a dry film resist (product name RY-5325) manufactured by Hitachi Kasei Co., Ltd. was used on the interlayer insulating resin 13 on which electroless copper was plated with a thickness of 1 μm to form a dry film resist pattern in which the line pattern was opened. After that, electrolytic copper plating with a thickness of 15 μm is performed. An independent copper wiring 14 is produced by peeling off an unnecessary dry film resist with a 20% monoethanolamine aqueous solution and etching a 1 μm-thick electroless copper plating layer exposed with a sulfuric acid-based etching solution. .. Further, the copper wiring 14 is sealed with a resin to form the wiring layer 15.

(Laminating copper wiring and interlayer insulating resin)
Further, by alternately laminating the wiring layer 15 and the interlayer insulating resin 13, the main substrate 1 having a multilayer structure can be obtained, but here, each layer is used. Such a construction method is called a semi-additive construction method, and the minimum wiring scale in the main substrate 1 having a multilayer structure is wiring / space (L / S) = 10/10 μm.

Finally, the solder resist 16 is coated and developed on both sides of the main substrate 1. As a result, as shown in FIG. 1, the main substrate 1 having the desired opening pattern can be formed. The manufacturing method of the main substrate 1 is not limited to the above.

<Rewiring board>
In parallel with the production of the main substrate 1, the rewiring substrate 10 shown in FIG. 2 is produced. The rewiring substrate 10 is formed on the side of the support 21 and one surface of the support 21, and has a peeling layer (here, including the LTHC layer 23 and the seed layer 24) provided with the first reference surface S1 and peeling. A wiring layer formed adjacent to the layer and having a plurality of connection terminals (here, the first plating layer 27, including the copper pillar 32a) and formed on the other side side of the support 21, the first reference. The end faces of the first plating layer 27 having the resin layer 25 provided with the second reference plane S2 parallel to the plane S1 and facing the support 21 have the same distance from the second reference plane S2. ..

The rewiring board 10 of the present embodiment is assembled to the main board 1 and then the support 21 is separated to form a so-called "coreless board", which enables connection with a semiconductor element. A general build-up multilayer wiring board (for example, main substrate 1) requires a highly rigid core substrate for alternately laminating wiring layers and insulating layers. However, if the core board is provided, the thickness of the wiring board increases, which is disadvantageous at the time of mounting. Therefore, at the time of manufacturing the rewiring board 10 of the present embodiment, the support 21 is used as described later in order to secure the rigidity, but for example, after being connected to the main board 1, the unnecessary support 21 is separated. Then, a thin semiconductor package substrate can be constructed by leaving only the wiring layer and the insulating layer.

<Manufacturing method of rewiring board>
Hereinafter, a method for manufacturing the rewiring board 10 will be described.

(Preparation of support)
As shown in FIG. 3, a support 21 made of a light-transmitting material is prepared. Here, the support 21 is made of soda lime glass having a thickness of 1.1 mm, but in general, the glass plate is often slightly distorted. Therefore, as shown in FIG. 4, the surface of the support 21 is ground with the grinding wheel 22. By grinding one surface of the support 21, the first reference surface S1 described later can be formed. Further, as will be described later, since the second reference surface S2 is formed on the resin layer 25, it is not necessary to grind the other surface of the support 21, which can reduce the manufacturing man-hours. The support 21 may be made of ceramic or resin.

(Formation of release layer)
Further, in FIG. 5, an LTHC resin manufactured by 3M is formed on the surface of the support 21 by spin coating to form an LTHC layer 23 having a film thickness of 800 nm. Subsequently, the edge rinse of the LTHC layer 23 is performed, and copper having a film thickness of 300 nm is sputtered and formed on the LTHC layer 23 as a seed layer 24 as a seed layer 24 so that the LTHC layer 23 is not exposed. The surface of the seed layer 24 is designated as the first reference plane S1. A release layer is formed by the LTHC layer 23 and the seed layer 24. Since the surface of the support 21 is a flat surface, the first reference surface S1 is also a highly accurate flat surface.

(Formation of resin layer)
Next, as shown in FIG. 6, an epoxy resin having a temperature of 10 μm or more as a thermosetting resin is coated on the back surface where the support 21 is exposed, and the resin layer 25 is formed by thermosetting. If the resin layer 25 is too thick, the warp becomes large due to the influence of the curing shrinkage of the epoxy resin, so a coating with a resin thickness of about 15 μm is preferable. Here, an inexpensive epoxy resin is used as an example, but a resin other than the epoxy resin may be used as long as it has a heat resistance of 200 ° C. or higher.

(Formation of reference plane)
Next, as shown in FIG. 7, the surface of the copper spatter (seed layer 24) of the support 21 is adsorbed and fixed to a porous adsorption stage of a grinding device (not shown), and the first reference surface (copper spatter surface) S1 is formed. The resin layer 25 on the back surface is ground with a grinding wheel 22 so that the parallelism is 1 μm or less as the reference surface. As a result, as shown in FIG. 8, a flat surface parallel to the first reference surface S1 (referred to as the second reference surface S2) can be formed.

(Formation of resin pattern layer)
Next, as shown in FIG. 9, the surface of the seed layer 24 is spin-coated with a 25 μm-thick photosensitive polyimide resin, exposed, developed, and cured, and provided with an opening pattern having an opening corresponding to the desired copper pillar. The resin pattern layer (wiring layer) 26 is formed.

(Formation of connection terminal)
Next, as shown in FIG. 10, power is supplied from the opening of the resin pattern layer 26, electrolytic solder plating of Sn-0.7% Cu is performed, and the first plating layer 27 is formed in contact with the first reference surface S1. Next, electrolytic nickel plating is performed to form the second plating layer 28, and electrolytic copper plating is further performed to form the third plating layer 29, so that electrolytic plating is sequentially performed. The third plating layer 29 is electrolytically copper-plated until it is higher than the surface of the photosensitive polyimide resin. At this point, the lower end surfaces (inner end surfaces) of the first plating layer 27 forming a part of the connection terminal have the same distance from the second reference surface S2 of the resin layer 25, respectively. Here, "equal distance" means that the distance of the resin layer 25 from the second reference plane is within 5 μm.

Next, the third plating layer 29 protruding from the surface of the resin pattern layer 26 is polished by a CMP apparatus (not shown) so that the height of the copper pillar portion 29a and the height of the surface of the resin pattern layer 26 are made uniform.

(Formation of wiring)
Next, as shown in FIG. 11, the photosensitive insulating resin 30 having the product name AH-3000 manufactured by Hitachi Kasei Co., Ltd. is coated with a spin coat to a thickness of 5 μm. Next, the via pattern corresponding to the pattern of the underlying copper pillar portion 29a is exposed and developed to form the via hole 30a. Here, the photosensitive insulating resin 30 may be formed by vacuum laminating a dry film type or by spin-coating or slit-coating a liquid photosensitive insulating resin.

The photosensitive insulating resin 31 on which the via holes 30a are formed is further coated with a spin coat to a thickness of 7 μm, aligned with the via holes 30a, and the line pattern 31a is exposed and developed. Here, the photosensitive insulating resin 31 may be formed by vacuum laminating a dry film type or by spin-coating or slit-coating a liquid photosensitive insulating resin.

Further, as shown in FIG. 12, copper as a seed layer is sputter-deposited on the surface of the photosensitive insulating resin 31 on which the line pattern 31a is formed by superimposing the via holes 30a at 300 nm, and then viafill electrolytic copper plating is performed. , The photosensitive insulating resin 31 of the line pattern is filled with the copper plating 32. Next, it is fixed to the porous adsorption stage of the grinding device, and the electrolytic copper plating on the surface is ground from the second reference surface S2 of the resin layer 25 until the height of the photosensitive insulating resin 31 becomes 10 μm, and the copper is independent. Form a line pattern of.

After that, wiring formation by the above-mentioned photosensitive insulating resin and copper plating may be repeated to form a multilayer wiring layer. A solder resist 33 is coated and developed on the photosensitive insulating resin 31 to form a desired aperture pattern.

Finally, a dry film resist (product name RY-5325) manufactured by Hitachi Chemical Co., Ltd. is laminated on the solder resist 33, exposed to a hole pattern having φ70 μm openings adjacent to each other in a matrix of 150 μm pitch, and then exposed to a seed layer. The copper to be formed is sputter-deposited at 300 nm, and then filled with electrolytic copper plating so as to fill the pore pattern.

(Exposure of connection terminal)
Further, after cutting this surface, the dry photoresist is peeled off with an amine-based stripping solution to form an independent copper pillar 32a so as to be exposed, and further diced piece by piece to form a piece. This completes the rewiring board 10 as shown in FIG.

<Semiconductor package substrate and its manufacturing method>
Hereinafter, a method for manufacturing a semiconductor package substrate will be described.

(Connection between rewiring board and main board)
First, the cream solder 34 of SAC305 is screen-printed on the wiring terminal 17 of the main board 1 manufactured in another process. Next, as shown in FIG. 13, the end face (outer end face) of the copper pillar 32a protruding from the piece reflow board 10 is mounted on the main board 1 while being aligned with the solder 34, and is not shown. Make a solder connection through the reflow device.

(Filling with underfill resin)
Next, as shown in FIG. 14, after the flux cleaning, the main substrate 1 and the rewiring substrate 10 are solidified by injecting the underfill resin 35 into the gap connected via the copper pillar 32a and the solder 34. ..

(Removal of support and resin pattern layer)
Further, the LTHC layer 23 is irradiated with laser light from the outside through the resin layer 25 and the support 21 on the rewiring substrate 10 side, and the support 21 is peeled off from the interface of the LTHC layer 23. Further, the resin pattern layer 26 is melted and peeled off with an alkaline stripping solution. As a result, the semiconductor package substrate 100 shown in FIG. 15 is completed. Here, the structure in which the support 21 and the peeling layer are removed from the rewiring board 10 is referred to as a rewiring unit.

In the completed semiconductor package substrate 100, the connection terminals provided with the first plating layer 27 connected to the wiring terminals of the main substrate 1 and having the same height are arranged at a pitch shorter than the pitch of the copper pillar 32a. It becomes easy to connect to a semiconductor chip and other electronic components via the first plating layer 27. According to this embodiment, it is possible to suppress open defects due to variations in the amount of solder, suppress the growth of the IMC layer, and secure connection reliability and mechanical strength even with a small amount of solder.

<Modification example of manufacturing method of rewiring board>
First, an LTHC resin (product name) manufactured by 3M Co., Ltd. is coated on the support as a temporary sticking peeling layer, the surface layer of the LTHC resin is ground, and 300 nm thick copper is sputter-deposited on the support as a seed layer. , Form a reference flat surface.

Next, in order to form a desired plurality of wiring layers composed of a via pattern and a line pattern, the above steps are repeated while aligning the lower line pattern, the via position of the insulating resin, and the upper line pattern, to form a multi-layer wiring structure. To build.

Next, a photosensitive dry film film having a thickness of 25 μm is attached on the final wiring layer, and the land of the final wiring layer is exposed and developed by aligning the position with the opening pattern. The opening pattern is supplied with power to perform electrolytic copper plating, electrolytic nickel plating, and electrolytic solder plating, and the photosensitive dry film resist is peeled off to form copper pillars.

Next, the support is cut into individual pieces to complete the rewiring board.

A main board including a glass cloth layer, which is omitted from the explanation, is manufactured in a separate process, and here, the copper pillars of the rewiring board are mounted while being aligned on the main board, and the main board and the rewiring board are mounted by the reflow device. Was solder-melted and connected. Clean the flux used in the solder connection, inject underfill resin between the rewiring board and the main board, and integrate the rewiring board and the main board.

Next, the LTHC resin of the temporary sticking peeling layer was irradiated with laser light from the outside through the support, and the support was peeled off. Further, the copper of the seed layer was etched out with an alkaline copper etching solution, and then the photosensitive polyimide film was melted and peeled off with an amine-based stripping solution to form a solder layer, a barrier layer, and a copper layer from above. The semiconductor chip connection terminal is exposed to complete the semiconductor package substrate.

Further, a semiconductor device is completed by mounting and mounting a plurality of semiconductor chips and passive electronic components on a semiconductor package substrate.

According to this embodiment, in a high-density wiring board with a narrow terminal pitch, stable connection can be achieved even with a small amount of solder by making the in-plane heights of the copper pillars uniform.

1 Main board 10 Rewiring board 21 Support 23 LTHC layer 24 Seed layer 25 Resin layer 32a Copper pillar 100 Semiconductor package board S1 First reference plane S2 Second reference plane

Claims (6)

With the support,
A peeling layer formed on one side of the support and provided with a first reference plane,
A wiring layer formed adjacent to the peeling layer and having a plurality of connection terminals,
It has a resin layer formed on the other side of the support and provided with a second reference plane parallel to the first reference plane.
A rewiring board characterized in that the end faces of the connection terminals facing the support have the same distance from the second reference plane. The rewiring according to claim 1, wherein the connection terminal of the wiring layer is formed by laminating a copper layer whose end faces are in contact with the first reference surface of the peeling layer, a barrier layer, and a solder layer. substrate. A step of forming a release layer having a first reference plane on one side of the support, and
A step of forming a resin layer having a second reference plane parallel to the first reference plane on the other side of the support.
A step of laminating on the peeling layer to form a resin pattern layer having an opening, and
A step of forming a plurality of connection terminals in the opening of the resin pattern layer so that the inner end faces are in contact with the first reference plane.
A step of exposing the vicinity of the outer end face of the connection terminal by removing a part of the resin pattern layer.
The process of connecting the outer end surface of the connection terminal and the wiring terminal of the main board with solder,
The process of filling the underfill resin around the connected connection terminals,
The step of removing the support and the peeling layer, and
A method for manufacturing a semiconductor package substrate, which comprises a step of removing the residue of the resin pattern layer. The semiconductor according to claim 3, wherein the support is formed of a light-transmitting material, and the release layer is peeled off by irradiating the support with a laser beam from the outside. Manufacturing method of package substrate. 3. 4. The method for manufacturing a semiconductor package substrate according to 4. A rewiring unit in which the support is separated from the rewiring board according to claim 1 or 2.
Has a main board with wiring terminals,
A semiconductor package substrate characterized in that the support is separated after connecting the connection terminal of the rewiring board and the wiring terminal of the main board.

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