JPWO2007007589A1 - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

A group III nitride semiconductor field effect transistor having excellent operational stability and capable of being manufactured at a high yield is provided. The HJFET 100 includes a group III nitride semiconductor layer structure including a heterojunction of the GaN channel layer 112 and the AlGaN electron supply layer 113, and a source electrode 101 and a drain electrode 103 formed separately on the group III nitride semiconductor layer structure. And a gate electrode 102 disposed between the source electrode 101 and the drain electrode 103. In a region between the gate electrode 102 and the drain electrode 103, an SiN film 121 is provided on the upper part of the group III nitride semiconductor layer structure. The impurity concentration in the AlGaN electron supply layer 113 at the interface between the SiN film 121 and the AlGaN electron supply layer 113 is 1E17 atoms / cm ³ or less.

Description

  The present invention relates to a field effect transistor using a group III nitride semiconductor and a method for manufacturing the same.

  Group III nitride semiconductors such as GaN have higher band gaps, higher dielectric breakdown electric fields, and higher electron saturation drift speeds than GaAs-based semiconductors. As a material that realizes an excellent electronic device, it has been expected.

  In addition, since group III nitride semiconductors have piezoelectricity, the heterojunction structure allows the use of high-concentration two-dimensional carrier gas generated in the heterojunction from spontaneous polarization and piezopolarization, and is generated by impurity doping. It has a feature that it can operate with a mechanism different from that of a GaAs-based semiconductor field effect transistor driven by a carrier.

  In such a III-nitride semiconductor device, a negative charge is induced on the surface of the semiconductor layer structure as carrier gas is generated at the heterojunction, which greatly affects various characteristics of the transistor. Development of negative charge control technology is important. Hereinafter, this point will be described.

  In a layered structure of a group III nitride semiconductor including a heterojunction, it is known that a large charge is generated in the channel layer due to piezoelectric polarization or the like, while a negative charge is generated on the surface of the semiconductor layer such as AlGaN (non-patent document). 1). Such negative charges directly affect the drain current and have a strong influence on device performance. Specifically, when a large negative charge is generated on the surface, the maximum drain current during AC operation is deteriorated as compared with DC. This phenomenon is hereinafter referred to as current collapse. Current collapse is not seen in GaAs heterojunction devices because the generation of polarization charge is extremely small, and is a unique phenomenon that is noticeable in group III nitride semiconductor devices.

  Conventionally, the current collapse has been reduced by forming a surface protective layer for such problems. In the structure in which the protective film is not provided, due to current collapse, a sufficient drain current cannot be obtained when a high voltage is applied, and it is difficult to obtain the advantage of using a group III nitride semiconductor material. In addition, the effect of suppressing current collapse varies depending on the material using the protective film, and it is generally known that SiN has a high effect of suppressing current collapse. Hereinafter, an example of a conventional transistor having a protective film will be described.

  FIG. 28 is a cross-sectional view showing a configuration of a conventional hetero-junction field effect transistor (hereinafter referred to as HJFET). The HJFET shown in FIG. 28 is reported in Non-Patent Document 2, for example.

  In the HJFET 200 of FIG. 28, a buffer layer 211 made of AlN, a GaN channel layer 212, and an AlGaN electron supply layer 213 are laminated on a sapphire substrate 209 in this order. A source electrode 201 and a drain electrode 203 are formed thereon, and these electrodes are in ohmic contact with the AlGaN electron supply layer 213. A gate electrode 202 is formed between the source electrode 201 and the drain electrode 203, and the gate electrode 202 is in Schottky contact with the AlGaN electron supply layer 213. In the uppermost layer, a SiN film 221 is formed as a surface protective film.

  Next, a method for manufacturing the HJFET 200 will be described. First, a semiconductor is grown on a substrate 209 made of sapphire by, for example, a molecular beam epitaxy (MBE) growth method or a metal organic vapor phase epitaxy (MOVPE) growth method. In this way, the buffer layer 211 (thickness 20 nm) made of undoped AlN, the undoped GaN channel layer 212 (thickness 2 μm), and the AlGaN electron supply layer 213 (thickness 25 nm) made of undoped AlGaN in this order from the substrate side. A semiconductor layer structure in which is stacked is obtained.

  Next, a part of the epitaxial layer structure is removed by etching until the GaN channel layer 212 is exposed, thereby forming an element isolation mesa (not shown). Then, after a photoresist is formed in a predetermined region of the AlGaN electron supply layer 213, a metal such as Ti / Al is vapor-deposited on the AlGaN electron supply layer 213, and a source electrode 201 and a drain electrode 203 are formed using a lift-off method or the like. Form. Then, by annealing this at 650 ° C., an ohmic junction is formed between these electrodes and the AlGaN electron supply layer 213.

Subsequently, after a photoresist is formed in a predetermined region of the AlGaN electron supply layer 213, Ni (upper layer) / Au (lower layer), for example, is deposited on the AlGaN electron supply layer 213 as a metal film for a gate electrode, and lift-off is performed. As a result, the gate electrode 202 that is Schottky-bonded to the AlGaN electron supply layer 213 is formed. Then, a SiN film 221 (film thickness 50 nm) is formed by a plasma CVD method or the like. With the above procedure, the HJFET 200 shown in FIG. 28 is obtained.
U. K. Misra, P.M. Parikh, and Yi-Feng Wu, “AlGaN / GaN HEMTs—Overview of device operation and applications.” Proc. IEEE, vol. 90, no. 6, pp. 1022-1031, 2002 2001 International Electron Device Meeting Digest (IEDM01-381-384), Ando (Y. Ando)

  However, the present inventors have examined the HJFET obtained by the above-described manufacturing method. As a result, even when a surface protective film is provided, the characteristics of the obtained transistor vary, and a sufficient drain current can be obtained. It became clear that there might not be.

The inventor presumed the cause as follows.
First, a sufficient drain current does not flow because impurities introduced into the interface between the AlGaN electron supply layer 213 and the SiN film 221 during the manufacturing process form interface states and carriers are trapped. Inferred. When interface states are formed by impurities, current collapse occurs, which causes a decrease in drain current.

Here, the current collapse has a trade-off relationship with the gate breakdown voltage. The negative polarization charge generated on the AlGaN surface has a great influence on the transistor characteristics depending on the electrical properties of the protective film (passivation film) deposited thereon. In general, when a large negative fixed charge is present on the surface, a high gate breakdown voltage can be obtained, but a current collapse during AC operation tends to increase. On the other hand, when the negative charge amount on the surface is small, the gate breakdown voltage is low, but the current collapse is small. The operation of the transistor is generally governed by this trade-off relationship. However, in the AlGaN (upper layer) / GaN (lower layer) heterostructure, for example, a negative charge of the order of 1E13 atoms / cm ² is generated on the surface. The trade-off relationship described above appears very remarkably. It is not uncommon for the withstand voltage value to change by an order of magnitude or more depending on the state of surface passivation. Such a large change is a phenomenon that cannot be seen in GaAs transistors. Conversely, III-nitride semiconductor transistors are devices that are extremely sensitive to the surface state, and in order to stably obtain high performance in terms of electrical characteristics at a high yield, careful attention must be paid to the control of the surface state. I need to pay.

  Second, the variation in transistor characteristics that still occurs even when the SiN film 221 is provided includes, for example, a variation in efficiency during the operation of the transistor. As a result of the examination by the present inventor, it has been inferred that variations in the gate leakage current of the HJFET 200 are caused by variations in the Schottky characteristics of the gate electrode 202 as a cause of variations in the operation efficiency of the transistors. Therefore, when the cause of the variation in the Schottky characteristics of the HJFET 200 was further examined, it was found that impurities introduced into the interface between the AlGaN electron supply layer 213 and the SiN film 221 also affect the Schottky characteristics. It was issued. Hereinafter, this point will be described.

  During the production of the conventional HJFET 200, the surface of the AlGaN electron supply layer 213 is exposed. For this reason, a photoresist is formed on the surface of the AlGaN electron supply layer 213 in the manufacturing process. Further, when removing the resist, it is exposed several times to plasma damage by plasma ashing. Further, high-temperature annealing is performed at the time of forming the ohmic electrode while the surface of the AlGaN electron supply layer 213 is exposed.

When the concentration of impurities such as oxygen at the interface between the surface of the group III nitride semiconductor layer 213 of the HJFET 200 and the gate electrode 202 obtained through such a manufacturing process was measured by SIMS (secondary ion mass spectrometry), 1E18 atoms was obtained. / Cm ^{3 to} 1E19 atoms / cm ³ . As described above, the impurity concentration is increased because the surface of the AlGaN electron supply layer 213 is more easily oxidized by being subjected to plasma damage during the electrode forming process described above or being exposed to the atmosphere after high-temperature annealing. It is thought that it is to become. In order to clean the surface of the AlGaN electron supply layer 213, etching with an acid or the like is effective. However, after forming an ohmic electrode or the like, the etching solution may wrap around even if it is covered with a resist. The metal is attacked and ohmic deterioration occurs. For this reason, it is difficult to sufficiently clean the surface state by etching after electrode formation.

Thus, in the HJFET 200, the surface state of the AlGaN electron supply layer is easily affected by the process. For this reason, the surface of the AlGaN electron supply layer 213 is subjected to a change in the crystallinity of the semiconductor and is in a state different from the initial clean state. Examples of such states are:
(I) a state in which the semiconductor crystal has changed due to plasma damage or high-temperature annealing, and (ii) a state in which oxygen is mixed into the surface of the AlGaN electron supply layer by exposure to the atmosphere.

Next, the measurement result of the Schottky characteristic of the obtained HJFET 200 will be described. FIG. 25A and FIG. 25B are diagrams for comparing the characteristics of the HJFET 200 (FIG. 28) obtained by the conventional manufacturing method and the HJFET 100 (FIG. 1) of an example described later. Here, Schottky barrier height φ _B (eV) (FIG. 25 (a)) and idealization factor n (FIG. 25 (b)) are shown for HJFETs obtained with ten 3-inch wafers. The idealization factor n is an index indicating the degree of deviation from the Schottky barrier height φ _B when ideally Schottky junction is performed, and when n = 1 is ideally Schottky junction. Correspondingly, the closer the n value is to 1, the better the Schottky property. From FIG. 25, in the HJFET200 obtained by the conventional manufacturing method, compared phi _B is dropped to an ideal Schottky junction, also, n is deviated from 1.

From the above examination, it can be seen that in an actual device, crystal defects and the like exist on the surface, so that the n value deviates from the ideal value n = 1, and as a result, the apparent φ _B decreases. This causes an increase in gate leakage current during AC operation, which hinders stable operation of the element. In addition, when there is some distribution of crystal defects, the Schottky characteristics vary accordingly, degrading the reproducibility of element characteristics. Therefore, in order to improve the stable operation of the element and the reproducibility of the characteristics, the n value is brought close to 1 and the crystal state is made uniform, that is, the crystallinity of the semiconductor surface forming the gate electrode is increased. It is important to control.

  The present inventor has made studies from this point of view, and by providing a surface protection film on the group III nitride semiconductor transistor and improving the cleanliness of the semiconductor surface, a transistor with less current collapse and excellent Schottky characteristics is obtained. I found out that it could be realized. The present invention has been made based on such novel findings.

According to the present invention,
A group III nitride semiconductor layer structure including a heterojunction;
A source electrode and a drain electrode formed separately on the group III nitride semiconductor layer structure;
A gate electrode disposed between the source electrode and the drain electrode;
With
In the region between the gate electrode and the drain electrode, an insulating film is provided on the group III nitride semiconductor layer structure,
A field effect transistor is provided, wherein an impurity concentration in the group III nitride semiconductor layer structure at an interface between the insulating film and the group III nitride semiconductor layer structure is 1E17 atoms / cm ³ or less.

In the field effect transistor of the present invention, in the region between the gate electrode and the drain electrode, the interface between the insulating film provided on the group III nitride semiconductor layer structure having a heterointerface and the group III nitride semiconductor layer structure The impurity concentration in is 1E17 atoms / cm ³ or less. For this reason, in the transistor of the present invention, the formation of interface states due to impurities in the group III nitride semiconductor layer structure is suppressed, and current collapse is effectively suppressed. The transistor of the present invention has excellent Schottky characteristics. It is presumed that the crystallinity of the group III nitride semiconductor layer structure is improved as the reason why the Schottky characteristics are excellent by setting the impurity concentration of the interface to 1E17 atoms / cm ³ or less. In addition, the transistor of the present invention is excellent in operational stability and has a structure that can be stably manufactured with high yield.

  In the present invention, the impurity concentration can be measured, for example, by SIMS (secondary ion mass spectrometry).

  In the present invention, from the viewpoint of suppressing current collapse, the insulating film can be, for example, an insulating film containing nitrogen, preferably a SiN film made of silicon and nitrogen.

Moreover, according to the present invention,
A method for producing the field effect transistor, comprising:
Forming a group III nitride semiconductor layer structure including a heterojunction in the deposition chamber;
Forming the insulating film on the group III nitride semiconductor layer structure;
A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming the gate electrode on the group III nitride semiconductor layer structure so as to embed the opening;
A method of manufacturing a field effect transistor is provided.

  According to the method of the present invention, the insulating film is formed before forming the gate electrode. In the conventional method, as described above with reference to FIG. 28 in the section of the background art, the surface protective film is formed after the gate electrode is formed. In the process, a photoresist is not formed on the surface of the group III nitride semiconductor layer, and the surface is not affected by plasma. Therefore, according to the manufacturing method of the present invention, it is possible to suppress oxidation of the nitride semiconductor surface due to aging. Therefore, a field effect transistor having a clean interface between the insulating film and the group III nitride semiconductor layer structure can be stably manufactured. Therefore, according to the present invention, current collapse due to oxidation of the group III nitride semiconductor layer can be suppressed. In addition, a field effect transistor with excellent uniformity of the Schottky interface can be stably manufactured. In addition, the crystal state of the surface of the group III nitride semiconductor layer in the region between the gate electrode and the drain electrode can be made favorable. In addition, the uniformity of the crystalline state can be improved.

Moreover, according to the present invention,
Forming a group III nitride semiconductor layer structure including a heterojunction in the deposition chamber;
Forming an insulating film on the group III nitride semiconductor layer structure;
A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode on the group III nitride semiconductor layer structure so as to embed the opening;
Including
A step of forming the insulating film without removing the group III nitride semiconductor layer structure from the film formation chamber after the step of forming the group III nitride semiconductor layer structure. A manufacturing method is provided.

Moreover, according to the present invention,
Forming a group III nitride semiconductor layer structure including a heterojunction in the deposition chamber;
Forming an insulating film on the group III nitride semiconductor layer structure;
A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode on the group III nitride semiconductor layer structure so as to embed the opening;
After the step of forming the group III nitride semiconductor layer structure, before the step of forming the insulating film,
Cleaning the surface of the group III nitride semiconductor layer structure by wet etching using an acid;
A method of manufacturing a field effect transistor is provided.

  In the manufacturing method of the present invention, the insulating film is formed in a state where the surface of the group III nitride semiconductor layer structure is clean. In the conventional manufacturing method in which an insulating film is formed on a group III nitride semiconductor layer structure in order to suppress current collapse, the insulating film is usually formed after electrode formation. The interface order has been formed by impurities on the surface of the semiconductor layer structure. On the other hand, according to the manufacturing method of the present invention, a field effect transistor having a clean interface can be obtained by devising a process of forming an insulating film on the group III nitride semiconductor layer structure. Therefore, current collapse caused by interface oxidation is suppressed, and a field effect transistor having excellent Schottky characteristics can be stably manufactured.

  In the present invention, after the step of forming the insulating film, a predetermined region of the insulating film is selectively removed by etching so that the removed region is embedded on the group III nitride semiconductor layer structure. The source electrode and the drain electrode may be formed separately from each other. At this time, either the step of forming the source electrode and the drain electrode or the step of forming the gate electrode may be performed first.

  As described above, according to the present invention, a group III nitride semiconductor field effect transistor that is excellent in operational stability and can be manufactured with high yield is realized.

  The above-described object and other objects, features, and advantages will become more apparent from the preferred embodiments described below and the accompanying drawings.

It is sectional drawing which shows the structure of the field effect transistor which concerns on an Example. It is sectional drawing which shows the structure of the field effect transistor which concerns on an Example. It is sectional drawing which shows the structure of the field effect transistor which concerns on an Example. It is sectional drawing which shows the structure of the field effect transistor which concerns on an Example. It is sectional drawing which shows the structure of the field effect transistor which concerns on an Example. It is sectional drawing which shows the structure of the field effect transistor which concerns on an Example. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 2. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 2. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 2. FIG. 3 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 2. It is sectional drawing which shows the manufacturing process of the field effect transistor of FIG. It is sectional drawing which shows the manufacturing process of the field effect transistor of FIG. It is sectional drawing which shows the manufacturing process of the field effect transistor of FIG. It is sectional drawing which shows the manufacturing process of the field effect transistor of FIG. FIG. 5 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 4. FIG. 5 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 4. FIG. 5 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 4. FIG. 6 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 5. FIG. 6 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 5. FIG. 6 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 5. FIG. 6 is a cross-sectional view showing a manufacturing process of the field effect transistor of FIG. 5. It is a figure which compares the manufacturing method of an Example and the conventional field effect transistor. It is a figure which compares the manufacturing method of an Example and the conventional field effect transistor. It is sectional drawing which shows the structure of the field effect transistor which concerns on an Example. It is sectional drawing which shows the structure of the conventional field effect transistor.

  Hereinafter, an HJFET having an AlGaN electron supply layer / GaN channel layer and a surface protective film (hereinafter also simply referred to as “protective film”) as an example of a group III nitride semiconductor structure will be described with reference to the drawings for embodiments of the present invention. To explain. In all the drawings, common constituent elements are denoted by the same reference numerals, and description thereof is omitted as appropriate. Further, in this specification, the laminated structure is expressed as “upper layer / lower layer (substrate side)”.

  FIG. 1 is a diagram showing a basic configuration of the field effect transistor of the present embodiment. This field effect transistor (HJFET 100) is formed on a group III nitride semiconductor layer structure (GaN channel layer 112, AlGaN electron supply layer 113) including a heterojunction and spaced apart on these group III nitride semiconductor layer structures. Source electrode 101 and drain electrode 103, and gate electrode 102 disposed between source electrode 101 and drain electrode 103. Since the HJFET 100 has a heterojunction structure, it is possible to use a high-concentration two-dimensional carrier gas generated in the heterojunction from spontaneous polarization and piezoelectric polarization.

The group III nitride semiconductor layer structure includes a channel layer made of In _x Ga _1-x N (0 ≦ x ≦ 1) and an electron supply layer made of Al _y Ga _1-y N (0 ≦ y ≦ 1). The hetero interface is an interface between In _x Ga _1-x N and Al _y Ga _1-y N. However, in the above formula, it is necessary to prevent x and y from simultaneously becoming zero.

  The HJFET 100 has an insulating film (SiN film 121) as a protective film on the laminated structure of the GaN channel layer 112 and the AlGaN electron supply layer 113 in the region between the gate electrode 102 and the drain electrode 103.

  The protective film is made of an insulating material like the SiN film 121. The SiN film 121 may be provided over the entire region between the gate electrode 102 and the drain electrode 103 or may be provided in a part of the region. By configuring the entire region between the gate electrode 102 and the drain electrode 103 to be covered with the SiN film 121, current collapse can be more effectively suppressed.

  The SiN film 121 is an insulating film containing nitrogen as at least one of the elements constituting the laminated structure of the GaN channel layer 112 and the AlGaN electron supply layer 113. When an element in the protective film moves to the interface between the AlGaN electron supply layer 113 and the protective film, there is a concern that a level is formed as an impurity at the interface, but nitrogen in the SiN film 121 constitutes the AlGaN electron supply layer 113. Since it is common to N, it does not become an impurity with respect to the AlGaN electron supply layer 113, and an interface state can be prevented from being formed. For this reason, generation | occurrence | production of an electric current collapse can be suppressed further effectively. Further, by using the SiN film 121 as the protective film, a material common to the AlGaN electron supply layer 113 can be used.

  In addition, when SiN is grown on the AlGaN epitaxial layer which is the AlGaN electron supply layer 113, SiN is so-called so as to reflect the crystallinity of the underlying layer so as to lattice match with the underlying AlGaN in the initial stage of growth according to the growth conditions. Epitaxial growth. At this time, the SiN film 121 is a film including an epitaxially grown region on the laminated structure of the GaN channel layer 112 and the AlGaN electron supply layer 113. By forming a film including an epitaxially grown region, the group III nitride semiconductor layer structure and the SiN film 121 can be manufactured in a continuous process. In addition, the stability of the film quality of the obtained SiN film 121 can be improved.

  The SiN film 121 is a film that substantially does not contain oxygen as a constituent element. Since oxygen tends to form a level in a group III nitride semiconductor, generation of current collapse can be more reliably suppressed by employing a structure that does not substantially contain oxygen. Note that “substantially free of oxygen” means that no oxygen is intentionally contained in the film, and if the generation of current collapse due to the formation of oxygen impurity levels can be suppressed, non- Intentionally included oxygen may be present. Moreover, it is preferable that oxygen concentration is below the detection limit in SIMS.

  The thickness of the SiN film 121 is, for example, not less than 5 nm and not more than 200 nm, more specifically, not less than 5 nm and not more than 100 nm. By setting the thickness to 5 nm or more, current collapse at the interface can be more reliably suppressed. The thickness of the SiN film 121 is, for example, 200 nm or less, preferably 150 nm or less, and more preferably 100 nm or less. By doing so, current collapse can be suppressed and gate breakdown voltage can be improved, and the trade-off between the two can be more effectively solved.

The SiN film 121 is a film grown on the surface of the clean AlGaN electron supply layer 113. In the HJFET 100, the impurity concentration at the interface between the SiN film 121 and the laminated structure of the GaN channel layer 112 and the AlGaN electron supply layer 113 is 1E17 atoms / cm ³ or less, preferably 1E15 atoms / cm ³ or less. By so doing, interface state formation in the AlGaN electron supply layer 113 can be suppressed, and the occurrence of current collapse can be suppressed. In addition, Schottky characteristics can be improved. In this specification, the impurity concentration is the total concentration of carbon and oxygen contained in the interface. In this embodiment and the following examples, the impurity concentration can be measured, for example, by SIMS (secondary ion mass spectrometry).

However, it is difficult to obtain the HJFET 100 that satisfies the interface impurity concentration by the above-described conventional method. In the present embodiment, the SiN film 121 is used as a surface protective film that effectively suppresses the occurrence of current collapse, and the SiN film 121 is formed while the surface of the AlGaN electron supply layer 113 is clean. An HJFET 100 having an impurity concentration can be obtained. As a method for forming the SiN film 121 in a state where the surface of the AlGaN electron supply layer 113 is clean, for example,
(I) a method of forming the SiN film 121 in the same film formation chamber without exposure to the air after the formation of the AlGaN electron supply layer 113;
(Ii) a method of forming the SiN film 121 after etching the surface of the AlGaN electron supply layer 113 with an acid or the like;
Is mentioned. When an HJFET was manufactured by these methods, an HJFET having an impurity concentration of 1E15 atoms / cm ³ or less at the interface between the surface of the AlGaN electron supply layer 113, the SiN film 121, and the gate electrode 102 was obtained by the method (i). In the method (ii), an HJFET having an impurity concentration of 1E17 atoms / cm ³ or less at the interface between the surface of the AlGaN electron supply layer 113 and the SiN film 121 and the gate electrode 102 was obtained. Note that these methods will be described in more detail in examples described later.

  Further, according to the above method, since the SiN film 121 is formed after the AlGaN electron supply layer 113 is formed and before the electrode is formed, the source electrode 101 and the drain electrode 103 are mounted on the SiN film 121. Yes. As a result, electric field concentration at the gate electrode side end of the drain electrode 103 during high voltage operation is alleviated, and an effect of improving the gate breakdown voltage is obtained.

(Example)
Hereinafter, examples of the present invention will be described with reference to the drawings, taking as an example the case where c-plane SiC is used as a growth substrate for a group III nitride semiconductor layer. In all the drawings, common constituent elements are given the same reference numerals, and common descriptions in the following description are omitted as appropriate.

Example 1
This example relates to an HJFET having the configuration shown in FIG. In this embodiment, the HJFET 100 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an AlGaN electron supply layer 113 is formed. On this AlGaN electron supply layer 113, the source electrode 101 and the drain electrode 103 are in ohmic contact, and the surface of the AlGaN electron supply layer 113 is covered with the SiN film 121.

7-9 is a figure which shows the manufacturing method of HJFET100 of a present Example.
This manufacturing method includes the following steps.
Step 101: A step of forming a group III nitride semiconductor layer structure (a laminated structure of an AlGaN electron supply layer 113 and a GaN channel layer 112) including a heterojunction, specifically, a GaN channel on the substrate 110 by an epitaxial growth method. Sequentially forming the layer 112 and the AlGaN electron supply layer 113;
Step 103: forming a protective film (SiN film 121) in a state where the surface of the AlGaN electron supply layer 113 is clean,
Step 105: A predetermined region of the SiN film 121 is selectively removed by etching to form an opening, and a gate is formed so as to bury the opening on the laminated structure of the AlGaN electron supply layer 113 and the GaN channel layer 112. After the step of forming the electrode 102 and the step 107: the step of forming the SiN film 121, a predetermined region of the SiN film 121 is selectively removed by etching, and the removed region is formed on the AlGaN electron supply layer 113. A step of forming the source electrode 101 and the drain electrode 103 apart from each other so as to be embedded.

  Note that, here, the case where the source electrode 101 and the drain electrode 103 are formed in Step 107 after the gate electrode 102 is formed in Step 105 is illustrated, but the gate electrode 102, the source electrode 101, and the drain electrode 103 are illustrated. If the procedure is such that the SiN film 121 is formed before forming, either step 105 or step 107 may be performed first. For example, in consideration of the type of metal used for each electrode, it can be determined from which step.

  The SiN film 121 in step 103 is formed at least between the formation region of the gate electrode 102 and the formation region of the drain electrode 103.

  In this embodiment, in step 101, after the group III nitride semiconductor layer structure is formed by the epitaxial growth method, the step 103 in which the SiN film 121 is subsequently formed in a clean atmosphere without taking out from the deposition chamber is performed. ing. Specifically, the clean atmosphere is an atmosphere that does not substantially contain oxygen. In this way, the surface of the AlGaN electron supply layer 113 is not exposed to the air in the middle, so that the impurity concentration at the interface between the AlGaN electron supply layer 113 and the SiN film 121 can be further effectively reduced and the current collapse can be achieved. Can be more effectively suppressed.

  Note that in this specification, the deposition chamber may be formed of a single chamber or may include a plurality of small chambers. In the case of using a film formation chamber including a plurality of small chambers, after forming one AlGaN electron supply layer 113, the substrate 110 is transferred to another small chamber without exposure to the atmosphere by releasing the vacuum, and the SiN film 121 is formed. May be. Since exposure to the atmosphere by releasing the vacuum is not performed, surface contamination of the AlGaN electron supply layer 113 can be effectively suppressed.

Hereinafter, the manufacturing process of the HJFET 100 will be described more specifically.
First, as shown in FIG. 7A, a semiconductor is grown on a substrate 110 made of SiC using an epitaxial growth method, and a buffer layer 111 (thickness 20 nm) made of undoped AlN is sequentially formed from the substrate 110 side. Then, a semiconductor layer structure is obtained in which an undoped GaN channel layer 112 (film thickness 2 μm) and an AlGaN electron supply layer 113 (film thickness 25 nm) made of undoped AlGaN are stacked (FIG. 7A). As the epitaxial growth method, for example, a molecular beam epitaxy (MBE) growth method or a metal organic vapor phase epitaxy (MOVPE) growth method is used.

  Then, a SiN film 121 (film thickness 60 nm) is formed on the AlGaN electron supply layer 113 (FIG. 7B). At this time, after the AlGaN electron supply layer 113 is formed, the SiN film 121 is formed in the same film forming apparatus without being exposed to the atmosphere. The SiN film 121 is formed by the same growth method as the growth method of the AlGaN electron supply layer 113 and the GaN channel layer 112.

  Subsequently, a part of the SiN film 121 is etched away until the GaN channel layer 112 is exposed, thereby forming an element isolation mesa (not shown). Then, a photoresist is formed in a predetermined region on the surface of the SiN film 121, and the exposed portion of the SiN film 121 is selectively removed by etching to expose the AlGaN electron supply layer 113 (FIG. 8C).

  Then, a source electrode 101 and a drain electrode 103 are formed on the AlGaN electron supply layer 113 by evaporating a metal such as Ti / Al (FIG. 8D), and annealing is performed at 650 ° C. Ohmic bonding is performed with the AlGaN electron supply layer 113.

  Next, a photoresist is formed in a predetermined region on the surface of the SiN film 121, and the exposed portion of the SiN film 121 is selectively etched away to provide an opening for exposing the AlGaN electron supply layer 113 (FIG. 9E). ). On the exposed AlGaN electron supply layer 113, for example, a gate metal of Ni / Au is vapor-deposited to form the Schottky contact gate electrode 102 (FIG. 9F). With the above procedure, the HJFET 100 shown in FIG. 1 is obtained.

  25 and 26 are diagrams for comparing the manufacturing method of the present embodiment and the conventional manufacturing method.

First, FIG. 25A and FIG. 25B are respectively obtained with 10 3-inch wafers in the above-described method of manufacturing the HJFET 100 of this embodiment and the method of manufacturing the conventional HJFET 200 (FIG. 28). It is a figure which shows Schottky barrier height (phi) _B and idealization factor n in the obtained HJFET.

  As can be seen from FIGS. 25 (a) and 25 (b), the HJFET 100 of this example provides excellent Schottky properties close to an ideal Schottky junction, and further suppresses variations between wafers. It can be seen that the uniformity is improved. This is presumably because the surface of the AlGaN electron supply layer 113 in the region where the gate electrode 102 is formed is not exposed to the atmosphere or plasma until the gate electrode 102 is formed, and the surface of the AlGaN electron supply layer 113 is not contaminated.

  FIG. 26 is a diagram showing the amount of current collapse when the device is prototyped on ten 3-inch wafers in the manufacturing method of this example and the conventional manufacturing method.

  In the field effect transistor 200 obtained by the conventional manufacturing method shown in FIG. 26, the surface of the AlGaN electron supply layer 213 provided between the gate electrode 202 and the drain electrode 203 undergoes various processes. It is difficult to control the negative charge, and even when a protective film is formed by the SiN film 221 and current collapse is suppressed, the degree of reduction of current collapse varies.

  In contrast, in the HJFET 100 of this example, it can be seen that the amount of current collapse is small and the variation thereof is small. In this embodiment, after the AlGaN electron supply layer 113 is formed using the same growth apparatus as the semiconductor layer, the SiN film 121 is continuously grown without being exposed to the atmosphere or plasma. Therefore, the SiN film 121 is formed before the gate electrode 102 is formed, and the interface between the semiconductor and the SiN film 121 is not damaged by the process, and a uniform and high-quality interface is formed. As described above, particularly in the group III nitride semiconductor device in which the influence of the negative surface charge is a serious problem as in the present invention, the current collapse is reduced and the uniformity of characteristics is improved due to this uniform interface formation and low interface impurity concentration. The effect of is remarkable.

Further, in the obtained HJFET, when the oxygen concentration in the AlGaN electron supply layer at the interface between the SiN film and the AlGaN electron supply layer was analyzed, it was 1E15 atoms / cm ³ or less in the case of the HJFET 100 of this example. When the thickness of the SiN film 121 is about 5 to 200 nm, the AlGaN electron supply layer 113 and the SiN film 121 having such an impurity concentration at the interface could be formed.

On the other hand, in the HJFET 200 shown in FIG. 28, after forming the electrode, the SiN film 221 is formed by plasma CVD, so that the oxygen concentration in the AlGaN electron supply layer 213 at the interface between the AlGaN electron supply layer 213 and the SiN film 221 is obtained. Was about 1E19 atoms / cm ³ .

Further, in the manufacturing process of the HJFET 100, when the AlGaN electron supply layer 113 is formed by the epitaxial growth method and then exposed to the atmosphere before the SiN film 121 is formed, the AlGaN at the interface between the SiN film 121 and the AlGaN electron supply layer 113 is used. The oxygen concentration in the electron supply layer 113 was about 1E19 atoms / cm ³ .

As described above, in the HJFET 100 of this example, after the AlGaN electron supply layer 113 is formed, the SiN film 121 is formed in the same film formation chamber without being exposed to the atmosphere. Collapse is suppressed, and it has a high output and excellent reliability. Further, the HJFET 100 has a configuration that can stably manufacture a structure as designed with a high yield because variations between wafers are suppressed. When an HJFET was manufactured by the method of this example, a transistor having an impurity concentration at the interface between the AlGaN electron supply layer 113 and the SiN film 121, in this case, an oxygen concentration of 1E15 atoms / cm ³ or less was obtained.

  In this embodiment, since the SiN film 121 functioning as a protective film contains nitrogen, which is a constituent element of the AlGaN electron supply layer 113, which is a group III nitride semiconductor layer, exposure to the atmosphere is performed after the formation of the AlGaN electron supply layer 113. The SiN film 121 can be formed in a continuous process without performing the above process. In addition, the stability of the quality of the obtained SiN film 121 can be improved.

  Further, in this embodiment, since the source electrode 101 and the gate electrode 102 are mounted on the SiN film 121 that is a protective film, the end portion of the drain electrode 103 on the gate electrode side during high voltage operation. The electric field concentration at can be reduced. Therefore, the gate breakdown voltage is improved.

(Example 2)
FIG. 2 is a cross-sectional view showing the configuration of the HJFET of this example. The basic configuration of the HJFET 130 shown in FIG. 2 is the same as that of the HJFET 100 (FIG. 1) of the first embodiment, on which the buffer layer 111, the GaN channel layer 112, the AlGaN electron supply layer 113, and the SiN film 121 are formed from the substrate 110 side. The source electrode 101, the drain electrode 103, and the gate electrode 102 are stacked in this order and the AlGaN electron supply layer 113 is provided, but the cleanliness of the interface between the AlGaN electron supply layer 113 and the SiN film 121 is maintained. The method is different from Example 1.

Such an HJFET 130 is manufactured by the following procedure.
10 to 13 are diagrams showing a method for manufacturing the HJFET in this example. In Example 1, after the step of forming the group III nitride semiconductor layer structure, the SiN film was formed without being exposed to the contaminated atmosphere (for example, air). However, the manufacturing method of this example is based on the group III nitride semiconductor. This is a case where the group III nitride semiconductor layer structure is exposed to a contaminated atmosphere after the step of forming the layer structure. In this embodiment, before the step of forming the SiN film 121 in order to remove impurities that form interface states on the surface of the group III nitride semiconductor layer structure,
Step 109: cleaning the surface of the group III nitride semiconductor layer structure by wet etching using an acid,
Is included.

  First, a semiconductor is grown on a substrate 110 made of SiC by, for example, a molecular beam epitaxy (MBE) growth method or a metal organic vapor phase epitaxy (MOVPE) growth method. Thus, in order from the substrate 110 side, the buffer layer 111 (thickness 20 nm) made of undoped AlN, the undoped GaN channel layer 112 (thickness 2 μm), and the AlGaN electron supply layer 113 (thickness 25 nm) made of undoped AlGaN. A semiconductor layer structure in which is stacked is obtained (FIG. 10A).

  Next, when the surface of the AlGaN electron supply layer 113 is contaminated by the atmosphere or the like, the surface of the semiconductor layer is cleaned by wet etching on the AlGaN electron supply layer 113 with an acid or the like (FIG. 10B), and then cleaned. A SiN film 121 (60 nm) is formed by a plasma CVD method or the like in an atmosphere (FIG. 11C). Specifically, hydrofluoric acid or hydrochloric acid is used as the acid. For example, etching is performed at room temperature for about 30 seconds to 1 minute, followed by washing with water and drying.

Even when the AlGaN electron supply layer 113 is exposed to the atmosphere or the like by the cleaning process in FIG. 10B, the surface is cleaned, and in the completed HJFET 130, the AlGaN electron supply layer 113, the SiN film 121, The impurity concentration at the interface can be 1E17 atoms / cm ³ or less.

  Subsequently, part of the SiN film 121 and part of the epitaxial layer structure are removed by etching until the GaN channel layer 112 is exposed, thereby forming an element isolation mesa (not shown). Then, a photoresist is formed in a predetermined region on the surface of the SiN film 121, and the exposed portion of the SiN film 121 is selectively etched away to expose the AlGaN electron supply layer 113 (FIG. 11D), thereby exposing the exposed AlGaN. A source electrode 101 and a drain electrode 103 are formed on the electron supply layer 113 by evaporating a metal such as Ti / Al, for example (FIG. 12E). Then, annealing is performed at 650 ° C. to form ohmic contact with the AlGaN electron supply layer 113. A photoresist is formed in a predetermined region on the surface of the SiN film 121, and the exposed portion of the SiN film 121 is selectively etched away to provide an exposed portion of the AlGaN electron supply layer 113 (FIG. 12F). For example, a Ni / Au gate metal is deposited on the exposed AlGaN electron supply layer 113 to form the Schottky contact gate electrode 102 (FIG. 13). Thus, the HJFET 130 shown in FIG. 2 is obtained.

  In this embodiment, before the electrode structure is formed, the semiconductor surface is cleaned by etching with an acid or the like (FIG. 10B). In addition, it can also be made to terminate so that the oxidation of the surface after that may be suppressed by the cleaning process by an acid. In addition, even if the AlGaN electron supply layer 113 is slightly contaminated after the surface of the AlGaN electron supply layer 113 is etched with acid or the like and before the SiN film 121 is formed, the SiN plasma CVD method is used. When the film 121 is formed, contaminants can be removed by plasma irradiation.

  As described above, in this example, since the SiN film 121 is formed on the cleaned surface of the AlGaN electron supply layer 113, the current collapse in the group III nitride semiconductor device in which the influence of the negative surface charge is a serious problem is generated. It is suppressed.

In the present embodiment, the AlGaN electron supply layer 113 once exposed to the atmosphere before the formation of the gate electrode 102 is contaminated by the atmosphere or the like by etching. Further, since the SiN film 121 is formed on the AlGaN electron supply layer 113 when the gate electrode 102 and the drain electrode 103 are formed, the surface of the AlGaN electron supply layer 113 is not exposed to plasma when forming the electrodes. Therefore, a photoresist is not formed on the AlGaN electron supply layer 113 in the subsequent manufacturing process, and the gate electrode 102 having an ideally close Schottky property can be obtained without the AlGaN electron supply layer 113 being attacked by plasma. In addition, since the cleaning process is performed, the crystal state of the surface of the AlGaN electron supply layer 113 in the region between the gate electrode 102 and the drain electrode 103 is good and uniform, and the surface state can be stabilized. . For this reason, while having the outstanding Schottky property, it can be set as the structure which can be manufactured stably with a high yield. When an HJFET was manufactured by the method of this example, a transistor having an impurity concentration at the interface between the AlGaN electron supply layer 113 and the SiN film 121, here an oxygen concentration of 1E17 atoms / cm ³ or less, was obtained.

  Also in this embodiment, since the source electrode 101 and the gate electrode 102 are on the SiN film 121 as in the case of the first embodiment, the gate electrode side of the drain electrode during high voltage operation is provided. It is possible to fabricate an element having an improved gate breakdown voltage due to relaxation of electric field concentration at the edge.

(Example 3)
FIG. 3 is a diagram showing a cross-sectional structure of the HJFET of this example.
The basic configuration of the HJFET 132 shown in FIG. 3 is the same as that of the HJFET of Example 1 or Example 2, but a protective film is laminated on the first insulating film (SiN film 121) and the SiN film 121. The second insulating film (SiO ₂ film 122) is different in that it is configured. Here, the SiO ₂ film 122 is provided in direct contact with the SiN film 121, but another insulating film is provided as an intervening layer between the first insulating film and the second insulating film. Also good.

More specifically, the HJFET 132 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an AlGaN electron supply layer 113 is formed. The source electrode 101 and the drain electrode 103 are ohmic-bonded on the AlGaN electron supply layer 113, the surface of the AlGaN electron supply layer 113 is covered with the SiN film 121, and the SiN film 121 is further composed of the SiO ₂ film 122. Covered with.

14 to 17 are views showing a method of manufacturing the HJFET shown in FIG.
First, a semiconductor is grown on a substrate 110 made of SiC by, for example, an MBE growth method or a metal organic vapor phase epitaxy MOVPE growth method. Thus, in order from the substrate 110 side, the buffer layer 111 (thickness 20 nm) made of undoped AlN, the undoped GaN channel layer 112 (thickness 2 μm), and the AlGaN electron supply layer 113 (thickness 25 nm) made of undoped AlGaN. A semiconductor layer structure in which is stacked is obtained (FIG. 14A).

  Next, similarly to Example 1, a SiN film 121 (60 nm) is formed on the AlGaN electron supply layer 113 by plasma CVD or the like without performing exposure to the atmosphere (FIG. 14B). When the AlGaN electron supply layer 113 is exposed to the atmosphere, the SiN film 121 is formed after the surface of the semiconductor layer is cleaned by etching with an acid or the like, as in the second embodiment.

Then, an SiO ₂ film 122 (100 nm) is formed on the SiN film 121 by an atmospheric pressure CVD method or the like (FIG. 15C).

Thereafter, a part of the SiN film 121 and the SiO ₂ film 122 and a part of the epitaxial layer structure are removed by etching until the GaN channel layer 112 is exposed, thereby forming an element isolation mesa (not shown). Then, a photoresist is formed in a predetermined region on the surface of the SiO ₂ film 122, and the predetermined regions of the SiN film 121 and the SiO ₂ film 122 are selectively etched away until the AlGaN electron supply layer 113 is exposed (FIG. 15 ( d)), for example, Ti / Al metal is deposited on the AlGaN electron supply layer 113 to form the source electrode 101 and the drain electrode 103 (FIG. 16 (e)), and annealing is performed at 650 ° C. to obtain ohmic resistance. Forming a sexual bond.

Subsequently, a photoresist is formed in a predetermined region on the surface of the SiO ₂ film 122, and the predetermined region of the SiN film 121 and the SiO ₂ film 122 is selectively removed by etching, thereby exposing the opening exposed in the AlGaN electron supply layer 113. A portion is provided (FIG. 16F). For example, a gate metal of Ni / Au is vapor-deposited on the exposed AlGaN electron supply layer 113 to form a gate electrode 102 having a Schottky junction (FIG. 17). Thus, the HJFET 132 shown in FIG. 3 is obtained.

  Also in this embodiment, the AlGaN electron supply layer 113 and the SiN film 121 are not exposed to the atmosphere before the electrode structure is formed, or by adopting a method of cleaning the surface of the AlGaN electron supply layer 113 with an acid or the like. The interface with is kept clean. For this reason, the same effect as Example 1 or Example 2 is acquired.

Furthermore, in this embodiment, since the SiN film 121 formed on the surface of the group III nitride semiconductor layer is covered with the SiO ₂ film 122, the deterioration with time of the SiN film 121 can be further reliably suppressed. it can. Therefore, the lifetime of element characteristics can be extended.

The SiO ₂ film 122 may be formed using the same film forming apparatus as the SiN film 121 or may be formed using a different film forming apparatus. Further, the planar shape of the SiO ₂ film 122 may be the same as or different from the SiN film 121. In addition, in the region between the gate electrode 102 and the drain electrode 103, the field plate portion 105 may be formed via the SiN film 121 on the AlGaN electron supply layer 113. This configuration will be described later in Example 4 and Example 5.

(Example 4)
FIG. 4 is a cross-sectional view showing the configuration of the HJFET of this example.
The basic configuration of the HJFET 134 shown in FIG. 4 is the same as that of the HJFET 100 of the first embodiment. However, the field plate portion 105 in which the gate electrode 102 protrudes in a bowl shape on the drain electrode 103 side and is formed on the SiN film 121. Is different from HJFET 100 in that

  The HJFET 134 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an AlGaN electron supply layer 113 is formed. On the AlGaN electron supply layer 113, the source electrode 101 and the drain electrode 103 are ohmic-bonded. A gate electrode 102 is provided between these electrodes. The gate electrode 102 has a field plate portion 105 and is in Schottky junction with the AlGaN electron supply layer 113. The surface of the AlGaN electron supply layer 113 is covered with a SiN film 121.

  The length of the field plate portion 105 in the gate length direction is, for example, 0.3 μm or more, preferably 0.5 μm or more. By doing so, current collapse can be suppressed more reliably. Further, the field plate portion 105 is configured not to overlap the drain electrode 103, and the length of the field plate portion 105 in the gate length direction is preferably 70% or less of the interval between the gate electrode and the drain electrode. As the length of the extended portion of the field plate portion 105 is larger, the effect of suppressing the current collapse is higher. However, if the field plate portion 105 is too long, the gate breakdown voltage is increased due to electric field concentration between the field plate portion 105 and the drain electrode 103. Decreases. Note that the distance between the gate electrode 102 and the drain electrode 103 refers to the length from the drain electrode side end of the gate electrode 102 to the gate electrode side end of the drain electrode 103.

18 to 20 are views showing a method of manufacturing the HJFET of FIG.
First, a semiconductor is grown on the substrate 110 made of SiC by, for example, the MBE growth method or the MOCVD growth method. Thus, in order from the substrate 110 side, the buffer layer 111 (thickness 20 nm) made of undoped AlN, the undoped GaN channel layer 112 (thickness 2 μm), and the AlGaN electron supply layer 113 (thickness 25 nm) made of undoped AlGaN. A semiconductor layer structure in which is stacked is obtained (FIG. 18A).

  Next, as in Example 1, an SiN film 121 (60 nm) is formed on the AlGaN electron supply layer 113 without performing exposure to the atmosphere by plasma CVD or the like (FIG. 18B). When the AlGaN electron supply layer 113 is exposed to the atmosphere, the SiN film 121 is formed after the surface of the semiconductor layer is cleaned by etching with an acid or the like, as in the second embodiment.

  Subsequently, a part of the SiN film 121 and a part of the epitaxial layer structure are removed by etching until the GaN channel layer 112 is exposed, thereby forming an element isolation mesa (not shown). Then, a photoresist is formed in a predetermined region of the SiN film 121, and the exposed portion of the SiN film 121 is selectively removed by etching until the AlGaN electron supply layer 113 is exposed (FIG. 19C). A metal such as Ti / Al is deposited on the exposed AlGaN electron supply layer 113 to form the source electrode 101 and the drain electrode 103 (FIG. 19D), and annealing is performed at 650 ° C. These electrodes and the AlGaN electron supply layer 113 are joined in ohmic contact. A photoresist is formed in a predetermined region of the SiN film 121, and an exposed portion of the SiN film 121 is selectively removed by etching to provide an opening, thereby exposing the AlGaN electron supply layer 113 (FIG. 20E).

  Then, for example, Ni / Au is deposited on the exposed AlGaN electron supply layer 113 as a metal film to be the gate electrode 102 to form the Schottky contact gate electrode 102 (FIG. 20F). At the same time, a field plate portion 105 made of Ni / Au is formed integrally with the gate electrode 102. Thus, the HJFET 134 shown in FIG. 4 is obtained.

  In this embodiment, the gate electrode 102 and the field plate portion 105 are formed at the same time. However, these may be performed in separate steps. It is also possible to form a resist having an opening at a predetermined position on the SiN film 121 and form the field plate portion 105 so as to fill the opening. In this case, the gap between the gate electrode 102 and the field plate portion 105 can be formed with a narrower gap.

  Also in this embodiment, the AlGaN electron supply layer 113 and the SiN film 121 are not exposed to the atmosphere before the electrode structure is formed, or by adopting a method of cleaning the surface of the AlGaN electron supply layer 113 with an acid or the like. The interface with is kept clean. For this reason, the same effect as Example 1 or Example 2 is acquired.

  Further, the HJFET 134 has a field plate portion 105. Therefore, even when a high reverse voltage is applied between the gate electrode 102 and the drain electrode 103, the electric field applied to the drain electrode side end of the gate electrode 102 is alleviated by the action of the field plate portion 105. Therefore, the electric field concentration at the drain electrode side end of the gate electrode 102 can be further reliably suppressed, and the gate breakdown voltage can be improved. Furthermore, since the surface potential can be modulated by the field plate portion 105 during a large signal operation, there is an effect of increasing the response speed of the surface trap and suppressing current collapse. Therefore, according to the present invention, the balance of current collapse, gate breakdown voltage, and gain can be remarkably improved. Moreover, even when the surface state varies due to variations in the manufacturing process, such good performance can be stably realized.

  In the above description, the case where the field plate portion 105 that is formed of the same member as the gate electrode 102 and functions as an electric field control unit is described as an example. The electric field control electrode is provided independently of the gate electrode 102 through the SiN film 121 in the upper part of the group III nitride semiconductor layer structure in the region between the gate electrode 102 and the drain electrode 103 without being limited to the configuration. It can also be configured.

  FIG. 27 is a cross-sectional view showing the configuration of such an HJFET. In FIG. 27, in place of the gate electrode 102 having the field plate portion 105, a gate electrode 102 and an electric field control electrode 106 provided separately from the gate electrode 102 are provided.

  Note that the electric field control electrode 106 may be formed at the same time as the gate electrode 102 or may be formed in a separate process. In another process, a resist having an opening at a predetermined position is formed on the SiN film 121, and the electric field control electrode 106 can be formed so as to fill the opening. In this case, the gap between the gate electrode 102 and the electric field control electrode 106 can be formed with a narrower gap.

  In FIG. 27, the electric field control electrode 106 may be independently controllable with respect to the gate electrode 102, and different electric potentials may be applied to the electric field control electrode 106 and the gate electrode 102. With such a structure, the field effect transistor can be driven under optimum conditions. Since the surface trap response can be suppressed by fixing the surface potential, current collapse can be suppressed more effectively than when the electric field control electrode 106 is set to the same potential as the gate electrode 102 and the surface potential is modulated. . In particular, in a group III nitride semiconductor device in which the influence of surface negative charge is a serious problem, the effect of independently controlling the electric field control electrode 106 is remarkable.

  Further, when the electric potential of the electric field control electrode 106 is fixed as described above, even if the electric potential of the gate electrode 102 changes, the gate capacitance hardly changes, so that a decrease in gain can be significantly suppressed.

(Example 5)
In the HJFET 134 according to the fourth embodiment having the field plate portion 105, the insulating film may have a laminated structure as in the third embodiment. FIG. 5 is a cross-sectional view showing the configuration of the HJFET of this example.

The HJFET 136 shown in FIG. 5 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an AlGaN electron supply layer 113 is formed. On the AlGaN electron supply layer 113, the source electrode 101 and the drain electrode 103 are in ohmic contact. A gate electrode 102 is provided between these electrodes. The gate electrode 102 has a field plate portion 105 and is in Schottky junction with the AlGaN electron supply layer 113. The surface of the AlGaN electron supply layer 113 is covered with a SiN film 121, and an SiO ₂ film 122 is further provided thereon. The field plate portion 105 is provided on the SiO ₂ film 122, and the SiN film 121 and the SiO ₂ film 122 are provided immediately below the field plate portion 105.

21 to 24 are views showing a method for manufacturing the HJFET 136.
First, a semiconductor is grown on the substrate 110 made of SiC by, for example, the MBE growth method or the MOVPE growth method. Thus, in order from the substrate 110 side, the buffer layer 111 (thickness 20 nm) made of undoped AlN, the undoped GaN channel layer 112 (thickness 2 μm), and the AlGaN electron supply layer 113 (thickness 25 nm) made of undoped AlGaN. A semiconductor layer structure in which is stacked is obtained (FIG. 21A).

  Next, after forming the AlGaN electron supply layer 113, an SiN film 121 (60 nm) is formed on the AlGaN electron supply layer 113 by plasma CVD or the like without exposing it to the atmosphere (FIG. 21B). When the AlGaN electron supply layer 113 is exposed to the atmosphere, the SiN film 121 is formed after etching with acid or the like to clean the surface of the semiconductor layer.

Subsequently, an SiO ₂ film 122 (100 nm) is formed on the SiN film 121 by an atmospheric pressure CVD method or the like (FIG. 22C).

Then, a part of the SiN film 121 and the SiO ₂ film 122 and a part of the epitaxial layer structure are removed by etching until the GaN channel layer 112 is exposed, thereby forming an element isolation mesa (not shown). Then, a photoresist is formed in a predetermined region on the surface of the SiO ₂ film 122, and the predetermined regions of the SiN film 121 and the SiO ₂ film 122 are selectively etched away until the AlGaN electron supply layer 113 is exposed (FIG. 22). (D)) A source electrode 101 and a drain electrode 103 are formed on the AlGaN electron supply layer 113 by vapor deposition of a metal such as Ti / Al (FIG. 23E), and annealing is performed at 650 ° C. Thus, these electrodes and the AlGaN electron supply layer 113 are ohmic-bonded.

Subsequently, a photoresist is formed in a predetermined region on the surface of the SiO ₂ film 122, and the predetermined region of the SiN film 121 and the SiO ₂ film 122 is selectively removed by etching to expose the AlGaN electron supply layer 113. An opening is provided (FIG. 23 (f)).

  Next, for example, Ni / Au is vapor-deposited on the exposed AlGaN electron supply layer 113 as a metal film to be the gate electrode 102 to form the gate electrode 102 which is Schottky-bonded to the AlGaN electron supply layer 113 (FIG. 24). At the same time, a field plate portion 105 made of Ni / Au is also formed. In this way, the HJFET 136 shown in FIG. 5 is obtained.

  In this embodiment, an example in which the gate electrode 102 and the field plate portion 105 are formed at the same time has been shown. It may be formed by the following. In this case, the gap between the gate electrode 102 and the field plate portion 105 can be formed with a narrower gap.

According to the present embodiment, in addition to the effects of the fourth embodiment, the following effects can be obtained. That is, in the HJFET 136, a protective film made of a stacked film of the SiN film 121 and the SiO ₂ film 122 is provided immediately below the field plate portion 105. By using the SiO ₂ film 122 having a low dielectric constant as compared with the configuration in which the protective film is composed only of the SiN film 121, an increase in parasitic capacitance caused by the field plate portion 105 can be suppressed. In particular, the SiN film 121 is formed to be thin enough not to change the film quality with time (150 nm or less, more preferably 100 nm or less), and the SiO ₂ film 122 is thickly laminated, thereby further effectively suppressing the increase in capacitance. be able to.

  In this embodiment, the gate electrode 102 having the field plate portion 105 may be replaced with the gate electrode 102 and the electric field control electrode 106 provided separately from the gate electrode 102.

  The electric field control electrode 106 may be formed at the same time as the gate electrode 102 or may be formed in a separate process. In another process, a resist having an opening at a predetermined position is formed on the SiN film 121, and the electric field control electrode 106 can be formed so as to fill the opening. In this case, the gap between the gate electrode 102 and the electric field control electrode 106 can be formed with a narrower gap.

Further, in this embodiment, since the SiN film 121 formed on the surface of the group III nitride semiconductor layer is covered with the SiO ₂ film 122, the deterioration with time of the SiN film 121 can be further reliably suppressed. it can. Therefore, as in the third embodiment, the device characteristics can be extended in life.

Also in this embodiment, as in the third embodiment, the source electrode 101 and the gate electrode 102 are on the SiN film 121 and the SiO ₂ film 122. For this reason, during high voltage operation, the electric field concentration at the gate side end of the drain electrode 103 can be relaxed, and the gate breakdown voltage can be improved.

In this embodiment, the surface protective film has the SiO ₂ film 122 as the upper layer. However, a low dielectric constant film having a relative dielectric constant of 4 or less is used from the viewpoint of improving gain and improving reliability. More preferably, it is used. Examples of such low dielectric constant materials include SiOC (sometimes referred to as SiOCH), BCB (benzocyclobutene), FSG (Fluorosilicate Glass: SiOF), HSQ (Hydrogen-Silicesquioxane), MSQ (Methyl-Silsequioxane), polymer. Or the material which made these porous is illustrated.

  Protecting the interface between the AlGaN electron supply layer 113 and the SiN film 121 even when the protective film, more specifically, the insulating film constituting the upper layer of the surface protective film contains C (carbon) as a constituent element Thus, the above-described effect can be obtained.

(Example 6)
The present embodiment is an example of an HJFET that employs a wide recess structure.
FIG. 6 is a cross-sectional view showing the configuration of the HJFET of this example. In the HJFET 138 shown in FIG. 6, a contact layer 114 composed of an undoped AlGaN layer is interposed between the source electrode 101 and the AlGaN electron supply layer 113 and between the drain electrode 103 and the AlGaN electron supply layer 113. In the HJFET 138, the contact layer 114 is provided on the AlGaN electron supply layer 113 in the formation region of the source electrode 101 and the drain electrode 103. The contact layer 114 has an opening, and the AlGaN electron supply layer 113 is exposed from the opening. The bottom surface of the opening is a recess surface with respect to the upper surface of the contact layer 114. A source electrode 101 and a drain electrode 103 are provided in contact with the upper surface of the contact layer 114. A gate electrode 102 is provided in contact with the exposed portion of the AlGaN electron supply layer 113. The bottom surfaces of the source electrode 101 and the drain electrode 103 are located above the bottom surface of the gate electrode 102 (on the side away from the substrate 110).

  The HJFET 138 is formed on a substrate 110 such as SiC. A buffer layer 111 made of a semiconductor layer is formed on the substrate 110. A GaN channel layer 112 is formed on the buffer layer 111. On the GaN channel layer 112, an AlGaN electron supply layer 113 is formed. A contact layer 114 is formed on the AlGaN electron supply layer 113. A source electrode 101 and a drain electrode 103 are ohmic-bonded to the surface of the contact layer 114. The surface of the AlGaN electron supply layer 113 is covered with a SiN film 121.

  The HJFET 138 of FIG. 6 has a configuration in which a contact layer 114 is added to the HJFET 100 (FIG. 1) of the first embodiment. With this configuration, in addition to the effects described in the first embodiment, there is an effect of further reducing the contact resistance.

  In addition, the adoption of the wide recess structure changes the electric field distribution at the end of the gate electrode 102 on the drain electrode side, so that an even better electric field relaxation effect can be obtained.

  Further, in the present embodiment, similarly to the first embodiment, the second embodiment, and the fourth embodiment, the source electrode 101 and the gate electrode 102 are on the SiN film 121. The gate breakdown voltage can be improved by relaxing the electric field concentration at the end of the gate electrode.

In the present embodiment, an example in which the protective film provided on the AlGaN electron supply layer 113 is a single layer is shown. However, as in the case of the above-described third and fourth embodiments, the insulating film has a two-layer structure. Alternatively, the field plate portion 105 can be formed. For example, the field plate unit 105 may have a two-layer structure including a SiN film 121 and a SiO ₂ film 122 as a protective film, and the field plate unit 105 may be provided on the SiO ₂ film 122. Also in this case, it is preferable that the SiO ₂ film 122 is an insulating film having a dielectric constant lower than that of the SiN film 121 as in the third embodiment. As such an insulating film, for example, when the first insulating film is SiN, a film containing no nitrogen can be used. By so doing, it is possible to effectively suppress the temporal change in the film quality of the insulating film and the increase in capacitance in the region below the field plate portion 105. Therefore, the reliability and high frequency characteristics of the HJFET 138 can be further improved. Further, the field plate portion 105 may extend to the top of the contact layer 114. By doing so, the electric field concentration at the drain side end of the gate electrode 102 can be more effectively dispersed and relaxed. In addition, when setting it as a recess structure, it can also be set as a multistage recess.

  In this embodiment, a gate recess structure in which a part of the drain electrode 103 is embedded in the AlGaN electron supply layer 113 can also be adopted.

  In the above description, the case where the contact layer 114 is composed of an undoped AlGaN layer has been described as an example. However, in this embodiment, the contact layer 114 may be doped with a predetermined impurity.

  In the above, this invention was demonstrated based on embodiment and an Example. These embodiments are examples, and it will be understood by those skilled in the art that various modifications can be made to each component and combination of each processing process, and such modifications are also within the scope of the present invention. .

  For example, in the above-described embodiment, the case where SiC is used as the material of the substrate 110 has been described as an example. Also good.

  In the above embodiment, the case where the SiN film is provided as an insulating protective film containing at least one of the elements constituting the group III nitride semiconductor layer structure has been described as an example. The material of the insulating film containing at least one of the elements constituting the structure is not limited to SiN, and other examples include nitrides such as BN. Even when such a film is used, generation of current collapse can be suppressed.

  In addition, the structure of the semiconductor layer below the gate electrode 102 is not limited to the illustrated structure, and various modes are possible. For example, not only the upper part of the GaN channel layer 112 but also a lower part of the AlGaN electron supply layer 113 may be provided.

In addition, an intermediate layer or a cap layer may be appropriately provided in this semiconductor layer structure. For example, the group III nitride semiconductor layer structure has a channel layer made of In _x Ga _1-x N (0 ≦ x ≦ 1), an electron supply layer made of Al _y Ga _1-y N (0 ≦ y ≦ 1), and It can be set as the structure which has the structure which the cap layer which consists of GaN laminated | stacked in this order. In this way, the effective Schottky height can be increased and a higher gate breakdown voltage can be realized. However, in the above formula, the case where x = y = 0 is excluded.

  In each of the above embodiments, a so-called gate recess structure in which a part of the lower portion of the gate electrode 102 is embedded in the AlGaN electron supply layer 113 can be employed. Thereby, an excellent gate breakdown voltage can be obtained.

In each of the above embodiments, the distance between the gate electrode 102 and the drain electrode 103 can be made longer than between the gate electrode 102 and the source electrode 101. This is a so-called offset structure, and the electric field concentration at the drain electrode side end portion of the gate electrode 102 can be more effectively dispersed and relaxed.

Claims (16)

A group III nitride semiconductor layer structure including a heterojunction;
A source electrode and a drain electrode formed separately on the group III nitride semiconductor layer structure;
A gate electrode disposed between the source electrode and the drain electrode;
With
In the region between the gate electrode and the drain electrode, an insulating film is provided on the group III nitride semiconductor layer structure,
A field effect transistor, wherein an impurity concentration in the group III nitride semiconductor layer structure at an interface between the insulating film and the group III nitride semiconductor layer structure is 1E17 atoms / cm ³ or less. The field effect transistor according to claim 1.
The field effect transistor according to claim 1, wherein the insulating film is an insulating film containing at least one of elements constituting the group III nitride semiconductor layer structure. The field effect transistor according to claim 2.
A field effect transistor, wherein the element constituting the group III nitride semiconductor layer structure is nitrogen. The field effect transistor according to any one of claims 1 to 3,
A field effect transistor, wherein the insulating film is a film that substantially does not contain oxygen as a constituent element. The field effect transistor according to any one of claims 1 to 4,
A field effect transistor, wherein an electric field control electrode is provided above the group III nitride semiconductor layer structure through the insulating film in a region between the gate electrode and the drain electrode. The field effect transistor according to claim 5,
The field effect transistor, wherein the field control electrode can be controlled independently of the gate electrode.   5. The field effect transistor according to claim 1, wherein the gate electrode has a field plate portion that extends in a hook shape on the drain electrode side and is formed on the insulating film. Effect transistor. The field effect transistor according to any one of claims 1 to 7,
A field effect transistor, wherein the insulating film has a thickness of 5 nm to 100 nm. The field effect transistor according to any one of claims 1 to 8,
2. The field effect transistor according to claim 1, wherein the insulating film includes a first insulating film and a second insulating film stacked on the first insulating film. The field effect transistor according to any one of claims 1 to 9,
A field effect transistor, wherein a contact layer is interposed between the source electrode and the group III nitride semiconductor layer structure and between the drain electrode and the group III nitride semiconductor layer structure. The field effect transistor according to claim 10.
The field effect transistor according to claim 1, wherein the contact layer comprises an undoped AlGaN layer. 12. The field effect transistor according to claim 1, wherein an impurity concentration in the group III nitride semiconductor layer structure at an interface between the insulating film and the group III nitride semiconductor layer structure is 1E15 atoms / cm ³ or less. A field effect transistor. A method of manufacturing a field effect transistor according to any one of claims 1 to 12,
Forming the group III nitride semiconductor layer structure including a heterojunction in a film formation chamber;
Forming the insulating film on the group III nitride semiconductor layer structure;
A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming the gate electrode on the group III nitride semiconductor layer structure so as to embed the opening;
A method of manufacturing a field effect transistor comprising: Forming a group III nitride semiconductor layer structure including a heterojunction in the deposition chamber;
Forming an insulating film on the group III nitride semiconductor layer structure;
A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode on the group III nitride semiconductor layer structure so as to embed the opening;
Including
A step of forming the insulating film without removing the group III nitride semiconductor layer structure from the film formation chamber after the step of forming the group III nitride semiconductor layer structure. Production method. Forming a group III nitride semiconductor layer structure including a heterojunction in the deposition chamber;
Forming an insulating film on the group III nitride semiconductor layer structure;
A step of selectively removing a predetermined region of the insulating film by etching to form an opening, and forming a gate electrode on the group III nitride semiconductor layer structure so as to embed the opening;
After the step of forming the group III nitride semiconductor layer structure, before the step of forming the insulating film,
Cleaning the surface of the group III nitride semiconductor layer structure by wet etching using an acid;
A method of manufacturing a field effect transistor comprising: In the manufacturing method of the field effect transistor in any one of Claims 13 thru | or 15,
After the step of forming the insulating film, a predetermined region of the insulating film is selectively removed by etching, and a source electrode and a drain electrode are embedded on the group III nitride semiconductor layer structure so as to embed the removed region And a step of forming the field effect transistors apart from each other.

Images