JP2018101755A - Heterojunction field effect transistor and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a heterojunction field effect transistor capable of preventing the degradation of high-frequency properties; and a manufacturing method of the heterojunction field effect transistor.SOLUTION: A heterojunction field effect transistor made of a nitride semiconductor comprises: a channel layer 3; a barrier layer 4, formed on the channel layer 3, which makes a heterojunction with the channel layer 3, and contains at least indium; a gate electrode 5 formed in a predetermined region on the barrier layer 4; a source electrode 6 and a drain electrode 7 which are respectively formed on one side and the other side of the gate electrode 5 on the barrier layer 4; and a protection film 9, made of aluminum oxide, which is formed in an area other than regions, on the barrier layer 4, where the gate electrode 5, the source electrode 6, and the drain electrode 7 are formed. In the protection film 9, a ratio of oxygen to aluminum in the aluminum oxide is 1.97 or greater.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a heterojunction field effect transistor made of a nitride semiconductor, which is a semiconductor containing nitride, and a method for manufacturing the same.

  High electron mobility transistors (HEMTs) using nitride semiconductors have the characteristics of a high breakdown electric field and high electron mobility, and are expected as devices that operate at high frequencies and high outputs. .

  Conventionally, in a heterojunction field effect transistor using AlGaN as a barrier layer, a structure using SiN as a protective film on a semiconductor surface has been proposed in order to improve the breakdown voltage and improve current collapse (for example, patents). Reference 1).

  In addition, a heterojunction field-effect transistor using a nitride semiconductor containing In (indium) in the barrier layer, for example, InAlN, has a high carrier concentration, and therefore, higher output is expected (for example, non-patent) References 1 and 2). Since InAlN has a large spontaneous polarization and generates a large discontinuous conduction band energy, it has an excellent electron confinement effect and is higher than the case where AlGaN is used for the barrier layer (2-Dimensional Electron Gas: 2DEG) concentration is obtained.

JP 2002-359256 A

A. Matulionis et al., “Window for better reliability of nitride heterostructure field effect transistors”, Microelectronics Reliability 52, 2012, p.p.2149-2152 J. Kuzmik et al., “Power Electronics on InAlN / (In) GaN: Prospect for a Record Performance”, IEEE ELECTRON DEVICE LETTERS, VOL.22, NO.11, 2001, p.p.510-512

  In a heterojunction field effect transistor using a nitride semiconductor containing In as a barrier layer, if a protective film containing Si is used, the breakdown voltage of the heterojunction field effect transistor is reduced and the high frequency characteristics are degraded due to the occurrence of current collapse. Arise. Therefore, a heterojunction field effect transistor using a nitride semiconductor containing In as a barrier layer has a problem that a protective film containing Si cannot be used.

  The present invention has been made to solve such a problem, and an object thereof is to provide a heterojunction field effect transistor capable of suppressing deterioration of high-frequency characteristics and a method for manufacturing the same.

  In order to solve the above problem, a heterojunction field effect transistor according to the present invention is a heterojunction field effect transistor made of a nitride semiconductor, and includes a first nitride semiconductor layer and a first nitride semiconductor layer. A second nitride semiconductor layer containing at least In that forms a heterojunction with the first nitride semiconductor layer, and a gate electrode formed in a predetermined region on the second nitride semiconductor layer; A source electrode and a drain electrode respectively formed on one side and the other side of the gate electrode on the second nitride semiconductor layer; and on the second nitride semiconductor layer, the gate electrode, the source electrode, and And a protective film made of aluminum oxide formed in a region other than the region where the drain electrode is formed. The protective film has a ratio of oxygen to aluminum in aluminum oxide of 1 It is 97 or more.

  In addition, a method for manufacturing a heterojunction field effect transistor according to the present invention is a method for manufacturing a heterojunction field effect transistor made of a nitride semiconductor, comprising: (a) forming a first nitride semiconductor layer; b) After step (a), forming a second nitride semiconductor layer containing at least In and forming a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer; and step (c). After (b), forming a source electrode and a drain electrode on the second nitride semiconductor layer on one side and the other side of the region where the gate electrode is to be formed, and (d) step ( c) a step of forming a gate electrode in a region where the gate electrode is to be formed on the second nitride semiconductor layer; and (e) after the step (d), on the second nitride semiconductor layer. , Gate electrode, source electrode, and drain electrode And a step of forming a protective film made of aluminum oxide in a region other than the region where the protective layer is formed by an ALD (Atomic Layer Deposition) method, and is supplied at the time of supplying ozone when forming the protective film in step (e) The ratio of the ozone amount to the total gas amount is 5.7% or more.

  In addition, a method for manufacturing a heterojunction field effect transistor according to the present invention is a method for manufacturing a heterojunction field effect transistor made of a nitride semiconductor, comprising: (a) forming a first nitride semiconductor layer; b) After step (a), forming a second nitride semiconductor layer containing at least In and forming a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer; and step (c). After (b), forming a source electrode and a drain electrode on the second nitride semiconductor layer on one side and the other side of the region where the gate electrode is to be formed, and (d) step ( c) a step of forming a protective film made of aluminum oxide on the second nitride semiconductor layer in a region other than the region where the source electrode and the drain electrode are formed by an ALD (Atomic Layer Deposition) method; (E After the step (d), an opening is formed in a region corresponding to a region where the gate electrode of the protective film is to be formed, and a gate electrode is formed in the opening. In the step (d), the protective film The ratio of the amount of ozone in the total amount of gas supplied at the time of ozone supply when forming is 5.7% or more.

  According to the present invention, the heterojunction field effect transistor is a heterojunction field effect transistor made of a nitride semiconductor, the first nitride semiconductor layer and the first nitride semiconductor layer formed on the first nitride semiconductor layer. A second nitride semiconductor layer including at least In that forms a heterojunction with the nitride semiconductor layer; a gate electrode formed in a predetermined region on the second nitride semiconductor layer; and the second nitride semiconductor layer A source electrode and a drain electrode respectively formed on one side and the other side of the gate electrode, and a region on the second nitride semiconductor layer where the gate electrode, the source electrode, and the drain electrode are formed A protective film made of aluminum oxide formed in a region other than the above, and since the ratio of oxygen to aluminum in aluminum oxide is 1.97 or more, the protective film has a high It is possible to suppress the deterioration of the wave characteristics.

  In addition, the method of manufacturing a heterojunction field effect transistor is a method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor, wherein (a) a step of forming a first nitride semiconductor layer, and (b) step After (a), a step of forming a second nitride semiconductor layer containing at least In and forming a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer, and (c) step (b) A step of forming a source electrode and a drain electrode on one side and the other side of the region where the gate electrode is to be formed on the second nitride semiconductor layer, and (d) step (c) A step of forming a gate electrode in a region where the gate electrode is to be formed on the second nitride semiconductor layer; and (e) after the step (d), on the second nitride semiconductor layer, Source electrode and drain electrode are formed Forming a protective film made of aluminum oxide in a region other than the region by an ALD (Atomic Layer Deposition) method, and in step (e), the total amount of gas supplied during ozone supply when forming the protective film Since the ratio of the amount of ozone occupied is 5.7% or more, it is possible to suppress the deterioration of the high frequency characteristics.

  In addition, the method of manufacturing a heterojunction field effect transistor is a method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor, wherein (a) a step of forming a first nitride semiconductor layer, and (b) step After (a), a step of forming a second nitride semiconductor layer containing at least In and forming a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer, and (c) step (b) A step of forming a source electrode and a drain electrode on one side and the other side of the region where the gate electrode is to be formed on the second nitride semiconductor layer, and (d) step (c) And (e) forming a protective film made of aluminum oxide on the second nitride semiconductor layer in a region other than the region where the source electrode and the drain electrode are formed by an ALD (Atomic Layer Deposition) method; Step (d) A step of forming an opening in a region corresponding to a region where the gate electrode of the protective film is to be formed, and forming a gate electrode in the opening; and in forming the protective film in the step (d) Since the ratio of the ozone amount to the total gas amount supplied at the time of ozone supply is 5.7% or more, it is possible to suppress the deterioration of the high frequency characteristics.

It is sectional drawing which shows an example of a structure of the heterojunction field effect transistor by Embodiment 1 of this invention. It is a figure which shows the high frequency characteristic with respect to ozone concentration at the time of protective film formation of the heterojunction field effect transistor by Embodiment 1 of this invention. It is a figure which shows the relationship between the ratio of the oxygen with respect to the aluminum in the aluminum oxide film by Embodiment 1 of this invention, and ozone concentration. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 1 of this invention. It is sectional drawing which shows an example of a structure of the heterojunction field effect transistor by Embodiment 2 of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention. It is sectional drawing which shows an example of the manufacturing process of the heterojunction field effect transistor by Embodiment 2 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment 1>
<Configuration>
First, the configuration of the heterojunction field effect transistor according to the first embodiment of the present invention will be described.

  FIG. 1 is a cross-sectional view showing an example of the configuration of the heterojunction field effect transistor according to the first embodiment. Note that the heterojunction field-effect transistor shown in FIG. 1 is a high electron mobility transistor using a group III nitride semiconductor. The group III nitride semiconductor refers to a nitride semiconductor containing a group III element.

  As shown in FIG. 1, the heterojunction field effect transistor according to the first embodiment includes a substrate 1, a buffer layer 2 formed on the substrate 1, and a first nitride semiconductor formed on the buffer layer 2. A channel layer 3 that is a layer and a barrier layer 4 that is a second nitride semiconductor layer formed on the channel layer 3 are provided.

The channel layer 3 is made of Al _x Ga _1-x N (0 ≦ x ≦ 1), which is a group III nitride semiconductor. The barrier layer 4 has a band gap larger than that of the channel layer 3 and is a group III nitride semiconductor containing at least In. In _y Al _z Ga _1-yz N (0 <y ≦ 1, 0 <z ≦ 1, 0 <y + z ≦ 1). The channel layer 3 and the barrier layer 4 form a heterojunction, and high-concentration carriers called two-dimensional electron gas are generated at the heterointerface between the channel layer 3 and the barrier layer 4. Since the channel layer 3 is an undoped layer that is not doped with impurities, the two-dimensional electron gas has high mobility. As a result, the heterojunction field effect transistor according to the first embodiment can be increased in frequency and current.

  On the surface of the barrier layer 4, a gate electrode 5 selectively formed as a Schottky electrode, and a source electrode 6 and a drain electrode 7 formed as ohmic electrodes so as to face each other with the gate electrode 5 interposed therebetween are provided. ing. That is, the gate electrode 5 is formed in a predetermined region on the barrier layer 4. The source electrode 6 and the drain electrode 7 are formed on the barrier layer 4 and on one side and the other side of the gate electrode 5, respectively. The gate electrode 5 is in Schottky contact with the barrier layer 4, and the source electrode 6 and the drain electrode 7 are in ohmic contact with the barrier layer 4.

  An isolation region 8 is formed in the channel layer 3 and the barrier layer 4 in a region other than the region where the heterojunction field effect transistor is formed. The element isolation region 8 is a region provided for isolating adjacent heterojunction field effect transistors.

A protective film 9 made of aluminum oxide is formed on the surface of the barrier layer 4 in a region other than the region where the gate electrode 5, the source electrode 6, and the drain electrode 7 are formed. The protective film 9 is formed by depositing aluminum oxide by an ALD (Atomic Layer Deposition) method. Specifically, trimethylaluminum (TMA: Al (CH ₃ ) ₃ ) serving as an aluminum raw material is supplied into the reaction furnace and adsorbed onto the barrier layer 4, and then TMA is exhausted. That is, TMA is purged with oxygen under reduced pressure. Next, ozone as a raw material of oxygen is supplied from the ozone generator into the reaction furnace to react with TMA adsorbed on the barrier layer 4, and then the ozone is exhausted. That is, ozone is purged with oxygen under reduced pressure. Note that oxygen is used to supply TMA and ozone. As described above, when one cycle of the four steps from the supply of TMA to the exhaust of ozone is performed in one cycle, aluminum oxide for one atomic layer is formed on the barrier layer 4. Then, by repeating the cycle one or more times, the protective film 9 made of aluminum oxide having high quality and good film thickness controllability can be formed.

  FIG. 2 is a diagram showing high-frequency characteristics with respect to ozone concentration when the protective film 9 is formed. The ozone concentration refers to the ratio of the amount of ozone supplied to the total amount of gas supplied into the reactor when supplying ozone when the protective film 9 is formed by the ALD method. The total gas amount is the sum of the oxygen supply amount and the ozone supply amount supplied into the reactor.

  The supply amount of oxygen is constant, and the ozone concentration is changed by changing only the supply amount of ozone. In addition, in the measurement of the drain current by DC (Direct Current) measurement and the measurement of the drain current by radio frequency (RF) measurement, the drain measured by DC measurement when the gate voltage is constant and the same drain voltage. The ratio of the drain current value measured by the high frequency measurement to the current value is used as an index of the high frequency characteristics of the transistor.

  As shown in FIG. 2, when the ozone concentration is increased, the high-frequency characteristics of the transistor are improved, and the ozone concentration is 5.7% or more, which is the same as the current value of the DC characteristics, that is, the high-frequency measurement with respect to the drain current value measured by DC measurement. The ratio of the drain current value measured in step 100 is 100%. As the ozone concentration increases, that is, the supply amount of activated oxygen increases, the oxygen content of aluminum oxide increases and becomes oxygen rich. When aluminum oxide is formed by the ALD method, indium oxide in a natural oxide layer made of indium or aluminum oxide existing on the semiconductor surface is likely to be aluminum oxide. This is because the standard generated cast energy is about -830 kJ / mol for indium oxide and about -1560 kJ / mol for aluminum oxide. Since aluminum oxide is more stable than indium oxide, the oxygen of indium oxide is removed and oxidized. It becomes aluminum. Thereby, the altered layer made of indium oxide existing on the semiconductor surface is removed, and the high frequency characteristics are improved.

  When deposition of aluminum oxide is started by the ALD method, trimethylaluminum, which is a raw material for aluminum, is first adsorbed, and the surface is covered with aluminum and combined with underlying oxygen to form a first aluminum layer. Next, the supplied active oxygen, ozone, is adsorbed and bonded onto the aluminum layer to form aluminum oxide. At this time, the oxygen of indium oxide formed on the surface of the indium oxide strengthens the bond with aluminum. It seems that the bond with and weakens. As the ozone concentration is increased, the high-frequency characteristics are improved. As the ozone concentration is higher, the altered layer made of indium oxide existing on the semiconductor surface is more likely to disappear.

  FIG. 3 is a diagram showing the relationship between the ratio of oxygen to aluminum and the ozone concentration in an aluminum oxide film obtained by XPS (X-ray Photoelectron Spectroscopy) analysis. The aluminum oxide film to be subjected to XPS analysis is formed by depositing on the Si substrate put together in the reaction furnace when forming the protective film 9 of the heterojunction field effect transistor shown in FIG. .

  As shown in FIG. 3, the ratio of oxygen to aluminum increases as the ozone concentration increases, similar to the high frequency characteristics shown in FIG. Further, in the high frequency characteristics shown in FIG. 2, the ratio of oxygen to aluminum in the aluminum oxide film in which the ratio of the drain current value measured by high frequency measurement to the drain current value measured by DC measurement is 100% is 1.97. . However, since the altered layer present on the semiconductor surface is at most several nm, if the ozone concentration is increased to 5.7% or more after that, the indium oxide present on the semiconductor surface is completely converted to aluminum oxide, so that the high frequency characteristics are saturated. To do. In addition, the ratio of oxygen to aluminum in the aluminum oxide film increases, but saturates similarly to the high frequency characteristics.

<Manufacturing method>
Next, a method for manufacturing a heterojunction field effect transistor according to the first embodiment will be described.

  FIG. 4 is a diagram illustrating an example of a manufacturing process of the heterojunction field effect transistor according to the first embodiment. As shown in FIG. 4, the heterojunction field effect transistor according to the first embodiment includes an epi fabrication process, a source / drain electrode formation process, an element isolation formation process, a gate electrode formation process, and a protective film formation process. Yes. Below, each process is demonstrated in order using FIGS.

<Epi fabrication process>
First, as shown in FIG. 5, for example, a substrate 1 made of sapphire, SiC (silicon carbide), GaN (gallium nitride), Si (silicon), or the like is prepared.

  Next, as shown in FIG. 6, on the main surface of the substrate 1 by an epitaxial growth method such as MOCVD (Metal Organic Chemical Vapor Deposition) method or MBE (Molecular Beam Epitaxy) method, for example. The buffer layer 2, the channel layer 3, and the barrier layer 4 are sequentially stacked.

The channel layer 3 is composed of Al _x Ga _1-x N (0 ≦ x ≦ 1) which is a group III nitride semiconductor. The film thickness of the channel layer 3 should just be the thickness which can flow an electron at least, for example, should just be 500 nm-3000 nm. The impurity concentration of the channel layer 3 does not matter.

The barrier layer 4 has a band gap larger than that of the channel layer 3 and is a group III nitride semiconductor containing at least In. In _y Al _z Ga _1-yz N (0 <y ≦ 1, 0 <z ≦ 1, 0 <y + z ≦ 1). For example, when the channel layer 3 is formed with x = 0 and the barrier layer 4 is formed with y = 0.18 and z = 0.82, the lattice constant of GaN whose barrier layer 4 is the channel layer 3 is used. Therefore, an unstrained barrier layer 4 with few defects such as misfit dislocations can be formed. The impurity concentration of the barrier layer 4 is set to 1 × 10 ¹⁸ cm ⁻³ or less in order to make the barrier layer 4 a high breakdown voltage layer. The impurity of the barrier layer 4 is always n-type. Nitride semiconductors contain n-type impurities because impurities enter the nitride semiconductor from the growth furnace or atmospheric gas even in the case of non-doping in which impurities are not intentionally doped. It will be. Therefore, even if the barrier layer 4 is non-doped during crystal growth, the actual impurity concentration may be 1 × 10 ¹⁸ cm ⁻³ or less.

<Source / drain electrode formation process>
Next, as shown in FIG. 7, a resist pattern 10 is formed on the barrier layer 4 in a region other than the region where the source electrode 6 and the drain electrode 7 are formed by photolithography. Then, using the resist pattern 10 as a mask, a laminated film of a metal that becomes an ohmic electrode, for example, Ti and Al is deposited. Examples of the laminated film include those that can be configured by laminating a metal selected from metals such as Ti, Al, Pt, Nb, Au, Hf, Zr, Sr, Ni, Ta, Mo, and W. The laminated film is deposited using, for example, an electron beam evaporation method or a sputtering method. Thereafter, when the resist pattern 10 is removed, the source electrode 6 and the drain electrode 7 as shown in FIG. 8 are formed on the barrier layer 4. Thus, the source electrode 6 and the drain electrode 7 are formed on the barrier layer 4 by the lift-off method. That is, the source electrode 6 and the drain electrode 7 are formed on the barrier layer 4 on one side and the other side of the region where the gate electrode 5 is to be formed.

  In addition, after depositing the laminated film, the source electrode 6 and the drain electrode 7 may be alloyed by annealing at a predetermined temperature. In order to realize further reduction in contact resistance, as shown in FIG. 9, a part of a region where the source electrode 6 and the drain electrode 7 are formed in the barrier layer 4 or the interface with the channel layer 3 is removed, It is desirable to form the source electrode 6 and the drain electrode 7 in the removed part.

<Element isolation formation process>
Next, as shown in FIG. 10, with the resist pattern 11 as a mask, an element isolation region 8 is formed across the channel layer 3 from the barrier layer 4 other than the region for manufacturing the heterojunction field effect transistor. Specifically, for example, as shown in FIG. 11, the element isolation region 8 is formed by using an ion implantation method in which ions 12 such as He, N, O, Mg, Ar, Ca, Fe, Zn, Sr, and Ba are irradiated. Form. Alternatively, the element isolation region 8 is formed using etching or the like.

<Gate electrode formation process>
Next, as shown in FIG. 12, a resist pattern 14 is formed in a region other than the gate electrode formation region 13 on the barrier layer 4 where the gate electrode 5 is to be formed by photolithography. Then, a metal serving as a Schottky electrode is deposited on the gate electrode formation region 13 using the resist pattern 14 as a mask, for example, using an electron beam evaporation method or a sputtering method. The metal serving as the Schottky electrode may be any metal that forms a Schottky contact with the barrier layer 4. The metal nitride is composed of a single layer film or a laminated film, and may have a Pt / Au structure, for example. Thereafter, when the resist pattern 14 is removed, a gate electrode 5 as shown in FIG. 13 is formed on the barrier layer 4. Thus, the gate electrode 5 is formed on the barrier layer 4 by the lift-off method. After forming the gate electrode 5, annealing may be performed at a predetermined temperature.

<Protective film formation process>
Next, a protective film 9 made of aluminum oxide is formed on the barrier layer 4 in a region other than the region where the gate electrode 5, the source electrode 6, and the drain electrode 7 are formed by the ALD method. The protective film 9 is desirably formed within a range of 1 nm to 100 nm, for example.

  Specifically, a sample as shown in FIG. 13 is placed on the stage in the reaction furnace. At this time, the temperature of the stage is preferably in the range of 200 ° C. to 400 ° C., for example. The supply of oxygen gas is desirably a predetermined pressure, for example, 50 Pa to 100 Pa. Each supply time in the supply of TMA and the supply of ozone is preferably in the range of 0.1 seconds to 5 seconds, for example. The exhaust time of TMA and ozone is preferably in the range of 1 second to 10 seconds, for example.

  Further, when supplying ozone, the amount of ozone supplied is set so that the ozone concentration becomes 5.7% or more. For example, when the total oxygen flow rate supplied to the reaction furnace as the carrier gas at the time of supplying ozone is 1000 sccm, the supply amount of ozone supplied to the reaction furnace is set to 59% in order to increase the ozone concentration to 5.7% or more. .3 sccm or more is necessary.

  Thus, by repeating one cycle consisting of TAM supply, TMA exhaust, ozone supply, and ozone exhaust a plurality of times, the gate electrode 5 on the barrier layer 4 as shown in FIG. A protective film 9 made of aluminum oxide can be formed in a region other than the region where the source electrode 6 and the drain electrode 7 are formed.

  In the above, only the minimum necessary elements that operate as a transistor are described, but after the above, a part of the protective film 9 covering each of the gate electrode 5, the source electrode 6, and the drain electrode 7 is wet-etched. It removes using the method or dry etching method. Then, a wiring electrode can be formed so as to be in contact with each of the gate electrode 5, the source electrode 6, and the drain electrode 7, and the above-described electrical characteristics can be measured.

  Finally, it is used as a device through processes such as a via hole forming process and an electrode protective film forming process. Therefore, each of the gate electrode 5, the source electrode 6, the drain electrode 7, and the protective film 9 may have a multilayer structure. Alternatively, a multi-finger structure in which a plurality of heterojunction field effect transistors are electrically connected in parallel may be employed.

  From the above, according to the first embodiment, the heterojunction field effect transistor includes the protective film 9 made of aluminum oxide on the barrier layer 4 containing In, and the protective film 9 is made of aluminum oxide. The ratio of oxygen to aluminum is 1.97 or more. Accordingly, the ratio of the drain current value measured by the high frequency measurement to the drain current value measured by the DC measurement can be set to 100%, and the deterioration of the high frequency characteristics due to the occurrence of current collapse can be suppressed.

<Embodiment 2>
<Configuration>
First, the configuration of the heterojunction field effect transistor according to the second embodiment of the present invention will be described.

  FIG. 14 is a cross-sectional view showing an example of the configuration of the heterojunction field effect transistor according to the second embodiment. As shown in FIG. 14, in the heterojunction field effect transistor according to the second embodiment, the gate electrode 5 has a portion covering a part on the surface of the protective film 9 opposite to the barrier layer 4, The portion is characterized by being formed to extend at least to the drain electrode 7 side. Since the other configuration is the same as that of the heterojunction field effect transistor according to the first embodiment shown in FIG. 1, detailed description thereof is omitted here.

<Manufacturing method>
Next, a method for manufacturing a heterojunction field effect transistor according to the second embodiment will be described.

  FIG. 15 is a diagram showing an example of the manufacturing process of the heterojunction field effect transistor according to the second embodiment. As shown in FIG. 15, the heterojunction field effect transistor according to the second embodiment is characterized in that a gate electrode forming step is performed after a protective film forming step. The epi fabrication process, source / drain electrode formation process, and element isolation formation process shown in FIG. 15 are the same as those in the first embodiment, and thus description thereof is omitted here. Below, a protective film formation process, a protective film processing process, and a gate electrode formation process are demonstrated in order using FIGS.

<Protective film formation process>
After the element isolation formation step, as shown in FIG. 16, a protective film 9 made of aluminum oxide is formed on the barrier layer 4 in a region other than the region where the source electrode 6 and the drain electrode 7 are formed. In addition, since the formation method of the protective film 9 is the same as that of Embodiment 1, detailed description is abbreviate | omitted here.

<Protective film processing process>
After the formation of the protective film 9, as shown in FIG. 17, a resist pattern 15 is formed on the barrier layer 4, the source electrode 6, and the drain electrode 7 in a region other than the gate electrode formation region 13 by photolithography. As a result, the resist pattern 15 has an opening corresponding to the gate electrode formation region 13.

  Next, as shown in FIG. 18, the protective film 9 exposed from the opening of the resist pattern 15 is removed by using a wet etching method or a dry etching method. As a result, the protective film 9 has an opening corresponding to the gate electrode formation region 13. At this time, the chemical film and temperature conditions used in the wet etching method, or the gas species and plasma conditions used in the dry etching method, the protective film 9 can be etched, but the barrier layer 4 can be almost etched. In other words, it is desirable that the etching rate of the barrier layer 4 is two orders of magnitude slower than the etching rate of the protective film 9.

  After removing the protective film 9 exposed from the opening of the resist pattern 15, the resist pattern 15 is removed. In order to remove the chemical component used in the wet etching method from the adsorption to the surface of the barrier layer 4 or the damage to the surface of the barrier layer 4 applied by the dry etching method, heat treatment may be performed in a nitrogen atmosphere. Desirably, the temperature of the heat treatment is desirably in the range of 300 ° C to 500 ° C.

<Gate electrode formation process>
Next, as shown in FIG. 19, the opening width in the gate length direction of the protective film 9, that is, the opening width that is longer than the opening width of the opening corresponding to the gate electrode formation region 13 formed in the protective film 9. A resist pattern 16 is formed.

  Next, a metal serving as a Schottky electrode is deposited in the opening of the resist pattern 16 by the same method as in the first embodiment. Thereafter, when the resist pattern 16 is removed, the gate electrode 5 as shown in FIG. 14 is formed from the opening of the barrier layer 4 to a part on the protective film 9, and the gate electrode 5 having a T-shaped cross section is formed. It is formed. Thus, the gate electrode 5 is formed from the opening of the barrier layer 4 to a part on the protective film 9 by the lift-off method. After forming the gate electrode 5, annealing may be performed at a predetermined temperature.

  Here, another method for forming the gate electrode 5 will be described.

  After forming the protective film 9 as shown in FIG. 16, a metal 17 serving as a Schottky electrode is formed on the barrier layer 4, the source electrode 6, the drain electrode 7, and the protective film 9 as shown in FIG. 20. Next, as shown in FIG. 21, a resist pattern 18 having a width corresponding to the length of the portion of the T-type gate electrode 5 covering the protective film 9 is formed on the metal 17 and the T-type gate electrode 5. It forms in the area | region to form. Then, as shown in FIG. 22, the metal 17 not covered with the resist pattern 18 is removed by a wet etching method using a chemical solution that dissolves the metal 17 or a dry etching method such as ion milling. Stop when you reach. Thereafter, when the resist pattern 18 is removed, a T-type gate electrode 5 similar to that shown in FIG. 14 is formed.

  The shape of the gate electrode 5 may be a Γ shape that covers only the drain electrode 7 side on the protective film 9 as shown in FIG. Since the gate electrode 5 has a Γ shape, the electric field concentrates also in the vicinity of the end portion of the gate electrode 5 that covers the drain electrode 7 side on the protective film 9. Can be reduced, and current collapse can be further suppressed.

  Further, as shown in FIG. 24, the length of the portion of the gate electrode 5 covering the protective film 9 may be different between the source electrode 6 side and the drain electrode 7 side. The length of the portion of the gate electrode 5 covering the protective film 9 is such that the electric field intensity is suppressed at the end of the gate electrode 5, the capacitance Cgs between the source electrode 6 and the gate electrode 5 is reduced, and the gate electrode 5. What is necessary is just to determine according to the reduction | decrease amount of the capacity | capacitance Cgd between 1 and a drain electrode. By adopting such a configuration, it is possible to improve the gain of the high frequency characteristics due to the capacity reduction.

  From the above, according to the second embodiment, the heterojunction field effect transistor includes the protective film 9 made of aluminum oxide on the barrier layer 4 containing In, and the protective film 9 is made of aluminum oxide. The ratio of oxygen to aluminum is 1.97 or more. Further, the gate electrode 5 has a part covering a part on the protective film 9, and the part is formed to extend at least to the drain electrode 7 side. Therefore, since the electric field strength at the end of the gate electrode 5 covering the drain electrode 7 side on the protective film 9 is reduced, the occurrence of current collapse can be further suppressed as compared with the first embodiment. In addition, by optimizing the length of the portion of the gate electrode 5 covering the protective film 9, it is possible to improve the gain of the high frequency characteristics due to the capacitance reduction.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5 gate electrode, 6 source electrode, 7 drain electrode, 8 element isolation region, 9 protective film, 10, 11 resist pattern, 12 ions, 13 gate electrode formation region 14, 15, 16 Resist pattern, 17 Metal, 18 Resist pattern.

Claims (7)

A heterojunction field effect transistor made of a nitride semiconductor,
A first nitride semiconductor layer;
A second nitride semiconductor layer formed on the first nitride semiconductor layer and forming a heterojunction with the first nitride semiconductor layer and including at least In;
A gate electrode formed in a predetermined region on the second nitride semiconductor layer;
A source electrode and a drain electrode formed on the second nitride semiconductor layer on one side and the other side of the gate electrode, respectively
A protective film made of aluminum oxide formed on a region of the second nitride semiconductor layer other than a region where the gate electrode, the source electrode, and the drain electrode are formed;
With
The heterojunction field effect transistor according to claim 1, wherein the protective film has a ratio of oxygen to aluminum in the aluminum oxide of 1.97 or more.   The gate electrode has a portion that covers a part of the surface of the protective film opposite to the second nitride semiconductor layer, and the portion is formed to extend at least to the drain electrode side. The heterojunction field effect transistor according to claim 1, characterized in that it is characterized in that: A method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor,
(A) forming a first nitride semiconductor layer;
(B) After the step (a), forming a second nitride semiconductor layer containing at least In and forming a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer;
(C) after the step (b), forming a source electrode and a drain electrode on the second nitride semiconductor layer and on one side and the other side of the region where the gate electrode is to be formed; ,
(D) after the step (c), forming the gate electrode in a region where the gate electrode is to be formed on the second nitride semiconductor layer;
(E) After the step (d), on the second nitride semiconductor layer, a protective film made of aluminum oxide in a region other than the region where the gate electrode, the source electrode, and the drain electrode are formed Forming an ALD (Atomic Layer Deposition) method,
With
The heterojunction field effect characterized in that, in the step (e), the ratio of the amount of ozone supplied to the total amount of gas supplied at the time of ozone supply when forming the protective film is 5.7% or more. Type transistor manufacturing method.   4. The method of manufacturing a heterojunction field effect transistor according to claim 3, wherein, in the step (e), the protective film has a ratio of oxygen to aluminum in the aluminum oxide of 1.97 or more. A method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor,
(A) forming a first nitride semiconductor layer;
(B) After the step (a), forming a second nitride semiconductor layer containing at least In and forming a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer;
(C) after the step (b), forming a source electrode and a drain electrode on the second nitride semiconductor layer and on one side and the other side of the region where the gate electrode is to be formed; ,
(D) After the step (c), a protective film made of aluminum oxide is formed on the second nitride semiconductor layer other than the region where the source electrode and the drain electrode are formed. Forming by the Deposition method,
(E) after the step (d), forming an opening in a region of the protective film corresponding to a region where the gate electrode is to be formed, and forming the gate electrode in the opening;
With
The heterojunction field effect characterized in that, in the step (d), the ratio of the amount of ozone supplied to the total amount of gas supplied at the time of ozone supply when forming the protective film is 5.7% or more. Type transistor manufacturing method.   6. The method of manufacturing a heterojunction field effect transistor according to claim 5, wherein, in the step (d), the protective film has a ratio of oxygen to aluminum in the aluminum oxide of 1.97 or more.   In the step (e), the gate electrode has a portion covering a part on the surface of the protective film opposite to the second nitride semiconductor layer, and the portion extends at least to the drain electrode side. The method of manufacturing a heterojunction field effect transistor according to claim 5, wherein the heterojunction field effect transistor is formed.

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