JPWO2004084597A1

JPWO2004084597A1 - MATERIAL FOR MULTILAYER WIRING BOARD CONTAINING CAPACITOR, MULTILAYER WIRING BOARD SUBSTRATE, MULTILAYER WIRING BOARD AND METHOD FOR PRODUCING THE SAME

Info

Publication number: JPWO2004084597A1
Application number: JP2005503751A
Authority: JP
Inventors: 島田　靖; 靖島田; 近藤　裕介; 裕介近藤; 斑目　健; 健斑目; 大塚　和久; 和久大塚; 島山　裕一; 裕一島山; 山口　正憲; 正憲山口; 悦男水嶋; 山本　和徳; 和徳山本; 高根沢　伸; 伸高根沢; 恭神代; 平田　善毅; 善毅平田
Original assignee: Resonac Corporation; Hitachi Chemical Co Ltd; Showa Denko Materials Co Ltd
Current assignee: Resonac Corporation; Showa Denko Materials Co Ltd
Priority date: 2003-03-20
Filing date: 2004-03-19
Publication date: 2006-06-29
Anticipated expiration: 2024-03-19
Also published as: WO2004084597A1; TW200424059A; JP4192946B2; TWI251536B

Abstract

本発明は、金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたことを特徴とするコンデンサ内蔵多層配線板用材料、多層配線板用基板および多層配線板と、これらの製造方法に関する。本発明によると、高密度配線化に優れ、かつ経済性に優れたコンデンサ内蔵多層配線板を提供することができる。The present invention relates to a multilayer wiring board material with a built-in capacitor, characterized in that a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil. The present invention relates to a circuit board, a multilayer wiring board, and a method for producing them. According to the present invention, it is possible to provide a multilayer wiring board with a built-in capacitor that is excellent in high-density wiring and excellent in economic efficiency.

Description

本発明は、コンデンサを内蔵した多層配線板用材料、多層配線板用基板および多層配線板と、これらの製造方法に関する。 The present invention relates to a multilayer wiring board material having a built-in capacitor, a multilayer wiring board substrate, a multilayer wiring board, and a method for manufacturing the same.

近年、電子機器は小型化・高機能化の要求が益々高まっている。機器の高機能化に伴い、搭載する半導体チップやコンデンサをはじめとする受動素子などの電子部品点数は増加し、従来の高密度化技術では小型化への対応が非常に困難となってきている。そこで、より効率的な実装を行うため搭載部品の一部を配線板内部に内蔵化する必要性が出てきた。
多層配線板に内蔵されるコンデンサの容量は数百ｐＦ〜数μＦレベルであり、５００ｐＦ／ｍｍ^２以上の容量密度が必要となる。コンデンサの誘電体としては、樹脂と高誘電率無機フィラーのコンポジット材料を用いる方法と無機薄膜材料を用いる方法とがある。高い容量密度のコンデンサを形成するためには、１）比誘電率の高い誘電体を用いること、２）厚みの薄い誘電体を用いることが効果的である。前者のコンポジット材料では、１）樹脂自体は比較的誘電率が低いために高誘電率化に限界があること、２）リーク電流がなく、かつ膜厚が数μｍレベルの絶縁膜を形成することは技術的に難しいことから、５００ｐＦ／ｍｍ^２以上の容量密度を有するコンデンサを得ることは難しかった。したがって、５００ｐＦ／ｍｍ^２以上の容量密度を有するコンデンサを得るためには、膜厚を数μｍ以下で形成可能な無機薄膜を利用することが必要である。
樹脂を用いた多層配線板の中に薄膜コンデンサを内蔵化する手法としては、ＣＶＤ法を用いた方法（特開平５−１９１０５３号公報の第４頁、第１図；特開平５−２２６８４４号公報の第４頁、第１図）や、スパッタリング法を用いた方法（特開２００２−２５２２９７号公報の第６頁、第１図）、あるいはゾルゲル法を用いる方法（特開平８−２１３７５４号公報の第１２頁、第２１図；特開平８−２１３７５８号公報の第１４頁、第２１図）などが提案されている。これらの手法により、樹脂を用いた多層配線板の中に膜厚が薄い誘電体薄膜を形成することができる。
しかし、特開平５−１９１０５３号公報および特開平５−２２６８４４号公報に開示された手法ではコンデンサ電極に対して任意の位置に引き出しパターンを形成できないために高密度配線化に限界があった。また、回路パターン上に薄膜を形成するために薄膜厚みの制御が難しかった。また、特開２００２−２５２２９７号公報に開示された手法では、任意の位置に引き出しパターンを形成しようとすると工程が複雑になり、経済性が悪かった。さらに、特開平８−２１３７５４号公報および特開平８−２１３７５８号公報に開示された手法では同一平面上に独立した電源パターンを形成することが困難だった。In recent years, there has been an increasing demand for downsizing and high functionality of electronic devices. As the functionality of devices increases, the number of electronic components such as mounted semiconductor chips and capacitors and other passive elements has increased, making it difficult to reduce the size with conventional high-density technologies. . Therefore, in order to perform more efficient mounting, it has become necessary to incorporate some of the mounted components inside the wiring board.
The capacitance of the capacitor built in the multilayer wiring board is several hundred pF to several μF level, and a capacitance density of 500 pF / mm ² or more is required. As a dielectric of a capacitor, there are a method using a composite material of a resin and a high dielectric constant inorganic filler and a method using an inorganic thin film material. In order to form a capacitor with a high capacitance density, it is effective to 1) use a dielectric having a high relative dielectric constant and 2) use a thin dielectric. In the former composite material, 1) the resin itself has a relatively low dielectric constant, so that there is a limit to increasing the dielectric constant; Is technically difficult, it was difficult to obtain a capacitor having a capacitance density of 500 pF / mm ² or more. Therefore, in order to obtain a capacitor having a capacitance density of 500 pF / mm ² or more, it is necessary to use an inorganic thin film that can be formed with a film thickness of several μm or less.
As a method of incorporating a thin film capacitor in a multilayer wiring board using resin, a method using a CVD method (Japanese Patent Laid-Open No. 5-191053, page 4, FIG. 1; Japanese Patent Laid-Open No. 5-226844). Page 4, Fig. 1), a method using a sputtering method (page 6, Fig. 1 of JP-A-2002-252297), or a method using a sol-gel method (JP-A-8-213754). 12th page, FIG. 21; 14th page, FIG. 21) of Japanese Patent Laid-Open No. 8-213758, etc. have been proposed. By these techniques, a thin dielectric film can be formed in a multilayer wiring board using resin.
However, the methods disclosed in Japanese Patent Application Laid-Open Nos. 5-191053 and 5-226844 have a limit to high-density wiring because a lead pattern cannot be formed at an arbitrary position with respect to the capacitor electrode. In addition, since the thin film is formed on the circuit pattern, it is difficult to control the thickness of the thin film. Further, in the method disclosed in Japanese Patent Application Laid-Open No. 2002-252297, an attempt to form a drawing pattern at an arbitrary position complicates the process and is not economical. Furthermore, it has been difficult to form independent power supply patterns on the same plane by the methods disclosed in Japanese Patent Application Laid-Open Nos. 8-213754 and 8-213758.

本発明は、金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたことを特徴とするコンデンサ内蔵多層配線板用材料、コンデンサ内蔵多層配線板用基板およびコンデンサ内蔵多層配線板の製造方法に関する。
本発明の実施形態によると、膜厚が均一で容量のばらつきが小さいコンデンサ内蔵多層配線板を提供することができる。
Ａ．本発明は、以下の実施形態に関する。
（１）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたことを特徴とするコンデンサ内蔵多層配線板用材料。
（２）誘電体薄膜がチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、チタン酸鉛、チタン酸ビスマス、二酸化チタン、ジルコン酸バリウム、ジルコン酸カルシウム、ジルコン酸鉛、チタン酸バリウムストロンチウム、チタン酸ジルコン酸鉛、ニオブ酸マグネシウム酸鉛−チタン酸鉛のいずれか、あるいはこれらのいずれか２種以上を含む固溶体、あるいはこれらのいずれか２種以上を含む積層体からなる膜であることを特徴とする（１）のコンデンサ内蔵多層配線板用材料。
（３）金属箔が銅からなり、かつ誘電体薄膜が形成される面に銅の酸化保護皮膜となる金属として、白金、金、銀、パラジウム、ルテニウム、イリジウムからなる群から選ばれた１種以上の金属膜を設けたことを特徴とする（１）および（２）のコンデンサ内蔵多層配線板用材料。
（４）金属箔が銅からなり、かつその表面に安定した自己酸化皮膜を形成する金属として、クロム、モリブデン、チタン、ニッケルからなる群から選ばれた１種以上の金属膜を設けたことを特徴とする（１）および（２）に記載のコンデンサ内蔵多層配線板用材料。
（５）金属箔の表面粗さが０．０１〜０．５μｍであることを特徴とする（１）〜（４）のコンデンサ内蔵多層配線板用材料。
（６）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜を真空蒸着法により形成することを特徴とするコンデンサ内蔵多層配線板用材料の製造方法。
（７）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜をイオンプレーティング法により形成することを特徴とするコンデンサ内蔵多層配線板用材料の製造方法。
（８）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜をＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法により形成することを特徴とするコンデンサ内蔵多層配線板用材料の製造方法。
（９）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜をスパッタリング法により形成することを特徴とするコンデンサ内蔵多層配線板用材料の製造方法。
（１０）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜をゾルゲル法により形成することを特徴とするコンデンサ内蔵多層配線板用材料の製造方法。
（１１）ロール状の金属箔を用い、かつ温度が一定に管理された加熱炉内を連続的に金属箔を移動させながら誘電体薄膜を形成することを特徴とする（６）〜（１０）のコンデンサ内蔵多層配線板材料の製造方法。
（１２）誘電体薄膜がチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、チタン酸鉛、チタン酸ビスマス、二酸化チタン、ジルコン酸バリウム、ジルコン酸カルシウム、ジルコン酸鉛、チタン酸バリウムストロンチウム、チタン酸ジルコン酸鉛、ニオブ酸マグネシウム酸鉛−チタン酸鉛のいずれか、あるいはこれらのいずれか２種以上を含む固溶体、あるいはこれらのいずれか２種以上を含む積層体からなる膜であることを特徴とする（６）〜（１１）のコンデンサ内蔵多層配線板用材料の製造方法。
（１３）金属箔が銅からなり、かつ誘電体薄膜が形成される面に銅の酸化保護皮膜となる金属として、白金、金、銀、パラジウム、ルテニウム、イリジウムからなる群から選ばれた１種以上の金属膜を設けたことを特徴とする（６）〜（１２）に記載のコンデンサ内蔵多層配線板用材料の製造方法。
（１４）金属箔が銅からなり、かつその表面に安定した自己酸化皮膜を形成する金属として、クロム、モリブデン、チタン、ニッケルからなる群から選ばれた１種以上の金属膜を設けたことを特徴とする（６）〜（１２）に記載のコンデンサ内蔵多層配線板用材料の製造方法。
（１５）金属箔の表面粗さが０．０１〜０．５μｍであることを特徴とする（６）〜（１４）記載のコンデンサ内蔵多層配線板用材料の製造方法。
（１６）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に１０〜５０μｍの金属層を形成する工程と、３）その金属層の任意の部分を残してエッチング除去して所望のコンデンサ電極１を形成する工程と、４）誘電体薄膜の少なくともコンデンサ電極１を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、５）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望のコンデンサ電極２を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１７）誘電体薄膜の表面に形成する金属層がクロム、モリブデン、チタン、ニッケルからなる群から選ばれた１種以上の金属層を少なくとも含むことを特徴とする（１６）のコンデンサ内蔵多層配線板の製造方法。
（１８）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に０．１〜５μｍの金属層を形成する工程と、３）コンデンサ電極１を含む任意の部分を残して金属めっきレジストを形成する工程と、４）金属めっきにより１０〜５０μｍのコンデンサ電極１を形成する工程と、５）金属めっきレジストを除去する工程と、６）誘電体薄膜の表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、７）誘電体薄膜の少なくともコンデンサ電極１を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、８）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望のコンデンサ電極２を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１９）誘電体薄膜の表面に形成する金属層がクロム、モリブデン、チタン、ニッケルからなる群から選ばれた少なくとも１種以上の金属層を含むことを特徴とする（１８）記載のコンデンサ内蔵多層配線板の製造方法。
（２０）金属めっきが銅、銀、錫、ニッケル、亜鉛からなる群から選ばれた少なくとも１種以上の金属を含むことを特徴とする（１８）、（１９）記載のコンデンサ内蔵多層配線板の製造方法。
（２１）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて１０〜５０μｍの金属層を形成して所望のコンデンサ電極１を形成する工程と、３）誘電体薄膜の少なくともコンデンサ電極１を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望のコンデンサ電極２を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２２）化学的な反応により金属化される導電性ペーストの金属粒子が金、白金、銀、銅、パラジウム、ルテニウムからなる群から選ばれた少なくとも１種以上の金属を含み、かつその平均粒径が０．１〜１０ｎｍであることを特徴とする（２１）のコンデンサ内蔵多層配線板の製造方法。
（２３）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）コンデンサ誘電体を形成した基板表面に１０〜５０μｍの金属層を形成する工程と、４）その金属層の任意の部分を残してエッチング除去して所望のコンデンサ電極１、コンデンサ電極２およびコンデンサ電極と電気的に絶縁された任意の導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２４）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料の金属箔の面と導体回路を有する基板とを介して積層するプリプレグにおいて、任意の箇所に絶縁材料の貫通穴が設けられ、かつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されていることを特徴とする（１６）〜（２３）記載のコンデンサ内蔵多層配線板の製造方法。
（２５）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料の金属箔の面と導体回路を有する基板とを介して積層するプリプレグにおいて、任意の箇所に絶縁材料の貫通穴が設けられ、かつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されていることを特徴とする（１６）〜（２３）記載のコンデンサ内蔵多層配線板の製造方法。
（２６）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に１０〜５０μｍの金属層を形成する工程と、３）その金属層の任意の部分を残してエッチング除去して所望のコンデンサ電極１を形成する工程と、４）誘電体薄膜の少なくともコンデンサ電極１を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、５）誘電体薄膜を除去して現れた金属層の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、６）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、７）その基板表面に０．１〜５μｍの金属層を形成する工程と、８）穴を含む任意の箇所を除いてめっきレジストを形成する工程と、９）めっきレジストを形成した箇所以外の基板表面に１０〜５０μｍの金属層を形成して層間の回路パターンを電気的に接続させる工程と、１０）基板表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、１１）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望のコンデンサ電極２を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２７）誘電体薄膜の表面に形成する金属層がクロム、モリブデン、チタン、ニッケルからなる群から選ばれた１種以上の金属層を少なくとも含むことを特徴とする（２６）のコンデンサ内蔵多層配線板の製造方法。
（２８）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に０．１〜５μｍの金属層を形成する工程と、３）コンデンサ電極１を含む任意の部分を残して金属めっきレジストを形成する工程と、４）金属めっきにより１０〜５０μｍのコンデンサ電極１を形成する工程と、５）金属めっきレジストを除去する工程と、６）誘電体薄膜の表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、７）誘電体薄膜の少なくともコンデンサ電極１を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、８）誘電体薄膜を除去して現れた金属層の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、９）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、１０）その基板表面に０．１〜５μｍの金属層を形成する工程と、１１）穴を含む任意の箇所を除いてめっきレジストを形成する工程と、１２）めっきレジストを形成した箇所以外の基板表面に１０〜５０μｍの金属層を形成して層間の回路パターンを電気的に接続させる工程と、１３）基板表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、１４）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望のコンデンサ電極２を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２９）誘電体薄膜の表面に形成する金属層がクロム、モリブデン、チタン、ニッケルからなる群から選ばれた少なくとも１種以上の金属層を含むことを特徴とする（２８）のコンデンサ内蔵多層配線板の製造方法。
（３０）金属めっきが銅、銀、錫、ニッケル、亜鉛からなる群から選ばれた少なくとも１種以上の金属を含むことを特徴とする（２８）、（２９）記載のコンデンサ内蔵多層配線板の製造方法。
（３１）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて１０〜５０μｍの金属層を形成して所望のコンデンサ電極１を形成する工程と、３）誘電体薄膜の少なくともコンデンサ電極１を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属層の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、５）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、６）その基板表面に０．１〜５μｍの金属層を形成する工程と、７）穴を含む任意の箇所を除いてめっきレジストを形成する工程と、８）めっきレジストを形成した箇所以外の基板表面に１０〜５０μｍの金属層を形成して層間の回路パターンを電気的に接続させる工程と、９）基板表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、１０）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望のコンデンサ電極２を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（３２）化学的な反応により金属化される導電性ペーストの金属粒子が金、白金、銀、銅、パラジウム、ルテニウムからなる群から選ばれた少なくとも１種以上の金属を含み、かつその平均粒径が０．１〜１０ｎｍであることを特徴とする（３１）のコンデンサ内蔵多層配線板の製造方法。
（３３）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）誘電体薄膜を除去して現れた金属層の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、４）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、５）コンデンサ誘電体を形成した基板表面と穴内の表面に１０〜５０μｍの金属層を形成する工程と、６）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望のコンデンサ電極２を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（３４）金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して積層する導体回路を有する基板において、基板の導体層が２層以上あり、かつその隣接する導体層の回路パターンが任意の箇所で導体化された穴により接続された基板であることを特徴とする（１６）〜（３３）記載のコンデンサ内蔵多層配線板の製造方法。
（３５）誘電体薄膜をエッチング除去する方法がイオンビームエッチング法、ＲＩＥ（ＲｅａｃｔｉｖｅＩｏｎＥｔｃｈｉｎｇ）法または溶液エッチング法のいずれかであることを特徴とする（１６）〜（３４）記載のコンデンサ内蔵多層配線板の製造方法。
（３６）コンデンサ電極２が多層配線板のグランド層または電源層であることを特徴とする（１６）〜（３５）記載のコンデンサ内蔵多層配線板の製造方法。
（３７）基板の絶縁材料が樹脂とガラス織布またはガラス不織布からなることを特徴とする（１６）〜（３６）記載のコンデンサ内蔵多層配線板の製造方法。
（３８）基板の絶縁材料に用いられている樹脂が熱硬化性樹脂であり、そのガラス転移点温度が１７０℃以上であることを特徴とする（１６）〜（３７）記載のコンデンサ内蔵多層配線板の製造方法。
Ｂ．さらに、本発明は、以下の実施形態に関する。
（１）基板内部に導体層間を接続するバイアホールを有し，かつ、表面に平滑な金属層を有する基板の表面に比誘電率が１０〜２０００で、かつ、膜厚が０．０５〜２μｍの誘電体薄膜を形成したことを特徴とするコンデンサ内蔵多層配線板用基板。
（２）基板内部に導体層間を接続するバイアホールが金属めっきにより電気的に接続されていることを特徴とする（１）のコンデンサ内蔵多層配線板用基板。
（３）基板内部に導体層間を接続するバイアホールが金属粉と樹脂とからなる導電性ペーストにより電気的に接続されていることを特徴とする（１）のコンデンサ内蔵多層配線板用基板。
（４）基板内部に導体層間を接続するバイアホールが化学的な反応により金属化される導電性ペーストにより電気的に接続されていることを特徴とする（１）または（３）のコンデンサ内蔵多層配線板用基板。
（５）誘電体薄膜がチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、チタン酸鉛、チタン酸ビスマス、二酸化チタン、ジルコン酸バリウム、ジルコン酸カルシウム、ジルコン酸鉛のいずれか、あるいはこれらのいずれかを含む２種以上の固溶体、あるいはこれらのいずれかを含む２種以上の積層体からなる膜であることを特徴とする（１）ないし（４）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（６）誘電体薄膜の形成方法が真空蒸着法、イオンプレーティング法、ＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法、スパッタリング法、ゾルゲル法のいずれかであることを特徴とする（１）ないし（５）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（７）誘電体薄膜の形成時の基板温度が２５℃〜３５０℃であることを特徴とする（１）ないし（６）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（８）基板の絶縁材料が樹脂とガラス織布またはガラス不織布からなることを特徴とする（１）ないし（７）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（９）基板の絶縁材料に用いられている樹脂が熱硬化性樹脂であり，そのガラス転移点温度が１７０℃以上であることを特徴とする（１）ないし（８）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（１０）基板表面の金属層が銅からなり，かつその表面に銅の酸化保護皮膜となる金属として、白金、金、銀、パラジウム、ルテニウム、イリジウムからなる群から選ばれた１種以上の金属膜を設けることを特徴とする（１）ないし（９）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（１１）基板表面の金属層が銅からなり，かつその表面に安定した自己酸化皮膜を形成する金属として、クロム、モリブデン、チタン、ニッケルからなる群から選ばれた少なくとも１種以上の金属膜を設けることを特徴とする（１）ないし（９）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（１２）基板表面の金属層の表面粗さが０．０１〜０．５μｍであることを特徴とする（１）ないし（１１）のいずれかに記載のコンデンサ内蔵多層配線板用基板。
（１３）（１）ないし（１２）のいずれかに記載のコンデンサ内蔵多層配線板用基板を内層板として用いるコンデンサ内蔵多層配線板の製造方法であって、１）誘電体薄膜の表面に１０〜５０μｍの金属層を形成する工程と、２）その金属層の任意の部分を残してエッチング除去して所望の第１のコンデンサ電極を形成する工程と、３）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１４）誘電体薄膜の表面に形成する金属層がクロム、モリブデン、チタン、ニッケルからなる群から選ばれた少なくとも１種以上の金属層を含むことを特徴とする（１３）のコンデンサ内蔵多層配線板の製造方法。
（１５）（１）ないし（１２）のいずれかに記載のコンデンサ内蔵多層配線板用基板を内層板として用いるコンデンサ内蔵多層配線板の製造方法であって、１）誘電体薄膜の表面に０．１〜５μｍの金属層を形成する工程と、２）第１のコンデンサ電極を含む任意の部分を残して金属めっきレジストを形成する工程と、３）金属めっきにより１０〜５０μｍの第１のコンデンサ電極を形成する工程と、４）金属めっきレジストを除去する工程と、５）誘電体薄膜の表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、６）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、７）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１６）誘電体薄膜の表面に形成する金属層がクロム、モリブデン、チタン、ニッケルからなる群から選ばれた少なくとも１種以上の金属層を含むことを特徴とする（１５）のコンデンサ内蔵多層配線板の製造方法。
（１７）金属めっきが銅、銀、錫、ニッケル、亜鉛からなる群から選ばれた少なくとも１種以上の金属を含むことを特徴とする（１５）または（１６）に記載のコンデンサ内蔵多層配線板の製造方法。
（１８）（１）ないし（１２）のいずれかに記載のコンデンサ内蔵多層配線板用基板を内層板として用いるコンデンサ内蔵多層配線板の製造方法であって、１）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて１０〜５０μｍの金属層を形成して所望の第１のコンデンサ電極を形成する工程と、２）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１９）化学的な反応により金属化される導電性ペーストの金属粒子が金，白金，銀，銅，パラジウム、ルテニウムからなる群から選ばれた少なくとも１種以上の金属を含み、かつ、その平均粒径が０．１〜１０ｎｍであることを特徴とする（１８）のコンデンサ内蔵多層配線板の製造方法。
（２０）（１）ないし（１２）のいずれかに記載のコデンサ内蔵多層配線板用基板を内層板として用いるコンデンサ内蔵多層配線板の製造方法であって、１）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、２）コンデンサ誘電体を形成した基板表面に１０〜５０μｍの金属層を形成する工程と、３）その金属層の任意の部分を残してエッチング除去して所望の第１のコンデンサ電極、第２のコンデンサ電極およびコンデンサ電極と電気的に絶縁された任意の導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２１）誘電体薄膜をエッチング除去する方法がイオンビームエッチング法、ＲＩＥ（ＲｅａｃｔｉｖｅＩｏｎＥｔｃｈｉｎｇ）法または溶液エッチング法のいずれかであることを特徴とする（１３）ないし（２０）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２２）第２のコンデンサ電極が多層配線板のグランド層または電源層であることを特徴とする（１３）ないし（２１）のいずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２３）複数の絶縁層と複数の導体層と前記導体層を電気的に接続する導体化されたバイアホールを有する多層配線板であり、かつ、少なくとも１層の絶縁層の比誘電率が２０〜２０００、かつ、膜厚が０．１〜１μｍの誘電体薄膜であり、その絶縁層に対向した電極を備えたコンデンサ内蔵多層配線板であって、１）第１のコンデンサ電極を形成する導体層のパターンは全てコンデンサの電極を形成し、２）誘電体薄膜の投影面は第１のコンデンサ電極の投影面を含み、３）第２のコンデンサ電極を形成する導体層には第２のコンデンサ電極とこの電極と電気的に絶縁された少なくとも１つのパターンを有することを特徴とするコンデンサ内蔵多層配線板。
（２４）複数の絶縁層と複数の導体層と前記導体層を電気的に接続する導体化されたバイアホールを有する多層配線板であり、かつ、少なくとも１層の絶縁層の比誘電率が２０〜２０００、かつ、膜厚が０．１〜１μｍの誘電体薄膜であり、その絶縁層に対向した電極を備えたコンデンサ内蔵多層配線板であって、１）コンデンサの誘電体を形成する誘電体薄膜の投影面に含まれる第１のコンデンサ電極を有し、２）誘電体薄膜の端部は全て第１のコンデンサ電極を形成する導体層が第２のコンデンサ電極に電気的に接続されたことを特徴とするコンデンサ内蔵多層配線板。
（２５）第２のコンデンサ電極が多層配線板のグランド層または電源層であることを特徴とする（２３）または（２４）に記載のコンデンサ内蔵多層配線板。
（２６）誘電体薄膜がチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、チタン酸鉛、チタン酸ビスマス、二酸化チタン、ジルコン酸バリウム、ジルコン酸カルシウム、ジルコン酸鉛のいずれか、あるいはこれらのいずれかを含む２種以上の固溶体、あるいはこれらのいずれかを含む２種以上の積層体からなる膜であることを特徴とする（２３）ないし（２５）のいずれかに記載のコンデンサ内蔵多層配線板。
（２７）基板の絶縁材料が樹脂とガラス織布またはガラス不織布からなることを特徴とする（２３）ないし（２６）のいずれかに記載のコンデンサ内蔵多層配線板。
（２８）基板の絶縁材料に用いられている樹脂が熱硬化性樹脂であり，そのガラス転移点温度が１７０℃以上であることを特徴とする（２３）ないし（２７）のいずれかに記載のコンデンサ内蔵多層配線板。
（２９）第２のコンデンサ電極が銅からなり，かつ、その表面に、白金、金、銀、パラジウム、ルテニウム、イリジウム、クロム、モリブデン、チタン、ニッケルからなる群から選ばれた少なくとも１種以上の金属層を含むことを特徴とする（２３）ないし（２８）いずれかに記載のコンデンサ内蔵多層配線板。
（３０）第２のコンデンサ電極の表面粗さが０．０１〜０．５μｍであることを特徴とする（２３）ないし（２９）のいずれかに記載のコンデンサ内蔵多層配線板。
（３１）第１のコンデンサ電極が銅、銀、錫、ニッケル、亜鉛、クロム、モリブデン、チタン、ニッケルからなる群から選ばれた少なくとも１種以上の金属層を含むことを特徴とする（２３）ないし（３０）のいずれかに記載のコンデンサ内蔵多層配線板。
（３２）第１のコンデンサ電極が化学的な反応により金属化された導電性ペーストからなり、その金属が白金，金，銀，銅，錫，パラジウム、ルテニウムからなる群から選ばれた少なくとも１種以上の金属を含むことを特徴とする（２３）ないし（３０）のいずれかに記載のコンデンサ内蔵多層配線板。
（３３）（２３）ないし（３２）のいずれかに記載のコンデンサ内蔵多層配線板に半導体チップを搭載させたことを特徴とする半導体装置。
Ｃ．さらに、本発明は次の実施形態に関する。
（１）金属箔の片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を、金属箔が絶縁材料と接するように絶縁材料の少なくとも片面に設けた基板を用いるコンデンサ内蔵多層配線板の製造方法であって、１）基板表面の誘電体薄膜上の所定の位置にコンデンサ電極となる金属層を形成する工程と、２）少なくとも基板表面の前記金属層上にエッチングレジストを形成する工程と、３）キレート剤と過酸化水素を含むエッチャントによって、誘電体薄膜をウェットエッチングする工程と、４）ウェットエッチング後にエッチングレジストを除去する工程とを有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２）エッチャントのキレート剤濃度が０．００１〜０．５ｍｏｌ／ｌであり、かつ、過酸化水素濃度が１〜５０ｗｔ％であり、かつ、エッチャントのｐＨが２〜７の範囲であることを特徴とする（１）のコンデンサ内蔵多層配線板の製造方法。
（３）キレート剤が、エチレンジアミン四酢酸（ＥＤＴＡ）、ヒドロキシエチルイミノ二酢酸（ＨＩＤＡ）、イミノ二酢酸（ＩＤＡ）、ジヒドロキシエチルグリシン（ＤＨＥＧ）及びこれらのアルカリ塩からなる群から選ばれる少なくとも１つであることを特徴とする（１）又は（２）に記載のコンデンサ内蔵多層配線板の製造方法。
（４）金属箔の片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を、金属箔が絶縁材料と接するように絶縁材料の少なくとも片面に設けた基板を用いるコンデンサ内蔵多層配線板の製造方法であって、１）基板表面の誘電体薄膜上の所定の位置にコンデンサ電極となる金属層を形成する工程と、２）少なくとも基板表面の前記金属層上にエッチングレジストを形成する工程と、３）硫酸、塩酸、りん酸、硝酸及び酢酸からなる群から選ばれる少なくとも１つの酸と過酸化水素を含むエッチャントによって、誘電体薄膜をウェットエッチングする工程と、４）ウェットエッチング後にエッチングレジストを除去する工程とを有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（５）エッチャントの酸の濃度が１〜３０ｗｔ％であり、かつ、過酸化水素濃度が１〜５０ｗｔ％であることを特徴とする（４）のコンデンサ内蔵多層配線板の製造方法。
（６）エッチングレジストとして感光性ドライフィルムを用いることを特徴とする（１）〜（５）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（７）感光性ドライフィルムの膜厚が、感光性ドライフィルムによって形成されたエッチングレジストによりウェットエッチングから保護されるコンデンサ電極となる金属層の厚みの１〜３倍であることを特徴とする（６）のコンデンサ内蔵多層配線板の製造方法。
（８）誘電体薄膜のウェットエッチングが、液温２０〜４５℃のエッチャントで行われることを特徴とする（１）〜（７）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（９）誘電体薄膜が、チタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、チタン酸鉛、チタン酸ビスマス、二酸化チタン、ジルコン酸バリウム、ジルコン酸カルシウム及びジルコン酸鉛のいずれか、あるいはこれらのいずれか２種以上を含む固溶体、あるいはこれらのいずれか２種以上を含む積層体からなる膜であることを特徴とする（１）〜（８）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
Ｄ．さらに、本発明は以下の実施形態に関する。
（１）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所をエッチング除去して、上記絶縁材料から形成された絶縁層を露出させる工程と、３）レーザ照射により、露出された絶縁層を除去して穴を形成し、金属箔Ａを露出させる工程と、４）穴内を含む基板表面の両面に金属層を形成する工程と、５）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状のコンデンサ電極Ａパターンをエッチングで形成する工程と、６）露出された誘電体薄膜からコンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、７）誘電体薄膜を除去して現れた金属箔Ａからコンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂをエッチングで形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２）（１）のコンデンサ内蔵多層配線板の製造方法であって、５）又は７）のエッチング工程において、基板の金属箔Ｂを積層した面に任意の形状の回路を形成することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（３）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所にレーザ照射することにより、金属箔Ｂと上記絶縁材料から形成された絶縁層とを同時に除去して穴を形成し、金属箔Ａを露出させる工程と、３）穴内を含む基板表面の両面に金属層を形成する工程と、４）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状のコンデンサ電極Ａパターンをエッチングで形成する工程と、５）露出された誘電体薄膜からコンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、６）誘電体薄膜を除去して現れた金属箔Ａからコンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂをエッチングで形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（４）（３）のコンデンサ内蔵多層配線板の製造方法であって、４）又は６）のエッチング工程において、基板の金属箔Ｂを積層した面に任意の形状の回路を形成することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（５）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）基板表面の少なくとも誘電体薄膜側に金属層を形成する工程と、３）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状のコンデンサ電極Ａパターンをエッチングで形成する工程と、４）露出された誘電体薄膜からコンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、５）誘電体薄膜を除去して現れた金属箔Ａにコンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂをエッチングで形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（６）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）基板表面の少なくとも誘電体薄膜側に金属層を形成する工程と、３）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状のコンデンサ電極Ａパターンをエッチングで形成する工程と、４）露出された誘電体薄膜からコンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、５）誘電体薄膜を除去して現れた金属箔Ａからコンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂをエッチングで形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（７）（５）又は（６）のコンデンサ内蔵多層配線板の製造方法であって、３）又は５）のエッチング工程において、基板の金属箔Ｂを積層した面に任意の形状の回路を形成することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（８）上記誘電体薄膜と上記金属層との間に、クロム、モリブデン、チタン及びニッケルからなる群から選ばれた少なくとも１種の他の金属層を形成する工程を含むことを特徴とする（１）〜（７）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（９）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所をエッチング除去して、上記絶縁材料から形成された絶縁層を露出させる工程と、３）レーザ照射により露出された絶縁層を除去して穴を形成し、金属箔Ａを露出させる工程と、４）穴内を含む基板の両面に０．１〜５μｍの金属層を形成する工程と、５）コンデンサ電極Ａとなる部分と穴部を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、６）金属めっきにより、上記のコンデンサ電極Ａとなる部分と穴部を含む部分に導体パターンを形成する工程と、７）金属めっきレジストを除去する工程と、８）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、９）露出された誘電体薄膜からコンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、１０）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂを形成する工程と、１１）露出された金属箔Ｂをエッチングにより回路形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１０）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所にレーザ照射することにより、金属箔Ｂと上記の絶縁材料から形成された絶縁層とを同時に除去して穴を形成し、金属箔Ａを露出させる工程と、３）穴内を含む基板の両面に０．１〜５μｍの金属層を形成する工程と、４）コンデンサ電極Ａとなる部分と穴部を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、５）金属めっきにより、上記のコンデンサ電極Ａとなる部分と穴部を含む部分に導体パターンを形成する工程と、６）金属めっきレジストを除去する工程と、７）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、８）露出された誘電体薄膜から、コンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、９）誘電体薄膜を除去して現れた金属箔Ａから、コンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂを形成する工程と、１０）露出された金属箔Ｂをエッチングにより回路形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１１）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されているプリプレグを介して金属箔Ｂを積層し基板とする工程と、２）基板の少なくとも誘電体薄膜側の表面に０．１〜５μｍの金属層を形成する工程と、３）コンデンサ電極Ａとなる部分を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、４）金属めっきによりコンデンサ電極Ａとなる部分を含む部分に導体パターンを形成する工程と、５）金属めっきレジストを除去する工程と、６）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、７）露出された誘電体薄膜から、コンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、８）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂを形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１２）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されているプリプレグを介して金属箔Ｂを積層し基板とする工程と、２）基板の少なくとも誘電体薄膜側の表面に０．１〜５μｍの金属層を形成する工程と、３）コンデンサ電極Ａとなる部分を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、４）金属めっきによりコンデンサ電極Ａとなる部分を含む部分に導体パターンを形成する工程と、５）金属めっきレジストを除去する工程と、６）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、７）露出された誘電体薄膜から、コンデンサ電極Ａパターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、８）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂを形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１３）少なくとも誘電体薄膜の表面に形成する０．１〜５μｍの金属層が：クロム、モリブデン、チタン及びニッケルからなる群から選ばれた少なくとも１種の金属層であるか；銅、銀、錫、ニッケル及び亜鉛からなる群から選ばれた少なくとも１種の金属層であるか；又は、クロム、モリブデン、チタン及びニッケルからなる群から選ばれた少なくとも１種の金属層と銅、銀、錫、ニッケル及び亜鉛からなる群から選ばれた少なくとも１種の金属層とを含むものであることを特徴とする（９）〜（１２）のいずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（１４）金属めっきにより形成される導体パターンが、銅、銀、錫、ニッケル及び亜鉛からなる群から選ばれた少なくとも１種以上の金属を含むことを特徴とする（９）〜（１３）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（１５）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて金属層を形成して所望のコンデンサ電極Ａを形成する工程と、３）誘電体薄膜の少なくともコンデンサ電極Ａを含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂを形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１６）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて金属層を形成して所望のコンデンサ電極Ａを形成する工程と、３）誘電体薄膜の少なくともコンデンサ電極Ａを含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状のコンデンサ電極Ｂを形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１７）金属箔Ａの表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）金属箔Ｂの任意の箇所をエッチング除去して、上記絶縁材料から形成された絶縁層を露出させる工程と、４）レーザ照射により露出された絶縁層を除去して穴を形成し、金属箔Ａを露出させる工程と、５）穴内を含む基板表面の両面に金属層を形成する工程と、６）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望のコンデンサ電極Ａ及びコンデンサ電極Ｂを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１８）金属箔Ａの表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）金属箔Ｂの任意の箇所にレーザ照射することにより、金属箔Ｂと上記絶縁材料から形成された絶縁層を同時に除去して穴を形成して金属箔Ａを露出させる工程と、４）穴内を含む基板表面の両面に金属層を形成する工程と、５）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望のコンデンサ電極Ａ及びコンデンサ電極Ｂを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（１９）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）基板の少なくともコンデンサ誘電体を有する表面に金属層を形成する工程と、４）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望のコンデンサ電極Ａ及びコンデンサ電極Ｂを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２０）金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法であって、１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）基板の少なくともコンデンサ誘電体を有する表面に金属層を形成する工程と、４）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望のコンデンサ電極Ａ及びコンデンサ電極Ｂを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（２１）化学的な反応により金属化される導電性ペーストが、金、白金、銀、銅、パラジウム及びルテニウムからなる群から選ばれた少なくとも１種以上の金属粒子を含み、かつその金属粒子の平均粒径が０．１〜１０ｎｍであることを特徴とする（６）、（１２）、（１５）、（１６）又は（２０）に記載のコンデンサ内蔵多層配線板の製造方法。
（２２）誘電体薄膜をエッチング除去する方法が、イオンビームエッチング法、ＲＩＥ（ＲｅａｃｔｉｖｅＩｏｎＥｔｃｈｉｎｇ）法又は溶液エッチング法のいずれかであることを特徴とする（１）〜（２１）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２３）コンデンサ電極Ｂが多層配線板のグランド層又は電源層であることを特徴とする（１）〜（２２）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２４）基板の絶縁層の形成に用いられる絶縁材料が樹脂とガラス織布又はガラス不織布からなるプリプレグであることを特徴とする（１）〜（２３）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２５）基板の絶縁層の形成に用いられる絶縁材料が、樹脂として熱硬化性樹脂を含有するプリプレグであって、その熱硬化性樹脂のガラス転移点温度が１７０℃以上であることを特徴とする（１）〜（２４）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２６）誘電体薄膜がチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、チタン酸鉛、チタン酸ビスマス、二酸化チタン、ジルコン酸バリウム、ジルコン酸カルシウム、ジルコン酸鉛、チタン酸バリウムストロンチウム、チタン酸ジルコン酸鉛及びニオブ酸マグネシウム酸鉛−チタン酸鉛のいずれか、あるいはこれらのいずれか２種以上を含む固溶体、あるいはこれらのいずれか２種以上を含む積層体からなる膜であるコンデンサ内蔵多層配線板用材料を用いたことを特徴とする（１）〜（２５）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２７）金属箔Ａが銅からなり、かつ誘電体薄膜が形成される面に銅の酸化保護皮膜となる金属として、白金、金、銀、パラジウム、ルテニウム及びイリジウムからなる群から選ばれた１種以上の金属膜を設けたコンデンサ内蔵多層配線板用材料を用いたことを特徴とする（１）〜（２６）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２８）金属箔Ａが銅からなり、かつ誘電体薄膜が形成される面に安定した自己酸化皮膜を形成する金属として、クロム、モリブデン、チタン及びニッケルからなる群から選ばれた１種以上の金属膜を設けたコンデンサ内蔵多層配線板用材料を用いたことを特徴とする（１）〜（２６）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
（２９）金属箔Ａの誘電体薄膜が形成される面の表面粗さが０．０１〜０．５μｍであるコンデンサ内蔵多層配線板用材料を用いたことを特徴とする（１）〜（２８）いずれかに記載のコンデンサ内蔵多層配線板の製造方法。
本明細書において開示の内容は、日本国特許出願２００３−０７７６９５（出願日２００３年３月２０日）、２００３−０７８３２４（出願日２００３年３月２０日）、２００３−３６８８５７（出願日２００３年１０月２９日）および２００３−３７６６０４（出願日２００３年１１月６日）に含まれる主題に関するものであって、これらを、全体を本明細書の一部として組み込む。The present invention provides a material for a multilayer wiring board with a built-in capacitor, a multilayer with a built-in capacitor, characterized in that a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil. The present invention relates to a method for manufacturing a wiring board substrate and a multilayer wiring board with a built-in capacitor.
According to the embodiment of the present invention, it is possible to provide a multilayer wiring board with a built-in capacitor having a uniform film thickness and a small capacitance variation.
A. The present invention relates to the following embodiments.
(1) A material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of a metal foil.
(2) Dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, strontium titanate , Any one of lead zirconate titanate, lead magnesium niobate-lead titanate, a solid solution containing any two or more of these, or a film comprising a laminate containing any two or more of these (1) A material for a multilayer wiring board with a built-in capacitor.
(3) One type selected from the group consisting of platinum, gold, silver, palladium, ruthenium, and iridium as a metal that forms a copper oxide protective film on the surface on which the metal foil is made of copper and the dielectric thin film is formed. The material for a multilayer wiring board with a built-in capacitor according to (1) and (2), wherein the above metal film is provided.
(4) The metal foil is made of copper and one or more metal films selected from the group consisting of chromium, molybdenum, titanium, and nickel are provided as a metal that forms a stable self-oxidation film on the surface thereof. The capacitor-embedded multilayer wiring board material according to any one of (1) and (2).
(5) The material for a multilayer wiring board with a built-in capacitor according to (1) to (4), wherein the surface roughness of the metal foil is 0.01 to 0.5 μm.
(6) Manufacture of a material for a multilayer wiring board with a built-in capacitor, characterized in that a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by a vacuum deposition method. Method.
(7) A material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by an ion plating method. Production method.
(8) A multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by a CVD (Chemical Vapor Deposition) method. Method of manufacturing materials.
(9) A method for producing a material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by sputtering. .
(10) A method for producing a material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by a sol-gel method .
(11) A dielectric thin film is formed using a roll-shaped metal foil and moving the metal foil continuously in a heating furnace whose temperature is controlled to be constant (6) to (10) Manufacturing method for multilayer wiring board materials with built-in capacitors.
(12) Dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, strontium titanate , Any one of lead zirconate titanate, lead magnesium niobate-lead titanate, a solid solution containing any two or more of these, or a film comprising a laminate containing any two or more of these (6)-(11) The manufacturing method of the material for multilayer wiring boards with a built-in capacitor | condenser characterized by these.
(13) One metal selected from the group consisting of platinum, gold, silver, palladium, ruthenium, and iridium as a metal that forms a copper oxide protective film on the surface on which the metal foil is made of copper and the dielectric thin film is formed. The method for producing a capacitor-embedded multilayer wiring board material according to any one of (6) to (12), wherein the above metal film is provided.
(14) The metal foil is made of copper and one or more metal films selected from the group consisting of chromium, molybdenum, titanium, and nickel are provided as a metal that forms a stable self-oxidation film on the surface thereof. A method for producing a capacitor-embedded multilayer wiring board material as described in any one of (6) to (12).
(15) The method for producing a material for a multilayer wiring board with a built-in capacitor according to any one of (6) to (14), wherein the metal foil has a surface roughness of 0.01 to 0.5 μm.
(16) A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil 1) a step of laminating a substrate having a conductor circuit via a prepreg on the surface of the metal foil of the capacitor-embedded multilayer wiring board material, and 2) forming a metal layer of 10 to 50 μm on the surface of the dielectric thin film. 3) etching to remove any portion of the metal layer to form a desired capacitor electrode 1, and 4) etching to leave any portion including at least the capacitor electrode 1 of the dielectric thin film. Removing the dielectric thin film to form a desired capacitor dielectric; and 5) removing the dielectric thin film and removing it by etching, leaving at least an arbitrary portion including the capacitor dielectric. Method of manufacturing a capacitor built multilayer wiring board characterized by having a step of forming a conductive pattern including a desired capacitor electrode 2.
(17) The multilayer wiring with a built-in capacitor according to (16), wherein the metal layer formed on the surface of the dielectric thin film contains at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. A manufacturing method of a board.
(18) A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil 1) a step of laminating a substrate having a conductor circuit on the surface of a metal foil of a capacitor-embedded multilayer wiring board material through a prepreg, and 2) a metal layer having a thickness of 0.1 to 5 μm on the surface of the dielectric thin film. 3) a step of forming a metal plating resist leaving any portion including the capacitor electrode 1, 4) a step of forming a capacitor electrode 1 of 10 to 50 μm by metal plating, and 5) a metal plating A step of removing the resist, 6) a step of etching away a metal layer of 0.1 to 5 μm formed on the surface of the dielectric thin film, and 7) an option including at least the capacitor electrode 1 of the dielectric thin film. Forming a desired capacitor dielectric by etching away leaving a portion; and 8) removing the dielectric thin film by etching away leaving at least any portion of the metal layer including the capacitor dielectric as desired. A method for producing a multilayer wiring board with a built-in capacitor, comprising the step of forming a conductor pattern including the capacitor electrode 2 of the above.
(19) The multilayer with a built-in capacitor according to (18), wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. A method for manufacturing a wiring board.
(20) The multilayer wiring board with a built-in capacitor according to (18) or (19), wherein the metal plating contains at least one metal selected from the group consisting of copper, silver, tin, nickel, and zinc. Production method.
(21) A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil 1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a capacitor-embedded multilayer wiring board material through a prepreg, and 2) a chemical reaction to an arbitrary portion of the surface of the dielectric thin film. Forming a desired capacitor electrode 1 by forming a metal layer having a thickness of 10 to 50 μm using a conductive paste metallized by 3), leaving at least an arbitrary portion of the dielectric thin film including the capacitor electrode 1 Etching away to form the desired capacitor dielectric; 4) Removing the dielectric thin film and removing the metal layer leaving at least any portion containing the capacitor dielectric. Method of manufacturing a capacitor built multilayer wiring board characterized by having a step of forming a conductive pattern including a desired capacitor electrode 2 and.
(22) The average particle size of the conductive paste metallized by a chemical reaction includes at least one metal selected from the group consisting of gold, platinum, silver, copper, palladium, and ruthenium. (21) The method for producing a multilayer wiring board with a built-in capacitor according to (21), wherein the diameter is 0.1 to 10 nm.
(23) A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil 1) a step of laminating on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor on a substrate having a conductor circuit via a prepreg, and 2) etching away leaving an arbitrary portion of the dielectric thin film. A step of forming a desired capacitor dielectric, 3) a step of forming a 10-50 μm metal layer on the surface of the substrate on which the capacitor dielectric is formed, and 4) etching away leaving any portion of the metal layer. Capacitor-embedded multilayer wiring comprising a step of forming a desired capacitor electrode 1, capacitor electrode 2, and an arbitrary conductor pattern electrically insulated from the capacitor electrode The method of production.
(24) It has a metal foil surface and a conductor circuit of a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil. In the prepreg laminated through the substrate, a through hole of an insulating material is provided at an arbitrary position, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler. (16)-(23) The manufacturing method of the multilayer wiring board with a built-in capacitor | condenser.
(25) The surface of the metal foil has a metal foil surface and a conductor circuit of a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided. A prepreg laminated with a substrate is characterized in that a through hole of an insulating material is provided at an arbitrary position, and the through hole is filled with a conductive paste that is metallized by a chemical reaction. (16)-(23) The manufacturing method of the multilayer wiring board with a built-in capacitor | condenser.
(26) A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil 1) a step of laminating a substrate having a conductor circuit via a prepreg on the surface of the metal foil of the capacitor-embedded multilayer wiring board material, and 2) forming a metal layer of 10 to 50 μm on the surface of the dielectric thin film. 3) etching to remove any portion of the metal layer to form a desired capacitor electrode 1, and 4) etching to leave any portion including at least the capacitor electrode 1 of the dielectric thin film. Removing the dielectric thin film to form a desired capacitor dielectric; and 5) removing the dielectric thin film to expose any portion of the metal layer that is exposed by etching to expose the cured insulating layer of the prepreg. And 6) removing the insulating layer exposed by the laser irradiation to form a hole to expose the inner conductive circuit, and 7) providing a 0.1 to 5 μm metal layer on the substrate surface. A step of forming, 8) a step of forming a plating resist except for an arbitrary portion including a hole, and 9) forming a metal layer of 10 to 50 μm on the substrate surface other than the portion where the plating resist is formed, and forming an interlayer circuit A step of electrically connecting the patterns, 10) a step of etching away a 0.1 to 5 μm metal layer formed on the substrate surface, and 11) an arbitrary portion including at least a capacitor dielectric and a hole made into a conductor. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step of forming a conductive pattern including a desired capacitor electrode 2 by removing the remaining etching.
(27) The multilayer wiring with a built-in capacitor according to (26), wherein the metal layer formed on the surface of the dielectric thin film includes at least one or more metal layers selected from the group consisting of chromium, molybdenum, titanium, and nickel. A manufacturing method of a board.
(28) A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil 1) a step of laminating a substrate having a conductor circuit on the surface of a metal foil of a capacitor-embedded multilayer wiring board material through a prepreg, and 2) a metal layer having a thickness of 0.1 to 5 μm on the surface of the dielectric thin film. 3) a step of forming a metal plating resist leaving any portion including the capacitor electrode 1, 4) a step of forming a capacitor electrode 1 of 10 to 50 μm by metal plating, and 5) a metal plating A step of removing the resist, 6) a step of etching away a metal layer of 0.1 to 5 μm formed on the surface of the dielectric thin film, and 7) an option including at least the capacitor electrode 1 of the dielectric thin film. A step of forming a desired capacitor dielectric by etching away leaving a portion; and 8) removing any portion of the metal layer that appears by removing the dielectric thin film to expose the cured insulating layer of the prepreg. And 9) removing the insulating layer exposed by the laser irradiation to form a hole to expose the inner conductive circuit, and 10) providing a 0.1 to 5 μm metal layer on the substrate surface. A step of forming, 11) a step of forming a plating resist excluding any portion including a hole, and 12) a circuit between the layers by forming a 10-50 μm metal layer on the substrate surface other than the portion where the plating resist is formed A step of electrically connecting the patterns; 13) a step of etching away a 0.1 to 5 μm metal layer formed on the substrate surface; and 14) including at least a capacitor dielectric and a hole made into a conductor. Method of manufacturing a capacitor built multilayer wiring board characterized by having a step of etching away leaving portions at will to form a conductive pattern including a desired capacitor electrode 2.
(29) The multilayer wiring with a built-in capacitor according to (28), wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. A manufacturing method of a board.
(30) The multilayer wiring board with a built-in capacitor according to (28) or (29), wherein the metal plating contains at least one metal selected from the group consisting of copper, silver, tin, nickel, and zinc. Production method.
(31) A method for manufacturing a capacitor-embedded multilayer wiring board using a capacitor-embedded multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of a metal foil 1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a capacitor-embedded multilayer wiring board material through a prepreg, and 2) a chemical reaction to an arbitrary portion of the surface of the dielectric thin film. Forming a desired capacitor electrode 1 by forming a metal layer having a thickness of 10 to 50 μm using a conductive paste metallized by 3), leaving at least an arbitrary portion of the dielectric thin film including the capacitor electrode 1 Etching away to form the desired capacitor dielectric, and 4) Exposing the insulating layer of the cured prepreg by etching away any part of the metal layer that appeared after removing the dielectric thin film 5) removing the insulating layer exposed by the laser irradiation to form a hole and exposing the inner conductive circuit; and 6) a 0.1 to 5 μm metal layer on the substrate surface. 7) A step of forming a plating resist excluding any portion including a hole, and 8) A 10-50 μm metal layer is formed on the surface of the substrate other than the portion where the plating resist is formed. A step of electrically connecting the circuit patterns, 9) a step of etching away a 0.1 to 5 μm metal layer formed on the substrate surface, and 10) an arbitrary portion including at least a capacitor dielectric and a hole made into a conductor. A method of manufacturing a multilayer wiring board with a built-in capacitor, which comprises a step of forming a conductive pattern including a desired capacitor electrode 2 by etching away the substrate.
(32) The average particle size of the conductive paste metallized by chemical reaction includes at least one metal selected from the group consisting of gold, platinum, silver, copper, palladium, and ruthenium. The method for producing a multilayer wiring board with a built-in capacitor according to (31), wherein the diameter is 0.1 to 10 nm.
(33) A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil 1) a step of laminating a substrate having a conductor circuit via a prepreg on the surface of a metal foil of a capacitor-embedded multilayer wiring board material, and 2) etching to remove any part of the dielectric thin film as desired. 3) a step of forming a capacitor dielectric, 3) a step of removing an insulating layer of a cured prepreg by etching away an arbitrary portion of a metal layer which appears by removing the dielectric thin film, and 4) exposure by laser irradiation. Removing the insulating layer formed to form a hole to expose the conductor circuit as an inner layer, and 5) forming a metal layer of 10 to 50 μm on the substrate surface on which the capacitor dielectric is formed and the surface in the hole. And 6) a step of forming a conductor pattern including a desired capacitor electrode 2 by etching away leaving at least an arbitrary portion including a capacitor dielectric and a hole made into a conductor. Manufacturing method of built-in multilayer wiring board.
(34) The surface of the metal foil is provided with a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm on the surface of the metal foil of the capacitor built-in multilayer wiring board material via a prepreg. A substrate having a conductor circuit to be laminated is characterized in that the substrate has two or more conductor layers, and the circuit pattern of the adjacent conductor layer is connected by a hole made into a conductor at an arbitrary position. (16)-(33) The manufacturing method of the multilayer wiring board with a built-in capacitor | condenser.
(35) The multilayer with a built-in capacitor according to any one of (16) to (34), wherein the method of etching and removing the dielectric thin film is any one of an ion beam etching method, an RIE (Reactive Ion Etching) method, and a solution etching method. A method for manufacturing a wiring board.
(36) The method for manufacturing a multilayer wiring board with a built-in capacitor according to any one of (16) to (35), wherein the capacitor electrode 2 is a ground layer or a power supply layer of the multilayer wiring board.
(37) The method for producing a multilayer wiring board with a built-in capacitor according to any one of (16) to (36), wherein the insulating material of the substrate is made of resin and glass woven fabric or glass nonwoven fabric.
(38) The multilayer wiring with a built-in capacitor according to any one of (16) to (37), wherein the resin used for the insulating material of the substrate is a thermosetting resin and has a glass transition temperature of 170 ° C. or higher. A manufacturing method of a board.
B. Furthermore, the present invention relates to the following embodiments.
(1) The dielectric constant is 10 to 2000 and the film thickness is 0.05 to 2 μm on the surface of the substrate having via holes connecting the conductor layers inside the substrate and having a smooth metal layer on the surface. A multilayer wiring board substrate with a built-in capacitor, characterized in that a dielectric thin film is formed.
(2) The substrate for a multilayer wiring board with a built-in capacitor according to (1), wherein via holes for connecting the conductor layers are electrically connected to each other by metal plating.
(3) The substrate for a multilayer wiring board with a built-in capacitor according to (1), wherein via holes for connecting the conductor layers are electrically connected to each other by a conductive paste made of metal powder and resin.
(4) A multilayer with a built-in capacitor according to (1) or (3), wherein via holes connecting between the conductor layers are electrically connected to each other by a conductive paste that is metallized by a chemical reaction. Circuit board substrate.
(5) The dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, or A capacitor built-in according to any one of (1) to (4), characterized in that it is a film comprising two or more kinds of solid solutions containing any of these or two or more kinds of laminated bodies containing any of these. Multi-layer circuit board.
(6) The method of forming a dielectric thin film is any one of a vacuum deposition method, an ion plating method, a CVD (Chemical Vapor Deposition) method, a sputtering method, and a sol-gel method. The board | substrate for multilayer wiring boards with a built-in capacitor | condenser in any one.
(7) The substrate for a multilayer wiring board with a built-in capacitor according to any one of (1) to (6), wherein the substrate temperature when forming the dielectric thin film is 25 ° C. to 350 ° C.
(8) The substrate for a multilayer wiring board with a built-in capacitor according to any one of (1) to (7), wherein the insulating material of the substrate is made of resin and glass woven fabric or glass nonwoven fabric.
(9) The resin used for the insulating material of the substrate is a thermosetting resin, and has a glass transition temperature of 170 ° C. or higher, according to any one of (1) to (8) PCB for multilayer wiring boards with built-in capacitors.
(10) One or more metals selected from the group consisting of platinum, gold, silver, palladium, ruthenium and iridium as a metal whose surface is made of copper and whose surface is a copper oxide protective film. The multilayer wiring board substrate with a built-in capacitor according to any one of (1) to (9), wherein a film is provided.
(11) At least one metal film selected from the group consisting of chromium, molybdenum, titanium, and nickel is used as a metal for forming a stable self-oxidation film on the surface of the metal layer on the substrate surface. The substrate for a multilayer wiring board with a built-in capacitor according to any one of (1) to (9), which is provided.
(12) The substrate for a multilayer wiring board with a built-in capacitor according to any one of (1) to (11), wherein the surface roughness of the metal layer on the substrate surface is 0.01 to 0.5 μm.
(13) A method of manufacturing a capacitor built-in multilayer wiring board using the capacitor built-in multilayer wiring board substrate according to any one of (1) to (12) as an inner layer board. A step of forming a metal layer of 50 μm, 2) a step of etching away leaving any portion of the metal layer to form a desired first capacitor electrode, and 3) at least a first capacitor of a dielectric thin film A step of forming a desired capacitor dielectric by etching away leaving an arbitrary portion including an electrode, and 4) leaving an arbitrary portion including at least the capacitor dielectric of the metal layer formed by removing the dielectric thin film. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step of forming a conductor pattern including a desired second capacitor electrode by etching away.
(14) The capacitor built-in multilayer wiring according to (13), wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. A manufacturing method of a board.
(15) A method of manufacturing a capacitor built-in multilayer wiring board using the capacitor built-in multilayer wiring board substrate according to any one of (1) to (12) as an inner layer board. A step of forming a metal layer of 1 to 5 μm, 2) a step of forming a metal plating resist leaving any portion including the first capacitor electrode, and 3) a first capacitor electrode of 10 to 50 μm by metal plating 4) a step of removing the metal plating resist, 5) a step of etching away a 0.1 to 5 μm metal layer formed on the surface of the dielectric thin film, and 6) at least the first of the dielectric thin film. Etching to remove any part including one capacitor electrode to form a desired capacitor dielectric; and 7) removing at least the capacitor from the metal layer that appears after removing the dielectric thin film. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step of forming a conductor pattern including a desired second capacitor electrode by etching and removing an arbitrary portion including an electric body.
(16) The multilayer wiring with a built-in capacitor according to (15), wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. A manufacturing method of a board.
(17) The multilayer wiring board with a built-in capacitor according to (15) or (16), wherein the metal plating includes at least one metal selected from the group consisting of copper, silver, tin, nickel, and zinc. Manufacturing method.
(18) A method of manufacturing a capacitor-embedded multilayer wiring board using the capacitor-embedded multilayer wiring board substrate according to any one of (1) to (12) as an inner layer board, and 1) an arbitrary surface of a dielectric thin film Forming a desired first capacitor electrode by forming a metal layer having a thickness of 10 to 50 μm using a conductive paste that is metallized by chemical reaction on the portion; and 2) at least a first of the dielectric thin film Etching to leave any part including the capacitor electrode to form a desired capacitor dielectric, and 3) removing the dielectric thin film to leave at least the part including the capacitor dielectric of the metal layer that appears. And a step of forming a conductive pattern including a desired second capacitor electrode by etching away, and a method of manufacturing a multilayer wiring board with a built-in capacitor.
(19) The average particle size of the conductive paste metallized by chemical reaction includes at least one metal selected from the group consisting of gold, platinum, silver, copper, palladium, and ruthenium. (18) The method for producing a multilayer wiring board with a built-in capacitor according to (18), wherein the particle diameter is 0.1 to 10 nm.
(20) A method for manufacturing a multilayer wiring board with a built-in capacitor using the substrate for a multilayer wiring board with a built-in capacitor according to any one of (1) to (12) as an inner layer board, and 1) an arbitrary portion of a dielectric thin film Leaving and etching away to form the desired capacitor dielectric, 2) forming a 10-50 μm metal layer on the substrate surface on which the capacitor dielectric is formed, and 3) any portion of the metal layer. A multilayer wiring board with a built-in capacitor, characterized by comprising a step of forming a desired first capacitor electrode, a second capacitor electrode, and an arbitrary conductor pattern electrically insulated from the capacitor electrode by etching and leaving Production method.
(21) The method according to any one of (13) to (20), wherein the method of etching and removing the dielectric thin film is any one of an ion beam etching method, an RIE (Reactive Ion Etching) method, and a solution etching method. Manufacturing method of multilayer wiring board with built-in capacitor.
(22) The method for producing a multilayer wiring board with a built-in capacitor according to any one of (13) to (21), wherein the second capacitor electrode is a ground layer or a power supply layer of the multilayer wiring board.
(23) A multilayer wiring board having a plurality of insulating layers, a plurality of conductor layers, and a conductive via hole for electrically connecting the conductor layers, and the relative dielectric constant of at least one insulating layer is 20 A dielectric thin film having a thickness of ˜2000 and a thickness of 0.1 to 1 μm, and a multilayer wiring board with a built-in capacitor provided with an electrode facing the insulating layer, and 1) a conductor for forming a first capacitor electrode All layer patterns form capacitor electrodes, 2) the projection surface of the dielectric thin film includes the projection surface of the first capacitor electrode, and 3) the second capacitor is formed on the conductor layer forming the second capacitor electrode. A multilayer wiring board with a built-in capacitor, comprising an electrode and at least one pattern electrically insulated from the electrode.
(24) A multilayer wiring board having a plurality of insulating layers, a plurality of conductor layers, and a conductive via hole for electrically connecting the conductor layers, and the relative dielectric constant of at least one insulating layer is 20 A dielectric thin film having a thickness of 0.1 to 1 [mu] m and a capacitor built-in multilayer wiring board provided with an electrode facing the insulating layer, and 1) a dielectric forming a capacitor dielectric A first capacitor electrode included in the projection surface of the thin film; and 2) a conductor layer that forms the first capacitor electrode is electrically connected to the second capacitor electrode at all ends of the dielectric thin film. A multilayer wiring board with a built-in capacitor.
(25) The capacitor built-in multilayer wiring board according to (23) or (24), wherein the second capacitor electrode is a ground layer or a power supply layer of the multilayer wiring board.
(26) The dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, or Capacitor built-in according to any one of (23) to (25), characterized in that it is a film composed of two or more kinds of solid solutions containing any of these or two or more kinds of laminated bodies containing any of these Multilayer wiring board.
(27) The multilayer wiring board with a built-in capacitor according to any one of (23) to (26), wherein the insulating material of the substrate is made of resin and glass woven fabric or glass nonwoven fabric.
(28) The resin used for the insulating material of the substrate is a thermosetting resin, and has a glass transition temperature of 170 ° C. or higher, according to any one of (23) to (27) Multi-layer wiring board with built-in capacitor.
(29) The second capacitor electrode is made of copper, and at least one or more kinds selected from the group consisting of platinum, gold, silver, palladium, ruthenium, iridium, chromium, molybdenum, titanium, nickel are formed on the surface thereof. The multilayer wiring board with a built-in capacitor according to any one of (23) to (28), comprising a metal layer.
(30) The multilayer wiring board with a built-in capacitor according to any one of (23) to (29), wherein the surface roughness of the second capacitor electrode is 0.01 to 0.5 μm.
(31) The first capacitor electrode includes at least one metal layer selected from the group consisting of copper, silver, tin, nickel, zinc, chromium, molybdenum, titanium, nickel (23) Thru | or the multilayer wiring board with a built-in capacitor | condenser in any one of (30).
(32) The first capacitor electrode is made of a conductive paste metallized by a chemical reaction, and the metal is at least one selected from the group consisting of platinum, gold, silver, copper, tin, palladium, and ruthenium. The multilayer wiring board with a built-in capacitor according to any one of (23) to (30), comprising the above metal.
(33) A semiconductor device wherein a semiconductor chip is mounted on the capacitor built-in multilayer wiring board according to any one of (23) to (32).
C. Furthermore, the present invention relates to the following embodiment.
(1) A capacitor-embedded multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of a metal foil so that the metal foil is in contact with an insulating material And a method of manufacturing a multilayer wiring board with a built-in capacitor using a substrate provided on at least one side of an insulating material, wherein 1) a step of forming a metal layer to be a capacitor electrode at a predetermined position on a dielectric thin film on the substrate surface; 2) a step of forming an etching resist on at least the metal layer on the substrate surface, 3) a step of wet etching the dielectric thin film with an etchant containing a chelating agent and hydrogen peroxide, and 4) an etching resist after the wet etching. A method of manufacturing a multilayer wiring board with a built-in capacitor.
(2) The etchant chelating agent concentration is 0.001 to 0.5 mol / l, the hydrogen peroxide concentration is 1 to 50 wt%, and the etchant pH is in the range of 2 to 7. (1) A method for producing a multilayer wiring board with a built-in capacitor.
(3) The chelating agent is at least one selected from the group consisting of ethylenediaminetetraacetic acid (EDTA), hydroxyethyliminodiacetic acid (HIDA), iminodiacetic acid (IDA), dihydroxyethylglycine (DHEG), and alkali salts thereof. The method for producing a multilayer wiring board with a built-in capacitor according to (1) or (2), wherein:
(4) A capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one surface of a metal foil so that the metal foil is in contact with an insulating material And a method of manufacturing a multilayer wiring board with a built-in capacitor using a substrate provided on at least one side of an insulating material, wherein 1) a step of forming a metal layer to be a capacitor electrode at a predetermined position on a dielectric thin film on the substrate surface; 2) a step of forming an etching resist on at least the metal layer on the surface of the substrate; and 3) an etchant containing at least one acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid and acetic acid and hydrogen peroxide. A multilayer with a built-in capacitor, comprising: a step of performing wet etching on the dielectric thin film; and 4) a step of removing the etching resist after the wet etching. Method of manufacturing a line plate.
(5) The method for producing a multilayer wiring board with a built-in capacitor according to (4), wherein the etchant has an acid concentration of 1 to 30 wt% and a hydrogen peroxide concentration of 1 to 50 wt%.
(6) The method for producing a multilayer wiring board with a built-in capacitor according to any one of (1) to (5), wherein a photosensitive dry film is used as an etching resist.
(7) The film thickness of the photosensitive dry film is 1 to 3 times the thickness of the metal layer to be a capacitor electrode protected from wet etching by the etching resist formed by the photosensitive dry film ( 6) The manufacturing method of the multilayer wiring board with a built-in capacitor.
(8) The method for producing a multilayer wiring board with a built-in capacitor according to any one of (1) to (7), wherein wet etching of the dielectric thin film is performed with an etchant having a liquid temperature of 20 to 45 ° C.
(9) The dielectric thin film is any one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate and lead zirconate, Alternatively, the multilayer wiring with a built-in capacitor according to any one of (1) to (8), wherein the multilayer wiring is a solid solution containing any two or more of these, or a film comprising a laminate containing any two or more of these. A manufacturing method of a board.
D. Furthermore, the present invention relates to the following embodiments.
(1) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) a step of laminating a metal foil B on a surface of a metal foil A of a capacitor wiring multilayer wiring board material through an insulating material to form a substrate, and 2) etching and removing an arbitrary portion of the metal foil B A step of exposing the insulating layer formed of the insulating material, 3) a step of removing the exposed insulating layer by laser irradiation to form a hole, and exposing the metal foil A, and 4) in the hole 5) forming a metal layer on both surfaces of the substrate surface including 5) forming a capacitor electrode A pattern of an arbitrary shape from the metal layer on the dielectric thin film of the multilayer wiring board material with a built-in capacitor; ) Exposed dielectric A step of etching a capacitor dielectric having an arbitrary shape including the capacitor electrode A pattern from the film, and 7) a capacitor electrode having an arbitrary shape including the capacitor dielectric pattern from the metal foil A appearing by removing the dielectric thin film. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step of forming B by etching.
(2) A method of manufacturing a multilayer wiring board with a built-in capacitor according to (1), wherein in the etching step of 5) or 7), a circuit having an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated. A method of manufacturing a multilayer wiring board with a built-in capacitor.
(3) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) a step of laminating a metal foil B on a surface of a metal foil A of a capacitor-embedded multilayer wiring board material through an insulating material to form a substrate, and 2) laser irradiation to an arbitrary portion of the metal foil B Removing the metal foil B and the insulating layer formed from the insulating material at the same time to form a hole to expose the metal foil A, and 3) providing a metal layer on both surfaces of the substrate surface including the inside of the hole. And 4) a step of etching a capacitor electrode A pattern of an arbitrary shape from a metal layer on the dielectric thin film of the capacitor built-in multilayer wiring board material, and 5) a capacitor electrode from the exposed dielectric thin film. A pattern And 6) a process of forming a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern from the metal foil A that has appeared after removing the dielectric thin film by etching. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising:
(4) The method for producing a multilayer wiring board with a built-in capacitor according to (3), wherein in the etching step of 4) or 6), a circuit having an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated. A method of manufacturing a multilayer wiring board with a built-in capacitor.
(5) Production of a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) A through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler. A step of laminating the metal foil B through the insulating material used to form a substrate, 2) a step of forming a metal layer on at least the dielectric thin film side of the substrate surface, and 3) dielectric of the multilayer wiring board material with a built-in capacitor. A step of etching a capacitor electrode A pattern having an arbitrary shape from a metal layer on the body thin film, and 4) etching a capacitor dielectric having an arbitrary shape including the capacitor electrode A pattern from the exposed dielectric thin film. A capacitor built-in process comprising: a step of forming a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern on the metal foil A that has appeared after removing the dielectric thin film; A method of manufacturing a multilayer wiring board.
(6) Manufacture of a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) Filling with a conductive paste in which a through hole is provided in an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material and the through hole is metallized by a chemical reaction A step of laminating the metal foil B through the insulating material used to form a substrate, 2) a step of forming a metal layer on at least the dielectric thin film side of the substrate surface, and 3) dielectric of the multilayer wiring board material with a built-in capacitor. Forming a capacitor electrode A pattern having an arbitrary shape from a metal layer on the thin body film by etching; and 4) removing an arbitrary shape capacitor dielectric including the capacitor electrode A pattern from the exposed dielectric thin film. And 5) forming a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern from the metal foil A that has appeared after removing the dielectric thin film by etching. A method of manufacturing a multilayer wiring board.
(7) A method for manufacturing a multilayer wiring board with a built-in capacitor according to (5) or (6), wherein a circuit having an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated in the etching step of 3) or 5) A method of manufacturing a multilayer wiring board with a built-in capacitor.
(8) It includes a step of forming at least one other metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel between the dielectric thin film and the metal layer ( 1)-(7) The manufacturing method of the multilayer wiring board with a built-in capacitor in any one.
(9) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) a step of laminating a metal foil B on a surface of a metal foil A of a capacitor wiring multilayer wiring board material through an insulating material to form a substrate, and 2) etching and removing an arbitrary portion of the metal foil B A step of exposing the insulating layer formed of the insulating material, 3) a step of removing the insulating layer exposed by laser irradiation to form a hole, and exposing the metal foil A, and 4) the inside of the hole. A step of forming a metal layer of 0.1 to 5 μm on both sides of the substrate to be included, 5) a step of forming a metal plating resist on the substrate surface leaving a portion to be the capacitor electrode A and an arbitrary portion including a hole, 6) By metal plating, A step of forming a conductor pattern in a portion including the densa electrode A and a portion including a hole, 7) a step of removing the metal plating resist, and 8) etching a 0.1 to 5 μm metal layer exposed on the substrate surface. A step of removing, 9) a step of forming a capacitor dielectric having an arbitrary shape including the capacitor electrode A pattern from the exposed dielectric thin film by etching, and 10) from the metal foil A appearing by removing the dielectric thin film A multilayer wiring board with a built-in capacitor, comprising: a step of forming a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern by etching; and 11) a step of forming a circuit by etching the exposed metal foil B Manufacturing method.
(10) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) a step of laminating a metal foil B on a surface of a metal foil A of a capacitor-embedded multilayer wiring board material through an insulating material to form a substrate, and 2) laser irradiation to an arbitrary portion of the metal foil B Thereby removing the metal foil B and the insulating layer formed of the above insulating material at the same time to form a hole to expose the metal foil A, and 3) 0.1 on both surfaces of the substrate including the inside of the hole. A step of forming a metal layer of ˜5 μm, 4) a step of forming a metal plating resist on the surface of the substrate leaving an arbitrary portion including a portion to be the capacitor electrode A and a hole, and 5) the above-described metal plating. Capacitor electrode A and hole A step of forming a conductor pattern on the portion including the metal, 6) a step of removing the metal plating resist, 7) a step of etching away the 0.1 to 5 μm metal layer exposed on the substrate surface, and 8) the exposure. A step of forming a capacitor dielectric having an arbitrary shape including the capacitor electrode A pattern by etching from the dielectric thin film, and 9) an arbitrary including the capacitor dielectric pattern from the metal foil A which has appeared after removing the dielectric thin film. And 10) a process for forming a circuit by etching the exposed metal foil B, and a method of manufacturing a multilayer wiring board with a built-in capacitor.
(11) Manufacture of a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) A through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler. A step of laminating a metal foil B through a prepreg, which is used as a substrate, 2) a step of forming a metal layer of 0.1 to 5 μm on the surface of at least the dielectric thin film side of the substrate, and 3) a capacitor electrode A A step of forming a metal plating resist on the surface of the substrate while leaving an arbitrary portion including the portion to become, 4) a step of forming a conductor pattern on the portion including the portion to be the capacitor electrode A by metal plating, and 5) gold A step of removing the plating resist, 6) a step of etching away the 0.1 to 5 μm metal layer exposed on the substrate surface, and 7) an arbitrary shape including the capacitor electrode A pattern from the exposed dielectric thin film. And 8) forming a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A that appears after removing the dielectric thin film, and exposing the capacitor dielectric B. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising the step of forming a circuit by etching the metal foil B.
(12) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) Filling with a conductive paste in which a through hole is provided in an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material and the through hole is metallized by a chemical reaction A step of laminating a metal foil B through a prepreg, which is used as a substrate, 2) a step of forming a metal layer of 0.1 to 5 μm on the surface of at least the dielectric thin film side of the substrate, and 3) a capacitor electrode A A step of forming a metal plating resist on the surface of the substrate leaving an arbitrary portion including the portion to become, 4) a step of forming a conductor pattern on the portion including the portion to be the capacitor electrode A by metal plating, and 5) a metal A step of removing the resist, 6) a step of etching away the 0.1 to 5 μm metal layer exposed on the substrate surface, and 7) an arbitrary pattern including the capacitor electrode A pattern from the exposed dielectric thin film. A step of forming a capacitor dielectric having a shape by etching; and 8) forming a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A that has appeared after removing the dielectric thin film, and exposing it. A method for producing a multilayer wiring board with a built-in capacitor, comprising the step of forming a circuit by etching the formed metal foil B.
(13) The metal layer of 0.1 to 5 μm formed on at least the surface of the dielectric thin film is at least one metal layer selected from the group consisting of: chromium, molybdenum, titanium and nickel; copper, silver, At least one metal layer selected from the group consisting of tin, nickel and zinc; or at least one metal layer selected from the group consisting of chromium, molybdenum, titanium and nickel and copper, silver, tin The method for producing a multilayer wiring board with a built-in capacitor according to any one of (9) to (12), comprising at least one metal layer selected from the group consisting of nickel and zinc.
(14) The conductor pattern formed by metal plating contains at least one metal selected from the group consisting of copper, silver, tin, nickel and zinc (9) to (13) A method for producing a multilayer wiring board with a built-in capacitor according to claim 1.
(15) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) A through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler. A step of laminating a metal foil B through an insulating material to be a substrate, and 2) forming a metal layer using a conductive paste that is metallized by chemical reaction on an arbitrary portion of the surface of the dielectric thin film Forming a desired capacitor electrode A, 3) etching and removing any portion of the dielectric thin film including at least the capacitor electrode A, and 4) forming a desired capacitor dielectric. body A step of forming a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A appearing after removing the film, and forming a circuit by etching the exposed metal foil B is provided. A method of manufacturing a multilayer wiring board with a built-in capacitor.
(16) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) Filling with a conductive paste in which a through hole is provided in an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material and the through hole is metallized by a chemical reaction A step of laminating a metal foil B through an insulating material to be a substrate, and 2) forming a metal layer using a conductive paste that is metallized by chemical reaction on an arbitrary portion of the surface of the dielectric thin film Forming a desired capacitor electrode A, 3) etching and removing any portion of the dielectric thin film including at least the capacitor electrode A, and 4) forming a desired capacitor dielectric. Thin body A capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern is formed by etching from the metal foil A that appears after removing the metal foil, and a circuit is formed by etching the exposed metal foil B. To manufacture a multilayer wiring board with a built-in capacitor.
(17) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil A 1) a step of laminating a metal foil B on a surface of a metal foil A of a capacitor-embedded multilayer wiring board material with an insulating material as a substrate, and 2) leaving an arbitrary portion of the dielectric thin film. Etching to remove the desired capacitor dielectric, 3) etching away any portion of the metal foil B to expose the insulating layer formed of the insulating material, and 4) laser irradiation. Removing the insulating layer exposed by forming a hole to expose the metal foil A, 5) forming a metal layer on both surfaces of the substrate surface including the inside of the hole, and 6) the metal layer and the metal foil. Etching leaving any part of A And grayed removed, method of manufacturing the capacitor built-in multilayer wiring board characterized by having a step of forming a desired capacitor electrode A and the capacitor electrode B.
(18) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil A 1) a step of laminating a metal foil B on a surface of a metal foil A of a capacitor-embedded multilayer wiring board material with an insulating material as a substrate, and 2) leaving an arbitrary portion of the dielectric thin film. Etching to remove a desired capacitor dielectric, and 3) irradiating a laser beam to an arbitrary portion of the metal foil B, thereby simultaneously removing the metal foil B and the insulating layer formed of the above insulating material. 4) exposing the metal foil A, 4) forming a metal layer on both sides of the substrate surface including the inside of the hole, and 5) etching away leaving the metal layer and any part of the metal foil A. Desired capacitor electrode A Method of manufacturing a capacitor built multilayer wiring board characterized by having a step of forming a fine capacitor electrode B.
(19) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) A through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler. A step of forming a substrate by laminating metal foil B through the insulating material, 2) a step of etching away leaving any portion of the dielectric thin film to form a desired capacitor dielectric, and 3) a substrate 4) forming a metal layer on at least the surface having the capacitor dielectric, and 4) removing the metal layer and the metal foil A by leaving an arbitrary portion, thereby removing the desired capacitor electrode A and capacitor electrode B. Method of manufacturing a capacitor built multilayer wiring board characterized by having a step of forming.
(20) Manufacture of a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A 1) Filling with a conductive paste in which a through hole is provided in an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer wiring board material and the through hole is metallized by a chemical reaction A step of forming a substrate by laminating metal foil B through the insulating material, 2) a step of etching away leaving any portion of the dielectric thin film to form a desired capacitor dielectric, and 3) a substrate Forming a metal layer on the surface having at least the capacitor dielectric; and 4) etching away leaving the metal layer and any part of the metal foil A to form the desired capacitor electrode A and capacitor electrode B. Method of manufacturing a capacitor built multilayer wiring board characterized by having a step of.
(21) The conductive paste that is metallized by a chemical reaction includes at least one metal particle selected from the group consisting of gold, platinum, silver, copper, palladium, and ruthenium, and The method for producing a multilayer wiring board with a built-in capacitor according to (6), (12), (15), (16) or (20), wherein the average particle size is 0.1 to 10 nm.
(22) The method for etching and removing the dielectric thin film is any one of an ion beam etching method, an RIE (Reactive Ion Etching) method, and a solution etching method. Manufacturing method for multilayer wiring boards with built-in capacitors.
(23) The method for manufacturing a multilayer wiring board with a built-in capacitor according to any one of (1) to (22), wherein the capacitor electrode B is a ground layer or a power supply layer of the multilayer wiring board.
(24) The capacitor built-in multilayer wiring board according to any one of (1) to (23), wherein the insulating material used for forming the insulating layer of the substrate is a prepreg made of resin and glass woven fabric or glass nonwoven fabric. Manufacturing method.
(25) The insulating material used for forming the insulating layer of the substrate is a prepreg containing a thermosetting resin as a resin, and the glass transition temperature of the thermosetting resin is 170 ° C. or higher. The manufacturing method of the multilayer wiring board with a built-in capacitor according to any one of (1) to (24).
(26) Dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, strontium titanate , Any one of lead zirconate titanate and lead magnesium niobate-lead titanate, a solid solution containing any two or more of these, or a capacitor made of a laminate containing any two or more of these The method for manufacturing a multilayer wiring board with a built-in capacitor according to any one of (1) to (25), wherein a material for a built-in multilayer wiring board is used.
(27) 1 selected from the group consisting of platinum, gold, silver, palladium, ruthenium, and iridium as the metal that forms the copper oxide protective film on the surface on which the metal foil A is made of copper and the dielectric thin film is formed. The method for producing a multilayer wiring board with a built-in capacitor according to any one of (1) to (26), wherein a material for a multilayer wiring board with a built-in capacitor provided with a metal film of a seed or more is used.
(28) One or more selected from the group consisting of chromium, molybdenum, titanium, and nickel as a metal that forms a stable self-oxidation film on the surface on which the metal foil A is made of copper and the dielectric thin film is formed The method for producing a multilayer wiring board with a built-in capacitor according to any one of (1) to (26), wherein a material for a multilayer wiring board with a built-in capacitor provided with a metal film is used.
(29) A capacitor-embedded multilayer wiring board material having a surface roughness of 0.01 to 0.5 μm on the surface of the metal foil A on which the dielectric thin film is formed (1) to (28) ) A method for manufacturing a multilayer wiring board with a built-in capacitor according to any one of the above.
The contents of the disclosure in this specification are as follows: Japanese patent applications 2003-077695 (filing date March 20, 2003), 2003-078324 (filing date March 20, 2003), 2003-368857 (filing date 2003-10) Month 29) and 2003-376604 (filing date November 6, 2003), which are incorporated herein in their entirety.

第１図は、本発明の実施例におけるコンデンサ内蔵多層配線板用材料を示す断面図である。第２図は、実施例Ａ−１と実施例Ａ−２及び実施例Ａ−５のプロセスを示す断面図である。第３図は、実施例Ａ−３のプロセスを示す断面図である。第４図は、実施例Ａ−４のプロセスを示す断面図である。第５図は、実施例Ａ−６のプロセスを示す断面図である。第６図は、実施例Ａ−７のプロセスを示す断面図である。第７図は、実施例Ａ−８のプロセスを示す断面図である。第８図は、比較例Ａ−１のプロセスを示す断面図である。
また、第９図から第１１図は、本発明の実施例Ｂに用いた内層基板を示す断面図である。第１２図は、実施例Ｂ−１のプロセス及び実施例Ｂ−４とＢ−５のプロセスの一部を示す断面図である。第１３図は、実施例Ｂ−６のプロセスを示す断面図である。第１４図は、実施例Ｂ−７のプロセスを示す断面図である。第１５図は、実施例Ｂ−８のプロセスを示す断面図である。第１６図は、比較例Ｂ−１のプロセスを示す断面図である。
さらに、第１７〜１９図は、実験例Ｃ−１〜Ｃ−９の製造工程を示す断面図である。
さらに、第２０図は、実施例Ｄ−１のプロセスを示す断面図である。第２１図は、実施例Ｄ−２のプロセスを示す断面図である。第２２図は、実施例Ｄ−３のプロセスを示す断面図である。第２３図は、実施例Ｄ−４および実施例Ｄ−５のプロセスを示す断面図である。第２４図は、実施例Ｄ−６のプロセスを示す断面図である。第２５図は、実施例Ｄ−７のプロセスを示す断面図である。第２６図は、実施例Ｄ−８および実施例Ｄ−９のプロセスを示す断面図である。第２７図は、実施例Ｄ−１０および実施例Ｄ−１１のプロセスを示す断面図である。第２８図は、実施例Ｄ−１２のプロセスを示す断面図である。第２９図は、実施例Ｄ−１３のプロセスを示す断面図である。第３０図は、実施例Ｄ−１４および実施例Ｄ−１５のプロセスを示す断面図である。第３１図は、比較例Ｄ−１のプロセスを示す断面図である。FIG. 1 is a sectional view showing a material for a multilayer wiring board with a built-in capacitor in an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the processes of Example A-1, Example A-2, and Example A-5. FIG. 3 is a cross-sectional view showing the process of Example A-3. FIG. 4 is a cross-sectional view showing the process of Example A-4. FIG. 5 is a sectional view showing the process of Example A-6. FIG. 6 is a cross-sectional view showing the process of Example A-7. FIG. 7 is a cross-sectional view showing the process of Example A-8. FIG. 8 is a cross-sectional view showing the process of Comparative Example A-1.
9 to 11 are cross-sectional views showing the inner layer substrate used in Example B of the present invention. FIG. 12 is a sectional view showing a part of the process of Example B-1 and the processes of Examples B-4 and B-5. FIG. 13 is a cross-sectional view showing the process of Example B-6. FIG. 14 is a cross-sectional view showing the process of Example B-7. FIG. 15 is a cross sectional view showing a process of Example B-8. FIG. 16 is a cross-sectional view showing the process of Comparative Example B-1.
Further, FIGS. 17 to 19 are sectional views showing manufacturing steps of Experimental Examples C-1 to C-9.
FIG. 20 is a sectional view showing the process of Example D-1. FIG. 21 is a cross sectional view showing a process of Example D-2. FIG. 22 is a cross sectional view showing a process of Example D-3. FIG. 23 is a cross-sectional view showing the process of Example D-4 and Example D-5. FIG. 24 is a cross sectional view showing a process of Example D-6. FIG. 25 is a cross sectional view showing a process of Example D-7. FIG. 26 is a cross-sectional view showing the process of Example D-8 and Example D-9. FIG. 27 is a cross-sectional view showing the process of Example D-10 and Example D-11. FIG. 28 is a cross sectional view showing a process of Example D-12. FIG. 29 is a cross sectional view showing a process of Example D-13. FIG. 30 is a cross sectional view showing a process of Example D-14 and Example D-15. FIG. 31 is a cross-sectional view showing the process of Comparative Example D-1.

（コンデンサ内蔵多層配線板用材料）
本発明の一実施態様は、金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたことを特徴とするコンデンサ内蔵多層配線板用材料に関する。この多層配線板用材料では、金属箔表面に誘電体薄膜を形成するために、均一な膜厚の誘電体薄膜を得ることが容易であり、コンデンサ容量のばらつきが小さい。
誘電体薄膜の膜厚は、絶縁性を確保してリーク電流を抑えるためには０．０５μｍ以上が好ましく、０．１μｍ以上がさらに好ましい。また、経済性を考慮すると２μｍ以下の膜厚が好ましく、１μｍ以下がさらに好ましい。したがって、膜厚としては０．０５〜２μｍが好ましく、０．１〜１μｍがさらに好ましいものである。５００ｐＦ／ｍｍ^２以上の容量密度を得るために必要な比誘電率は、膜厚が０．０５μｍの場合に２．９以上、０．１μｍの場合に５．７以上、１μｍの場合に５７以上、２μｍの場合に１１３以上である。したがって、比誘電率として２．９〜１１３の薄膜誘電体を用いれば、０．０５〜２μｍの膜厚で５００ｐＦ／ｍｍ^２の薄膜キャパシタを形成可能である。しかし、薄膜誘電体の比誘電率が高いほど内蔵キャパシタの小型化に優位性があり、１０〜２０００が好ましく、２０〜２０００がさらに好ましい。ここで、比誘電率とは、２５℃に温度管理された環境の下でＩＰＣ−６５０２．５．５．２に準じて１ＭＨｚの周波数で測定した値を指し示す。また、膜厚の値は、電極を形成したコンデンサの断面を走査型電子顕微鏡に挙げられるような０．０５μｍ未満の厚みを観察可能な装置を用いて得ることが可能である。
誘電体薄膜としては、比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜を形成できれば限定するものではないが、チタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、チタン酸鉛、チタン酸ビスマス、二酸化チタン、ジルコン酸バリウム、ジルコン酸カルシウム、ジルコン酸鉛、チタン酸バリウムストロンチウム、チタン酸ジルコン酸鉛、ニオブ酸マグネシウム酸鉛−チタン酸鉛などの誘電体からなる膜を用いることが好ましい。この時に２種類以上の固溶体や積層体も用いることができる。一般的にペロブスカイト結晶構造を持つ金属酸化物は高い比誘電率を示すことが知られており、好ましく用いることができる。
金属箔としては、例えば、銅箔、銀箔、錫箔、ニッケル箔、亜鉛箔が挙げられる。これらの中でも、電気的な特性と経済性考慮すると銅箔が好ましい。金属箔の厚さは、１０〜５０μｍが好ましい。銅箔を用いる場合には、銅箔の表面に、銅の酸化保護皮膜となる金属の層および／または安定した自己酸化皮膜を形成する金属の層を設けることが好ましい。これらの皮膜は、０．１〜３μｍであることが好ましい。
銅の酸化保護皮膜となる金属の層として、白金、金、銀、パラジウム、ルテニウム、イリジウムなどの金属膜が好ましい。金属箔として銅箔を用いた場合、銅の表面に金属酸化物の誘電体薄膜を直接形成すると、金属酸化物から銅に酸素が供給されて界面に酸化銅が発生し、密着性を低減させる。したがって、金属酸化物から供給される酸素を遮断し、かつ銅との密着性を確保する酸化保護皮膜を形成することが好ましい。
自己酸化皮膜を形成する金属の層として、クロム、モリブデン、チタン、ニッケルなどの金属膜が好ましい。金属箔に銅箔を用いた場合、酸化銅の発生により密着性が低減する可能性があるため、金属酸化物の誘電体薄膜から供給される酸素を遮断し、かつ銅との密着性を確保する自己酸化皮膜を形成することが好ましい。
金属箔の表面粗さは０．０１〜０．５μｍであることが好ましい。誘電体薄膜の厚みは、前記の通り、好ましくは０．０５〜２μｍ、さらに好ましくは０．１〜１μｍである。誘電体薄膜を形成する基板の表面粗さは、少なくとも誘電体薄膜の厚みよりも低いことが必要であり、リーク電流等の絶縁膜としての信頼性を確保するためには、誘電体薄膜の厚みの５０％未満であることが好ましい。したがって０．０２５〜０．５μｍの表面粗さが好ましいが、信頼性を確固とするためには表面粗さを０．０１〜０．５μｍとすることが最も好ましい。ここで、表面粗さとは、表面を走査型顕微鏡を用いて観察し、任意の十点における凹凸の差の平均値を指し示す。
誘電体薄膜の金属箔への形成方法は、例えば、真空蒸着法、イオンプレーティング法、ＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法、スパッタリング法またはゾルゲル法により形成してもよい。
真空蒸着法は、１．３×１０^−４Ｐａ以下の高真空中で薄膜材料を加熱蒸着させ、この蒸発粒子を基板上に付着させて誘電体薄膜を形成する技術である。イオンプレーティング法は、真空蒸着膜の基板への付着強度を高めるために、蒸発粒子をイオン化し電界により加速してから基板に付着させて誘電体薄膜を形成する技術である。ＣＶＤ法は、薄膜を形成する元素を含むハロゲン化物、硫化物、水素化物、有機金属化合物などを高温中あるいはプラズマ中で熱分解・酸化・還元・重合あるいは気相化学反応などさせたのちに、薄膜組成を基板上に付着させて誘電体薄膜を形成する技術である。スパッタリング法は、イオンをターゲットに照射し、スパッタ蒸発したターゲット物質を基板上に付着させて誘電体薄膜を形成する技術である。ゾルゲル法は、薄膜を形成する元素を含むゾル溶液を基板上にコーティングし、縮合反応によりゲル化させたのちに高温アニールして誘電体薄膜を形成する技術である。
誘電体薄膜を金属箔表面に形成する際には、ロール状の金属箔を用い、かつ温度が一定に管理された加熱炉内を連続的に金属箔を移動させながら誘電体薄膜を形成することが好ましい。連続処理を行うことにより、均一の品質の誘電体薄膜を形成することが可能となり、経済的にも優れる。
（コンデンサ内蔵多層配線板用基板）
さらに、本発明の一実施形態は、基板内部に導体層間を接続するバイアホールを有し，かつ、表面に平滑な金属層を有する基板の表面に、比誘電率が１０〜２０００で、かつ、膜厚が０．０５〜２μｍの誘電体薄膜を形成したコンデンサ内蔵多層配線板用基板に関する。
この実施形態によると、基板内部にバイアホールを有する基板を用いることにより、コンデンサ電極と接続する配線パターンを任意に設計することが可能となる。また、表面が平滑な金属層表面に誘電体薄膜を形成するために均一な膜厚の誘電体薄膜を得ることが容易であり、コンデンサ容量のばらつきも小さい。
金属層としては、銅が好ましく、銅箔の表面に酸化保護皮膜および／または自己酸化皮膜を設けて銅の酸化を防ぐことが好ましい。誘電体薄膜については、コンデンサ内蔵多層配線板用材料に用いる誘電体薄膜と同様のものを用いることができ、前記と同様に形成できる。
バイアホールによる導体層間の接続は、金属めっきまたは導電性ペーストにより行うことができる。
金属めっきとしては、銅、銀、ニッケル、亜鉛、錫などの金属やそれらの合金を用いることができる。金属めっきによる層間の接続方法は、１）金属張り積層板にドリル穴明けやレーザ穴明けにより貫通穴を形成、２）めっき触媒付与、３）薄付け無電解めっき、４）厚付け電気めっき、５）熱硬化性穴埋め樹脂を貫通穴へ充填、６）熱硬化性穴埋め樹脂を硬化、７）基板表面の平滑化を目的とした研磨、８）めっき触媒付与、９）薄付け無電解めっき、１０）厚付け電気めっきする方法により、行ってもよい。厚付け電気めっきを厚付け無電解めっきとしてもよい。
導電性ペーストとしては、金属フィラーと樹脂とからなる導電性ペースト、または化学的な反応により金属化される導電性ペーストが挙げられる。
金属フィラー（金属粉）と樹脂とからなる導電性ペーストとしては、金属フィラーと熱硬化性樹脂からものが好ましい。金属フィラーとしては、例えば、銀、銅、錫、亜鉛又はその合金等が挙げられる。その粒径は、０．５〜１０μｍである。熱硬化性樹脂としては、例えばフェノール樹脂、エポキシ樹脂、シアネート樹脂等が挙げられる。導電性ペースト中の金属フィラーの含有量は、６０〜８０体積％であることが好ましい。熱硬化性樹脂と金属フィラーとからなる導電性ペーストとしては、市販品として、ＤＤペースト（タツタシステム・エレクトロニクス株式会社製、商品名）、ドータイト（藤倉化成株式会社製、商品名）、ユニメック導電性ペースト（ナミックス株式会社製、商品名）等を用いることができる。
化学的な反応により金属化される導電性ペーストは、熱硬化性樹脂と金属フィラーとからなる導電性ペーストに対して体積抵抗率が低く、電気特性的に有利である。このような導電性ペーストとしては、例えば、微細な金属粒子、分散剤、溶剤からなるペーストが挙げられる。この導電性ペースト中の金属粒子の含有量は、６０〜８０重量％が好ましい。化学的な反応により金属化される導電性ペーストの金属粒子としては、例えば、金、白金、銀、銅、パラジウム、ルテニウムなどが挙げられる。その平均粒径が０．１〜１０ｎｍであることが好ましい。この導電性ペーストは、ガス中蒸発法で形成された非常に微細な金属粒子が、分散剤で保護されているため、室温では、液体とほとんど同じ挙動を示し、印刷、塗布、含浸等で回路形成などが可能である。また、一定温度（１５０〜２００℃）まで加熱すると、補足物質が活性化し、分散剤を除去するなどの化学的な反応により、微細な金属粒子間を接触させ、融合と融着を加速し、金属化された電気伝導体を形成する性質を有する。積層のための加熱加圧時の温度、すなわち金属の融点に達しない温度で金属化させるためには、０．１〜１０ｎｍの金属粒子を用いて反応活性を上げることが好ましい。また、酸素との反応を抑制するために、酸化しにくい金属である金、白金、銀、銅、パラジウム、ルテニウムなどの金属粒子を用いることが好ましい。このような化学的な反応により金属化される導電性ペーストとして、ナノペースト（ハリマ化成株式会社製、商品名）などの市販品を用いることができるが、これに限定したものではない。
導電性ペーストを用いた層間の接続方法は、１）絶縁層となるプリプレグにドリル穴明けやレーザ穴明けにより貫通穴を形成する工程、２）導電性ペーストを貫通穴へ充填する工程、３）金属箔で挟み、加圧加熱し硬化させる工程を含んでいてもよい。加熱する温度は、２５℃〜３５０℃であることが好ましい。３５０℃を超えると一般的な樹脂においては、熱分解が起こるためである。
金属めっきおよび導電性ペーストのいずれによる層間の接続においても、２層基板に限定するものではなく、３層以上の基板においても基板内部に導体層間を接続するバイアホールが金属により電気的に接続されていてもよい。
基板に用いる絶縁材料は、樹脂とガラス織布またはガラス不織布からなることが好ましい。基板の加熱処理を行うためには高温においても基板の剛性を確保することが必要である。したがって、樹脂と無機フィラーのみからなる絶縁材料や樹脂とセルロースや合成樹脂などの紙からなる絶縁材料等を用いるよりも、樹脂とガラス織布またはガラス不織布からなる絶縁材料を用いることが好ましいものである。また、耐熱性の高いフッ素樹脂やポリエーテルエーテルケトンなどの熱可塑性樹脂やポリイミドやポリアミドイミドなどの熱硬化性樹脂のシートを用いることも可能であるが、経済性に劣る。織布や不織布の材質は、高温における剛性の高い、すなわち弾性率の高いものであれば限定するものではなく、Ｄガラス，ＥガラスやＳガラスなどが使用可能である。
基板の絶縁材料に用いられている樹脂は、熱硬化性樹脂であり，そのガラス転移点温度が１７０℃以上であることが好ましい。熱硬化性樹脂とガラス織布またはガラス不織布からなる絶縁材料を用いた基板は加工性や経済性に優れている。また、ガラス転移点温度が１７０℃以上であることにより、誘電体薄膜の形成時の熱による劣化を抑えることが可能となる。ガラス転移点温度が１７０℃以上である熱硬化性樹脂としては、例えば、エポキシ樹脂、変性ポリイミド樹脂、変性トリアジン樹脂、変性ポリフェニレンオキサイド樹脂、変性ポリフェニレンエーテル樹脂、変性シアネートエステル樹脂などを用いることができるが、限定するものではない。エポキシ樹脂を用いた基板材料としては、市販のものとして、ＭＣＬ−Ｅ−６７９、ＭＣＬ−Ｅ−６７９Ｆ（以上、日立化成工業株式会社製、商品名）、Ｒ−１７５５、Ｒ−１５１５（以上、松下電工株式会社製、商品名）、ＥＬＣ−４７８１（住友ベークライト株式会社製、商品名）、ＣＳ−３６６５、ＣＳ−３３６５Ｓ、ＣＳ−３２８７（以上、利昌工業株式会社製、商品名）などを使用できる。また、変性ポリイミド樹脂を用いた銅張積層板としては、市販のものとして、ＭＣＬ−Ｉ−６７１（日立化成工業株式会社製、商品名）、Ｒ−４７０５（松下電工株式会社製、商品名）などを使用できる。また、変性トリアジン樹脂を用いた銅張積層板としては、市販のものとして、ＣＣＬ−８３０、ＣＣＬ−８３２、ＣＣＬ−８３２ＨＳ（以上、三菱ガス化学株式会社製、商品名）などを使用できる。また、変性ポリフェニレンエーテル樹脂を用いた銅張積層板としては、ＣＳ−３３７６Ｂ（利昌工業株式会社製、商品名）、ＴＬＣ−Ｗ−５９６（京セラケミカル株式会社製、商品名）などを使用できる。上記の各々の銅張り積層板に対応する多層化絶縁材料（プリプレグ）も、各メーカから市販されており、用いることが可能である。
（コンデンサ内蔵多層配線板）
コンデンサ内蔵多層配線板は、上記のコンデンサ内蔵多層配線板用材料を用いて、この銅箔面に絶縁層を介して導体回路を有する基板を積層し、コンデンサの形成および銅箔と導体パターンとの導通を行うことにより製造してもよい。また、コンデンサ内蔵多層配線板は、上記のコンデンサ内蔵多層配線板用基板を用いて、コンデンサの形成を行うことにより製造してもよい。さらに、上記のコンデンサ内蔵多層配線板用材料の金属箔（以下、金属箔Ａとする。）に絶縁層を介して金属箔（以下、金属箔Ｂとする。）を積層し、コンデンサの形成および金属箔Ａおよび金属箔Ｂの導通を行うことにより製造してもよい。以下これらについて説明する。
（第１のコンデンサ電極の形成）
基板表面の誘電体薄膜上にコンデンサ電極（以下、第１のコンデンサ電極とする。）を形成する。
第１のコンデンサ電極の厚みは１０〜５０μｍが好ましい。１０μｍ未満の場合には、電極１の外層にさらに絶縁層を形成したときに電極の引き出しパターンとして非貫通穴を設ける際、レーザ加工をすると誘電体薄膜の下の金属層がダメージを受け、破損しやすいという問題が発生し易い。また、５０μｍを超えると、エッチングで電極パターンを形成する際の加工精度が劣る場合がある。
誘電体薄膜上の所定の位置に第１のコンデンサ電極を形成する方法としては、誘電体薄膜上の全面に金属層を形成した後、エッチングにより形成する方法（第１の方法）、めっきレジスト形成後、金属めっきを行う方法（第２の方法）、および導電性ペーストにより印刷する方法（第３の方法）などがある。
第１の方法は、金属めっきまたはスパッタリングにより１０〜５０μｍの金属層を形成する工程と、任意の箇所をエッチング除去する工程とを含んでいてもよい。第１のコンデンサ電極となる金属層としては、種々の金属が挙げられるが、電気的特性および経済性を考慮すると銅が好ましい。金属層として銅を用いる場合は、誘電体薄膜からの酸素の移動による銅の酸化を防ぐため、金属層にクロム、モリブデン、チタンまたはニッケルなどをさらに含めるか、あるいは、金属層と誘電体薄膜の間にクロム、モリブデン、チタンまたはニッケルなど自己酸化被膜となる金属層を設けることが好ましい。
第２の方法は、誘電体薄膜の表面に０．１〜５μｍの金属層を形成する工程と、第１のコンデンサ電極を含む任意の部分を残して金属めっきレジストを形成する工程と、金属めっきにより１０〜５０μｍの第１のコンデンサ電極を形成する工程と、金属めっきレジストをエッチング除去する工程と、誘電体薄膜の表面に形成した０．１〜５μｍの金属層をエッチング除去する工程とを含む。０．１〜５μｍの金属層としては、種々の金属が挙げられるが、電気的特性と経済性を考慮すると銅が好ましい。銅を用いる場合には、銅の酸化を防止するために、０．１〜５μｍの金属層との間に自己酸化性被膜を形成する金属層を設けることが好ましい。自己酸化性皮膜を形成する金属層は、クロム、モリブデン、チタン、ニッケルなどの金属層が好ましい。金属めっきにより形成された１０〜５０μｍの金属層としては、電気的特性および経済性を考慮すると、銅、銀、錫、ニッケルまたは亜鉛を含むことが好ましい。めっきレジストとしては、例えば、フォテックＨ−９３３０（商品名、日立化成工業株式会社製）を使用することができる。めっきレジストのエッチング液および０．１〜５μｍの金属層のエッチング液としては、公知のものを使用できる。
第３の方法は、誘電体薄膜上の第１のコンデンサ電極を形成する任意の箇所に化学的な反応により金属化される導電性ペーストを印刷し、硬化させる工程を含んでいてもよい。また、第１のコンデンサ電極となる箇所を含む部分に導電性ペーストを印刷し、不要な箇所をエッチングして第１のコンデンサ電極を形成してもよい。化学的な反応により金属化される導電性ペーストとしては、コンデンサ内蔵多層配線板用基板に使用できる前記の導電性ペーストが使用できるが、特に金属粒子の平均粒径が０．１〜１０ｎｍのものが好ましい。化学的な反応により金属化される導電性ペーストを用いることにより、処理工程数の多いめっきプロセスを用いることなく第１のコンデンサ電極が形成でき、コンデンサ内蔵多層配線板の製造日数を低減することができる。
（コンデンサ誘電体の形成）
前記のコンデンサ内蔵多層配線板用材料または基板の誘電体薄膜を、コンデンサ誘電体となる箇所を残してエッチング除去することにより、コンデンサ誘導体を形成する。
エッチング除去する方法としては、例えば、イオンビームエッチング法、ＲＩＥ（ＲｅａｃｔｉｖｅＩｏｎＥｔｃｈｉｎｇ）法やウェットエッチング法が挙げられる。
イオンビームエッチング法は、アルゴン等の不活性ガスのイオンを電界により加速してから基板に照射し誘電体薄膜を除去する技術である。
ＲＩＥ法は、減圧強電界下で、フロン系ガスなどの反応性のガスプラズマを発生させ、それにより誘電体薄膜を除去する技術である。
ウェットエッチング法は、エッチング溶液（エッチャント）などの誘電体を溶解せしめることが可能なエッチング溶液（エッチャント）を用いて誘電体薄膜を除去する技術である。エッチャントとしては、公知のものを用いることができ、例えば、フッ酸を含んだ溶液、アンモニアおよび過酸化水素含む水溶液、およびＥＤＴＡ、アンモニアおよび過酸化水素を含む水溶液などが挙げられる。しかし、フッ酸は反応性が高いことから危険性がある。アンモニアおよび過酸化水素含む水溶液、およびＥＤＴＡ、アンモニアおよび過酸化水素を含む水溶液は、アルカリ性である。そのため、エッチングによってパターニングを行う場合、エッチングレジストには耐アルカリ性のレジスト、すなわちゴム系レジストなどを用いる必要がある。このようなレジストでは現像液や剥離液に特殊な薬品や溶剤を用いていることから専用の設備を設ける必要がある。そこで、次の２つの方法によるエッチャントを用いる方法により誘電体薄膜のエッチングを行ってもよい。
２つの方法とは、キレート剤と過酸化水素を含むエッチャントを用いる方法（第１の方法）、および硫酸、塩酸、りん酸、硝酸及び酢酸からなる群から選ばれる少なくとも１つの酸と過酸化水素を含むエッチャントを用いる方法（第２の方法）である。第１と第２の方法において行う誘電体薄膜のエッチングはウェットエッチングであり、ドライプロセスによるエッチングに比べ生産性に優れている。また、大型基板にも対応できるため経済的である。さらには、通常のフォトリソプロセスで使用するアルカリ現像型のエッチングレジストを使用するため、専用の設備を設ける必要がなく、特殊な薬液も使用しないため安価であり、かつ効率良く薄膜パターニングを行うことが可能である。
第１の方法では、誘電体薄膜のエッチャントとして、キレート剤と過酸化水素を含むものを用い、通常、エッチャントは水溶液である。フッ酸を用いずにキレート剤と過酸化水素を含む水溶液により誘電体薄膜をエッチングすることができるため、薬液の取り扱いが容易であり危険性を低減することができる。また、キレート剤や過酸化水素は通常のプリント配線板製造プロセスで使用されているものであり、使用に際して新たに大きな負荷がかかることがない。エッチャントのキレート剤濃度は、０．００１〜０．５ｍｏｌ／ｌとするのが望ましい。誘電体薄膜のエッチングには、最低０．００１ｍｏｌ／ｌが必要であり、限界濃度である０．５ｍｏｌ／ｌまでの範囲で任意に設定することができる。さらに望ましくは、０．１〜０．３ｍｏｌ／ｌとすることにより、安定性の良いエッチングレートを得ることができる。また、過酸化水素濃度は１〜５０ｗｔ％とするのが望ましい。この範囲内で過酸化水素濃度を任意に設定することでエッチングレートの調整が可能である。使用上最低限許容されるエッチングレートを得るためには、少なくとも１ｗｔ％の過酸化水素が必要であり、薬液の取扱い性に問題のない５０ｗｔ％までの範囲で任意に設定することができる。さらに望ましくは、２０〜３０ｗｔ％とすることで適正なエッチングレートを得ることができ、かつ液濃度の管理も容易に行うことが可能となる。上述した濃度に管理されたエッチャントは、酸性エッチャントであり、エッチャントのｐＨは２〜７の範囲で管理されることが望ましい。なお、緩衝液によりｐＨをアルカリ側に調整することも可能であるが、その場合、耐アルカリ性のエッチングレジストを用いる必要があり、耐アルカリ性を有するレジストは一般に専用の設備や薬液が必要である。従って、前記の理由からも、エッチャントのｐＨは２〜７の範囲で管理されることが望ましい。
本発明に用いるキレート剤は、エチレンジアミン四酢酸（ＥＤＴＡ）、ヒドロキシエチルイミノ二酢酸（ＨＩＤＡ）、イミノ二酢酸（ＩＤＡ）、ジヒドロキシエチルグリシン（ＤＨＥＧ）及びこれらのアルカリ塩の群から選ばれる少なくとも１つのキレート剤であることが、好ましい。前記のキレート剤は水溶性であることから、ＮＨ_４ＯＨ、ＮａＯＨなどのアルカリ溶液を用いる必要がない。これは前述した酸性エッチャントを得るために有効であり、レジストの選択が容易であることに加え、薬液コストの低減にも寄与するものである。
第２の方法において用いられる誘電体薄膜のエッチャントは、硫酸、塩酸、りん酸、硝酸及び酢酸からなる群から選ばれる酸と過酸化水素を含み、通常、水溶液である。前記の酸は、通常の配線板製造にも使用されるものであり、フッ酸に比べ取り扱いが容易である。これらの酸と過酸化水素の水溶液により、容易に誘電体薄膜をエッチングすることが可能となるものである。
エッチャントの硫酸、塩酸、りん酸、硝酸及び酢酸からなる群から少なくとも１つ選ばれる酸の濃度を１〜３０ｗｔ％とするのが好ましい。より高濃度にするほどエッチングレートを高くすることが可能であるが、薬液の取り扱いが難しくなる。したがって、濃度は３０ｗｔ％を上限とするのが好ましい。また、使用上最低限許容されるエッチングレートを得るためには１ｗｔ％以上とするのが好ましい。さらに好ましくは、５〜３０ｗｔ％とすることで取扱い性に優れ、かつ適正なエッチングレートを得ることが可能である。また、薬液の取り扱いも容易で優れたエッチングレートを得ることが可能となるものである。
第１と第２の方法において、少なくとも基板表面の所定の位置に形成されたコンデンサ電極となる金属層上にエッチングレジストが形成されていればよい。エッチングレジストとしては、市販の感光性ドライフィルムやアルカリ現像型レジストインクなどが、使用できるが、感光性ドライフィルムを用いることが好ましい。感光性ドライフィルムは、プリント配線板製造プロセスで最も汎用なレジスト材である。低コストなレジスト形成が可能なばかりでなく、作業性にも非常に優れている。使用するエッチングレジストは特に限定されるものではないが、例えばＦＸ１４０（デュポンＭＲＣドライフィルム株式会社製、商品名）、ＮＩＴ２４０（ニチゴー・モートン株式会社製、商品名）、Ｈ−９０４０（日立化成工業株式会社製、商品名）などを用いることができる。なお、市販のアルカリ現像型レジストインクとしては、ＰＥＲ−２０（太陽インキ製造株式会社製、商品名）などが挙げられる。エッチングレジストを、基板表面のコンデンサ電極となる金属層上と誘電体薄膜上に形成し、回路パターンを焼き付け、さらに現像を行う。なお、現像には炭酸ナトリウム水溶液、エッチングレジストの剥離には水酸化ナトリウム水溶液を用いることができ、環境に対する負荷が小さいことも特長である。また、スクリーン印刷などで、インク状エッチングレジストを用い、コンデンサ電極となる金属層上のみに、エッチングレジストを形成してもかまわない。
感光性ドライフィルムを用いる場合、その膜厚は、コンデンサ電極となる金属層の１〜３倍の厚みであることが望ましい。保護される金属層の厚みより薄い場合では、金属層と被エッチング層表面の段差の埋込み性が悪くボイドが発生し、エッチング不良を招きやすい。また、３倍を超えると、エッチング性が低下するためパターンの微細化が困難となる。さらに望ましくは金属層の２〜３倍とすることである。２〜３倍とすることで、段差に対して良好な追従性を有し、かつエッチング性にも優れるからである。
第１と第２の方法において、誘電体薄膜のエッチングが２０〜４５℃で行われるコンデンサ内蔵多層配線板の製造方法である。２０℃を下回るとエッチングレートが著しく低下するためエッチングに多大な時間を要し不経済である。また、４５℃を超えるとレジストの密着性が低下し、エッチング不良を招きやすくなる。したがって、エッチング温度は２０〜４５℃とするのが好ましい。より好ましくは２０〜３０℃とすることにより良好なエッチングレートとレジスト密着性を両立でき、作業性と歩留りの向上が図れるものである。
誘電体薄膜と第１のコンデンサ電極との間に、前記の酸化保護皮膜または自己酸化皮膜として金属層を設けることが好ましい。コンデンサ内蔵多層配線板用材料に用いたものと同様のものを用いることができる。
（第２のコンデンサ電極の形成）
前記のコンデンサ内蔵多層配線板用材料またはコンデンサ内蔵多層配線板用基板に含まれる金属箔または金属層を、任意の部分を残してエッチングすることにより、コンデンサ電極（第２のコンデンサ電極）を得ることができる。エッチングは公知の方法により行うことができる。
第２のコンデンサ電極の形成は、第１のコンデンサ電極の形成と同時または第１のコンデンサ電極の形成後に行ってもよい。特に、第２のコンデンサ電極の形成を第１のコンデンサ電極の形成と同時に行うと、製造プロセス工程が簡略化され、製造日数が低減し、経済性に優れる。この場合には、コンデンサ誘電体を形成して、その上に第１のコンデンサ電極となる金属層を形成した後、第１および第２のコンデンサ電極を同時にエッチングする。
第２のコンデンサ電極が多層配線板のグランド層または電源層と共通である場合には、第２のコンデンサ電極をグランド層または電源層の層に用いることが好ましい。一般的にグランド層または電源層のパターンは配線パターンよりも大きな面積を有する。本発明において作製されるコンデンサ電極の面積は、誘電体薄膜上に形成される第１のコンデンサ電極よりも誘電体薄膜を形成するときに基板表面を被覆していた金属層をパターニングして形成した第２のコンデンサ電極の方が大きくなるために、第２のコンデンサ電極をグランド層または電源層に用いることが好ましいとするものである。
（第２のコンデンサ電極と導体回路を有する基板の導体との接続）
本発明の一実施形態である、コンデンサ内蔵多層配線板用材料を用いてコンデンサ内層多層配線板を製造する場合は、コンデンサ内蔵多層層配線板用材料の銅箔面に、絶縁層を介して導体回路を有する基板を積層してもよい。このコンデンサ内層多層配線板においては、第２のコンデンサ電極と導体回路との接続は：絶縁層を除去して電解めっきによって接続してもよいし（第１の方法）；予め導電性ペーストが貫通穴に充填された絶縁層を用いることにより接続させてもよい（第２の方法）。
第１の方法は、第１および第２のコンデンサ電極およびコンデンサ誘電体を形成後、レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と；その基板表面に０．１〜５μｍの金属層を形成する工程と；穴を含む任意の箇所を除いてめっきレジストを形成する工程と；めっきレジストを形成した箇所以外の基板表面に１０〜５０μｍの金属層を形成して層間の回路パターンを電気的に接続させる工程；基板表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と；少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去する工程を含んでいてもよい。金属層、めっきレジスト等については、第１のコンデンサ電極に用いたものと同様のものを用いることができる。
第２の方法は、絶縁層となるプリプレグ等の絶縁材料にドリルやレーザにより貫通穴を形成する工程と、化学的な反応により金属化される導電性ペーストを、スクリーン印刷等を用いて貫通穴へ充填する工程とを備えていてもよい。導電性ペーストは、前記のコンデンサ内蔵多層配列用基板に用いる導電性ペーストと同様のものを用いることができる。
本発明の一実施形態である、コンデンサ内蔵多層配線板用基板を用いてコンデンサ内蔵多層配線板を製造する場合は、基板内部に導体層間を接続するバイアホールが備えられているので、特に導通は行わなくてよい。
本発明の一実施形態である、コンデンサ内蔵多層配線板用材料を用いてコンデンサ内層多層配線板を製造する場合には、コンデンサ内蔵多層層配線板用材料の銅箔面に、絶縁層を介して金属箔Ｂを積層することができる。このコンデンサ内層多層配線板においては、絶縁層および金属箔Ｂを除去して穴形成後、穴内に金属層を形成することにより接続してもよいし（第１の方法）；予め導電性ペーストが貫通穴に充填された絶縁層を用いることにより接続してもよい（第２の方法）。
第１の方法においては、絶縁層の除去はレーザにより行うことができ、金属箔Ｂの除去はレーザまたはエッチングより行うことができる。レーザを用いて金属箔Ｂと絶縁層を同時に除去して穴を形成すると、製造プロセス工程が簡略化され、製造日数を低減し、経済性に優れる。このような製造方法を可能とする金属箔Ｂとしては、レーザ光のエネルギーを吸収しやすい処理を施されていることが好ましい。銅箔の場合、このような処理としては、酸化銅処理、マイクロエッチング処理、粗化めっき処理などの表面粗化処理が有効であり、その表面粗さとしては０．１〜３μｍが好ましい。０．１μｍ未満の場合には、レーザ光の吸収が十分でなく加工性に劣り、３μｍを超えると加工精度に劣る。また銅箔の厚みとしては、１〜１８μｍが好ましい。１μｍ未満の銅箔は取り扱い性に劣り、１８μｍを超える銅箔は加工性に劣る。また、銅表面の粗化処理の他にニッケルなどのレーザ光を吸収しやすい金属層を表面に設けても良い。このような金属層や基板表面の金属層を形成する方法としては、例えば、スパッタリング法、無電解めっき法、電解めっき法及びこれらの組み合わせた方法が挙げられる。
次に、形成した穴に金属層を形成することにより、金属箔Ｂと金属箔Ａ（コンデンサ電極）とを電気的に接続することができる。この電気的な接続は、例えば、電解めっきにより、または導電性ペーストの形成により行うことができる。第１の方法は、穴内を含む基板の両面に０．１〜５μｍの金属層を形成する工程と、穴部を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、金属めっきにより、穴部を含む部分に導体パターンを形成する工程と、不要な金属めっきレジストを除去する工程と、不要な部分に形成された０．１〜５μｍの金属層を除去する工程とを含んでいてもよい。金属層、めっきレジスト等については、第１のコンデンサ電極に用いたものと同様のものを用いることができる。
なお、コンデンサ内蔵多層配線板用材料の誘電体薄膜上に金属層２を形成する前に、穴を含む基板表面の両面に金属層を形成すると、穴内の金属層形成と、第１のコンデンサ電極となる金属層の形成が同時に行われるので好ましい。金属層の形成は、穴内を含む基板の両面に０．１〜５μｍの金属層を形成する工程と、穴部を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、金属めっきにより穴部を含む部分に導体パターンを形成する工程と、金属めっきレジストを除去する工程と、基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程とを備えていてもよい。また、金属箔Ｂと金属箔Ａ（コンデンサ電極）との電気的な接続は、前に説明した導電性ペーストによって行ってもよい。
第２の方法において、絶縁層となるプリプレグ等の絶縁材料にドリル穴明けやレーザ穴明けにより貫通穴を形成する工程と、化学的な反応により金属化される導電性ペーストを、スクリーン印刷等を用いて貫通穴へ充填する工程とを備えていてもよい。導電性ペーストは、前記のコンデンサ内蔵多層配列用基板に用いる導電性ペーストと同様である。
本発明においては、必要に応じて、基板の両面または片面に、さらに絶縁層を介して回路層を１層以上形成することにより、３層以上のコンデンサ内蔵多層配線板を得ることができる。
本発明の一実施態様において、コンデンサ内蔵多層配線板は、第１のコンデンサ電極を形成する導体層のパターンは全てコンデンサの電極を形成し、誘電体薄膜の投影面は第１のコンデンサ電極の投影面を含み、第２のコンデンサ電極を形成する導体層には第２のコンデンサ電極とこの電極と電気的に絶縁された少なくとも１つのパターンを有することができる。
本発明の一実施態様において、これらの製造方法により作製したコンデンサ内蔵多層配線板においては、第１のコンデンサ電極を形成する金属層のパターンの下部には第２のコンデンサ電極を形成する金属のパターンが存在する。そのために、第１のコンデンサ電極を形成する金属層に配線パターンを形成すると、第２のコンデンサ電極を形成する金属層との間に寄生容量が発生し、電気信号の伝送特性が劣化するという問題が発生し、好ましくない。したがって、配線パターンは第２のコンデンサ電極の金属層に設置することが好ましい。
また、本発明の一実施態様において、これらの製造方法により作製したコンデンサ内蔵多層配線板においては、１）コンデンサの誘電体を形成する誘電体薄膜の投影面に含まれる第１のコンデンサ電極を有し、２）誘電体薄膜の端部は全て第１のコンデンサ電極を形成する導体層が第２のコンデンサ電極に電気的に接続されていてもよい。これによると、製造プロセス工程が簡略化され、製造日数低減や経済性に優れたコンデンサ内蔵多層配線板である。
本発明の一実施態様においては、これらの製造方法により作成したコンデンサ内蔵が多層配線板は、半導体チップを搭載してもよい。コンデンサを基板に内蔵しているため、搭載部品の低減が可能であり、小型の半導体装置を提供できる。
コンデンサ内蔵多層配線板の製造方法を具体的に挙げる。
次の製造方法は、金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法の具体例である。
（ａ−１）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に１０〜５０μｍの金属層を形成する工程と、３）その金属層の任意の部分を残してエッチング除去して所望の第１のコンデンサ電極を形成する工程と、４）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、５）誘電体薄膜を除去して現れた金属箔の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ａ−２）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に０．１〜５μｍの金属層を形成する工程と、３）第１のコンデンサ電極を含む任意の部分を残して金属めっきレジストを形成する工程と、４）金属めっきにより１０〜５０μｍの第１のコンデンサ電極を形成する工程と、５）金属めっきレジストを除去する工程と、６）誘電体薄膜の表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、７）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、８）誘電体薄膜を除去して現れた金属箔の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ａ−３）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて１０〜５０μｍの金属層を形成して所望の第１のコンデンサ電極を形成する工程と、３）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属箔の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ａ−４）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）コンデンサ誘電体を形成した基板表面に１０〜５０μｍの金属層を形成する工程と、４）その金属層の任意の部分を残してエッチング除去して所望の第１のコンデンサ電極、第２のコンデンサ電極およびコンデンサ電極と電気的に絶縁された任意の導体パターンを形成する工程を有する。
（ａ−５）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に１０〜５０μｍの金属層を形成する工程と、３）その金属層の任意の部分を残してエッチング除去して所望の第１のコンデンサ電極を形成する工程と、４）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、５）誘電体薄膜を除去して現れた金属箔の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、６）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、７）その基板表面に０．１〜５μｍの金属層を形成する工程と、８）穴を含む任意の箇所を除いてめっきレジストを形成する工程と、９）めっきレジストを形成した箇所以外の基板表面に１０〜５０μｍの金属層を形成して層間の回路パターンを電気的に接続させる工程と、１０）基板表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、１１）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ａ−６）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面に０．１〜５μｍの金属層を形成する工程と、３）第１のコンデンサ電極を含む任意の部分を残して金属めっきレジストを形成する工程と、４）金属めっきにより１０〜５０μｍの第１のコンデンサ電極を形成する工程と、５）金属めっきレジストを除去する工程と、６）誘電体薄膜の表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、７）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、８）誘電体薄膜を除去して現れた金属箔の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、９）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、１０）その基板表面に０．１〜５μｍの金属層を形成する工程と、１１）穴を含む任意の箇所を除いてめっきレジストを形成する工程と、１２）めっきレジストを形成した箇所以外の基板表面に１０〜５０μｍの金属層を形成して層間の回路パターンを電気的に接続させる工程と、１３）基板表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、１４）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ａ−７）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて１０〜５０μｍの金属層を形成して所望の第１のコンデンサ電極を形成する工程と、３）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属箔の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、５）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、６）その基板表面に０．１〜５μｍの金属層を形成する工程と、７）穴を含む任意の箇所を除いてめっきレジストを形成する工程と、８）めっきレジストを形成した箇所以外の基板表面に１０〜５０μｍの金属層を形成して層間の回路パターンを電気的に接続させる工程と、９）基板表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、１０）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ａ−８）１）コンデンサ内蔵多層配線板用材料の金属箔の面にプリプレグを介して導体回路を有する基板に積層する工程と、２）誘電体薄膜任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）誘電体薄膜を除去して現れた金属箔の任意の箇所をエッチング除去して硬化したプリプレグの絶縁層を露出させる工程と、４）レーザ照射により露出された絶縁層を除去して穴を形成し、内層となっている導体回路を露出させる工程と、５）コンデンサ誘電体を形成した基板表面と穴内の表面に１０〜５０μｍの金属層を形成する工程と、６）少なくともコンデンサ誘電体と導体化された穴を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
次の製造方法は、基板内部に導体層間を接続するバイアホールを有し，かつ、表面に平滑な金属層を有する基板の表面に比誘電率が１０〜２０００で、かつ、膜厚が０．０５〜２μｍの誘電体薄膜を形成したことを特徴とするコンデンサ内蔵多層配線板用基板を内層板として用いるコンデンサ内蔵多層配線板の製造方法の具体例である。
（ｂ−１）１）誘電体薄膜の表面に１０〜５０μｍの金属層を形成する工程と、２）その金属層の任意の部分を残してエッチング除去して所望の第１のコンデンサ電極を形成する工程と、３）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ｂ−２）１）誘電体薄膜の表面に０．１〜５μｍの金属層を形成する工程と、２）第１のコンデンサ電極を含む任意の部分を残して金属めっきレジストを形成する工程と、３）金属めっきにより１０〜５０μｍの第１のコンデンサ電極を形成する工程と、４）金属めっきレジストを除去する工程と、５）誘電体薄膜の表面に形成した０．１〜５μｍの金属層をエッチング除去する工程と、６）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、７）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有する。
（ｂ−３）１）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて１０〜５０μｍの金属層を形成して所望の第１のコンデンサ電極を形成する工程と、２）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）誘電体薄膜を除去して現れた金属層の少なくともコンデンサ誘電体を含む任意の部分を残してエッチング除去して所望の第２のコンデンサ電極を含む導体パターンを形成する工程を有することを特徴とするコンデンサ内蔵多層配線板の製造方法。
（ｂ−４）１）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、２）コンデンサ誘電体を形成した基板表面に１０〜５０μｍの金属層を形成する工程と、３）その金属層の任意の部分を残してエッチング除去して所望の第１のコンデンサ電極、第２のコンデンサ電極およびコンデンサ電極と電気的に絶縁された任意の導体パターンを形成する工程を有する。
次の製造方法は、金属箔の片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を、金属箔が絶縁材料と接するように絶縁材料の少なくとも片面に設けた基板を用いるコンデンサ内蔵多層配線板の製造方法の具体例に関する。
（ｃ−１）１）基板表面の誘電体薄膜上の所定の位置にコンデンサ電極となる金属層を形成する工程と、２）少なくとも基板表面の前記金属層上にエッチングレジストを形成する工程と、３）キレート剤と過酸化水素を含むエッチャントによって、誘電体薄膜をウェットエッチングする工程と、４）ウェットエッチング後にエッチングレジストを除去する工程とを有する。
（ｃ−２）１）基板表面の誘電体薄膜上の所定の位置にコンデンサ電極となる金属層を形成する工程と、２）少なくとも基板表面の前記金属層上にエッチングレジストを形成する工程と、３）硫酸、塩酸、りん酸、硝酸及び酢酸からなる群から選ばれる少なくとも１つの酸と過酸化水素を含むエッチャントによって、誘電体薄膜をウェットエッチングする工程と、４）ウェットエッチング後にエッチングレジストを除去する工程とを有する。
次の製造方法は、金属箔Ａの片面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたコンデンサ内蔵多層配線板用材料を用いるコンデンサ内蔵多層配線板の製造方法の具体例である。
（ｄ−１）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所をエッチング除去して、上記絶縁材料から形成された絶縁層を露出させる工程と、３）レーザ照射により、露出された絶縁層を除去して穴を形成し、金属箔Ａを露出させる工程と、４）穴内を含む基板表面の両面に金属層を形成する工程と、５）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状の第１のコンデンサ電極パターンをエッチングで形成する工程と、６）露出された誘電体薄膜から第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、７）誘電体薄膜を除去して現れた金属箔Ａからコンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極をエッチングで形成する工程を有する。
（ｄ−２）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所にレーザ照射することにより、金属箔Ｂと上記絶縁材料から形成された絶縁層とを同時に除去して穴を形成し、金属箔Ａを露出させる工程と、３）穴内を含む基板表面の両面に金属層を形成する工程と、４）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状の第１のコンデンサ電極パターンをエッチングで形成する工程と、５）露出された誘電体薄膜から第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、６）誘電体薄膜を除去して現れた金属箔Ａからコンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極をエッチングで形成する工程を有する。
（ｄ−３）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）基板表面の少なくとも誘電体薄膜側に金属層を形成する工程と、３）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状の第１のコンデンサ電極パターンをエッチングで形成する工程と、４）露出された誘電体薄膜から第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、５）誘電体薄膜を除去して現れた金属箔Ａにコンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極をエッチングで形成する工程を有する。
（ｄ−４）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）基板表面の少なくとも誘電体薄膜側に金属層を形成する工程と、３）コンデンサ内蔵多層配線板用材料の誘電体薄膜上の金属層から任意の形状の第１のコンデンサ電極パターンをエッチングで形成する工程と、４）露出された誘電体薄膜から第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、５）誘電体薄膜を除去して現れた金属箔Ａからコンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極をエッチングで形成する工程を有する。
（ｄ−５）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所をエッチング除去して、上記絶縁材料から形成された絶縁層を露出させる工程と、３）レーザ照射により露出された絶縁層を除去して穴を形成し、金属箔Ａを露出させる工程と、４）穴内を含む基板の両面に０．１〜５μｍの金属層を形成する工程と、５）第１のコンデンサ電極となる部分と穴部を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、６）金属めっきにより、上記の第１のコンデンサ電極となる部分と穴部を含む部分に導体パターンを形成する工程と、７）金属めっきレジストを除去する工程と、８）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、９）露出された誘電体薄膜から第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、１０）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極を形成する工程と、１１）露出された金属箔Ｂをエッチングにより回路形成する。
（ｄ−６）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）金属箔Ｂの任意の箇所にレーザ照射することにより、金属箔Ｂと上記絶縁材料から形成された絶縁層とを同時に除去して穴を形成し、金属箔Ａを露出させる工程と、３）穴内を含む基板の両面に０．１〜５μｍの金属層を形成する工程と、４）第１のコンデンサ電極となる部分と穴部を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、５）金属めっきにより、上記の第１のコンデンサ電極となる部分と穴部を含む部分に導体パターンを形成する工程と、６）金属めっきレジストを除去する工程と、７）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、８）露出された誘電体薄膜から、第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、９）誘電体薄膜を除去して現れた金属箔Ａから、コンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極を形成する工程と、１０）露出された金属箔Ｂをエッチングにより回路形成する工程を有する。
（ｄ−７）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）基板の少なくとも誘電体薄膜側の表面に０．１〜５μｍの金属層を形成する工程と、３）第１のコンデンサ電極となる部分を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、４）金属めっきにより第１のコンデンサ電極となる部分を含む部分に導体パターンを形成する工程と、５）金属めっきレジストを除去する工程と、６）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、７）露出された誘電体薄膜から、第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、８）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極を形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有する。
（ｄ−８）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）基板の少なくとも誘電体薄膜側の表面に０．１〜５μｍの金属層を形成する工程と、３）第１のコンデンサ電極となる部分を含む任意の部分を残して基板表面に金属めっきレジストを形成する工程と、４）金属めっきにより第１のコンデンサ電極となる部分を含む部分に導体パターンを形成する工程と、５）金属めっきレジストを除去する工程と、６）基板表面に露出された０．１〜５μｍの金属層をエッチング除去する工程と、７）露出された誘電体薄膜から、第１のコンデンサ電極パターンを含む任意の形状のコンデンサ誘電体をエッチングで形成する工程と、８）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極を形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有する。
（ｄ−９）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて金属層を形成して所望の第１のコンデンサ電極を形成する工程と、３）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極を形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有する。
（ｄ−１０）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の表面の任意の部分に化学的な反応により金属化される導電性ペーストを用いて金属層を形成して所望の第１のコンデンサ電極を形成する工程と、３）誘電体薄膜の少なくとも第１のコンデンサ電極を含む任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、４）誘電体薄膜を除去して現れた金属箔Ａから、エッチングにより、コンデンサ誘電体パターンを含む任意の形状の第２のコンデンサ電極を形成し、露出された金属箔Ｂをエッチングにより回路形成する工程を有する。
（ｄ−１１）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）金属箔Ｂの任意の箇所をエッチング除去して、上記絶縁材料から形成された絶縁層を露出させる工程と、４）レーザ照射により露出された絶縁層を除去して穴を形成し、金属箔Ａを露出させる工程と、５）穴内を含む基板表面の両面に金属層を形成する工程と、６）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望の第１のコンデンサ電極及び第２のコンデンサ電極を形成する工程を有する。
（ｄ−１２）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）金属箔Ｂの任意の箇所にレーザ照射することにより、金属箔Ｂと上記絶縁材料から形成された絶縁層とを同時に除去して穴を形成して金属箔Ａを露出させる工程と、４）穴内を含む基板表面の両面に金属層を形成する工程と、５）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望の第１のコンデンサ電極及び第２のコンデンサ電極を形成する工程を有する。
（ｄ−１３）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が熱硬化性樹脂と金属フィラーを含む導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）基板の少なくともコンデンサ誘電体を有する表面に金属層を形成する工程と、４）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望の第１のコンデンサ電極及び第２のコンデンサ電極を形成する工程を有する。
（ｄ−１４）１）コンデンサ内蔵多層配線板用材料の金属箔Ａの面に、任意の箇所に貫通穴が設けられかつその貫通穴が化学的な反応により金属化される導電性ペーストで充填されている絶縁材料を介して金属箔Ｂを積層し基板とする工程と、２）誘電体薄膜の任意の部分を残してエッチング除去して所望のコンデンサ誘電体を形成する工程と、３）基板の少なくともコンデンサ誘電体を有する表面に金属層を形成する工程と、４）その金属層及び金属箔Ａの任意の部分を残してエッチング除去して、所望の第１のコンデンサ電極及び第２のコンデンサ電極を形成する工程を有する。
以下に、本発明の実施例を図面を用いてより具体的に述べる。
（実施例Ａ）
コンデンサ内蔵多層配線板用材料Ａ−１
銅箔１０２である厚み３５μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）の表面にチタンテトライソプロポキシド、ジルコンテトラターシャリーブトキシド、ジピバロイルメタン鉛錯体、二酸化窒素を用いたマイクロ波プラズマＣＶＤにより、基材温度３５０℃の条件下で厚さ０．５μｍのＰＺＴ（チタン酸ジルコン酸鉛）薄膜１０１を形成した（図１（ａ））。
コンデンサ内蔵多層配線板用材料Ａ−２
銅箔１０２である厚み３５μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）の表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜１０３を形成した。さらにその基板表面にチタンテトライソプロポキシド、ジルコンテトラターシャリーブトキシド、ジピバロイルメタン鉛錯体、二酸化窒素を用いたマイクロ波プラズマＣＶＤにより、基材温度３５０℃の条件下で厚さ０．５μｍのＰＺＴ（チタン酸ジルコン酸鉛）薄膜１０１を形成した（図１（ｂ））。
コンデンサ内蔵多層配線板用材料Ａ−３
銅箔１０２である厚み３５μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）の表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜１０３を形成した。さらにその表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度３５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜１０１を形成した（図１（ｂ））。
実施例Ａ−１
コンデンサ内蔵多層配線板用材料Ａ−２の銅箔１０２表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２（ａ））。板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）を基材として、所望の箇所に導体化された接続穴１０６と回路パターンを作製した両面基板１０４に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った後に、その一方の面に厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を、また他方の面に厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して前述のコンデンサ内蔵多層配線板用材料を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した（図２（ｂ））。ここで、符号１０５はめっき銅を、符号１０７は絶縁樹脂基材（プリプレグ硬化物）を指す。さらにそのＰＺＴ薄膜表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜１０８を形成した。さらにその表面に電気銅めっきにより２０μｍの金属層１０９を形成した（図２（ｃ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要な銅の金属層をエッチング除去し、フェリシアン化カリウム水溶液を用いてクロムの金属層をエッチング除去して、第１のコンデンサ電極のパターンを形成した（図２（ｄ））。続いて、所望のパターンのレジストを形成し、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜とルテニウム薄膜をエッチング除去した（図２（ｅ））。次に、この基板の表面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴を形成し、窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明け１１０を行った（図２（ｆ））。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成した。この基板の表面に所望のめっきレジスト１１１を形成し、電気銅めっきを行い、内層の回路導体と基板表面の導体層とを電気的に接続する金属層を形成した（図２（ｇ））。めっきレジストを剥離後、基板表面の０．５μｍの銅薄膜をエッチング除去して、その後、さらに所望のエッチングレジストを形成し、塩化第二鉄溶液によって不要な銅の金属層をエッチング除去して、第２のコンデンサ電極を含む回路パターンを形成して回路板を作製した（図２（ｈ））。
この回路板の回路表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。（１）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）、（２）厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）、（３）回路板、（４）絶縁樹脂基材１１２として、厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ、（５）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）の順に重ね、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した。キャリア銅箔を剥がし、不要な基板端部を切断後、この基板の表面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴を形成した。
この基板表面に設けた窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明けを行った。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、洗浄触媒付与、密着促進後無電解銅めっきを行い、レーザ穴内壁と銅箔表面に約２０μｍの無電解銅めっき層を形成した。この基板表面のパッドや回路パターンなど必要な箇所にエッチングレジストを形成し、不要な銅をエッチング除去して、外層回路を形成した。
この基板表面にソルダーレジストＰＳＲ−４０００ＡＵＳ５（太陽インキ製造株式会社、商品名）をロールコータで３０μｍ塗布、乾燥後に露光・現像して所望の箇所にソルダーレジスト１１３を形成した。その後、３μｍの無電解ニッケルめっきと０．１μｍの無電解金めっきを外層回路パターン露出部表面層に形成して、コンデンサ内蔵多層配線板を得た（図２（ｉ））。
実施例Ａ−２
コンデンサ内蔵多層配線板用材料Ａ−２をコンデンサ内蔵多層配線板用材料Ａ−３に替えた以外は実施例Ａ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実施例Ａ−３
コンデンサ内蔵多層配線板用材料Ａ−３の銅箔１０２表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図３（ａ））。板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）を基材として、所望の箇所に導体化された接続穴と回路パターンを作製した両面基板１０４に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った後に、その一方の面に絶縁樹脂基材１０７である厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を、また他方の面に絶縁樹脂基材１０７である厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して前述のコンデンサ内蔵多層配線板用材料を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した（図３（ｂ））。ここで、１０５はめっき銅であり１０６は穴埋め樹脂である。さらにそのＰＺＴ薄膜１０１表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜１０８を形成した。さらにその表面に触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成した。この基板の表面に所望のめっきレジストを形成し、電気銅めっきを行い、厚み２０μｍの第１のコンデンサ電極となる金属層１０９を形成した（図３（ｃ））。めっきレジストを剥離後、基板表面の０．５μｍの銅薄膜と０．０５μｍのクロム薄膜をエッチング除去して、第１のコンデンサ電極のパターンを形成した（図３（ｄ））。続いて、所望のパターンのレジストを形成し、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜とルテニウム薄膜をエッチング除去した（図３（ｅ））。次に、この基板の表面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴を形成し、窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明け１１０を行った（図３（ｆ））。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成した。この基板の表面に所望のめっきレジスト１１１を形成し、電気銅めっきを行い、内層の回路導体と基板表面の導体層とを電気的に接続する金属層を形成した（図３（ｇ））。めっきレジストを剥離後、基板表面の０．５μｍの銅薄膜をエッチング除去して、その後、さらに所望のエッチングレジストを形成し、塩化第二鉄溶液によって不要な銅の金属層をエッチング除去して、第２のコンデンサ電極を含む回路パターンを形成して回路板を作製した（図３（ｈ））。その後の多層配線板の加工は実施例Ａ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図３（ｉ））。ここで、１１２は絶縁樹脂基材であり、１１３はソルダーレジストである。
実施例Ａ−４
コンデンサ内蔵多層配線板用材料Ａ−３の銅箔表面１０２に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図４（ａ））。板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）を基材として、所望の箇所に導体化された接続穴と回路パターンを作製した両面基板１０４に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った後に、その一方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を、また他方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して前述のコンデンサ内蔵多層配線板用材料を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した（図４（ｂ））。ここで、１０５はめっき銅であり、１０６は穴埋め樹脂である。さらにそのＰＺＴ薄膜表面の所望の箇所にスクリーン印刷により、化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社、商品名）を４０μｍの厚みで印刷後、温度２００℃で加熱時間１時間の条件でベーキングし、導電性ペーストを金属化して、第１のコンデンサ電極のパターンを形成した（図４（ｃ））。続いて、所望のパターンのレジストを形成し、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜とルテニウム薄膜をエッチング除去した（図４（ｄ））。次に、この基板の表面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴を形成し、窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明け１１０を行った（図４（ｅ））。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成した。この基板の表面に所望のめっきレジスト１１１を形成し、電気銅めっきを行い、内層の回路導体と基板表面の導体層とを電気的に接続する金属層を形成した（図４（ｆ））。めっきレジストを剥離後、基板表面の０．５μｍの銅薄膜をエッチング除去して、その後、さらに所望のエッチングレジストを形成し、塩化第二鉄溶液によって不要な銅の金属層をエッチング除去して、第２のコンデンサ電極を含む回路パターンを形成して回路板を作製した（図４（ｇ））。その後の多層配線板の加工については実施例Ａ−１と同様な工程で行い、コンデンサ内蔵多層配線板を得た（図４（ｈ））。
ここで、１１２は絶縁樹脂基材であり、１１３はソルダーレジストである。(Materials for multilayer wiring boards with built-in capacitors)
One embodiment of the present invention is a multilayer wiring board material with a built-in capacitor, characterized in that a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of a metal foil. About. In this multilayer wiring board material, since the dielectric thin film is formed on the surface of the metal foil, it is easy to obtain a dielectric thin film having a uniform film thickness, and the variation in the capacitor capacity is small.
The thickness of the dielectric thin film is preferably 0.05 μm or more, and more preferably 0.1 μm or more, in order to ensure insulation and suppress leakage current. In consideration of economy, the film thickness is preferably 2 μm or less, more preferably 1 μm or less. Therefore, the film thickness is preferably 0.05 to 2 μm, more preferably 0.1 to 1 μm. 500pF / mm ² The relative dielectric constant necessary to obtain the above capacitance density is 2.9 or more when the film thickness is 0.05 μm, 5.7 or more when 0.1 μm, 57 or more when 1 μm, and 2 μm 113 or more. Therefore, if a thin film dielectric having a relative dielectric constant of 2.9 to 113 is used, the film thickness is 0.05 to 2 μm and 500 pF / mm. ² The thin film capacitor can be formed. However, the higher the relative dielectric constant of the thin film dielectric, the more superior the size of the built-in capacitor is, and 10 to 2000 is preferable, and 20 to 2000 is more preferable. Here, the relative dielectric constant indicates a value measured at a frequency of 1 MHz in accordance with IPC-650 2.5.5.2 under an environment temperature-controlled at 25 ° C. Further, the value of the film thickness can be obtained by using an apparatus capable of observing a thickness of less than 0.05 μm as exemplified by a scanning electron microscope in the cross section of the capacitor on which the electrode is formed.
The dielectric thin film is not limited as long as a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm can be formed. However, barium titanate, strontium titanate, calcium titanate, titanium Dielectrics such as magnesium oxide, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, barium strontium titanate, lead zirconate titanate, lead magnesium niobate-lead titanate It is preferable to use a film made of At this time, two or more kinds of solid solutions and laminates can also be used. In general, a metal oxide having a perovskite crystal structure is known to exhibit a high relative dielectric constant, and can be preferably used.
Examples of the metal foil include copper foil, silver foil, tin foil, nickel foil, and zinc foil. Among these, copper foil is preferable in consideration of electrical characteristics and economy. As for the thickness of metal foil, 10-50 micrometers is preferable. When using copper foil, it is preferable to provide a metal layer that forms a copper oxidation protective film and / or a metal layer that forms a stable self-oxidized film on the surface of the copper foil. These films are preferably 0.1 to 3 μm.
As the metal layer serving as the copper oxide protective film, a metal film of platinum, gold, silver, palladium, ruthenium, iridium or the like is preferable. When a copper foil is used as the metal foil, if a metal oxide dielectric thin film is directly formed on the copper surface, oxygen is supplied from the metal oxide to the copper and copper oxide is generated at the interface, thereby reducing adhesion. . Therefore, it is preferable to form an oxidation protective film that blocks oxygen supplied from the metal oxide and ensures adhesion with copper.
As the metal layer forming the self-oxidized film, a metal film of chromium, molybdenum, titanium, nickel or the like is preferable. When copper foil is used as metal foil, adhesion may be reduced by the generation of copper oxide, so oxygen supplied from the metal oxide dielectric thin film is blocked and adhesion with copper is ensured. It is preferable to form a self-oxidizing film.
The surface roughness of the metal foil is preferably 0.01 to 0.5 μm. As described above, the thickness of the dielectric thin film is preferably 0.05 to 2 μm, more preferably 0.1 to 1 μm. The surface roughness of the substrate on which the dielectric thin film is formed needs to be at least lower than the thickness of the dielectric thin film, and the thickness of the dielectric thin film is required to ensure reliability as an insulating film such as a leakage current. Is preferably less than 50%. Accordingly, a surface roughness of 0.025 to 0.5 μm is preferable, but in order to ensure reliability, the surface roughness is most preferably 0.01 to 0.5 μm. Here, the surface roughness refers to the average value of the difference in unevenness at any ten points by observing the surface with a scanning microscope.
The dielectric thin film may be formed on the metal foil by, for example, a vacuum deposition method, an ion plating method, a CVD (Chemical Vapor Deposition) method, a sputtering method, or a sol-gel method.
The vacuum deposition method is 1.3 × 10 ^-4 In this technique, a thin film material is heated and deposited in a high vacuum of Pa or less, and the evaporated particles are deposited on a substrate to form a dielectric thin film. The ion plating method is a technique for forming a dielectric thin film by ionizing evaporated particles and accelerating them by an electric field and then adhering them to the substrate in order to increase the adhesion strength of the vacuum deposited film to the substrate. The CVD method is a method in which halides, sulfides, hydrides, organometallic compounds, etc. containing elements that form a thin film are subjected to thermal decomposition, oxidation, reduction, polymerization, or gas phase chemical reaction in high temperature or plasma. This is a technique for forming a dielectric thin film by depositing a thin film composition on a substrate. Sputtering is a technique for forming a dielectric thin film by irradiating a target with ions and depositing a sputtered target material on a substrate. The sol-gel method is a technique in which a dielectric thin film is formed by coating a sol solution containing an element that forms a thin film on a substrate, gelling it by a condensation reaction, and annealing at a high temperature.
When forming a dielectric thin film on the surface of a metal foil, use a roll-shaped metal foil and form the dielectric thin film while moving the metal foil continuously in a heating furnace controlled at a constant temperature. Is preferred. By performing the continuous treatment, it becomes possible to form a dielectric thin film of uniform quality, which is economically excellent.
(Substrate for multilayer wiring board with built-in capacitor)
Furthermore, in one embodiment of the present invention, the surface of the substrate having via holes connecting the conductor layers inside the substrate and having a smooth metal layer on the surface has a relative dielectric constant of 10 to 2000, and The present invention relates to a substrate for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a film thickness of 0.05 to 2 μm is formed.
According to this embodiment, by using a substrate having a via hole inside the substrate, it is possible to arbitrarily design a wiring pattern connected to the capacitor electrode. In addition, since the dielectric thin film is formed on the surface of the metal layer having a smooth surface, it is easy to obtain a dielectric thin film having a uniform film thickness, and variations in capacitor capacitance are small.
As the metal layer, copper is preferable, and it is preferable to prevent oxidation of copper by providing an oxidation protection film and / or a self-oxidation film on the surface of the copper foil. The dielectric thin film can be the same as the dielectric thin film used for the capacitor built-in multilayer wiring board material, and can be formed in the same manner as described above.
Connection between conductor layers by via holes can be made by metal plating or conductive paste.
As the metal plating, metals such as copper, silver, nickel, zinc, tin, and alloys thereof can be used. The methods for connecting the layers by metal plating are as follows: 1) forming through holes by drilling or laser drilling in metal-clad laminates, 2) applying plating catalyst, 3) thin electroless plating, 4) thick electroplating, 5) Filling through holes with thermosetting hole filling resin, 6) Curing thermosetting hole filling resin, 7) Polishing for smoothing substrate surface, 8) Applying plating catalyst, 9) Thin electroless plating, 10) You may carry out by the method of thick electroplating. Thick electroplating may be thick electroless plating.
Examples of the conductive paste include a conductive paste made of a metal filler and a resin, or a conductive paste that is metalized by a chemical reaction.
As an electrically conductive paste which consists of a metal filler (metal powder) and resin, the thing from a metal filler and a thermosetting resin is preferable. Examples of the metal filler include silver, copper, tin, zinc, or an alloy thereof. The particle size is 0.5 to 10 μm. Examples of the thermosetting resin include a phenol resin, an epoxy resin, and a cyanate resin. The content of the metal filler in the conductive paste is preferably 60 to 80% by volume. As a conductive paste composed of a thermosetting resin and a metal filler, commercially available products include DD paste (Tatsuta System Electronics Co., Ltd., trade name), Dotite (Fujikura Kasei Co., Ltd., trade name), Unimec conductivity. A paste (trade name, manufactured by NAMICS CORPORATION) or the like can be used.
A conductive paste that is metallized by a chemical reaction has a lower volume resistivity than a conductive paste made of a thermosetting resin and a metal filler, and is advantageous in terms of electrical characteristics. Examples of such a conductive paste include a paste made of fine metal particles, a dispersant, and a solvent. The content of metal particles in this conductive paste is preferably 60 to 80% by weight. Examples of the metal particles of the conductive paste that is metallized by a chemical reaction include gold, platinum, silver, copper, palladium, ruthenium, and the like. The average particle size is preferably 0.1 to 10 nm. This conductive paste has very fine metal particles formed by evaporation in a gas and protected with a dispersant, so it exhibits almost the same behavior as a liquid at room temperature, and can be printed, applied, impregnated, etc. Formation is possible. Also, when heated to a certain temperature (150 to 200 ° C.), the supplementary substance is activated, and the chemical reaction such as removal of the dispersing agent brings the metal particles into contact with each other, accelerating the fusion and fusion, It has the property of forming a metalized electrical conductor. In order to metallize at a temperature at the time of heating and pressurization for stacking, that is, a temperature that does not reach the melting point of the metal, it is preferable to increase the reaction activity by using metal particles of 0.1 to 10 nm. In order to suppress reaction with oxygen, it is preferable to use metal particles such as gold, platinum, silver, copper, palladium, and ruthenium, which are difficult to oxidize. Commercially available products such as nano paste (trade name, manufactured by Harima Chemicals Co., Ltd.) can be used as the conductive paste that is metallized by such a chemical reaction, but is not limited thereto.
The connection method between the layers using the conductive paste is as follows: 1) a step of forming a through hole by drilling or laser drilling in the prepreg to be an insulating layer, 2) a step of filling the through hole with the conductive paste, 3) It may include a step of sandwiching between metal foils and pressurizing and curing. It is preferable that the temperature to heat is 25 to 350 degreeC. This is because thermal decomposition occurs in general resins when the temperature exceeds 350 ° C.
The connection between layers by either metal plating or conductive paste is not limited to a two-layer substrate, and a via hole that connects the conductor layers is electrically connected to the inside of the substrate by a metal even in a substrate having three or more layers. It may be.
The insulating material used for the substrate is preferably made of resin and glass woven fabric or glass nonwoven fabric. In order to perform the heat treatment of the substrate, it is necessary to ensure the rigidity of the substrate even at a high temperature. Therefore, it is preferable to use an insulating material consisting of a resin and a glass woven fabric or a glass nonwoven fabric rather than using an insulating material consisting only of a resin and an inorganic filler or an insulating material consisting of a resin and paper such as cellulose or synthetic resin. is there. Further, it is possible to use a sheet of a thermoplastic resin such as a highly heat-resistant fluorine resin or polyether ether ketone, or a thermosetting resin such as polyimide or polyamideimide, but it is inferior in economic efficiency. The material of the woven fabric or the nonwoven fabric is not limited as long as it has high rigidity at high temperature, that is, a material having a high elastic modulus, and D glass, E glass, S glass, or the like can be used.
The resin used for the insulating material of the substrate is a thermosetting resin, and its glass transition temperature is preferably 170 ° C. or higher. A substrate using an insulating material made of a thermosetting resin and glass woven fabric or glass nonwoven fabric is excellent in workability and economy. In addition, when the glass transition temperature is 170 ° C. or higher, it is possible to suppress deterioration due to heat during the formation of the dielectric thin film. Examples of the thermosetting resin having a glass transition temperature of 170 ° C. or higher include epoxy resins, modified polyimide resins, modified triazine resins, modified polyphenylene oxide resins, modified polyphenylene ether resins, and modified cyanate ester resins. However, it is not limited. As a substrate material using an epoxy resin, as commercially available materials, MCL-E-679, MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.), R-1755, R-1515 (above, Matsushita Electric Works Co., Ltd., trade name), ELC-4781 (Sumitomo Bakelite Co., trade name), CS-3665, CS-3365S, CS-3287 (above, Risho Kogyo Co., trade name) are used. it can. Moreover, as a copper clad laminated board using a modified polyimide resin, as a commercially available thing, MCL-I-671 (made by Hitachi Chemical Co., Ltd., brand name), R-4705 (made by Matsushita Electric Works, brand name) Etc. can be used. Moreover, as a copper clad laminated board using modified | denatured triazine resin, CCL-830, CCL-832, CCL-832HS (above, Mitsubishi Gas Chemical Co., Ltd. make, brand name) etc. can be used as a commercially available thing. Moreover, as a copper clad laminated board using modified polyphenylene ether resin, CS-3376B (Risho Industrial Co., Ltd., brand name), TLC-W-596 (Kyocera Chemical Co., Ltd. brand name), etc. can be used. Multi-layered insulating materials (prepregs) corresponding to each of the above-described copper-clad laminates are also commercially available from each manufacturer and can be used.
(Multilayer wiring board with built-in capacitor)
A multilayer wiring board with a built-in capacitor is formed by laminating a substrate having a conductor circuit on the copper foil surface through an insulating layer using the above-described material for a multilayer wiring board with a built-in capacitor, and forming a capacitor and forming a copper foil and a conductive pattern. You may manufacture by performing conduction | electrical_connection. Moreover, the multilayer wiring board with a built-in capacitor may be manufactured by forming a capacitor using the above-mentioned substrate for a multilayer wiring board with a built-in capacitor. Further, a metal foil (hereinafter referred to as metal foil B) is laminated on a metal foil (hereinafter referred to as metal foil A) of the above-mentioned capacitor-embedded multilayer wiring board material via an insulating layer to form capacitors. You may manufacture by performing conduction | electrical_connection of the metal foil A and the metal foil B. FIG. These will be described below.
(Formation of first capacitor electrode)
A capacitor electrode (hereinafter referred to as a first capacitor electrode) is formed on the dielectric thin film on the substrate surface.
The thickness of the first capacitor electrode is preferably 10 to 50 μm. If it is less than 10 μm, when a non-through hole is provided as an electrode lead pattern when an insulating layer is further formed on the outer layer of the electrode 1, the metal layer under the dielectric thin film is damaged and damaged when laser processing is performed. The problem of being easy to occur is likely to occur. Moreover, when it exceeds 50 micrometers, the processing precision at the time of forming an electrode pattern by an etching may be inferior.
As a method of forming the first capacitor electrode at a predetermined position on the dielectric thin film, a method of forming a metal layer on the entire surface of the dielectric thin film and then etching it (first method), plating resist formation Thereafter, there are a method of performing metal plating (second method) and a method of printing with a conductive paste (third method).
The 1st method may include the process of forming a 10-50 micrometers metal layer by metal plating or sputtering, and the process of carrying out the etching removal of arbitrary locations. The metal layer to be the first capacitor electrode includes various metals, but copper is preferable in consideration of electrical characteristics and economy. When copper is used as the metal layer, in order to prevent copper oxidation due to oxygen migration from the dielectric thin film, the metal layer further includes chromium, molybdenum, titanium or nickel, or the metal layer and the dielectric thin film It is preferable to provide a metal layer serving as a self-oxidation film, such as chromium, molybdenum, titanium, or nickel.
The second method includes a step of forming a metal layer of 0.1 to 5 μm on the surface of the dielectric thin film, a step of forming a metal plating resist leaving an arbitrary portion including the first capacitor electrode, and metal plating. Forming a 10-50 μm first capacitor electrode, etching a metal plating resist, and etching a 0.1-5 μm metal layer formed on the surface of the dielectric thin film. . The metal layer having a thickness of 0.1 to 5 μm includes various metals, but copper is preferable in consideration of electrical characteristics and economy. When using copper, in order to prevent copper oxidation, it is preferable to provide a metal layer that forms a self-oxidizing film between the metal layer of 0.1 to 5 μm. The metal layer forming the self-oxidizing film is preferably a metal layer of chromium, molybdenum, titanium, nickel or the like. The metal layer of 10 to 50 μm formed by metal plating preferably contains copper, silver, tin, nickel or zinc in consideration of electrical characteristics and economy. As the plating resist, for example, Photec H-9330 (trade name, manufactured by Hitachi Chemical Co., Ltd.) can be used. As the etching solution for the plating resist and the etching solution for the metal layer of 0.1 to 5 μm, known ones can be used.
The third method may include a step of printing and curing a conductive paste that is metallized by a chemical reaction at an arbitrary position where the first capacitor electrode is formed on the dielectric thin film. Alternatively, the first capacitor electrode may be formed by printing a conductive paste on a portion including a portion to be the first capacitor electrode and etching an unnecessary portion. As the conductive paste that is metallized by a chemical reaction, the above-mentioned conductive paste that can be used for a substrate for a multilayer wiring board with a built-in capacitor can be used. In particular, the average particle diameter of metal particles is 0.1 to 10 nm. Is preferred. By using a conductive paste that is metallized by a chemical reaction, the first capacitor electrode can be formed without using a plating process with a large number of processing steps, and the number of manufacturing days of the multilayer wiring board with a built-in capacitor can be reduced. it can.
(Formation of capacitor dielectric)
A capacitor derivative is formed by etching away the dielectric thin film of the capacitor built-in multilayer wiring board or the substrate, leaving a portion to be a capacitor dielectric.
Examples of the etching removal method include an ion beam etching method, an RIE (Reactive Ion Etching) method, and a wet etching method.
The ion beam etching method is a technique in which ions of an inert gas such as argon are accelerated by an electric field and then irradiated onto a substrate to remove a dielectric thin film.
The RIE method is a technique for generating a reactive gas plasma such as a chlorofluorocarbon gas under a strong electric field under reduced pressure, thereby removing the dielectric thin film.
The wet etching method is a technique for removing a dielectric thin film using an etching solution (etchant) capable of dissolving a dielectric such as an etching solution (etchant). As the etchant, a known one can be used, and examples thereof include a solution containing hydrofluoric acid, an aqueous solution containing ammonia and hydrogen peroxide, and an aqueous solution containing EDTA, ammonia and hydrogen peroxide. However, hydrofluoric acid is dangerous because of its high reactivity. An aqueous solution containing ammonia and hydrogen peroxide and an aqueous solution containing EDTA, ammonia and hydrogen peroxide are alkaline. Therefore, when patterning is performed by etching, it is necessary to use an alkali-resistant resist, that is, a rubber-based resist as the etching resist. In such resists, special chemicals and solvents are used for the developer and the stripping solution, so it is necessary to provide dedicated equipment. Therefore, the dielectric thin film may be etched by a method using an etchant according to the following two methods.
The two methods are a method using an etchant containing a chelating agent and hydrogen peroxide (first method), and at least one acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid and acetic acid and hydrogen peroxide. This is a method (second method) using an etchant containing Etching of the dielectric thin film performed in the first and second methods is wet etching, which is more productive than etching by a dry process. Moreover, since it can respond also to a large substrate, it is economical. Furthermore, since an alkali development type etching resist used in a normal photolithography process is used, it is not necessary to provide a dedicated facility, and a special chemical solution is not used, so that it is inexpensive and can perform thin film patterning efficiently. Is possible.
In the first method, an etchant containing a chelating agent and hydrogen peroxide is used as the etchant for the dielectric thin film, and the etchant is usually an aqueous solution. Since the dielectric thin film can be etched with an aqueous solution containing a chelating agent and hydrogen peroxide without using hydrofluoric acid, the chemical solution is easy to handle and the danger can be reduced. In addition, chelating agents and hydrogen peroxide are used in a normal printed wiring board manufacturing process, so that a large new load is not applied when used. The chelating agent concentration of the etchant is preferably 0.001 to 0.5 mol / l. Etching of the dielectric thin film requires a minimum of 0.001 mol / l, and can be arbitrarily set within a range up to a limit concentration of 0.5 mol / l. More desirably, an etching rate with good stability can be obtained by setting the amount to 0.1 to 0.3 mol / l. The hydrogen peroxide concentration is desirably 1 to 50 wt%. The etching rate can be adjusted by arbitrarily setting the hydrogen peroxide concentration within this range. In order to obtain an etching rate that is at least acceptable in use, hydrogen peroxide of at least 1 wt% is necessary, and it can be arbitrarily set within a range of up to 50 wt% with no problem in handling of chemicals. More desirably, by setting the content to 20 to 30 wt%, an appropriate etching rate can be obtained, and the liquid concentration can be easily managed. The etchant controlled to the above-described concentration is an acidic etchant, and the pH of the etchant is preferably controlled in the range of 2-7. In addition, although it is possible to adjust pH to the alkali side with a buffer solution, in that case, it is necessary to use an alkali-resistant etching resist, and a resist having alkali resistance generally requires dedicated equipment or a chemical solution. Therefore, it is desirable to manage the pH of the etchant in the range of 2 to 7 for the above reason.
The chelating agent used in the present invention is at least one selected from the group consisting of ethylenediaminetetraacetic acid (EDTA), hydroxyethyliminodiacetic acid (HIDA), iminodiacetic acid (IDA), dihydroxyethylglycine (DHEG), and alkali salts thereof. A chelating agent is preferred. Since the chelating agent is water-soluble, NH ₄ There is no need to use an alkaline solution such as OH or NaOH. This is effective for obtaining the acidic etchant described above, and contributes to the reduction of the chemical cost in addition to the easy selection of the resist.
The etchant for the dielectric thin film used in the second method contains an acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid and acetic acid and hydrogen peroxide, and is usually an aqueous solution. The acid is also used for normal wiring board manufacture, and is easier to handle than hydrofluoric acid. These aqueous solutions of acid and hydrogen peroxide can easily etch the dielectric thin film.
The concentration of the acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid and acetic acid in the etchant is preferably 1 to 30 wt%. The higher the concentration, the higher the etching rate, but the handling of the chemical becomes difficult. Accordingly, the upper limit of the concentration is preferably 30 wt%. Further, in order to obtain an etching rate that is minimally allowable in use, it is preferably 1 wt% or more. More preferably, by setting the content to 5 to 30 wt%, it is possible to obtain excellent etching properties and an appropriate etching rate. In addition, the chemical solution can be easily handled and an excellent etching rate can be obtained.
In the first and second methods, it is only necessary that an etching resist is formed on a metal layer which becomes a capacitor electrode formed at least at a predetermined position on the substrate surface. As the etching resist, a commercially available photosensitive dry film or an alkali developing resist ink can be used, but it is preferable to use a photosensitive dry film. The photosensitive dry film is the most general-purpose resist material in the printed wiring board manufacturing process. Not only is it possible to form a low-cost resist, but the workability is also excellent. The etching resist to be used is not particularly limited. For example, FX140 (DuPont MRC Dry Film Co., Ltd., trade name), NIT240 (Nichigo Morton Co., Ltd., trade name), H-9040 (Hitachi Chemical Co., Ltd.) Company name, product name) can be used. In addition, as a commercially available alkali developing resist ink, PER-20 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) and the like can be given. An etching resist is formed on the metal layer to be the capacitor electrode on the substrate surface and the dielectric thin film, the circuit pattern is baked, and further development is performed. In addition, a sodium carbonate aqueous solution can be used for development, and a sodium hydroxide aqueous solution can be used for peeling off the etching resist, which is also characterized by a low environmental load. In addition, an ink-like etching resist may be used for screen printing or the like, and the etching resist may be formed only on the metal layer that becomes the capacitor electrode.
When using a photosensitive dry film, the film thickness is desirably 1 to 3 times the thickness of the metal layer to be the capacitor electrode. In the case where the thickness of the metal layer to be protected is smaller than the thickness of the metal layer to be protected, the embedding property of the step between the metal layer and the surface of the layer to be etched is poor, and voids are likely to occur, resulting in poor etching. On the other hand, if it exceeds 3 times, the etching property is lowered, so that it is difficult to make the pattern fine. More preferably, it is 2 to 3 times the metal layer. It is because it has favorable followable | trackability with respect to a level | step difference and is excellent also in etching property by setting it as 2 to 3 times.
In the first and second methods, the dielectric thin film is etched at 20 to 45 [deg.] C. to produce a multilayer wiring board with a built-in capacitor. If the temperature is lower than 20 ° C., the etching rate is remarkably lowered, so that a long time is required for etching, which is uneconomical. On the other hand, if it exceeds 45 ° C., the adhesiveness of the resist is lowered, and etching defects are likely to occur. Therefore, the etching temperature is preferably 20 to 45 ° C. More preferably, by setting the temperature to 20 to 30 ° C., both good etching rate and resist adhesion can be achieved, and workability and yield can be improved.
It is preferable to provide a metal layer as the oxidation protective film or the self-oxidized film between the dielectric thin film and the first capacitor electrode. The thing similar to what was used for the material for multilayer wiring boards with a built-in capacitor | condenser can be used.
(Formation of second capacitor electrode)
A capacitor electrode (second capacitor electrode) is obtained by etching a metal foil or a metal layer contained in the capacitor built-in multilayer wiring board material or the capacitor built-in multilayer wiring board substrate, leaving an arbitrary portion. Can do. Etching can be performed by a known method.
The formation of the second capacitor electrode may be performed simultaneously with the formation of the first capacitor electrode or after the formation of the first capacitor electrode. In particular, when the second capacitor electrode is formed simultaneously with the formation of the first capacitor electrode, the manufacturing process steps are simplified, the number of manufacturing days is reduced, and the economy is excellent. In this case, after forming a capacitor dielectric and forming a metal layer to be a first capacitor electrode thereon, the first and second capacitor electrodes are etched simultaneously.
When the second capacitor electrode is common to the ground layer or the power supply layer of the multilayer wiring board, the second capacitor electrode is preferably used as the ground layer or the power supply layer. In general, the pattern of the ground layer or the power supply layer has a larger area than the wiring pattern. The area of the capacitor electrode produced in the present invention was formed by patterning the metal layer that covered the substrate surface when forming the dielectric thin film rather than the first capacitor electrode formed on the dielectric thin film. Since the second capacitor electrode is larger, the second capacitor electrode is preferably used for the ground layer or the power supply layer.
(Connection between second capacitor electrode and conductor of substrate having conductor circuit)
In the case of manufacturing a capacitor inner layer multilayer wiring board using the capacitor built-in multilayer wiring board material according to an embodiment of the present invention, a conductor is provided on the copper foil surface of the capacitor built-in multilayer wiring board material via an insulating layer. A substrate having a circuit may be stacked. In this capacitor inner layer multilayer wiring board, the connection between the second capacitor electrode and the conductor circuit may be made by removing the insulating layer and connecting by electrolytic plating (first method); You may connect by using the insulating layer with which the hole was filled (2nd method).
In the first method, after forming the first and second capacitor electrodes and the capacitor dielectric, the insulating layer exposed by the laser irradiation is removed to form a hole, and the inner conductive circuit is exposed. Forming a metal layer having a thickness of 0.1 to 5 μm on the surface of the substrate; forming a plating resist excluding an arbitrary portion including a hole; and forming 10 to a substrate surface other than the portion where the plating resist is formed. Forming a 50 μm metal layer and electrically connecting the circuit patterns between the layers; etching and removing the 0.1 to 5 μm metal layer formed on the substrate surface; at least a capacitor dielectric and a hole made into a conductor And a step of etching away leaving any part including. About a metal layer, a plating resist, etc., the thing similar to what was used for the 1st capacitor electrode can be used.
The second method is a method of forming a through hole with an insulating material such as a prepreg serving as an insulating layer by a drill or a laser, and a conductive paste that is metallized by a chemical reaction using a screen printing or the like. And a step of filling in. As the conductive paste, the same conductive paste as that used for the capacitor built-in multilayer array substrate can be used.
In the case of manufacturing a multilayer wiring board with a built-in capacitor using a substrate for a multilayer wiring board with a built-in capacitor, which is an embodiment of the present invention, since a via hole for connecting conductor layers is provided inside the board, conduction is particularly good. You don't have to do it.
When manufacturing a capacitor inner layer multilayer wiring board using a capacitor built-in multilayer wiring board material according to an embodiment of the present invention, an insulating layer is interposed on the copper foil surface of the capacitor built-in multilayer wiring board material. Metal foil B can be laminated. In this capacitor inner layer multilayer wiring board, the insulating layer and the metal foil B may be removed to form a hole, and then connected by forming a metal layer in the hole (first method); You may connect by using the insulating layer with which the through-hole was filled (2nd method).
In the first method, the insulating layer can be removed by laser, and the metal foil B can be removed by laser or etching. If the metal foil B and the insulating layer are simultaneously removed using a laser to form a hole, the manufacturing process steps are simplified, the number of manufacturing days is reduced, and the economy is excellent. The metal foil B that enables such a manufacturing method is preferably subjected to a treatment that easily absorbs the energy of the laser beam. In the case of copper foil, surface roughening treatment such as copper oxide treatment, microetching treatment, and roughening plating treatment is effective as such treatment, and the surface roughness is preferably 0.1 to 3 μm. When the thickness is less than 0.1 μm, the laser beam is not sufficiently absorbed and the workability is poor, and when it exceeds 3 μm, the processing accuracy is poor. Moreover, as thickness of copper foil, 1-18 micrometers is preferable. A copper foil of less than 1 μm is inferior in handleability, and a copper foil in excess of 18 μm is inferior in workability. In addition to the roughening treatment of the copper surface, a metal layer that easily absorbs laser light such as nickel may be provided on the surface. Examples of a method for forming such a metal layer or a metal layer on the substrate surface include a sputtering method, an electroless plating method, an electrolytic plating method, and a combination thereof.
Next, the metal foil B and the metal foil A (capacitor electrode) can be electrically connected by forming a metal layer in the formed hole. This electrical connection can be performed, for example, by electrolytic plating or by forming a conductive paste. The first method includes a step of forming a metal layer having a thickness of 0.1 to 5 μm on both sides of the substrate including the inside of the hole, a step of forming a metal plating resist on the surface of the substrate leaving an arbitrary portion including the hole, and a metal Including a step of forming a conductor pattern in a portion including a hole by plating, a step of removing an unnecessary metal plating resist, and a step of removing a metal layer of 0.1 to 5 μm formed in the unnecessary portion. You may go out. About a metal layer, a plating resist, etc., the thing similar to what was used for the 1st capacitor electrode can be used.
In addition, before forming the metal layer 2 on the dielectric thin film of the capacitor-embedded multilayer wiring board material, forming the metal layer on both surfaces of the substrate surface including the hole, the formation of the metal layer in the hole and the first capacitor electrode Since the formation of the metal layer is performed simultaneously, it is preferable. The metal layer is formed by forming a metal layer having a thickness of 0.1 to 5 μm on both surfaces of the substrate including the inside of the hole, forming a metal plating resist on the surface of the substrate leaving an arbitrary portion including the hole, Even if it has a process of forming a conductor pattern in a portion including a hole by plating, a process of removing a metal plating resist, and a process of etching away a 0.1 to 5 μm metal layer exposed on the substrate surface Good. Further, the electrical connection between the metal foil B and the metal foil A (capacitor electrode) may be performed by the conductive paste described above.
In the second method, a step of forming a through hole by drilling or laser drilling in an insulating material such as a prepreg serving as an insulating layer, a conductive paste that is metallized by a chemical reaction, screen printing, etc. And a step of filling the through-holes. The conductive paste is the same as the conductive paste used for the multilayer capacitor built-in substrate.
In the present invention, a multilayer wiring board with a built-in capacitor having three or more layers can be obtained by forming one or more circuit layers on both sides or one side of the substrate via an insulating layer as necessary.
In one embodiment of the present invention, in the multilayer wiring board with a built-in capacitor, the pattern of the conductor layer forming the first capacitor electrode forms the capacitor electrode, and the projection surface of the dielectric thin film projects the first capacitor electrode. The conductor layer including the surface and forming the second capacitor electrode may have the second capacitor electrode and at least one pattern electrically insulated from the electrode.
In one embodiment of the present invention, in the capacitor built-in multilayer wiring board produced by these manufacturing methods, the metal pattern for forming the second capacitor electrode is formed below the metal layer pattern for forming the first capacitor electrode. Exists. For this reason, when a wiring pattern is formed on the metal layer forming the first capacitor electrode, a parasitic capacitance is generated between the metal layer forming the second capacitor electrode and the transmission characteristics of the electric signal are deteriorated. Is not preferable. Therefore, it is preferable to install the wiring pattern on the metal layer of the second capacitor electrode.
In one embodiment of the present invention, the multilayer wiring board with a built-in capacitor produced by these manufacturing methods has 1) a first capacitor electrode included in the projection surface of the dielectric thin film that forms the dielectric of the capacitor. 2) A conductor layer that forms the first capacitor electrode may be electrically connected to the second capacitor electrode at all ends of the dielectric thin film. According to this, it is a multilayer wiring board with a built-in capacitor that has simplified manufacturing process steps, reduced manufacturing days, and is economical.
In one embodiment of the present invention, the built-in capacitor multilayer wiring board produced by these manufacturing methods may be mounted with a semiconductor chip. Since the capacitor is built in the substrate, the number of mounted components can be reduced, and a small semiconductor device can be provided.
The manufacturing method of the multilayer wiring board with a built-in capacitor will be specifically mentioned.
The next manufacturing method is a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of a metal foil. This is a specific example of the manufacturing method.
(A-1) 1) A step of laminating a substrate having a conductor circuit via a prepreg on the surface of the metal foil of the capacitor built-in multilayer wiring board material, and 2) a metal layer of 10 to 50 μm on the surface of the dielectric thin film. Forming a desired first capacitor electrode by etching away leaving any portion of the metal layer, and 4) optional including at least the first capacitor electrode of the dielectric thin film. Forming a desired capacitor dielectric by etching away leaving a portion; and 5) removing the dielectric thin film by etching away leaving at least any portion of the metal foil containing the capacitor dielectric as desired. Forming a conductor pattern including the second capacitor electrode.
(A-2) 1) A step of laminating a substrate having a conductor circuit through a prepreg on the surface of a metal foil of a capacitor-embedded multilayer wiring board material; A step of forming a layer, 3) a step of forming a metal plating resist leaving any portion including the first capacitor electrode, and 4) a step of forming a first capacitor electrode of 10 to 50 μm by metal plating, 5) a step of removing the metal plating resist, 6) a step of etching away a 0.1 to 5 μm metal layer formed on the surface of the dielectric thin film, and 7) at least a first capacitor electrode of the dielectric thin film. A step of forming a desired capacitor dielectric by etching away leaving any portion including, and 8) leaving at least any portion including the capacitor dielectric of the metal foil that appears after removing the dielectric thin film. It is removed by etching with a step of forming a conductive pattern including a desired second capacitor electrode.
(A-3) 1) A step of laminating a substrate having a conductor circuit via a prepreg on the surface of a metal foil of a capacitor-embedded multilayer wiring board material, and 2) a chemical treatment on an arbitrary portion of the surface of the dielectric thin film. Forming a desired first capacitor electrode by forming a metal layer having a thickness of 10 to 50 μm using a conductive paste metallized by reaction; and 3) an option including at least a first capacitor electrode of a dielectric thin film A step of forming a desired capacitor dielectric by removing the portion of the metal foil, and 4) removing the dielectric thin film by etching and removing any portion of the metal foil including at least the capacitor dielectric. Forming a conductor pattern including a desired second capacitor electrode.
(A-4) 1) A step of laminating on a surface of a metal foil of a material for a multilayer wiring board with a built-in capacitor on a substrate having a conductor circuit via a prepreg, and 2) etching away leaving an arbitrary portion of the dielectric thin film. Forming a desired capacitor dielectric, 3) forming a 10-50 μm metal layer on the substrate surface on which the capacitor dielectric is formed, and 4) etching away leaving any portion of the metal layer. Forming a desired first capacitor electrode, a second capacitor electrode, and an arbitrary conductor pattern electrically insulated from the capacitor electrode.
(A-5) 1) A step of laminating a substrate having a conductor circuit through a prepreg on the surface of the metal foil of the capacitor wiring multilayer wiring board material, and 2) a metal layer of 10 to 50 μm on the surface of the dielectric thin film. Forming a desired first capacitor electrode by etching away leaving any portion of the metal layer, and 4) optional including at least the first capacitor electrode of the dielectric thin film. 5) removing a dielectric thin film to form a desired capacitor dielectric, and 5) removing any portion of the metal foil that appears by removing the dielectric thin film to expose the cured insulating layer of the prepreg. And 6) removing the insulating layer exposed by the laser irradiation to form a hole to expose the inner conductive circuit, and 7) providing a 0.1 to 5 μm metal layer on the substrate surface. Craft to form 8) A step of forming a plating resist except for an arbitrary portion including a hole, and 9) A 10-50 μm metal layer is formed on the substrate surface other than the portion where the plating resist is formed, and an inter-layer circuit pattern is formed. 10) a step of electrically connecting, 10) a step of etching away a 0.1 to 5 μm metal layer formed on the substrate surface, and 11) leaving any part including at least a capacitor dielectric and a hole made into a conductor. Etching to remove and forming a conductor pattern including a desired second capacitor electrode.
(A-6) 1) A step of laminating a substrate having a conductor circuit via a prepreg on the surface of a metal foil of a capacitor-embedded multilayer wiring board material; A step of forming a layer, 3) a step of forming a metal plating resist leaving any portion including the first capacitor electrode, and 4) a step of forming a first capacitor electrode of 10 to 50 μm by metal plating, 5) a step of removing the metal plating resist, 6) a step of etching away a 0.1 to 5 μm metal layer formed on the surface of the dielectric thin film, and 7) at least a first capacitor electrode of the dielectric thin film. A step of forming a desired capacitor dielectric by etching away leaving an arbitrary portion including, and 8) a prepreg cured by removing any portion of the metal foil that has appeared by removing the dielectric thin film. A step of exposing the insulating layer, 9) a step of removing the insulating layer exposed by laser irradiation to form a hole, and exposing a conductor circuit as an inner layer, and 10) 0.1 to 0.1% of the substrate surface. A step of forming a metal layer of 5 μm, 11) a step of forming a plating resist except for any part including a hole, and 12) a metal layer of 10 to 50 μm on the substrate surface other than the part where the plating resist is formed Electrically connecting the circuit patterns between the layers, 13) etching away the 0.1-5 μm metal layer formed on the substrate surface, and 14) forming at least a capacitor dielectric and a hole made into a conductor. A step of forming a conductor pattern including a desired second capacitor electrode by etching away the remaining arbitrary portion.
(A-7) 1) A step of laminating a substrate having a conductor circuit via a prepreg on the surface of a metal foil of a capacitor-embedded multilayer wiring board material, and 2) a chemical treatment on any part of the surface of the dielectric thin film. Forming a desired first capacitor electrode by forming a metal layer having a thickness of 10 to 50 μm using a conductive paste metallized by reaction; and 3) an option including at least a first capacitor electrode of a dielectric thin film And removing the dielectric thin film to form a desired capacitor dielectric, and 4) exposing the cured insulating layer of the prepreg by etching away any portion of the metal foil that appears by removing the dielectric thin film. 5) removing the insulating layer exposed by laser irradiation to form a hole and exposing the inner conductive circuit, and 6) a metal layer of 0.1 to 5 μm on the substrate surface Form 7) a step of forming a plating resist except for an arbitrary portion including a hole, and 8) a circuit pattern between layers by forming a 10-50 μm metal layer on the substrate surface other than the portion where the plating resist is formed 9) a step of etching away a 0.1-5 μm metal layer formed on the substrate surface, and 10) leaving at least an arbitrary portion including a capacitor dielectric and a hole made into a conductor. Etching to remove and forming a conductor pattern including a desired second capacitor electrode.
(A-8) 1) A step of laminating on a substrate having a conductor circuit via a prepreg on the surface of the metal foil of the capacitor-embedded multilayer wiring board material, and 2) etching away leaving any part of the dielectric thin film. A step of forming a desired capacitor dielectric, 3) a step of removing a dielectric thin film and exposing an insulating layer of a cured prepreg by etching and removing an arbitrary portion of a metal foil, and 4) by laser irradiation. Removing the exposed insulating layer to form a hole to expose the inner conductive circuit; and 5) forming a 10 to 50 μm metal layer on the surface of the substrate on which the capacitor dielectric is formed and in the hole. And 6) forming a conductor pattern including a desired second capacitor electrode by etching away leaving at least an arbitrary portion including a capacitor dielectric and a hole made into a conductor.
In the next manufacturing method, the relative permittivity is 10 to 2000 on the surface of the substrate having via holes connecting the conductor layers inside the substrate and having a smooth metal layer on the surface, and the film thickness is 0. It is a specific example of a method for manufacturing a multilayer wiring board with a built-in capacitor using a substrate for a multilayer wiring board with a built-in capacitor as an inner layer board, wherein a dielectric thin film of 05 to 2 μm is formed.
(B-1) 1) Step of forming a metal layer of 10 to 50 μm on the surface of the dielectric thin film, and 2) Forming a desired first capacitor electrode by etching away leaving any portion of the metal layer And 3) a process of forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film, and 4) removing the dielectric thin film. A step of forming a conductive pattern including a desired second capacitor electrode by etching and removing an arbitrary portion including at least the capacitor dielectric of the metal layer;
(B-2) 1) a step of forming a metal layer of 0.1 to 5 μm on the surface of the dielectric thin film, and 2) a step of forming a metal plating resist leaving any portion including the first capacitor electrode, 3) a step of forming a first capacitor electrode of 10 to 50 μm by metal plating, 4) a step of removing the metal plating resist, and 5) a metal layer of 0.1 to 5 μm formed on the surface of the dielectric thin film 6) a step of etching and removing an arbitrary portion including at least the first capacitor electrode of the dielectric thin film to form a desired capacitor dielectric; and 7) removing the dielectric thin film. The conductive layer including a desired second capacitor electrode is formed by etching away leaving at least an arbitrary portion including the capacitor dielectric of the metal layer appearing.
(B-3) 1) A desired first capacitor electrode is formed by forming a metal layer of 10 to 50 μm using a conductive paste that is metallized by a chemical reaction on an arbitrary portion of the surface of the dielectric thin film. A step of forming, 2) a step of etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film to form a desired capacitor dielectric, and 3) removing the dielectric thin film and appearing A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step of forming a conductive pattern including a desired second capacitor electrode by etching and removing an arbitrary portion including at least a capacitor dielectric of the metal layer .
(B-4) 1) A step of etching away leaving an arbitrary portion of the dielectric thin film to form a desired capacitor dielectric, and 2) A metal layer of 10 to 50 μm is formed on the substrate surface on which the capacitor dielectric is formed. 3) forming a desired first capacitor electrode, a second capacitor electrode, and an arbitrary conductor pattern electrically insulated from the capacitor electrode by etching away leaving any portion of the metal layer; The process of carrying out.
The following manufacturing method is for a multilayer wiring board material with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil. The present invention relates to a specific example of a method for manufacturing a multilayer wiring board with a built-in capacitor using a substrate provided on at least one surface of an insulating material so as to be in contact with the capacitor.
(C-1) 1) a step of forming a metal layer serving as a capacitor electrode at a predetermined position on the dielectric thin film on the substrate surface, and 2) a step of forming an etching resist on at least the metal layer on the substrate surface; 3) a step of wet etching the dielectric thin film with an etchant containing a chelating agent and hydrogen peroxide; and 4) a step of removing the etching resist after the wet etching.
(C-2) 1) a step of forming a metal layer to be a capacitor electrode at a predetermined position on the dielectric thin film on the substrate surface, 2) a step of forming an etching resist on at least the metal layer on the substrate surface, 3) a step of wet etching the dielectric thin film with an etchant containing at least one acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid and acetic acid and hydrogen peroxide; and 4) removing the etching resist after the wet etching. The process of carrying out.
The next manufacturing method is a multilayer wiring with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of a metal foil A It is a specific example of the manufacturing method of a board.
(D-1) 1) The process of laminating metal foil B on the surface of metal foil A of the capacitor built-in multilayer wiring board material with an insulating material as a substrate, and 2) etching and removing an arbitrary portion of metal foil B A step of exposing the insulating layer formed of the insulating material, 3) a step of removing the exposed insulating layer by laser irradiation to form a hole, and exposing the metal foil A, and 4) in the hole A step of forming metal layers on both surfaces of the substrate surface including 5) a step of forming a first capacitor electrode pattern of any shape from the metal layer on the dielectric thin film of the multilayer wiring board material with a built-in capacitor by etching; 6) a step of forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern from the exposed dielectric thin film by etching; and 7) a capacitor dielectric from the metal foil A that appears by removing the dielectric thin film. Body pattern A step of forming a second capacitor electrode of any shape including the above by etching.
(D-2) 1) The process of laminating metal foil B on the surface of metal foil A of the capacitor built-in multilayer wiring board material via an insulating material to form a substrate, and 2) laser irradiation to an arbitrary portion of metal foil B Removing the metal foil B and the insulating layer formed from the insulating material at the same time to form a hole to expose the metal foil A, and 3) providing a metal layer on both surfaces of the substrate surface including the inside of the hole. A step of forming, 4) a step of forming a first capacitor electrode pattern of an arbitrary shape from a metal layer on the dielectric thin film of the capacitor wiring multilayer wiring board material, and 5) from the exposed dielectric thin film A step of forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern by etching; and 6) a second of an arbitrary shape including the capacitor dielectric pattern from the metal foil A which is formed by removing the dielectric thin film. Capacitor Forming an electrode by etching.
(D-3) 1) On the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor, through holes are provided at arbitrary locations, and the through holes are filled with a conductive paste containing a thermosetting resin and a metal filler. A step of laminating the metal foil B through the insulating material used to form a substrate, 2) a step of forming a metal layer on at least the dielectric thin film side of the substrate surface, and 3) dielectric of the multilayer wiring board material with a built-in capacitor. Forming a first capacitor electrode pattern of any shape from a metal layer on the body thin film by etching; and 4) forming a capacitor dielectric of any shape including the first capacitor electrode pattern from the exposed dielectric thin film. A step of forming by etching, and 5) a step of forming a second capacitor electrode of any shape including the capacitor dielectric pattern by etching on the metal foil A that appears after removing the dielectric thin film. .
(D-4) 1) Filled with a conductive paste in which through holes are provided at arbitrary positions on the surface of the metal foil A of the capacitor wiring multilayer wiring board material and the through holes are metallized by a chemical reaction. A step of laminating the metal foil B through the insulating material used to form a substrate, 2) a step of forming a metal layer on at least the dielectric thin film side of the substrate surface, and 3) dielectric of the multilayer wiring board material with a built-in capacitor. Forming a first capacitor electrode pattern of any shape from a metal layer on the body thin film by etching; and 4) forming a capacitor dielectric of any shape including the first capacitor electrode pattern from the exposed dielectric thin film. A step of forming by etching, and 5) a step of forming a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A that appears after removing the dielectric thin film. .
(D-5) 1) A step of laminating metal foil B on the surface of metal foil A of the capacitor built-in multilayer wiring board material through an insulating material to form a substrate, and 2) etching and removing an arbitrary portion of metal foil B A step of exposing the insulating layer formed of the insulating material, 3) a step of removing the insulating layer exposed by laser irradiation to form a hole, and exposing the metal foil A, and 4) the inside of the hole. Forming a metal layer having a thickness of 0.1 to 5 μm on both sides of the substrate to be included, and 5) forming a metal plating resist on the surface of the substrate while leaving any portion including the first capacitor electrode and the hole. And 6) a step of forming a conductor pattern on the portion including the first capacitor electrode and the portion including the hole by metal plating, 7) a step of removing the metal plating resist, and 8) exposure on the substrate surface. Etched 0.1 to 5 μm metal layer And 9) a step of etching a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern from the exposed dielectric thin film by etching; and 10) a metal appearing by removing the dielectric thin film. A step of forming a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern from the foil A by etching; and 11) a circuit is formed by etching the exposed metal foil B.
(D-6) 1) Step of laminating metal foil B on the surface of metal foil A of the capacitor built-in multilayer wiring board material through an insulating material to form a substrate, and 2) laser irradiation to any part of metal foil B Removing the metal foil B and the insulating layer formed from the insulating material at the same time to form a hole to expose the metal foil A, and 3) 0.1 to both sides of the substrate including the inside of the hole. A step of forming a metal layer of 5 μm, 4) a step of forming a metal plating resist on the surface of the substrate leaving an arbitrary portion including a portion to be the first capacitor electrode and a hole, and 5) the above by metal plating A step of forming a conductor pattern in a portion including the first capacitor electrode and a portion including the hole, 6) a step of removing the metal plating resist, and 7) a 0.1 to 5 μm metal exposed on the substrate surface Etching away the layer; 8) exposure Forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern by etching from the dielectric thin film, and 9) removing the dielectric thin film from the metal foil A that appears and removing the capacitor dielectric pattern. And a step of forming a circuit by etching the exposed metal foil B.
(D-7) 1) On the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor, through holes are provided at arbitrary locations, and the through holes are filled with a conductive paste containing a thermosetting resin and a metal filler. A step of laminating a metal foil B through a conductive insulating material to form a substrate, 2) a step of forming a metal layer of 0.1 to 5 μm on the surface of at least the dielectric thin film side of the substrate, and 3) a first A step of forming a metal plating resist on the substrate surface leaving an arbitrary portion including a portion to be a capacitor electrode, and 4) a step of forming a conductor pattern on a portion including a portion to be a first capacitor electrode by metal plating, 5) a step of removing the metal plating resist, 6) a step of etching away the 0.1 to 5 μm metal layer exposed on the substrate surface, and 7) a first capacitor electrode from the exposed dielectric thin film. pattern And 8) a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A that has appeared after removing the dielectric thin film. And forming a circuit by etching the exposed metal foil B.
(D-8) 1) Filled with a conductive paste in which through holes are provided at arbitrary locations on the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor and the through holes are metallized by a chemical reaction. A step of laminating a metal foil B through a conductive insulating material to form a substrate, 2) a step of forming a metal layer of 0.1 to 5 μm on the surface of at least the dielectric thin film side of the substrate, and 3) a first A step of forming a metal plating resist on the substrate surface leaving an arbitrary portion including a portion to be a capacitor electrode, and 4) a step of forming a conductor pattern on a portion including a portion to be a first capacitor electrode by metal plating, 5) a step of removing the metal plating resist, 6) a step of etching away the 0.1 to 5 μm metal layer exposed on the substrate surface, and 7) a first capacitor electrode from the exposed dielectric thin film. Pattern And 8) a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A that appears after removing the dielectric thin film. And forming a circuit by etching the exposed metal foil B.
(D-9) 1) On the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor, through holes are provided at arbitrary locations, and the through holes are filled with a conductive paste containing a thermosetting resin and a metal filler. A step of laminating a metal foil B through an insulating material to be a substrate, and 2) forming a metal layer using a conductive paste that is metallized by chemical reaction on an arbitrary portion of the surface of the dielectric thin film Forming a desired first capacitor electrode; and 3) forming a desired capacitor dielectric by etching away any portion of the dielectric thin film that includes at least the first capacitor electrode. 4) A second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern is formed by etching from the metal foil A that appears after removing the dielectric thin film, and the exposed metal foil B is etched to form a circuit. Forming.
(D-10) 1) Filled with a conductive paste in which through holes are provided in arbitrary positions on the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor, and the through holes are metallized by a chemical reaction. A step of laminating a metal foil B through an insulating material to be a substrate, and 2) forming a metal layer using a conductive paste that is metallized by chemical reaction on an arbitrary portion of the surface of the dielectric thin film Forming a desired first capacitor electrode; and 3) forming a desired capacitor dielectric by etching away any portion of the dielectric thin film that includes at least the first capacitor electrode. 4) A second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern is formed by etching from the metal foil A that appears after removing the dielectric thin film, and the exposed metal foil B is etched to form a circuit. Forming.
(D-11) 1) A step of laminating metal foil B on the surface of metal foil A of the capacitor built-in multilayer wiring board material with an insulating material as a substrate, and 2) leaving an arbitrary portion of the dielectric thin film Etching to remove the desired capacitor dielectric, 3) etching away any portion of the metal foil B to expose the insulating layer formed of the insulating material, and 4) laser irradiation. Removing the insulating layer exposed by forming a hole to expose the metal foil A, 5) forming a metal layer on both surfaces of the substrate surface including the inside of the hole, and 6) the metal layer and the metal foil. A desired first capacitor electrode and a second capacitor electrode are formed by etching away leaving an arbitrary portion of A.
(D-12) 1) Step of laminating metal foil B on the surface of metal foil A of the capacitor built-in multilayer wiring board material via an insulating material to form a substrate, and 2) leaving any part of the dielectric thin film Etching to remove the desired capacitor dielectric, and 3) irradiating the metal foil B with any laser to simultaneously remove the metal foil B and the insulating layer formed of the insulating material. Forming a hole to expose the metal foil A, 4) forming a metal layer on both sides of the substrate surface including the inside of the hole, and 5) etching away leaving the metal layer and the metal foil A at any part. And forming a desired first capacitor electrode and second capacitor electrode.
(D-13) 1) On the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor, through holes are provided at arbitrary locations, and the through holes are filled with a conductive paste containing a thermosetting resin and a metal filler. A step of forming a substrate by laminating metal foil B through the insulating material, 2) a step of etching away leaving any portion of the dielectric thin film to form a desired capacitor dielectric, and 3) a substrate Forming a metal layer on at least the surface having the capacitor dielectric, and 4) removing the metal layer and any part of the metal foil A by etching to leave a desired first capacitor electrode and second capacitor. Forming an electrode.
(D-14) 1) Filling with a conductive paste in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor and the through hole is metallized by a chemical reaction A step of forming a substrate by laminating metal foil B through the insulating material, 2) a step of etching away leaving any portion of the dielectric thin film to form a desired capacitor dielectric, and 3) a substrate Forming a metal layer on at least the surface having the capacitor dielectric, and 4) removing the metal layer and any part of the metal foil A by etching to leave a desired first capacitor electrode and second capacitor. Forming an electrode.
Hereinafter, embodiments of the present invention will be described more specifically with reference to the drawings.
(Example A)
Material for multilayer wiring boards with built-in capacitors A-1
Titanium tetraisopropoxide, zircon tetratertiary butoxide, dipivaloylmethane lead complex on the surface of rolled copper foil M-BNH-18 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 35 μm, which is copper foil 102, A PZT (lead zirconate titanate) thin film 101 having a thickness of 0.5 μm was formed by microwave plasma CVD using nitrogen dioxide under a substrate temperature condition of 350 ° C. (FIG. 1A).
Capacitor built-in multilayer wiring board material A-2
A ruthenium thin film 103 having a thickness of 0.2 μm was formed on the surface of a rolled copper foil M-BNH-18 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 35 μm, which is the copper foil 102, by a DC sputtering method. Furthermore, the thickness of the substrate is 0.5 μm under the condition of a substrate temperature of 350 ° C. by microwave plasma CVD using titanium tetraisopropoxide, zircon tetratertiary butoxide, dipivaloylmethane lead complex and nitrogen dioxide. The PZT (lead zirconate titanate) thin film 101 was formed (FIG. 1B).
Material for multilayer wiring boards with built-in capacitors A-3
A ruthenium thin film 103 having a thickness of 0.2 μm was formed on the surface of a rolled copper foil M-BNH-18 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 35 μm, which is the copper foil 102, by a DC sputtering method. Further, a ferroelectric thin film forming material PZT (Kanto Chemical Co., Ltd., trade name) was applied to the surface and prebaked at a temperature of 150 ° C. for 30 minutes. The coating and pre-baking were further repeated 5 times, followed by heat treatment at a temperature of 350 ° C. for 1 hour to form a PZT thin film 101 having a thickness of 0.5 μm (FIG. 1B).
Example A-1
The surface of the copper foil 102 of the multilayer wiring board material A-2 with a built-in capacitor was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment ( FIG. 2 (a)). Using a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) with a thickness of 0.2 mm as a base material, connecting holes 106 and circuit patterns made into conductors at desired locations The prepared double-sided substrate 104 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment, and then a glass having a thickness of 100 μm was formed on one surface thereof. Through an epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.), a copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd., trade name) with a thickness of 18 μm and a glass epoxy with a thickness of 100 μm on the other side. Through the prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name), the aforementioned multilayer wiring board material with a built-in capacitor is disposed, and the temperature is 1 0 ° C., pressure 1.5 MPa, and laminated and integrated with press conditions of heat pressing time 60 min (Figure 2 (b)). Here, reference numeral 105 denotes plated copper, and reference numeral 107 denotes an insulating resin substrate (cured prepreg). Further, a 0.05 μm chromium thin film 108 was formed on the surface of the PZT thin film by DC sputtering. Further, a 20 μm-thick metal layer 109 was formed on the surface by electrolytic copper plating (FIG. 2C). A desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer is etched away using an aqueous ferric chloride solution, and a chromium metal layer is etched away using an aqueous potassium ferricyanide solution. The capacitor electrode pattern was formed (FIG. 2D). Subsequently, a resist having a desired pattern is formed and CF ₄ The PZT thin film and the ruthenium thin film were removed by etching by RIE using gas (FIG. 2E). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary copper foil is removed by etching using an aqueous ferric chloride solution to form a φ0.1 mm window hole at a desired location. Using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation, laser drilling 110 was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a number of shots of 4 (FIG. 2F). After removing resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution, electroless copper plating was performed after catalyst application and adhesion promotion, to form a 0.5 μm copper thin film. A desired plating resist 111 was formed on the surface of the substrate, and copper electroplating was performed to form a metal layer that electrically connected the circuit conductor on the inner layer and the conductor layer on the surface of the substrate (FIG. 2G). After removing the plating resist, the 0.5 μm copper thin film on the substrate surface is removed by etching. Then, a desired etching resist is formed, and an unnecessary copper metal layer is removed by etching with a ferric chloride solution. A circuit pattern including the second capacitor electrode was formed to produce a circuit board (FIG. 2 (h)).
The circuit surface of this circuit board was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (1) 35 μm thick copper foil MT35S3 (trade name) manufactured by Mitsui Mining & Smelting Co., Ltd., with copper foil 35 μm carrier, (2) 100 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) ), (3) Circuit board, (4) Glass epoxy prepreg GEA-679F with filler of 100 μm thickness as insulating resin base material 112, (5) 3 μm thick copper foil MT35S3 with 35 μm carrier copper foil (Mitsui Metal Mining Co., Ltd.) (Product name, product name) in order, and laminated and integrated under press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. After peeling off the carrier copper foil and cutting unnecessary substrate edges, a desired etching resist is formed on the surface of this substrate, and unnecessary copper foil is removed by etching using a ferric chloride aqueous solution, to a desired location. A window hole with a diameter of 0.15 mm was formed.
Laser drilling was performed at a window hole provided on the surface of the substrate using an ML505GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation under conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of four. After removing the resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution, applying a cleaning catalyst, promoting adhesion, and then performing electroless copper plating to form an electroless copper plating layer of about 20 μm on the laser hole inner wall and the copper foil surface did. Etching resist was formed on necessary portions such as pads and circuit patterns on the surface of the substrate, and unnecessary copper was removed by etching to form an outer layer circuit.
Solder resist PSR-4000 AUS5 (Taiyo Ink Mfg. Co., Ltd., trade name) was applied to the substrate surface with a roll coater at 30 μm, dried, exposed and developed to form a solder resist 113 at a desired location. Thereafter, 3 μm electroless nickel plating and 0.1 μm electroless gold plating were formed on the surface layer of the exposed portion of the outer circuit pattern to obtain a multilayer wiring board with a built-in capacitor (FIG. 2 (i)).
Example A-2
A multilayer wiring board with a built-in capacitor was obtained by the same process as in Example A-1, except that the material for a multilayer wiring board with a built-in capacitor A-2 was changed to a material for a multilayer wiring board with a built-in capacitor A-3.
Example A-3
The surface of the copper foil 102 of the capacitor built-in multilayer wiring board material A-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pre-treatment for multilayering adhesion ( FIG. 3 (a)). Using a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) with a plate thickness of 0.2 mm as a base material, conductor connection holes and circuit patterns are produced at desired locations. The double-sided substrate 104 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment, and then the insulating resin base material 107 on one surface thereof. Through a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm, a copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd., product name) having a thickness of 18 μm is provided on the other side. In addition, the above-mentioned coating is made through a 100 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is an insulating resin base material 107. Arranged capacitor built multilayer wiring board materials, temperature 170 ° C., pressure 1.5 MPa, and laminated and integrated in the press for 60 minutes between heated pressing time (Figure 3 (b)). Here, 105 is plated copper and 106 is hole filling resin. Further, a 0.05 μm chromium thin film 108 was formed on the surface of the PZT thin film 101 by DC sputtering. Furthermore, after applying the catalyst to the surface and promoting adhesion, electroless copper plating was performed to form a 0.5 μm copper thin film. A desired plating resist was formed on the surface of the substrate, and electrolytic copper plating was performed to form a metal layer 109 serving as a first capacitor electrode having a thickness of 20 μm (FIG. 3C). After removing the plating resist, the 0.5 μm copper thin film and the 0.05 μm chromium thin film on the substrate surface were removed by etching to form a first capacitor electrode pattern (FIG. 3D). Subsequently, a resist having a desired pattern is formed and CF ₄ The PZT thin film and the ruthenium thin film were removed by etching by RIE using gas (FIG. 3E). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary copper foil is removed by etching using an aqueous ferric chloride solution to form a φ0.1 mm window hole at a desired location. Using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation, laser drilling 110 was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (FIG. 3F). After removing resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution, electroless copper plating was performed after catalyst application and adhesion promotion, to form a 0.5 μm copper thin film. A desired plating resist 111 was formed on the surface of the substrate, and copper electroplating was performed to form a metal layer that electrically connected the circuit conductor on the inner layer and the conductor layer on the surface of the substrate (FIG. 3G). After removing the plating resist, the 0.5 μm copper thin film on the substrate surface is removed by etching. Then, a desired etching resist is formed, and an unnecessary copper metal layer is removed by etching with a ferric chloride solution. A circuit pattern including the second capacitor electrode was formed to produce a circuit board (FIG. 3 (h)). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example A-1 (FIG. 3 (i)). Here, 112 is an insulating resin base material, and 113 is a solder resist.
Example A-4
The copper foil surface 102 of the multilayer wiring board material A-3 with a built-in capacitor was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment ( FIG. 4 (a)). Using a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) with a plate thickness of 0.2 mm as a base material, conductor connection holes and circuit patterns are produced at desired locations. The double-sided substrate 104 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment, and then the insulating resin base material 107 on one surface thereof. As a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm, a copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd., product name) having a thickness of 18 μm is provided on the other surface. As the insulating resin base material 107, a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm is used. Arranged capacitor built multilayer wiring board materials, temperature 170 ° C., pressure 1.5 MPa, and laminated and integrated in the press for 60 minutes between heated pressing time (Figure 4 (b)). Here, 105 is plated copper, and 106 is hole filling resin. Furthermore, after printing nano paste (Harima Kasei Co., Ltd., trade name), which is a conductive paste that is metallized by chemical reaction, by screen printing at a desired location on the surface of the PZT thin film at a temperature of 200 ° C. Was baked under the condition of heating time of 1 hour, and the conductive paste was metallized to form a first capacitor electrode pattern (FIG. 4C). Subsequently, a resist having a desired pattern is formed and CF ₄ The PZT thin film and the ruthenium thin film were removed by etching by RIE using gas (FIG. 4D). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary copper foil is removed by etching using an aqueous ferric chloride solution to form a φ0.1 mm window hole at a desired location. Using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation, laser drilling 110 was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (FIG. 4E). After removing resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution, electroless copper plating was performed after catalyst application and adhesion promotion, to form a 0.5 μm copper thin film. A desired plating resist 111 was formed on the surface of the substrate, and electrolytic copper plating was performed to form a metal layer that electrically connected the circuit conductor on the inner layer and the conductor layer on the surface of the substrate (FIG. 4 (f)). After removing the plating resist, the 0.5 μm copper thin film on the substrate surface is removed by etching. Then, a desired etching resist is formed, and an unnecessary copper metal layer is removed by etching with a ferric chloride solution. A circuit pattern including the second capacitor electrode was formed to produce a circuit board (FIG. 4G). Subsequent processing of the multilayer wiring board was performed in the same process as in Example A-1, and a multilayer wiring board with a built-in capacitor was obtained (FIG. 4 (h)).
Here, 112 is an insulating resin base material, and 113 is a solder resist.

実施例Ａ−５
コンデンサ内蔵多層配線板用材料Ａ−３を用い、ＰＺＴ薄膜とルテニウム薄膜をエッチング除去する方法がＲＩＥ法ではなく、ＰＺＴ薄膜に対して２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液、ルテニウム薄膜に対してルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いてエッチングした以外は実施例Ａ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２（ｉ））。
実施例Ａ−６
コンデンサ内蔵多層配線板用材料Ａ−３の銅箔１０２表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図５（ａ））。板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）を基材として、所望の箇所に導体化された接続穴と回路パターンを作製した両面基板１０４に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った後に、その一方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を、また他方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して前述のコンデンサ内蔵多層配線板用材料を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した（図５（ｂ））。ここで、１０５はめっき銅であり、１０６は穴埋め樹脂である。続いて、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜をエッチング除去し、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いてルテニウム薄膜をエッチング除去してＰＺＴ薄膜のパターニングを行った（図５（ｃ））。次に、この基板の表面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴を形成し、窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明け１１０を行った（図５（ｄ））。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、ＤＣスパッタリング法により、０．０５μｍのクロム薄膜１０８を形成した。さらにその表面に電気銅めっきにより２０μｍの金属層１０９を形成した（図５（ｅ））。この際に、薄膜誘電体層表面とレーザ穴内は、銅の金属層が形成されていた。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要な銅の金属層をエッチング除去し、フェリシアン化カリウム水溶液を用いてクロムの金属層をエッチング除去して、第１のコンデンサ電極と第２のコンデンサ電極およびその他の配線パターンを形成して回路板を作製した（図５（ｆ））。その後の多層配線板の加工については実施例Ａ−１と同様な工程で行い、コンデンサ内蔵多層配線板を得た（図５（ｇ））。ここで、１１２絶縁樹脂基材であり、１１３はソルダーレジストである。
実施例Ａ−７
コンデンサ内蔵多層配線板用材料Ａ−３の銅箔表面１０２に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図６（ａ））。板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）を基材として、所望の箇所に導体化された接続穴と回路パターンを作製した両面基板１０４に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った後に、その一方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を、また他方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して前述のコンデンサ内蔵多層配線板用材料を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した（図６（ｂ））。ここで、１０５はめっき銅であり、１０６は穴埋め樹脂である。このプリプレグは、両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃，圧力１．５ＭＰａ，加熱加圧時間１０分の条件のホットプレスで貼り付けた後、所望の箇所にドリル穴明けを行った後、スクリーン印刷により、銅ペーストＮＦ２０００（タツタシステム・エレクトロニクス株式会社、商品名）１１６を充填し、その後に表面のＰＥＴフィルムを剥がしたものを用いた。この基板のＰＺＴ薄膜表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜１０８を形成した。さらにその表面に電気銅めっきにより２０μｍの金属層１０９を形成した（図６（ｃ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要な銅の金属層をエッチング除去し、フェリシアン化カリウム水溶液を用いてクロムの金属層をエッチング除去して、第１のコンデンサ電極のパターンを形成した（図６（ｄ））。続いて、所望のパターンのレジストを形成し、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜とルテニウム薄膜をエッチング除去した（図６（ｅ））。次に、この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄溶液によって不要な銅の金属層をエッチング除去して、第２のコンデンサ電極を含む回路パターンを形成して回路板を作製した（図６（ｆ））。その後の多層配線板の加工は実施例Ａ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図６（ｇ））。ここで、１１２は絶縁樹脂基材であり、１１３はソルダーレジストである。
実施例Ａ−８
コンデンサ内蔵多層配線板用材料Ａ−３の銅箔表面１０２に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図７（ａ））。板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）を基材として、所望の箇所に導体化された接続穴と回路パターンを作製した両面基板１０４に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った後に、その一方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を、また他方の面に絶縁樹脂基材１０７として厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して前述のコンデンサ内蔵多層配線板用材料を配し、温度２００℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した（図７（ｂ））。なお、１０５はめっき銅を、１０６は穴埋め樹脂を示す。このプリプレグは、両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃，圧力１．５ＭＰａ，加熱加圧時間１０分の条件のホットプレスで貼り付けた後、所望の箇所にドリル穴明けを行った後、スクリーン印刷により、化学的な反応により金属化される導電性ペースト１１７であるナノペースト（ハリマ化成株式会社、商品名）を充填し、その後に表面のＰＥＴフィルムを剥がしたものを用いた。その後のコンデンサの加工と多層配線板の加工については実施例Ａ−１と同様な工程で行い、コンデンサ内蔵多層配線板を得た（図７（ｃ））。なお、１１２は絶縁樹脂基材を、１１３はソルダーレジストであうる。
比較例Ａ−１
板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）を基材として、厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を用い、所望の箇所に導体化された接続穴と回路パターンを作製した４層基板の表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜を形成した（図８（ａ））。ここで、１０２は銅箔、１０５はめっき銅、１０６は穴埋め樹脂、１０７は絶縁樹脂基材である。所望のパターンのレジストを形成し、ＲＩＥ法によってルテニウム薄膜１０３をエッチング除去し、その後塩化第二鉄水溶液を用いて内層基板表面の銅の金属層をエッチング除去し、第２のコンデンサ電極を含む回路パターンを形成した（図８（ｂ））。さらにその基板表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度２５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜１０１を形成した（図８（ｃ））。さらにそのＰＺＴ薄膜表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜を形成した。さらにその表面に電気銅めっきにより２０μｍの金属層１０９を形成した（図８（ｄ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要な銅の金属層をエッチング除去し、フェリシアン化カリウム水溶液を用いてクロムの金属層をエッチング除去して、第１のコンデンサ電極のパターンを形成して回路板を作製した（図８（ｅ））。その後の多層配線板の加工は実施例Ａ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図８（ｆ））。ここで、１１２は絶縁樹脂基材であり、１１３はソルダーレジストを示す。
試験方法は以下の通りである。
（誘電体の膜厚）
誘電体の膜厚は、電極を形成したコンデンサをＦｏｃｕｓｅｄＩｏｎＢｅａｍｓｙｓｔｅｍ（ＦＩＢ：ＦＢ−２０００Ａ、（株）日立製作所製、商品名）により切削し、その断面観察を走査型電子顕微鏡を用いて行い、膜をはさむ電極と電極の間の距離の５点平均をとった。
（比誘電率）
比誘電率は、２５℃に温度管理された環境の下で、ＩＰＣ−６５０２．５．５．２に準じて１ＭＨｚの周波数で測定して得た。
（コンデンサ容量）
コンデンサ容量は、インピーダンスアナライザ４２９１Ｂ（アジレントテクノロジー株式会社製、商品名）に５０Ω同軸ケーブルＳＵＣＯＦＬＥＸ１０４／１００（ＳＵＨＮＥＲ社製、商品名）を介して高周波信号測定プローブＭＩＣＲＯＰＲＯＢＥＡＣＰ５０（ＧＳＧ２５０型、Ｃａｓｃａｄｅ社製、商品名）に接続した測定システムを用いた。キャパシタの電極サイズは１ｍｍ□とし１ＧＨｚの容量を測定した。測定サンプル数は５とした。

実施例Ａ−１〜Ａ−８は、いずれも、金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたことを特徴とするコンデンサ内蔵多層配線板用材料を用いて作製したコンデンサ内蔵基板である。作製したコンデンサ容量のばらつきは全て±１０％未満であり、均一で良好なコンデンサを作製することができた。
また、比較例Ａ−１は、誘電体薄膜を金属層がパターニングされた基板の表面に形成されたコンデンサ内蔵基板であるために、膜厚のばらつきが大きく、結果としてコンデンサ容量のばらつきも最大５４％と大きかった。
上記の実施形態によると、本発明によって、コンデンサを形成する誘電体薄膜の比誘電率が２０〜２０００でかつ膜厚が０．１〜１μｍであり、かつ容量ばらつきの小さなコンデンサを有する多層配線板を提供することができる。
（実施例Ｂ）
内層基板Ｂ−１
銅箔厚３μｍ、板厚０．２ｍｍの両面銅箔張ガラスエポキシ積層板ＭＣＬ−Ｅ−６７９Ｆ（日立化成工業株式会社製、商品名）に所望のドリル穴明け（直径２００μｍ）を行った。そして、この基板に、超音波洗浄と過マンガン酸アルカリ溶液を用いて炭化した樹脂カスを除去した後、触媒付与、密着促進後、無電解銅めっきを行い、ドリル穴内壁と銅箔表面に約１５μｍの無電解銅めっき層２０４を形成した。得られた基板表面に次亜塩素酸ナトリウムを主成分とする黒化処理と、ジメチルアミノボランを主成分とする還元処理により粗化処理を行った。そして、この基板のドリル穴内にスクリーン印刷によりペーストタイプの熱硬化型絶縁材料ＨＲＰ−７００ＢＡ（太陽インキ製造株式会社製、商品名）を穴埋め樹脂２０３として充填し、１７０℃で６０分間の熱処理により硬化させた。この基板をバフブラシにより研磨し、余分な絶縁材料を除去した。この基板に触媒付与、密着促進後、無電解銅めっきを行い、基板表面に約１５μｍの無電解銅めっき層を形成し、基板内部に導体層間を接続するバイアホールを有し、かつ表面に平滑な金属層を有する基板を作製した。走査型電子顕微鏡を用いて観察した像から求めた基板表面の金属層の表面粗さは０．３μｍであった。作製した内層基板の断面図を図９に示した。なお、２０２は絶縁樹脂基材を、２０１は銅箔を示す。
内層基板Ｂ−２
厚み２００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）の両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃，圧力１．５ＭＰａ，加熱加圧時間１０分の条件のホットプレスで貼り付けた。このプリプレグに所望のドリル穴明け（直径２００μｍ）を行った後、スクリーン印刷により、銅ペーストＮＦ２０００（タツタシステム・エレクトロニクス株式会社製、商品名）２０５を充填した。表面のＰＥＴフィルムを剥がし、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社製、商品名）で両面から挟み、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板内部に導体層間を接続するバイアホールを有し、かつ表面に平滑な金属層を有する基板を作製した。走査型電子顕微鏡を用いて観察した像から求めた基板表面の金属層の表面粗さは０．２μｍであった。作製した内層基板の断面図を図１０に示した。
内層基板Ｂ−３
厚み２００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）の両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃，圧力１．５ＭＰａ，加熱加圧時間１０分の条件のホットプレスで貼り付けた。このプリプレグに所望のドリル穴明け（直径２００μｍ）を行った後、スクリーン印刷により、化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社製、商品名）２０６を充填した。表面のＰＥＴフィルムを剥がし、厚み１８μｍの銅箔ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）で両面から挟み、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板内部に導体層間を接続するバイアホールを有し、かつ表面に平滑な金属層を有する基板を作製した。走査型電子顕微鏡を用いて観察した像から求めた基板表面の金属層の表面粗さは０．２μｍであった。作製した内層基板の断面図を図１１に示した。
実施例Ｂ−１
内層基板Ｂ−１の基板表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜２０７を形成した（図１２（ａ））。さらにその基板表面にチタンテトライソプロポキシド、ジルコンテトラターシャリーブトキシド、ジピバロイルメタン鉛錯体、二酸化窒素を用いたマイクロ波プラズマＣＶＤにより、基板温度２５０℃の条件下で厚さ０．５μｍのＰＺＴ（チタン酸ジルコン酸鉛）薄膜２０８を形成した（図１２（ｂ））。さらにそのＰＺＴ薄膜表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜２０９を形成した。さらにその表面に電気銅めっきにより２０μｍの金属層２１０を形成した（図１２（ｃ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要な銅の金属層２１０をエッチング除去し、フェリシアン化カリウム水溶液を用いてクロムの金属層２０９をエッチング除去して、第１のコンデンサ電極２１７のパターンを形成した（図１２（ｄ））。続いて、所望のパターンのレジストを形成し、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜２０８とルテニウム薄膜２０７をエッチング除去した（図１２（ｅ））。次に、さらに所望のエッチングレジストを形成し、塩化第二鉄溶液によって不要な銅の金属層をエッチング除去して、第２のコンデンサ電極２１８を含む回路パターンを形成してコンデンサ内蔵多層配線板に用いる内層板２１９を作製した（図１２（ｆ））。
この内層板の回路表面に、次亜塩素酸ナトリウムを主成分とする黒化処理と、ジメチルアミノボランを主成分とする還元処理によって、粗化処理を行った。（１）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）、（２）絶縁樹脂基材２１１として厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）、（３）内層板２１９、（４）絶縁樹脂基材２１１として厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ、（５）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）の順に重ね、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した。キャリア銅箔を剥がし、不要な基板端部を切断後、この基板の表面に所望のエッチングレジストを形成し、不要な銅箔をエッチング除去して、所望の箇所に直径０．１５ｍｍの窓穴を形成した。
この基板表面に設けた窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明けを行った。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、洗浄、触媒付与、密着促進後無電解銅めっきを行い、レーザ穴内壁と銅箔表面に約２０μｍの無電解銅めっき層を形成した。この基板表面のパッドや回路パターンなど必要な箇所にエッチングレジストを形成し、不要な銅をエッチング除去して、外層回路２１３を形成した。
この基板表面にソルダーレジストＰＳＲ−４０００ＡＵＳ５（太陽インキ製造株式会社製、商品名）をロールコータで３０μｍ塗布、乾燥後に露光・現像して所望の箇所にソルダーレジスト２１２を形成した。その後、３μｍの無電解ニッケルめっきと０．１μｍの無電解金めっきを外層回路パターン露出部表面層に形成して、コンデンサ内蔵多層配線板２２０を得た（図４（ｇ））。
実施例Ｂ−２
内層基板Ｂ−１を内層基板Ｂ−２に替えた以外は実施例Ｂ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実施例Ｂ−３
内層基板Ｂ−１を内層基板Ｂ−３に替えた以外は実施例Ｂ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実施例Ｂ−４
内層基板Ｂ−１の基板表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜２０７を形成した（図１２（ａ））。さらにその基板表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社製、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度２５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜２０８を形成した（図１２（ｂ））。その後のコンデンサの加工と多層配線板の加工については実施例Ｂ−１と同様な工程で行い、コンデンサ内蔵多層配線板を得た（図１２（ｇ））。
実施例Ｂ−５
ＰＺＴ薄膜２０８とルテニウム薄膜２０７をエッチング除去する方法がＲＩＥ法ではなく、ＰＺＴ薄膜に対して２０重量％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液、ルテニウム薄膜に対してルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社製、商品名）を用いてエッチングした以外は実施例Ｂ−４と同様な工程によりコンデンサ内蔵多層配線板を得た（図１２（ｇ））。
実施例Ｂ−６
内層基板Ｂ−１の基板表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜２０７を形成した（図１３（ａ））。さらにその基板表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社製、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度２５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜２０８を形成した（図１３（ｂ））。さらにそのＰＺＴ薄膜表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜２０９を形成した。さらにその表面を洗浄、触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成した。
この基板の表面に所望のめっきレジスト２１５を形成し、電気銅めっきを行い、厚み２０μｍの第１のコンデンサ電極となる金属層２１４を形成した（図１３（ｃ））。めっきレジスト２１５を剥離後、基板表面の０．５μｍの銅薄膜と０．０５μｍのクロム薄膜をエッチング除去して、第１のコンデンサ電極２１７のパターンを形成した（図１３（ｄ））。続いて、所望のパターンのレジストを形成し、２０重量％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜２０８をエッチング除去し、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社製、商品名）用いてルテニウム薄膜２０７をエッチング除去した（図１３（ｅ））。次に、さらに所望のエッチングレジストを形成し、塩化第二鉄溶液によって不要な銅の金属層をエッチング除去して、第２のコンデンサ電極２１８を含む回路パターンを形成して内層板２１９を作製した（図１３（ｆ））。その後の多層配線板の加工は実施例Ｂ−１と同様な工程によりコンデンサ内蔵多層配線板２２０を得た（図１３（ｇ））。
実施例Ｂ−７
内層基板Ｂ−１の基板表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜２０７を形成した（図１４（ａ））。さらにその基板表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社製、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度２５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜２０８を形成した（図１４（ｂ））。さらにそのＰＺＴ薄膜表面の所望の箇所にスクリーン印刷により、化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社製、商品名）２１６を４０μｍの厚みで印刷後、温度２００℃で加熱時間１時間の条件でベーキングし、導電性ペーストを金属化して、第１のコンデンサ電極２１７のパターンを形成した（図１４（ｃ））。続いて、所望のパターンのレジストを形成し、２０重量％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜をエッチング除去し、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社製、商品名）を用いてルテニウム薄膜をエッチング除去した（図１４（ｄ））。次に、さらに所望のエッチングレジストを形成し、塩化第二鉄溶液によって不要な銅の金属層をエッチング除去して、第２のコンデンサ電極２１８を含む回路パターンを形成して内層板２１９を作製した（図１４（ｅ））。その後の多層配線板の加工は実施例Ｂ−１と同様な工程によりコンデンサ内蔵多層配線板２２０を得た（図１４（ｆ））。
実施例Ｂ−８
内層基板Ｂ−１の基板表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜２０７を形成した（図１５（ａ））。さらにその基板表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社製、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度２５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜２０８を形成した（図１５（ｂ））。続いて、所望のパターンのレジストを形成し、２０重量％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜２０８をエッチング除去し、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社製、商品名）を用いてルテニウム薄膜をエッチング除去してＰＺＴ薄膜のパターニングを行った（図１５（ｃ））。そのＰＺＴ薄膜表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜２０９を形成した。さらにその表面に電気銅めっきにより２０μｍの金属層２１０を形成した（図１５（ｄ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要な銅の金属層をエッチング除去し、フェリシアン化カリウム水溶液を用いてクロムの金属層をエッチング除去して、第１のコンデンサ電極２１７と第２のコンデンサ電極２１８およびその他の配線パターンを形成して内層板２１９を作製した（図１５（ｅ））。その後の多層配線板の加工は実施例Ｂ−１と同様な工程によりコンデンサ内蔵多層配線板２２０を得た（図１５（ｆ））。
比較例Ｂ−１
内層基板Ｂ−１の基板表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜２０７を形成した（図１６（ａ））。所望のパターンのレジストを形成し、ＲＩＥ法によってルテニウム薄膜２０７をエッチング除去し、その後塩化第二鉄水溶液を用いて内層基板表面の銅の金属層をエッチング除去し、第２のコンデンサ電極２１８を含む回路パターンを形成した（図１６（ｂ））。さらにその基板表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社製、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度２５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜２０８を形成した（図１６（ｃ））。さらに、そのＰＺＴ薄膜表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜２０９を形成した。さらにその表面に電気銅めっきにより２０μｍの金属層２１０を形成した（図１６（ｄ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要な銅の金属層をエッチング除去し、フェリシアン化カリウム水溶液を用いてクロムの金属層をエッチング除去して、第１のコンデンサ電極２１７のパターンを形成して内層板２１９を作製した（図１６（ｅ））。その後の多層配線板の加工は実施例Ｂ−１と同様な工程によりコンデンサ内蔵多層配線板２２０を得た（図１６（ｆ））。
以上で得られたコンデンサ内蔵多層配線板について、誘電体の膜厚、非誘電率およびコンデンサ容量の試験を行った。試験方法を上記と同様である。
これらの測定結果をまとめて表２に示した。

実施例Ｂ−１〜Ｂ−８は、いずれも、基板内部に導体層間を接続するバイアホールを有し，かつ表面に平滑な金属層を有する基板の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜を形成することにより作製したコンデンサ内蔵基板である。作製したコンデンサ容量のばらつきは全て±１０％未満であり、均一で良好なコンデンサを作製することができた。
また、比較例Ｂ−１は、誘電体薄膜を金属層がパターニングされた基板の表面に形成されたコンデンサ内蔵基板であるために、膜厚のばらつきが大きく、結果としてコンデンサ容量のばらつきも最大５４％と大きかった。
上記の実施例によると、膜厚が均一で、容量ばらつきの小さなコンデンサを内蔵したコンデンサ内蔵多層配線板を提供することができる。
（実験例Ｃ）
コンデンサ内蔵多層配線板用材料Ｃ−１
厚み３５μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）１０２の表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜１０３を形成した。さらにその表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度３５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜１０１を形成した。このようにして、銅箔２（金属箔）１０２の片面に、ルテニウム薄膜１０３を介してＰＺＴ薄膜１０１（誘電体薄膜）を設けたコンデンサ内蔵多層配線板用材料Ｃ−１を作製した（図１参照）。このようにして得られたＰＺＴ薄膜の比誘電率は１００であった。
コンデンサ内蔵多層配線板用材料Ｃ−２
厚み３５μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）１０２の表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜１０３を形成した。さらにその表面にチタンテトライソプロポキシド、ジルコンテトラターシャリーブトキシド、ジピバロイルメタン鉛錯体、二酸化窒素を用いたマイクロ波プラズマＣＶＤにより、基材温度３５０℃の条件下で厚さ０．５μｍのＰＺＴ（チタン酸ジルコン酸鉛）薄膜１０１を形成し、コンデンサ内蔵多層配線板用材料Ｃ−２を得た。このようにして得られたＰＺＴ薄膜の比誘電率は７０であった。
薄膜エッチャント１
エチレンジアミン四酢酸・二ナトリウム塩（ＥＤＴＡ・２Ｎａ）、過酸化水素（Ｈ_２Ｏ_２）、水を混合し、ＥＤＴＡ・２Ｎａ０．１ｍｏｌ／ｌ、Ｈ_２Ｏ_２３０ｗｔ％を成分とするｐＨ４．０の水溶液を作製した。
薄膜エッチャント２
イミノ二酢酸（ＩＤＡ）、Ｈ_２Ｏ_２、水を混合し、ＩＤＡ０．１ｍｏｌ／ｌ、Ｈ_２Ｏ_２３０ｗｔ％を成分とするｐＨ２．０の水溶液を作製した。
薄膜エッチャント３
エチレンジアミン四酢酸・二ナトリウム塩（ＥＤＴＡ・２Ｎａ）、Ｈ_２Ｏ_２、水を混合し、ＥＤＴＡ・２Ｎａ０．０１ｍｏｌ／ｌ、Ｈ_２Ｏ_２１０ｗｔ％を成分とするｐＨ４．２の水溶液を作製した。
薄膜エッチャント４
りん酸、Ｈ_２Ｏ_２、水を混合し、りん酸３０ｗｔ％、Ｈ_２Ｏ_２２０ｗｔ％を成分とする水溶液を作製した。
薄膜エッチャント５
硫酸、Ｈ_２Ｏ_２、水を混合し、硫酸５ｗｔ％、Ｈ_２Ｏ_２１０ｗｔ％を成分とする水溶液を作製した。
実験例Ｃ−１
コンデンサ内蔵多層配線板用材料Ｃ−１の銅箔表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。図１７において、銅箔は３０３，ルテニウム薄膜は３０２，ＰＺＴ薄膜３０１として示す。この銅箔３０３表面に絶縁樹脂基材３０４（絶縁材料）となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔５ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）３０５を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を得た（図１７（ａ）参照）。さらにそのＰＺＴ薄膜３０１表面にＤＣスパッタリング法により、０．０５μｍのクロム膜３０６を形成した。次に、この基板の銅箔３０５表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。次に不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴３０７を形成し、水酸化ナトリウム水溶液にてレジストを剥離した（図２（ｂ）参照）。続いて窓穴３０７の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明け３０８を行った（図１７（ｃ）参照）。その後、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去し、触媒付与、密着促進後無電解銅めっきを行い、基板の表面に０．５μｍの銅薄膜を形成した。さらに、この基板表面に電気銅めっきを行い、内層の回路導体と基板表面の導体層とを電気的に接続するめっき銅３０９からなる金属層を形成した（図１７（ｄ）参照）。続いてこの基板の表面に、膜厚３０μｍのドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。さらに、塩化第二鉄水溶液を用いて不要なめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてレジストを剥離し、フェリシアン化カリウム水溶液を用いてクロム膜３０６をエッチング除去して、第１のコンデンサ電極（金属層）３１０のパターンを形成した（図１８（ａ）参照）。次にこの基板の第１のコンデンサ電極３１０側に、エッチングレジスト３１１となる膜厚４０μｍのドライフィルムレジストＨ−９０４０（日立化成工業株式会社製、商品名）をラミネートし（図１８（ｂ）参照）、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、第１のコンデンサ電極３１０上にエッチングレジスト３１１を形成した（図１８（ｃ）参照）。続いて、薄膜エッチャント（１）を用いて２０℃でＰＺＴ薄膜３０１をエッチング除去し、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社製、商品名）を用いてルテニウム薄膜３０２をエッチング除去して（図１８（ｄ）参照）、水酸化ナトリウム水溶液にてエッチングレジスト３１１を剥離した（図１８（ｅ）参照）。この基板にドライフィルムレジストＨ−９０４０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。続いて塩化第二鉄水溶液にて不要な銅箔３０３、不要な銅箔３０５及びその上のめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてレジストを剥離し、銅箔３０３から形成された第２のコンデンサ電極３１２を含む回路パターンを形成して回路板を作製した（図１９（ａ）参照）。
この回路板の回路表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。（１）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）、（２）厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）、（３）回路板、（４）厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ、（５）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）の順に重ね、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化することにより、回路板の両面上に、絶縁樹脂基材３１３を介して銅箔３１４を積層した。キャリア銅箔を剥がし、不要な基板端部を切断後（図１９（ｂ）参照）、この基板の表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。次に不要な銅箔３１４を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴を形成した。
この回路板表面に設けた窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明け３１０を行った（図１９（ｃ）参照）。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、洗浄触媒付与、密着促進後無電解銅めっきを行い、レーザ穴内壁と銅箔表面に約２０μｍの無電解めっき銅３１５の層を形成した。この回路板表面のパッドや回路パターンなど必要な箇所にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）を用いてエッチングレジストを形成し、不要な銅をエッチング除去して、銅箔３１４及びめっき銅３１５から形成された外層回路を形成した（図１９（ｄ）参照）。
この回路板表面にソルダーレジストＰＳＲ−４０００ＡＵＳ５（太陽インキ製造株式会社製、商品名）をロールコータで３０μｍ塗布、乾燥後に露光・現像して所望の箇所にソルダーレジスト３１６を形成した。その後、３μｍの無電解ニッケルめっきと０．１μｍの無電解金めっき（Ｎｉ／Ａｕめっき３１７）を外層回路パターン露出部表面層に形成して、コンデンサ内蔵多層配線板を得た（図１９（ｅ）参照）。
実験例Ｃ−２
コンデンサ内蔵多層配線板用材料Ｃ−１をコンデンサ内蔵多層配線板用材料Ｃ−２に替えた以外は、実験例Ｃ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実験例Ｃ−３
薄膜エッチャント（１）を薄膜エッチャント（２）に替えた以外は、実験例Ｃ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実験例Ｃ−４
薄膜エッチャント（１）を薄膜エッチャント（３）に替え、３０℃で用いた以外は実験例Ｃ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実験例Ｃ−５
薄膜エッチャント（１）を薄膜エッチャント（４）に替えた以外は、実験例Ｃ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実験例Ｃ−６
薄膜エッチャント（１）を薄膜エッチャント（５）に替えた以外は、実験例Ｃ−１と同様な工程によりコンデンサ内蔵多層配線板を得た。
実験例Ｃ−７
コンデンサ内蔵多層配線板用材料Ｃ−１の銅箔３０３表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。この銅箔３０３表面に絶縁樹脂基材３０４（絶縁材料）となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔５ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を得た（図１７（ａ）参照）。さらにそのＰＺＴ薄膜３０１表面にＤＣスパッタリング法により、０．０５μｍのクロム膜３０６を形成した。次に、この基板の銅箔３０５表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。次に不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴３０７を形成し（図１７（ｂ）参照）、水酸化ナトリウム水溶液にてレジストを剥離した。続いて窓穴７の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴３０８明けを行った（図１７（ｃ）参照）。その後、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去し、触媒付与、密着促進後無電解銅めっきを行い、基板の両面に０．５μｍの銅薄膜を形成した。さらに、この基板表面に電気銅めっきを行い、内層の回路導体と基板表面の導体層とを電気的に接続するめっき銅３０９からなる金属層を形成した（図１７（ｄ）参照）。続いてこの基板の表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。さらに、塩化第二鉄水溶液を用いて不要なめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてレジストを剥離し、フェリシアン化カリウム水溶液を用いてクロム膜３０６をエッチング除去して、第１のコンデンサ電極３１０のパターンを形成した（図１８（ａ）参照）。次にこの基板の第１のコンデンサ電極３１０側にエッチングレジスト３１１となるアルカリ現像型レジストＰＥＲ−２０（太陽インキ製造株式会社製、商品名）を２０μｍ塗布し（図１８（ｂ）参照）、１００℃で１５分プリベークした後所望のネガパターンを露光して１３０℃で３０分乾燥し、炭酸ナトリウム水溶液にて現像し第１のコンデンサ電極３１０上にエッチングレジスト３１１を形成した（図１８（ｃ）参照）。続いて、薄膜エッチャント（１）を用いて２０℃でＰＺＴ薄膜３０１をエッチング除去し、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社製、商品名）を用いてルテニウム薄膜３０２をエッチング除去して（図１８（ｄ）参照）、水酸化ナトリウム水溶液にてエッチングレジスト３１１を剥離した（図１８（ｅ）参照）。この基板にドライフィルムレジストＨ−９０４０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。続いて塩化第二鉄水溶液にて不要な銅箔３０３、不要な銅箔３０５及びその上のめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてエッチングレジストを剥離し銅箔３０３から形成された第２のコンデンサ電極３１２を含む回路パターンを形成して回路板を作製した（図１９（ａ）参照）。
この回路板を用い、その後実験例Ｃ−１と同様な工程によって多層化し、コンデンサ内蔵多層配線板を得た。
実験例Ｃ−８
コンデンサ内蔵多層配線板用材料Ｃ−１の銅箔３０３表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。この銅箔３０３表面に絶縁樹脂基材３０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔５ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を得た（図１７（ａ）参照）。さらにそのＰＺＴ薄膜３０１表面にＤＣスパッタリング法により、０．０５μｍのクロム膜３０６を形成した。次に、この基板の銅箔３０５表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。次に不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴３０７を形成し、水酸化ナトリウム水溶液にてレジストを剥離した（図１７（ｂ）参照）。続いて窓穴３０７の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴３０８明けを行った（図１７（ｃ）参照）。その後、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去し、触媒付与、密着促進後無電解銅めっきを行い、基板の両面に０．５μｍの銅薄膜を形成した。さらに、この基板表面に電気銅めっきを行い、内層の回路導体と基板表面の導体層とを電気的に接続するめっき銅３０９からなる金属層を形成した（図１７（ｄ）参照）。続いてこの基板の表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。さらに、塩化第二鉄水溶液を用いて不要なめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてレジストを剥離し、フェリシアン化カリウム水溶液を用いてクロム膜３０６をエッチング除去して、第１のコンデンサ電極３１０のパターンを形成した（図１８（ａ）参照）。次にこの基板の第１のコンデンサ電極３１０側にエッチングレジスト３１１となる溶剤現像型レジストＡＺ９２４５（クラリアントジャパン株式会社製、商品名）を１２μｍ塗布し（（図１８（ｂ）参照）、１１０℃で１０分プリベークした後所望のポジパターンを露光して１２０℃で１０分乾燥し、ＡＺ４００Ｋデベロッパー（クラリアントジャパン株式会社製、商品名）にて現像してエッチングレジスト３１１を形成した（図１８（ｃ）参照）。続いて、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いて２０℃でＰＺＴ薄膜３０１をエッチング除去し、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社製、商品名）を用いてルテニウム薄膜３０２をエッチング除去して（図３の（ｄ）参照）、ＡＺリムーバー７００（クラリアントジャパン株式会社製、商品名）にてエッチングレジスト３１１を剥離した（図１８（ｅ）参照）。この基板にドライフィルムレジストＨ−９０４０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。続いて塩化第二鉄水溶液にて不要な銅箔３０３、不要な銅箔３０５及びその上のめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてレジストを剥離し、銅箔３０３から形成された第２のコンデンサ電極３１２を含む回路パターンを形成して回路板を作製した（図１９（ａ）参照）。
この回路板の回路表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。（１）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）、（２）厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）、（３）回路板、（４）厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ、（５）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）の順に重ね、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化することにより、回路板の両面上に、絶縁樹脂基材３１３を介して銅箔３１４を積層した。キャリア銅箔を剥がし、不要な基板端部を切断後（図１９（ｂ）参照）、この基板の表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。次に不要な銅箔３１４を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴を形成した。
この回路板表面に設けた窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明けを行った（図１９（ｃ）参照）。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、洗浄触媒付与、密着促進後無電解銅めっきを行い、レーザ穴内壁と銅箔表面に約２０μｍの無電解銅めっき層を形成した。この回路板表面のパッドや回路パターンなど必要な箇所にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）を用いてエッチングレジストを形成し、不要な銅をエッチング除去して、銅箔３１４及びめっき銅３１５から形成された外層回路を形成した（図１９（ｄ）参照）。この回路板表面にソルダーレジストＰＳＲ−４０００ＡＵＳ５（太陽インキ製造株式会社製、商品名）をロールコータで３０μｍ塗布、乾燥後に露光・現像して所望の箇所にソルダーレジスト３１６を形成した。その後、３μｍの無電解ニッケルめっきと０．１μｍの無電解金めっき（Ｎｉ／Ａｕめっき１７）を外層回路パターン露出部表面層に形成して、コンデンサ内蔵多層配線板を得た（図１９（ｅ）参照）。
実験例Ｃ−９
コンデンサ内蔵多層配線板用材料Ｃ−１の銅箔３０３表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。この銅箔３０３表面に絶縁樹脂基材３０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔５ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を配し、温度１７０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を得た（図１７（ａ）参照）。さらにそのＰＺＴ薄膜３０１表面にＤＣスパッタリング法により、０．０５μｍのクロム膜３０６を形成した。次に、この基板の銅箔３０５表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。次に不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１ｍｍの窓穴３０７を形成し、水酸化ナトリウム水溶液にてレジストを剥離した（図１７（ｂ）参照）。続いて窓穴３０７の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴３０８明けを行った（図１７（ｃ）参照）。その後、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去し、触媒付与、密着促進後無電解銅めっきを行い、基板の両面に０．５μｍの銅薄膜を形成した。さらに、この基板表面に電気銅めっきを行い、内層の回路導体と基板表面の導体層とを電気的に接続するめっき銅３０９からなる金属層を形成した（図１７（ｄ）参照）。続いてこの基板の表面にドライフィルムレジストＨ−９０３０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。さらに、塩化第二鉄水溶液を用いて不要なめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてレジストを剥離し、フェリシアン化カリウム水溶液を用いてクロム膜３０６をエッチング除去して、第１のコンデンサ電極３１０のパターンを形成した（図１８（ａ）参照）。次にこの基板の第１のコンデンサ電極３１０側にエッチングレジスト３１１となる溶剤現像型レジストＡＺ９２４５（クラリアントジャパン株式会社製、商品名）を１２μｍ塗布し（図１８（ｂ）参照）、１１０℃で１０分プリベークした後所望のポジパターンを露光して１２０℃で１０分乾燥し、ＡＺ４００Ｋデベロッパー（クラリアントジャパン株式会社製、商品名）にて現像してエッチングレジスト３１１を形成した（図１８（ｃ）参照）。続いて、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜３０１とルテニウム薄膜３０２をエッチング除去した後（図１８（ｄ）参照）、ＡＺリムーバー７００（クラリアントジャパン株式会社製、商品名）にてエッチングレジスト３１１を剥離した（図１８（ｅ）参照）。この基板にドライフィルムレジストＨ−９０４０（日立化成工業株式会社製、商品名）をラミネートし、所望のネガパターンを露光して炭酸ナトリウム水溶液にて現像し、エッチングレジストを形成した。続いて塩化第二鉄水溶液にて不要な銅箔３０３、不要な銅箔３０５及びその上のめっき銅３０９をエッチング除去した後、水酸化ナトリウム水溶液にてレジストを剥離し、銅箔３０３から形成された第２のコンデンサ電極３１２を含む回路パターンを形成して回路板を作製した（図１９（ａ）参照）。
この回路板を用い、その後実験例Ｃ−８と同様な工程によってコンデンサ内蔵多層配線板を得た（図１９（ｅ）参照）。
実験例Ｃ−１〜Ｃ−７において、薄膜のエッチング時にエッチング残渣やレジストの剥れ等はいずれの基板にもみられず、パターニング性は良好であった。次に、コンデンサ容量を測定した。コンデンサ容量はインピーダンスアナライザ４２９１Ｂ（アジレントテクノロジー株式会社製、商品名）に５０Ω同軸ケーブルＳＵＣＯＦＬＥＸ１０４／１００（ＳＵＨＮＥＲ社製、商品名）を介して高周波信号測定プローブＭＩＣＲＯＰＲＯＢＥＡＣＰ５０（ＧＳＧ２５０型、Ｃａｓｃａｄｅ社製、商品名）に接続した測定システムを用いた。キャパシタの電極サイズは１ｍｍ□とし１ＧＨｚの容量を測定した。この結果を表３に示す。

表３に示したように、実験例Ｃ−１〜Ｃ−７で作製したコンデンサ内蔵多層配線板のコンデンサ容量のばらつきは、全て±１０％未満であり、均一で良好なコンデンサを作製することができた。これは実験例Ｃ−８〜Ｃ−９と同等のばらつきであり、実験例Ｃ−１〜Ｃ−７を用いても実験例Ｃ−８〜Ｃ−９と同等な精度のコンデンサ内蔵多層配線が得られることがわかる。しかも、従来のＣＦ_４ガスを用いたＲＩＥ法（実験例Ｃ−９）や２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液（実験例Ｃ−８）などとは、異なり、前述したようにアルカリ現像型のレジストを用いたウェットエッチング法であるため、従来のプリント配線板の工程に容易に適用することが可能であり、作業性及び経済性の点で優れている。
（実施例Ｄ）
コンデンサ内蔵多層配線板用材料Ｄ−１
厚み１８μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）の表面にチタンテトライソプロポキシド、ジルコンテトラターシャリーブトキシド、ジピバロイルメタン鉛錯体、二酸化窒素を用いたマイクロ波プラズマＣＶＤにより、基材温度３５０℃の条件下で厚さ０．５μｍのＰＺＴ（チタン酸ジルコン酸鉛）薄膜を形成した。このようにして、銅箔１０２（金属箔Ａ）の片面にＰＺＴ薄膜１０１（誘電体薄膜）が設けられたコンデンサ内蔵多層配線板用材料Ｄ−１を得た（図１（ａ））。
コンデンサ内蔵多層配線板用材料Ｄ−２
厚み１８μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）の表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜を形成した。さらにその基板表面にチタンテトライソプロポキシド、ジルコンテトラターシャリーブトキシド、ジピバロイルメタン鉛錯体、二酸化窒素を用いたマイクロ波プラズマＣＶＤにより、基材温度３５０℃の条件下で厚さ０．５μｍのＰＺＴ（チタン酸ジルコン酸鉛）薄膜を形成した。このようにして、銅箔１０２（金属箔Ａ）の片面に、ルテニウム薄膜１０３を介してＰＺＴ薄膜１０１（誘電体薄膜）が設けられたコンデンサ内蔵多層配線板用材料Ｄ−２を得た（図１（ｂ））。
コンデンサ内蔵多層配線板用材料Ｄ−３
厚み１８μｍの圧延銅箔Ｍ−ＢＮＨ−１８（三井金属鉱業株式会社製、商品名）の表面にＤＣスパッタリング法により、０．２μｍのルテニウム薄膜を形成した。さらにその表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度３５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜を形成した。このようにして、銅箔１０２（金属箔Ａ）の片面に、ルテニウム薄膜１０３を介してＰＺＴ薄膜１０１（誘電体薄膜）が設けられたコンデンサ内蔵多層配線板用材料（３）を得た（図１（ｂ））。
実施例Ｄ−１
コンデンサ内蔵多層配線板用材料Ｄ−１の銅箔４０２（金属箔Ａ）の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２０（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４（絶縁層）となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１２μｍの銅箔４０５（金属箔Ｂ）ＧＴＳ−１２（古河サーキットフォイル株式会社、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を得た（図２０（ｂ））。次に、この基板の両面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴４０５′を形成した（図２０（ｃ））。続いて、窓穴４０５′の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ照射によってレーザ穴４０６を明け、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去した（図２０（ｄ））。さらにそのＰＺＴ薄膜４０１（誘電体薄膜）表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。その後、基板両面に、触媒付与剤（Ｎｅｏｇａｎｔｈ８４３、アトテックジャパン（株）製、商品名）を用いた触媒付与処理、密着促進剤（ＮｅｏｇａｎｔｈＷＡ、アトテックジャパン（株）製、商品名）を用いた密着促進処理を行なった後、無電解銅めっきを行い、０．５μｍの銅薄膜を形成し、さらに基板両面に電気銅めっきにより２０μｍの金属層を形成し、めっき銅４０８からなる金属層を形成した（図２０（ｅ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いて不要なめっき銅４０８をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜４０７をエッチング除去して、第１のコンデンサ電極４０９のパターンを形成した（図２０（ｆ））。続いて、所望のパターンのレジストを形成し、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜４０１をエッチング除去し、コンデンサ誘電体４０１′を形成した（図２０（ｇ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２、銅箔４０５及びめっき銅４０８の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２０（ｈ））。
この回路板の回路表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った。（１）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）、（２）絶縁樹脂基材４１２となる厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）、（３）回路板、（４）絶縁樹脂基材４１２となる厚み１００μｍのフィラー入りガラスエポキシプリプレグＧＥＡ−６７９Ｆ、（５）３５μｍキャリア銅箔付き厚み３μｍの銅箔ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）の順に重ね、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化した。キャリア銅箔を剥がし、不要な基板端部を切断後、この基板の表面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴を形成した。
この基板表面に設けた窓穴の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ穴明けを行った。超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去後、洗浄触媒付与、密着促進後無電解銅めっきを行い、レーザ穴内壁と銅箔表面に約２０μｍの無電解銅めっき層を形成した。この基板表面のパッドや回路パターンなど必要な箇所にエッチングレジストを形成し、不要な銅をエッチング除去して、外層回路を形成した。
この基板表面にソルダーレジストＰＳＲ−４０００ＡＵＳ５（太陽インキ製造株式会社、商品名）をロールコータで３０μｍ塗布、乾燥後に露光・現像して所望の箇所にソルダーレジスト４１１を形成した。その後、３μｍの無電解ニッケルめっきと０．１μｍの無電解金めっき（Ｎｉ−Ａｕめっき４２０）を外層回路パターン露出部表面層に形成して、コンデンサ内蔵多層配線板を得た（図２０（ｉ））。
実施例Ｄ−２
コンデンサ内蔵多層配線板用材料Ｄ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２１（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１２μｍの銅箔５ＧＴＳ−１２（古河サーキットフォイル株式会社、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２１（ｂ））。次に、この基板の両面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴４０５′を形成した（図２１（ｃ））。続いて、窓穴４０５′の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ照射してレーザ穴４０６を明け、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去した（図２１（ｄ））。さらにそのＰＺＴ薄膜４０１の表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。その後、基板両面に触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成し、さらに基板両面に電気銅めっきにより２０μｍの金属層を形成し、めっき銅４０８からなる金属層を形成した（図２１（ｅ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いてめっき銅４０８の不要部分をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜４０７をエッチング除去して、第１のコンデンサ電極４０９のパターンを形成した（図２１（ｆ））。続いて、所望のパターンのレジストを形成し、ＣＦ_４ガスを用いたＲＩＥ法によってＰＺＴ薄膜４０１とルテニウム薄膜４０３の不要部分をエッチング除去し、コンデンサ誘電体４０１′を形成した（図２１（ｇ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２、銅箔４０５及びめっき銅４０８の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２１（ｈ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２１（ｉ））。
実施例Ｄ−３
コンデンサ内蔵多層配線板用材料Ｄ−２の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２２（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、３５μｍキャリア銅箔付き厚み３μｍの銅箔５ＭＴ３５Ｍ３（三井金属鉱業株式会社製、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２２（ｂ））。次に、キャリア銅箔を手作業により剥離後、三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、基板の銅箔４０５の面に出力パワー３０ｍＪ、パルス幅１５μｓ、ショット数６回の条件でレーザ穴明けを行い、φ０．１５ｍｍのレーザ穴４０６を作製した。その後、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去した（図２２（ｃ））。さらにそのＰＺＴ薄膜４０１の表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。その後、基板両面に触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成し、さらに基板両面に電気銅めっきにより２０μｍの金属層を形成し、めっき銅４０８からなる金属層を形成した（図２２（ｄ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いてめっき銅４０８からなる金属層の不要部分をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜４０７をエッチング除去して、第１のコンデンサ電極４０９のパターンを形成した（図２２（ｅ））。続いて、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１の不要部分をエッチング除去してＰＺＴ薄膜のパターニングを行い、コンデンサ誘電体４０１′を形成した（図２２（ｆ））。続いて、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いて、露出したルテニウム薄膜４０３をエッチング除去した（図２２（ｇ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２、銅箔４０５及びめっき銅４０８の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２２（ｈ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２２（ｉ））。
実施例Ｄ−４
コンデンサ内蔵多層配線板用材料Ｃ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２３（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、３５μｍキャリア銅箔付き厚み３μｍの銅箔５ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２３（ｂ））。このプリプレグは、両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃、圧力１．５ＭＰａ、加熱加圧時間１０分の条件のホットプレスで貼り付けた後、所望の箇所にドリル穴明けを行った後、スクリーン印刷により、熱硬化性樹脂に銅粉が分散された導電性ペースト１３ＡＥ１６５０（タツタシステム・エレクトロニクス株式会社、商品名）を充填し、その後に表面のＰＥＴフィルムを剥がしたものを用いた。次に、ＰＺＴ薄膜４０１の表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成したのち、基板の両面に電気銅めっきにより２０μｍのめっき銅４０８からなる金属層を形成した（図２３（ｃ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いてめっき銅４０８からなる金属層の不要部分をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜７をエッチング除去して、第１のコンデンサ電極４０９のパターンを形成した（図２３（ｄ））。続いて、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１の不要部分をエッチング除去してＰＺＴ薄膜のパターニングを行い、コンデンサ誘電体４０１′を形成した（図２３（ｅ））。続いて、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いて、露出したルテニウム薄膜４０３をエッチング除去した（図２３（ｆ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２、銅箔４０５及びめっき銅４０８の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２３（ｇ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２３（ｈ））。
実施例Ｄ−５
コンデンサ内蔵多層配線板用材料と積層するプリプレグの穴に充填する導電性ペーストを化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社、商品名）に替えた以外は実施例Ｄ−４と同様な工程によりコンデンサ内蔵多層配線板を得た。
実施例Ｄ−６
コンデンサ内蔵多層配線板用材Ｄ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２４（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、３５μｍキャリア銅箔付き厚み３μｍの銅箔５ＭＴ３５Ｓ３（三井金属鉱業株式会社製、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２４（ｂ））。次に、キャリア銅箔を剥がした基板の銅箔４０５の表面に所望のエッチングレジストを形成し、不要な銅箔を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴４０５′を形成した（図２４（ｃ））。続いて、窓穴４０５′の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ照射してレーザ穴４０６を明け、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去した（図２４（ｄ））。さらにそのＰＺＴ薄膜４０１の表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。その後、この基板両面に触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜１９を形成した。このようにして形成した０．０５μｍのクロム薄膜４０７と０．５μｍの銅薄膜４１９とが、セミアディティブ法の下地金属層（厚さ０．１〜５μｍの金属層）を形成する。この基板の両面に所望のめっきレジスト４１４を形成し、電気銅めっきを行い、厚み２０μｍの第１のコンデンサ電極４０９及びレーザ穴４０６を含む部分の回路となるめっき銅４１５からなる導体パターンを形成した（図２４（ｅ））。めっきレジスト４１４を剥離後、基板両面の０．５μｍの銅薄膜４１９の不要部分と０．０５μｍのクロム薄膜４０７の不要部分をエッチング除去して、第１のコンデンサ電極４０９のパターンを形成した。このときに３μｍ厚の銅箔４０５もパターニングして回路を形成した（図２４（ｆ））。続いて、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１の不要部分をエッチング除去してＰＺＴ薄膜４０１のパターニングを行い、コンデンサ誘電体４０１′を形成した（図２４（ｇ））。続いて、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いて、露出したルテニウム薄膜４０３をエッチング除去した（図２４（ｈ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２４（ｉ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２４（ｊ））。
実施例Ｄ−７
コンデンサ内蔵多層配線板用材料Ｃ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２５（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、３５μｍキャリア銅箔付き厚み３μｍの銅箔５ＭＴ３５Ｍ３（三井金属鉱業株式会社製、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２５（ｂ））。キャリア銅箔を手作業により剥離後、三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー３０ｍＪ、パルス幅１５μｓ、ショット数６回の条件でレーザ穴明けを行い、φ０．１５ｍｍのレーザ穴４０６を作製した。その後、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去した（図２５（ｃ））。さらにＰＺＴ薄膜４０１の表面にＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。さらにこの基板の両面に触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜４１９を形成した。このようにして形成した０．０５μｍのクロム薄膜４０７と０．５μｍの銅薄膜４１９とが、セミアディティブ法の下地金属層（厚さ０．１〜５μｍの金属層）を形成する。この基板の表面に所望のめっきレジスト４１４を形成し、電気銅めっきを行い、厚み２０μｍの第１のコンデンサ電極４０９及びレーザ穴４０６を含む部分の回路となるめっき銅４１５からなる導体パターンを形成した（図２５（ｄ））。めっきレジスト４１４を剥離後、基板表面に露出した０．５μｍの銅薄膜４１９と０．０５μｍのクロム薄膜４０７の露出部分をエッチング除去して、第１のコンデンサ電極４０９及びレーザ穴４０６を含む部分の回路パターンを形成した。このときに３μｍ厚の銅箔４０５もパターニングして回路を形成した（図２５（ｅ））。続いて、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１をエッチング除去してＰＺＴ薄膜４０１のパターニングを行い、コンデンサ誘電体４０１′を形成した（図２５（ｆ））。その後、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いてルテニウム薄膜４０３の露出部分をエッチング除去した（図２５（ｇ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２５（ｈ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２５（ｉ））。
実施例Ｄ−８
コンデンサ内蔵多層配線板用材料Ｄ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２６（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔５ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２６（ｂ））。このプリプレグは、両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃、圧力１．５ＭＰａ、加熱加圧時間１０分の条件のホットプレスで貼り付けた後、所望の箇所にドリル穴明けを行った後、スクリーン印刷により、熱硬化性樹脂に銅粉が分散された導電性ペースト１３ＡＥ１６５０（タツタシステム・エレクトロニクス株式会社、商品名）を充填し、その後に表面のＰＥＴフィルムを剥がしたものを用いた。次に、ＰＺＴ薄膜４０１の表面にＤＣスパッタリング法により０．０５μｍのクロム薄膜４０７を形成した。その後、この基板両面に触媒付与、密着促進後、無電解銅めっきを行い、０．５μｍの銅薄膜４１９を形成した。このようにして形成した０．０５μｍのクロム薄膜４０７と０．５μｍの銅薄膜４１９とが、セミアディティブ法の下地金属層（厚さ０．１〜５μｍの金属層）を形成する。その後、基板両面に所望のめっきレジスト４１４を形成し、電気銅めっきを行い、厚み２０μｍの第１のコンデンサ電極４０９となる導体パターンを形成した（図２６（ｃ））。めっきレジスト４１４を剥離後、基板表面の露出した０．５μｍの銅薄膜４１９を塩化第二鉄水溶液でエッチング除去し、露出した０．０５μｍのクロム薄膜４０７をフェリシアン化カリウム水溶液を用いてエッチング除去して、第１のコンデンサ電極４０９のパターンを形成した（図２６（ｄ））。続いて、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１の不要部分をエッチング除去してＰＺＴ薄膜４０１のパターニングを行い、コンデンサ誘電体４０１′を形成した（図２６（ｅ））。続いて、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いて露出したルテニウム薄膜４０３をエッチング除去した（図２６（ｆ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２及び銅箔４０５の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２６（ｇ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２６（ｈ））。
実施例Ｄ−９
コンデンサ内蔵多層配線板用材料と積層するプリプレグの穴に充填する導電性ペーストを化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社、商品名）に替えた以外は実施例Ｄ−８と同様な工程によりコンデンサ内蔵多層配線板を得た。
実施例Ｄ−１０
コンデンサ内蔵多層配線板用材料Ｄ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２７（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１８μｍの銅箔５ＧＴＳ−１８（古河サーキットフォイル株式会社、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２７（ｂ））。このプリプレグは、両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃、圧力１．５ＭＰａ、加熱加圧時間１０分の条件のホットプレスで貼り付けた後、所望の箇所にドリル穴明けを行った後、スクリーン印刷により、熱硬化性樹脂に銅粉が分散された導電性ペーストＡＥ１６５０（タツタシステム・エレクトロニクス株式会社、商品名）を充填し、その後に表面のＰＥＴフィルムを剥がしたものを用いた。次に、ＰＺＴ薄膜４０１の表面の所望の箇所に、スクリーン印刷により、化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社、商品名）を４０μｍの厚みで印刷後、温度２００℃で加熱時間１時間の条件でベーキングし、導電性ペーストを金属化して、第１のコンデンサ電極４１６のパターンを形成した（図２７（ｃ））。続いて、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１の不要部分をエッチング除去してＰＺＴ薄膜のパターニングを行ってコンデンサ誘電体４０１′を形成した後、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いてルテニウム薄膜４０３の露出部分をエッチング除去した（図２７（ｄ））。次に、この基板の表面に所望のエッチングレジストを形成し、銅箔４０２及び銅箔４０５の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、第２のコンデンサ電極４１０を含む回路パターンを形成して回路板を作製した（図２７（ｅ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２７（ｆ））。
実施例Ｄ−１１
コンデンサ内蔵多層配線板用材料と積層するプリプレグの穴に充填する導電性ペーストを化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社、商品名）に替えた以外は実施例Ｄ−１０と同様な工程によりコンデンサ内蔵多層配線板を得た。
実施例Ｄ−１２
コンデンサ内蔵多層配線板用材料Ｄ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２８（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、厚み１２μｍの銅箔５ＧＴＳ−１２（古河サーキットフォイル株式会社、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を形成した（図２８（ｂ））。次に、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１をエッチング除去してＰＺＴ薄膜のパターニングを行ってコンデンサ誘電体４０１′を形成した後、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いてルテニウム薄膜４０３をエッチング除去した（図２８（ｃ））。この基板の両面に所望のエッチングレジストを形成し、銅箔４０５の不要部分を塩化第二鉄水溶液を用いてエッチング除去して、所望の箇所にφ０．１５ｍｍの窓穴４０５′を形成した（図２８（ｄ））。続いて、窓穴４０５′の箇所に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー２６ｍＪ、パルス幅１００μｓ、ショット数４回の条件でレーザ照射してレーザ穴４０６を明け、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去した（図２８（ｅ））。さらに基板のコンデンサ誘電体４０１′側の面に、ＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。その後、基板の両面に、触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成し、さらにその上に電気銅めっきにより２０μｍの金属層を形成し、めっき銅４０８からなる金属層を形成した（図２８（ｆ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いてめっき銅４０８及び銅箔４０５の不要部分をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜４０７をエッチング除去し、さらに塩化第二鉄水溶液を用いて露出した銅箔４０２をエッチング除去して、第１のコンデンサ電極４０９と第２のコンデンサ電極４１０を含む回路パターンを形成した（図２８（ｇ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２８（ｈ））。
実施例Ｄ−１３
コンデンサ内蔵多層配線板用材料Ｄ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図２９（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、３５μｍキャリア銅箔付き厚み３μｍの銅箔５ＭＴ３５Ｍ３（三井金属鉱業株式会社製、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化して基板を得た（図２９（ｂ））。次に、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１をエッチング除去してＰＺＴ薄膜のパターニングを行ってコンデンサ誘電体４０１′を形成した後、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いてルテニウム薄膜４０３の露出部分をエッチング除去した（図２９（ｃ））。キャリア銅箔を手作業により剥離後、銅箔４０５の所定の表面に三菱電機株式会社製ＭＬ５０５ＧＴ型炭酸ガスレーザを用いて、出力パワー３０ｍＪ、パルス幅１５μｓ、ショット数６回の条件でレーザ照射し、φ０．１５ｍｍのレーザ穴４０６を作製した。その後、超音波洗浄とアルカリ過マンガン酸液で炭化した樹脂カスを除去した（図２９（ｄ））。さらにその基板のコンデンサ誘電体４０１′を形成した面上に、ＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。その後、基板両面に触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成し、さらにその上に電気銅めっきにより２０μｍの金属層を形成し、めっき銅４０８からなる金属層を形成した（図２９（ｅ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いてめっき銅４０８及び銅箔４０５の不要部分をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜４０７をエッチング除去し、さらに塩化第二鉄水溶液を用いて露出した銅箔４０２をエッチング除去して、第１のコンデンサ電極４０９と第２のコンデンサ電極４１０を含む回路パターンを形成した（図２９（ｆ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図２９（ｇ））。
実施例Ｄ−１４
コンデンサ内蔵多層配線板用材料Ｄ−３の銅箔４０２の表面に、多層化接着前処理として、有機酸系マイクロエッチング剤ＣＺ−８１００Ｂ（メック株式会社製、商品名）による粗化処理を行った（図３０（ａ））。このコンデンサ内蔵多層配線板用材料の銅箔４０２の表面に、絶縁樹脂基材４０４となる厚み１００μｍのガラスエポキシプリプレグＧＥＡ−６７９Ｆ（日立化成工業株式会社製、商品名）を介して、３５μｍキャリア銅箔付き厚み３μｍの銅箔５ＭＴ３５５３（三井鉱山株式会社、商品名）を配し、温度１８０℃、圧力１．５ＭＰａ、加熱加圧時間６０分のプレス条件で積層一体化し、基板を得た（図３０（ｂ））。このプリプレグは、両面に厚み２５μｍのポリエチレンテレフタレート（ＰＥＴ）のフィルムを温度１００℃、圧力１．５ＭＰａ、加熱加圧時間１０分の条件のホットプレスで貼り付けた後、所望の箇所にドリル穴明けを行った後、スクリーン印刷により、熱硬化性樹脂に銅粉が分散された導電性ペーストＡＥ１６５０（タツタシステム・エレクトロニクス株式会社、商品名）を充填し、その後に表面のＰＥＴフィルムを剥がしたものを用いた。
次に、所望のパターンのレジストを形成し、２０％重フッ化アンモニウム（ＮＨ_４Ｆ・ＨＦ）水溶液を用いてＰＺＴ薄膜４０１をエッチング除去してＰＺＴ薄膜のパターニングを行ってコンデンサ誘電体４０１′を形成した後、ルテニウムエッチング液ＲＥＣ−０１（関東化学株式会社、商品名）を用いてルテニウム薄膜４０３の露出部分をエッチング除去した（図３０（ｃ））。さらに基板のコンデンサ誘電体４０１′の面側に、ＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成したのち、触媒付与、密着促進後無電解銅めっきを行い、０．５μｍの銅薄膜を形成した。さらに基板両面に電気銅めっきにより２０μｍのめっき銅４０８からなる金属層を形成した（図３０（ｄ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いてめっき銅４０８及び銅箔４０５の不要部分をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜７をエッチング除去し、さらに塩化第二鉄水溶液を用いて露出した銅箔４０２エッチング除去して、第１のコンデンサ電極４０９と第２のコンデンサ電極４１０を含む回路パターンを形成した（図３０（ｅ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図３０（ｆ））。
実施例Ｄ−１５
コンデンサ内蔵多層配線板用材料と積層するプリプレグの穴に充填する導電性ペーストを化学的な反応により金属化される導電性ペーストであるナノペースト（ハリマ化成株式会社、商品名）に替えた以外は実施例Ｄ−１４と同様な工程によりコンデンサ内蔵多層配線板を得た。
比較例Ｄ−１
両面の回路パターンを接続する導体穴（穴内は穴うめ樹脂４１８にて充填されている）を有する板厚０．２ｍｍの両面回路基板（図３１（ａ））を用意した。この基板の片面に、ＤＣスパッタリング法により、０．２μｍのルテニウム薄膜４０３を形成した。所望のパターンのレジストを形成し、ＲＩＥ法によって、回路上以外のルテニウム薄膜４０３をエッチング除去し、第２のコンデンサ電極４２１を含む回路パターンを形成した（図３１（ｂ））。さらにその基板表面に強誘電体薄膜形成材料ＰＺＴ（関東化学株式会社、商品名）を塗布し、温度１５０℃で加熱時間３０分間のプリベークを行った。塗布とプリベークをさらに５回繰り返し、その後に温度２５０℃で加熱時間１時間の熱処理を行って、厚さ０．５μｍのＰＺＴ薄膜４０１を形成した（図３１（ｃ））。さらにそのＰＺＴ薄膜４０１の表面に、ＤＣスパッタリング法により、０．０５μｍのクロム薄膜４０７を形成した。さらにその表面に電気銅めっきにより２０μｍのめっき銅４０８からなる金属層を形成した（図３１（ｄ））。この基板の表面に所望のエッチングレジストを形成し、塩化第二鉄水溶液を用いてめっき銅４０８の不要部分をエッチング除去し、フェリシアン化カリウム水溶液を用いて露出したクロム薄膜４０７をエッチング除去して、第１のコンデンサ電極４２２のパターンを形成して回路板を作製した（図３１（ｅ））。その後の多層配線板の加工は実施例Ｄ−１と同様な工程によりコンデンサ内蔵多層配線板を得た（図３１（ｆ））。
実施例Ｄ−１〜Ｄ−１５および比較例Ｄ−１で得られたコンデンサ内蔵多層配線板について、誘電体の膜厚、比誘電率およびコンデンサ容量を測定した。各測定方法は前記と同様である。以下の表４に測定結果を示す。

実施例Ｄ−１〜Ｄ−１５は、いずれも、金属箔の表面に比誘電率が１０〜２０００でかつ膜厚が０．０５〜２μｍの誘電体薄膜が設けられたことを特徴とするコンデンサ内蔵多層配線板用材料を用いて作製したコンデンサ内蔵基板である。作製したコンデンサ容量のばらつきは全て±１０％未満であり、均一で良好なコンデンサを作製することができた。
また、比較例は、誘電体薄膜を金属層がパターニングされた基板の表面に形成されたコンデンサ内蔵基板であるために、膜厚のばらつきが大きく、結果としてコンデンサ容量のばらつきも最大５４％と大きかった。
前述したところがこの発明の好ましい実施態様であること、多くの変更および修正をこの発明の精神と範囲にそむくことなくなく実行できることは当業者にとって了解されよう。Example A-5
The method of etching and removing the PZT thin film and the ruthenium thin film using the capacitor built-in multilayer wiring board material A-3 is not the RIE method, but 20% ammonium bifluoride (NH ₄ F.HF) A multilayer wiring board with a built-in capacitor is obtained by the same process as in Example A-1, except that an aqueous solution and a ruthenium thin film are etched using a ruthenium etching solution REC-01 (Kanto Chemical Co., Ltd., trade name). (FIG. 2 (i)).
Example A-6
The surface of the copper foil 102 of the capacitor built-in multilayer wiring board material A-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pre-treatment for multilayering adhesion ( FIG. 5 (a)). Using a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) with a plate thickness of 0.2 mm as a base material, conductor connection holes and circuit patterns are produced at desired locations. The double-sided substrate 104 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment, and then the insulating resin base material 107 on one surface thereof. As a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm, a copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd., product name) having a thickness of 18 μm is provided on the other surface. As the insulating resin base material 107, a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm is used. Arranged capacitor built multilayer wiring board materials, temperature 170 ° C., pressure 1.5 MPa, and laminated and integrated with press conditions of heat pressing time 60 min (Figure 5 (b)). Here, 105 is plated copper, and 106 is hole filling resin. Subsequently, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ F / HF) aqueous solution was used to etch away the PZT thin film, and ruthenium thin film was etched away using ruthenium etchant REC-01 (trade name) (FIG. 5) to pattern the PZT thin film (FIG. 5). (C)). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary copper foil is removed by etching using an aqueous ferric chloride solution to form a φ0.1 mm window hole at a desired location. Using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation, laser drilling 110 was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (FIG. 5D). After removing the resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution, a 0.05 μm chromium thin film 108 was formed by DC sputtering. Further, a 20 μm-thick metal layer 109 was formed on the surface by electrolytic copper plating (FIG. 5E). At this time, a copper metal layer was formed on the surface of the thin film dielectric layer and in the laser hole. A desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer is etched away using an aqueous ferric chloride solution, and a chromium metal layer is etched away using an aqueous potassium ferricyanide solution. The circuit board was produced by forming the capacitor electrode, the second capacitor electrode, and other wiring patterns (FIG. 5F). Subsequent processing of the multilayer wiring board was performed in the same process as in Example A-1 to obtain a multilayer wiring board with a built-in capacitor (FIG. 5G). Here, 112 is an insulating resin base material, and 113 is a solder resist.
Example A-7
The copper foil surface 102 of the multilayer wiring board material A-3 with a built-in capacitor was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment ( FIG. 6 (a)). Using a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) with a plate thickness of 0.2 mm as a base material, conductor connection holes and circuit patterns are produced at desired locations. The double-sided substrate 104 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment, and then the insulating resin base material 107 on one surface thereof. As a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm, a copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd., product name) having a thickness of 18 μm is provided on the other surface. As the insulating resin base material 107, a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm is used. Arranged capacitor built multilayer wiring board materials, temperature 170 ° C., pressure 1.5 MPa, and laminated and integrated in the press for 60 minutes between heated pressing time (Figure 6 (b)). Here, 105 is plated copper, and 106 is hole filling resin. In this prepreg, a polyethylene terephthalate (PET) film having a thickness of 25 μm is pasted on both sides with a hot press at a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes, and then drilled at a desired location. After performing the above, a copper paste NF2000 (Tatsuta System Electronics Co., Ltd., trade name) 116 was filled by screen printing, and then the surface PET film was peeled off. A 0.05 μm chromium thin film 108 was formed on the surface of the PZT thin film of this substrate by DC sputtering. Further, a 20 μm-thick metal layer 109 was formed on the surface by electrolytic copper plating (FIG. 6C). A desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer is etched away using an aqueous ferric chloride solution, and a chromium metal layer is etched away using an aqueous potassium ferricyanide solution. A capacitor electrode pattern was formed (FIG. 6D). Subsequently, a resist having a desired pattern is formed and CF ₄ The PZT thin film and the ruthenium thin film were removed by etching by RIE using gas (FIG. 6E). Next, a desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer is removed by etching with a ferric chloride solution, a circuit pattern including a second capacitor electrode is formed, and a circuit board is formed. It produced (FIG.6 (f)). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example A-1 (FIG. 6G). Here, 112 is an insulating resin base material, and 113 is a solder resist.
Example A-8
The copper foil surface 102 of the multilayer wiring board material A-3 with a built-in capacitor was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment ( FIG. 7 (a)). Using a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) with a plate thickness of 0.2 mm as a base material, conductor connection holes and circuit patterns are produced at desired locations. The double-sided substrate 104 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment, and then the insulating resin base material 107 on one surface thereof. As a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm, a copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd., product name) having a thickness of 18 μm is provided on the other surface. As the insulating resin base material 107, a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm is used. Arranged capacitor built multilayer wiring board materials, temperature 200 ° C., pressure 1.5 MPa, and laminated and integrated in the press for 60 minutes between heated pressing time (FIG. 7 (b)). Reference numeral 105 denotes plated copper, and 106 denotes hole filling resin. In this prepreg, a polyethylene terephthalate (PET) film having a thickness of 25 μm is pasted on both sides with a hot press at a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes, and then drilled at a desired location. After performing the above, a nano paste (Harima Kasei Co., Ltd., trade name) which is a conductive paste 117 that is metallized by a chemical reaction is filled by screen printing, and then the PET film on the surface is peeled off. Using. Subsequent processing of the capacitor and processing of the multilayer wiring board were performed in the same process as in Example A-1, and a multilayer wiring board with a built-in capacitor was obtained (FIG. 7C). In addition, 112 may be an insulating resin base material and 113 may be a solder resist.
Comparative Example A-1
A glass epoxy prepreg GEA-679F (Hitachi Chemical Industry Co., Ltd.) having a thickness of 100 μm, based on a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 0.2 mm. A 0.2 μm ruthenium thin film was formed by DC sputtering on the surface of a four-layer substrate in which connection holes and circuit patterns made into conductors were formed at desired locations (FIG. 8A). ). Here, 102 is a copper foil, 105 is plated copper, 106 is a hole-filling resin, and 107 is an insulating resin substrate. A resist having a desired pattern is formed, the ruthenium thin film 103 is etched away by RIE, and then the copper metal layer on the inner substrate surface is etched away using an aqueous ferric chloride solution, thereby including a circuit including the second capacitor electrode. A pattern was formed (FIG. 8B). Further, a ferroelectric thin film forming material PZT (Kanto Chemical Co., Ltd., trade name) was applied to the surface of the substrate, and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, and then a heat treatment was performed at a temperature of 250 ° C. for 1 hour to form a PZT thin film 101 having a thickness of 0.5 μm (FIG. 8C). Further, a 0.05 μm chromium thin film was formed on the surface of the PZT thin film by DC sputtering. Further, a 20 μm metal layer 109 was formed on the surface by electrolytic copper plating (FIG. 8D). A desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer is etched away using an aqueous ferric chloride solution, and a chromium metal layer is etched away using an aqueous potassium ferricyanide solution. A circuit board was prepared by forming a capacitor electrode pattern (FIG. 8E). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example A-1 (FIG. 8F). Here, 112 is an insulating resin base material, and 113 is a solder resist.
The test method is as follows.
(Dielectric film thickness)
The thickness of the dielectric is determined by cutting the capacitor on which the electrode is formed with a Focused Ion Beam system (FIB: FB-2000A, manufactured by Hitachi, Ltd., trade name), and performing a cross-sectional observation using a scanning electron microscope. The average of the five points of the distance between the electrodes sandwiching the membrane was taken.
(Relative permittivity)
The relative dielectric constant was obtained by measuring at a frequency of 1 MHz according to IPC-650 2.5.5.2 under an environment where the temperature was controlled at 25 ° C.
(Capacitor capacity)
Capacitor capacity is high-frequency signal measurement probe MICROPROBE ACP50 (GSG250, Cascade, product) via 50Ω coaxial cable SUCOFLEX104 / 100 (product name, SUHNER) on impedance analyzer 4291B (product name, manufactured by Agilent Technologies) Name) was used. The electrode size of the capacitor was 1 mm □, and the capacity of 1 GHz was measured. The number of measurement samples was 5.

Examples A-1 to A-8 are all characterized in that a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil. This is a capacitor built-in board manufactured using a built-in multilayer wiring board material. Variations in the capacitance of the produced capacitors were all less than ± 10%, and uniform and good capacitors could be produced.
Further, Comparative Example A-1 is a capacitor built-in substrate in which the dielectric thin film is formed on the surface of the substrate on which the metal layer is patterned. Therefore, the variation in the film thickness is large, and as a result, the variation in the capacitor capacity is 54 at the maximum. It was as big as%.
According to the above embodiment, according to the present invention, a multilayer wiring board having a capacitor having a relative dielectric constant of 20 to 2000, a film thickness of 0.1 to 1 μm, and a capacitor having a small variation in capacitance. Can be provided.
(Example B)
Inner layer substrate B-1
Desired drilling (diameter 200 μm) was performed on a double-sided copper foil-clad glass epoxy laminate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a copper foil thickness of 3 μm and a plate thickness of 0.2 mm. Then, after removing carbonized resin residue by ultrasonic cleaning and alkali permanganate solution on this substrate, after applying the catalyst and promoting adhesion, electroless copper plating is performed, and the inner wall of the drill hole and the copper foil surface are approximately A 15 μm electroless copper plating layer 204 was formed. The resulting substrate surface was roughened by a blackening treatment containing sodium hypochlorite as a main component and a reduction treatment containing dimethylaminoborane as a main component. Then, a paste type thermosetting insulating material HRP-700BA (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) is filled as the hole filling resin 203 by screen printing in the drill hole of this substrate, and cured by heat treatment at 170 ° C. for 60 minutes. I let you. The substrate was polished with a buff brush to remove excess insulating material. After applying the catalyst to this substrate and promoting adhesion, electroless copper plating is performed to form an electroless copper plating layer of about 15 μm on the substrate surface, and there are via holes connecting the conductor layers inside the substrate, and the surface is smooth. A substrate having a metal layer was prepared. The surface roughness of the metal layer on the substrate surface determined from the image observed using a scanning electron microscope was 0.3 μm. A cross-sectional view of the produced inner layer substrate is shown in FIG. Reference numeral 202 denotes an insulating resin base material, and 201 denotes a copper foil.
Inner layer substrate B-2
A 200 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) is coated with a 25 μm thick polyethylene terephthalate (PET) film at a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes. Affixed with hot press conditions. After drilling a desired drill hole (diameter 200 μm) in this prepreg, copper paste NF2000 (trade name, manufactured by Tatsuta System Electronics Co., Ltd.) 205 was filled by screen printing. The PET film on the surface is peeled off and sandwiched from both sides with 18 μm thick copper foil GTS-18 (trade name, manufactured by Furukawa Circuit Foil Co., Ltd.) under the press conditions of temperature 170 ° C., pressure 1.5 MPa, and heating and pressing time 60 minutes. A substrate that was laminated and integrated, had via holes connecting the conductor layers inside the substrate, and had a smooth metal layer on the surface was produced. The surface roughness of the metal layer on the substrate surface determined from the image observed using a scanning electron microscope was 0.2 μm. A cross-sectional view of the produced inner layer substrate is shown in FIG.
Inner layer substrate B-3
A 200 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) is coated with a 25 μm thick polyethylene terephthalate (PET) film at a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes. Affixed with hot press conditions. After drilling the desired prepreg (diameter: 200 μm), it is filled with nano paste (trade name, manufactured by Harima Kasei Co., Ltd.) 206, which is a conductive paste that is metalized by chemical reaction by screen printing. did. The PET film on the surface is peeled off, sandwiched from both sides with 18 μm thick copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd., trade name), and laminated under press conditions of temperature 170 ° C., pressure 1.5 MPa, and heating and pressing time 60 minutes. A substrate having a via hole connecting the conductor layers inside the substrate and having a smooth metal layer on the surface was produced. The surface roughness of the metal layer on the substrate surface determined from the image observed using a scanning electron microscope was 0.2 μm. A cross-sectional view of the produced inner layer substrate is shown in FIG.
Example B-1
A 0.2 μm-thick ruthenium thin film 207 was formed on the substrate surface of the inner layer substrate B-1 by DC sputtering (FIG. 12A). Furthermore, by the microwave plasma CVD using titanium tetraisopropoxide, zircon tetratertiary butoxide, dipivaloylmethane lead complex, and nitrogen dioxide on the substrate surface, the thickness of 0.5 μm is obtained under the condition of the substrate temperature of 250 ° C. A PZT (lead zirconate titanate) thin film 208 was formed (FIG. 12B). Further, a 0.05 μm chromium thin film 209 was formed on the surface of the PZT thin film by DC sputtering. Further, a 20 μm metal layer 210 was formed on the surface by electrolytic copper plating (FIG. 12C). A desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer 210 is etched away using an aqueous ferric chloride solution, and a chromium metal layer 209 is etched away using an aqueous potassium ferricyanide solution. A pattern of the first capacitor electrode 217 was formed (FIG. 12D). Subsequently, a resist having a desired pattern is formed and CF ₄ The PZT thin film 208 and the ruthenium thin film 207 were removed by etching by RIE using gas (FIG. 12E). Next, a desired etching resist is further formed, an unnecessary copper metal layer is removed by etching with a ferric chloride solution, and a circuit pattern including a second capacitor electrode 218 is formed to form a capacitor built-in multilayer wiring board. An inner layer plate 219 to be used was produced (FIG. 12 (f)).
A roughening process was performed on the circuit surface of the inner layer plate by a blackening process mainly including sodium hypochlorite and a reduction process mainly including dimethylaminoborane. (1) Copper foil MT35S3 having a thickness of 3 μm with 35 μm carrier copper foil (trade name) manufactured by Mitsui Metal Mining Co., Ltd., (2) Glass epoxy prepreg GEA-679F with a filler having a thickness of 100 μm as insulating resin base material 211 (Hitachi Chemical Industries) (3) Inner layer plate 219, (4) Glass epoxy prepreg GEA-679F with filler of 100 μm thickness as insulating resin substrate 211, (5) Copper foil MT35S3 with thickness of 3 μm with 35 μm carrier copper foil (Mitsui Metal Mining Co., Ltd., trade name) was stacked in this order, and the layers were integrated under press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. After peeling off the carrier copper foil and cutting off the unnecessary edge of the substrate, a desired etching resist is formed on the surface of this substrate, the unnecessary copper foil is etched away, and a window hole with a diameter of 0.15 mm is formed at the desired location. Formed.
Laser drilling was performed at a window hole provided on the surface of the substrate using an ML505GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation under conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of four. After removing the resin residue carbonized with ultrasonic cleaning and alkaline permanganate solution, washing, applying catalyst, promoting adhesion, and then electroless copper plating, and an electroless copper plating layer of about 20 μm on the inner wall of the laser hole and the copper foil surface Formed. Etching resist was formed on necessary portions such as pads and circuit patterns on the surface of the substrate, and unnecessary copper was removed by etching to form the outer layer circuit 213.
Solder resist PSR-4000 AUS5 (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name) was applied to the substrate surface with a roll coater at 30 μm, dried, exposed and developed to form a solder resist 212 at a desired location. Thereafter, 3 μm electroless nickel plating and 0.1 μm electroless gold plating were formed on the surface layer of the exposed portion of the outer circuit pattern to obtain a capacitor built-in multilayer wiring board 220 (FIG. 4G).
Example B-2
A multilayer wiring board with a built-in capacitor was obtained by the same process as in Example B-1, except that the inner layer substrate B-1 was changed to the inner layer substrate B-2.
Example B-3
A multilayer wiring board with a built-in capacitor was obtained by the same process as in Example B-1, except that the inner layer substrate B-1 was changed to the inner layer substrate B-3.
Example B-4
A 0.2 μm-thick ruthenium thin film 207 was formed on the substrate surface of the inner layer substrate B-1 by DC sputtering (FIG. 12A). Further, a ferroelectric thin film forming material PZT (trade name, manufactured by Kanto Chemical Co., Inc.) was applied to the surface of the substrate, and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, followed by heat treatment at a temperature of 250 ° C. for 1 hour to form a PZT thin film 208 having a thickness of 0.5 μm (FIG. 12B). Subsequent processing of the capacitor and processing of the multilayer wiring board were performed in the same process as in Example B-1, and a multilayer wiring board with a built-in capacitor was obtained (FIG. 12 (g)).
Example B-5
The method of etching and removing the PZT thin film 208 and the ruthenium thin film 207 is not the RIE method, but 20 wt% ammonium bifluoride (NH ₄ F.HF) A multilayer wiring board with a built-in capacitor was manufactured by the same process as Example B-4, except that ruthenium etching solution REC-01 (trade name, manufactured by Kanto Chemical Co., Ltd.) was etched on the aqueous solution and ruthenium thin film. Obtained (FIG. 12 (g)).
Example B-6
A 0.2 μm-thick ruthenium thin film 207 was formed on the substrate surface of the inner layer substrate B-1 by DC sputtering (FIG. 13A). Further, a ferroelectric thin film forming material PZT (trade name, manufactured by Kanto Chemical Co., Inc.) was applied to the surface of the substrate, and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, and then a heat treatment was performed at a temperature of 250 ° C. for 1 hour to form a PZT thin film 208 having a thickness of 0.5 μm (FIG. 13B). Further, a 0.05 μm chromium thin film 209 was formed on the surface of the PZT thin film by DC sputtering. Further, the surface was washed, provided with a catalyst, and after adhesion was promoted, electroless copper plating was performed to form a 0.5 μm copper thin film.
A desired plating resist 215 was formed on the surface of the substrate, and electrolytic copper plating was performed to form a metal layer 214 serving as a first capacitor electrode having a thickness of 20 μm (FIG. 13C). After stripping the plating resist 215, the 0.5 μm copper thin film and the 0.05 μm chromium thin film on the substrate surface were removed by etching to form a pattern of the first capacitor electrode 217 (FIG. 13D). Subsequently, a resist having a desired pattern is formed, and 20 wt% ammonium bifluoride (NH ₄ The PZT thin film 208 was removed by etching using an F / HF solution, and the ruthenium thin film 207 was removed by etching using a ruthenium etching solution REC-01 (trade name, manufactured by Kanto Chemical Co., Ltd.) (FIG. 13E). Next, a desired etching resist was further formed, an unnecessary copper metal layer was removed by etching with a ferric chloride solution, and a circuit pattern including a second capacitor electrode 218 was formed to produce an inner layer plate 219. (FIG. 13 (f)). Subsequent processing of the multilayer wiring board obtained the capacitor built-in multilayer wiring board 220 by the same process as in Example B-1 (FIG. 13G).
Example B-7
A 0.2 μm-thick ruthenium thin film 207 was formed on the substrate surface of the inner layer substrate B-1 by DC sputtering (FIG. 14A). Further, a ferroelectric thin film forming material PZT (trade name, manufactured by Kanto Chemical Co., Inc.) was applied to the surface of the substrate, and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, and then a heat treatment was performed at a temperature of 250 ° C. for 1 hour to form a PZT thin film 208 having a thickness of 0.5 μm (FIG. 14B). Furthermore, after printing nano paste (made by Harima Kasei Co., Ltd., trade name) 216 having a thickness of 40 μm on a desired portion of the surface of the PZT thin film by screen printing, a metal paste by chemical reaction is printed at a temperature of 40 μm. Baking was performed at 200 ° C. for 1 hour, and the conductive paste was metallized to form a pattern of the first capacitor electrode 217 (FIG. 14C). Subsequently, a resist having a desired pattern is formed, and 20 wt% ammonium bifluoride (NH ₄ F / HF) aqueous solution was used to etch away the PZT thin film, and ruthenium thin film was etched away using ruthenium etchant REC-01 (trade name, manufactured by Kanto Chemical Co., Ltd.) (FIG. 14D). Next, a desired etching resist was further formed, an unnecessary copper metal layer was removed by etching with a ferric chloride solution, and a circuit pattern including a second capacitor electrode 218 was formed to produce an inner layer plate 219. (FIG. 14 (e)). Subsequent processing of the multilayer wiring board resulted in a capacitor built-in multilayer wiring board 220 by the same process as in Example B-1 (FIG. 14F).
Example B-8
A 0.2 μm-thick ruthenium thin film 207 was formed on the substrate surface of the inner layer substrate B-1 by DC sputtering (FIG. 15A). Further, a ferroelectric thin film forming material PZT (trade name, manufactured by Kanto Chemical Co., Inc.) was applied to the surface of the substrate, and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, and then a heat treatment was performed at a temperature of 250 ° C. for 1 hour to form a PZT thin film 208 having a thickness of 0.5 μm (FIG. 15B). Subsequently, a resist having a desired pattern is formed, and 20 wt% ammonium bifluoride (NH ₄ F / HF) aqueous solution was used to etch away PZT thin film 208, and ruthenium thin film was etched away using ruthenium etchant REC-01 (trade name, manufactured by Kanto Chemical Co., Ltd.) to pattern PZT thin film ( FIG. 15 (c)). A 0.05 μm chromium thin film 209 was formed on the surface of the PZT thin film by DC sputtering. Further, a 20 μm metal layer 210 was formed on the surface by electrolytic copper plating (FIG. 15D). A desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer is etched away using an aqueous ferric chloride solution, and a chromium metal layer is etched away using an aqueous potassium ferricyanide solution. The inner electrode 219 was formed by forming the capacitor electrode 217, the second capacitor electrode 218, and other wiring patterns (FIG. 15E). Subsequent processing of the multilayer wiring board resulted in a capacitor built-in multilayer wiring board 220 by the same process as in Example B-1 (FIG. 15F).
Comparative Example B-1
A 0.2 μm-thick ruthenium thin film 207 was formed on the substrate surface of the inner layer substrate B-1 by DC sputtering (FIG. 16A). A resist having a desired pattern is formed, the ruthenium thin film 207 is etched away by RIE, and then the copper metal layer on the inner substrate surface is etched away using an aqueous ferric chloride solution to include the second capacitor electrode 218. A circuit pattern was formed (FIG. 16B). Further, a ferroelectric thin film forming material PZT (trade name, manufactured by Kanto Chemical Co., Inc.) was applied to the surface of the substrate, and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, followed by heat treatment at a temperature of 250 ° C. for 1 hour to form a PZT thin film 208 having a thickness of 0.5 μm (FIG. 16C). Further, a 0.05 μm chromium thin film 209 was formed on the surface of the PZT thin film by DC sputtering. Further, a 20 μm metal layer 210 was formed on the surface by electrolytic copper plating (FIG. 16D). A desired etching resist is formed on the surface of the substrate, an unnecessary copper metal layer is etched away using an aqueous ferric chloride solution, and a chromium metal layer is etched away using an aqueous potassium ferricyanide solution. The pattern of the capacitor electrode 217 was formed to produce an inner layer plate 219 (FIG. 16E). Subsequent processing of the multilayer wiring board yielded a capacitor built-in multilayer wiring board 220 by the same process as in Example B-1 (FIG. 16F).
The capacitor built-in multilayer wiring board obtained above was tested for dielectric film thickness, non-dielectric constant, and capacitor capacity. The test method is the same as above.
These measurement results are summarized in Table 2.

In each of Examples B-1 to B-8, the relative permittivity is 10 to 2000 on the surface of the substrate having via holes connecting the conductor layers inside the substrate and having a smooth metal layer on the surface. This is a capacitor built-in substrate produced by forming a dielectric thin film having a film thickness of 0.05 to 2 μm. Variations in the capacitance of the produced capacitors were all less than ± 10%, and uniform and good capacitors could be produced.
Further, since Comparative Example B-1 is a capacitor built-in substrate in which the dielectric thin film is formed on the surface of the substrate on which the metal layer is patterned, the variation in the film thickness is large, and as a result, the variation in the capacitance of the capacitor is 54 at the maximum. It was as big as%.
According to the above embodiment, it is possible to provide a multilayer wiring board with a built-in capacitor in which a capacitor with a uniform film thickness and a small capacitance variation is built-in.
(Experiment C)
Capacitor built-in multilayer wiring board material C-1
A ruthenium thin film 103 having a thickness of 0.2 μm was formed on the surface of a rolled copper foil M-BNH-18 (product name, manufactured by Mitsui Metal Mining Co., Ltd.) 102 having a thickness of 35 μm by a DC sputtering method. Further, a ferroelectric thin film forming material PZT (Kanto Chemical Co., Ltd., trade name) was applied to the surface and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, followed by heat treatment at a temperature of 350 ° C. for 1 hour to form a PZT thin film 101 having a thickness of 0.5 μm. In this way, a capacitor built-in multilayer wiring board material C-1 in which a PZT thin film 101 (dielectric thin film) was provided on one surface of a copper foil 2 (metal foil) 102 via a ruthenium thin film 103 was produced (FIG. 1). reference). The relative dielectric constant of the PZT thin film thus obtained was 100.
Capacitor built-in multilayer wiring board material C-2
A ruthenium thin film 103 having a thickness of 0.2 μm was formed on the surface of a rolled copper foil M-BNH-18 (product name, manufactured by Mitsui Metal Mining Co., Ltd.) 102 having a thickness of 35 μm by a DC sputtering method. Furthermore, the surface of the substrate is 0.5 μm thick under the condition of a substrate temperature of 350 ° C. by microwave plasma CVD using titanium tetraisopropoxide, zircon tetratertiary butoxide, dipivaloylmethane lead complex, and nitrogen dioxide. A PZT (lead zirconate titanate) thin film 101 was formed, and a capacitor built-in multilayer wiring board material C-2 was obtained. The relative dielectric constant of the PZT thin film thus obtained was 70.
Thin film etchant 1
Ethylenediaminetetraacetic acid disodium salt (EDTA 2Na), hydrogen peroxide (H ₂ O ₂ ), Water, EDTA · 2Na 0.1 mol / l, H ₂ O ₂ An aqueous solution having a pH of 4.0 containing 30 wt% as a component was prepared.
Thin film etchant 2
Iminodiacetic acid (IDA), H ₂ O ₂ , Water is mixed, IDA 0.1 mol / l, H ₂ O ₂ An aqueous solution having a pH of 2.0 containing 30 wt% as a component was prepared.
Thin film etchant 3
Ethylenediaminetetraacetic acid / disodium salt (EDTA · 2Na), H ₂ O ₂ , Water, EDTA · 2Na 0.01 mol / l, H ₂ O ₂ An aqueous solution having a pH of 4.2 containing 10 wt% as a component was prepared.
Thin film etchant 4
Phosphoric acid, H ₂ O ₂ , Water mixed, phosphoric acid 30wt%, H ₂ O ₂ An aqueous solution containing 20 wt% as a component was prepared.
Thin film etchant 5
Sulfuric acid, H ₂ O ₂ , Water mixed, sulfuric acid 5wt%, H ₂ O ₂ An aqueous solution containing 10 wt% as a component was prepared.
Experimental Example C-1
The copper foil surface of the capacitor-embedded multilayer wiring board material C-1 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment. In FIG. 17, the copper foil is shown as 303, the ruthenium thin film is shown as 302, and the PZT thin film 301 is shown. A copper foil 5GTS-18 (thickness 18 μm) is passed through a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness 100 μm to be an insulating resin base material 304 (insulating material) on the surface of the copper foil 303. Furukawa Circuit Foil Co., Ltd., trade name) 305 was disposed, and integrated and laminated under press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a heating and pressurizing time of 60 minutes (see FIG. 17A). Further, a 0.05 μm chromium film 306 was formed on the surface of the PZT thin film 301 by DC sputtering. Next, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper foil 305 of the substrate, a desired negative pattern is exposed and developed with an aqueous sodium carbonate solution, and an etching resist. Formed. Next, unnecessary copper foil was removed by etching with a ferric chloride aqueous solution to form a φ0.1 mm window hole 307 at a desired location, and the resist was peeled off with a sodium hydroxide aqueous solution (FIG. 2B). )reference). Subsequently, laser drilling 308 was performed at the location of the window hole 307 under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 using an ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation (see FIG. 17C). ). Then, the resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution was removed, and after applying the catalyst and promoting adhesion, electroless copper plating was performed to form a 0.5 μm copper thin film on the surface of the substrate. Further, electrolytic copper plating was performed on the surface of the substrate to form a metal layer made of plated copper 309 for electrically connecting the inner circuit conductor and the conductive layer on the substrate surface (see FIG. 17D). Subsequently, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a film thickness of 30 μm is laminated on the surface of the substrate, a desired negative pattern is exposed, developed with an aqueous sodium carbonate solution, and an etching resist. Formed. Further, after removing unnecessary plated copper 309 by etching using ferric chloride aqueous solution, the resist is stripped by using sodium hydroxide aqueous solution, and chromium film 306 is removed by etching using potassium ferricyanide aqueous solution. A pattern of the capacitor electrode (metal layer) 310 was formed (see FIG. 18A). Next, a dry film resist H-9040 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a film thickness of 40 μm to be the etching resist 311 is laminated on the first capacitor electrode 310 side of the substrate (see FIG. 18B). ), A desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist 311 on the first capacitor electrode 310 (see FIG. 18C). Subsequently, the PZT thin film 301 is etched away at 20 ° C. using a thin film etchant (1), and the ruthenium thin film 302 is etched away using a ruthenium etching solution REC-01 (trade name, manufactured by Kanto Chemical Co., Ltd.) The etching resist 311 was peeled off with an aqueous sodium hydroxide solution (see FIG. 18D) (see FIG. 18E). A dry film resist H-9040 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on this substrate, and a desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Subsequently, the unnecessary copper foil 303, the unnecessary copper foil 305 and the plated copper 309 thereon are removed by etching with a ferric chloride aqueous solution, and then the resist is peeled off with a sodium hydroxide aqueous solution to form the copper foil 303. A circuit pattern including the second capacitor electrode 312 was formed to produce a circuit board (see FIG. 19A).
The circuit surface of this circuit board was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (1) 35 μm thick copper foil MT35S3 (trade name) manufactured by Mitsui Mining & Smelting Co., Ltd., with copper foil 35 μm carrier, (2) 100 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) ), (3) Circuit board, (4) Filled glass epoxy prepreg GEA-679F with a thickness of 100 μm, (5) 3 μm thick copper foil MT35S3 with 35 μm carrier copper foil (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) The copper foil 314 was laminated | stacked through the insulating resin base material 313 on both surfaces of the circuit board by carrying out lamination | stacking and integration by the press conditions of temperature 170 degreeC, pressure 1.5MPa, and heating and pressurization time 60 minutes. After peeling off the carrier copper foil and cutting off the unnecessary substrate end (see FIG. 19B), a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the substrate, and desired. The negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Next, unnecessary copper foil 314 was removed by etching using a ferric chloride aqueous solution to form a window hole with a diameter of 0.15 mm at a desired location.
Using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation at the position of the window hole provided on the surface of the circuit board, laser drilling 310 was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (FIG. 19). (See (c)). After removing the resin residue carbonized with ultrasonic cleaning and alkaline permanganate solution, applying a cleaning catalyst, promoting adhesion, and performing electroless copper plating, and a layer of electroless plated copper 315 of about 20 μm on the inner wall of the laser hole and the copper foil surface Formed. An etching resist is formed using dry film resist H-9030 (manufactured by Hitachi Chemical Co., Ltd., trade name) on necessary places such as pads and circuit patterns on the surface of the circuit board, and unnecessary copper is removed by etching. An outer layer circuit formed of the foil 314 and the plated copper 315 was formed (see FIG. 19D).
Solder resist PSR-4000 AUS5 (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name) was applied to the surface of the circuit board by a roll coater at 30 μm, dried, exposed and developed to form a solder resist 316 at a desired location. Thereafter, 3 μm electroless nickel plating and 0.1 μm electroless gold plating (Ni / Au plating 317) were formed on the outer layer circuit pattern exposed portion surface layer to obtain a multilayer wiring board with a built-in capacitor (FIG. 19 (e) )reference).
Experimental Example C-2
A multilayer wiring board with a built-in capacitor was obtained by the same process as Experimental Example C-1, except that the material C-1 for a multilayer wiring board with a built-in capacitor was changed to a material C-2 with a multilayer wiring board with a built-in capacitor.
Experimental Example C-3
A multilayer wiring board with a built-in capacitor was obtained by the same process as in Experimental Example C-1, except that the thin film etchant (1) was replaced with the thin film etchant (2).
Experimental Example C-4
A multilayer wiring board with a built-in capacitor was obtained by the same process as in Experimental Example C-1, except that the thin film etchant (1) was replaced with the thin film etchant (3) and used at 30 ° C.
Experimental Example C-5
A multilayer wiring board with a built-in capacitor was obtained by the same process as in Experimental Example C-1, except that the thin film etchant (1) was replaced with the thin film etchant (4).
Experimental Example C-6
A multilayer wiring board with a built-in capacitor was obtained by the same process as in Experimental Example C-1, except that the thin film etchant (1) was replaced with the thin film etchant (5).
Experimental Example C-7
The surface of the copper foil 303 of the capacitor-embedded multilayer wiring board material C-1 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. A copper foil 5GTS-18 (thickness 18 μm) is passed through a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness 100 μm to be an insulating resin base material 304 (insulating material) on the surface of the copper foil 303. Furukawa Circuit Foil Co., Ltd., trade name) was placed and integrated under the press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to obtain a substrate (see FIG. 17A). Further, a 0.05 μm chromium film 306 was formed on the surface of the PZT thin film 301 by DC sputtering. Next, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper foil 305 of the substrate, a desired negative pattern is exposed and developed with an aqueous sodium carbonate solution, and an etching resist. Formed. Next, unnecessary copper foil is removed by etching using a ferric chloride aqueous solution to form a φ0.1 mm window hole 307 at a desired location (see FIG. 17B). Was peeled off. Subsequently, using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation at the position of the window hole 7, a laser hole 308 was drilled under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (see FIG. 17C). ). Thereafter, the resin residue carbonized by ultrasonic cleaning and an alkaline permanganate solution was removed, and after application of the catalyst and adhesion promotion, electroless copper plating was performed to form a 0.5 μm copper thin film on both surfaces of the substrate. Further, electrolytic copper plating was performed on the surface of the substrate to form a metal layer made of plated copper 309 for electrically connecting the inner circuit conductor and the conductive layer on the substrate surface (see FIG. 17D). Subsequently, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the substrate, and a desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Further, after removing unnecessary plated copper 309 by etching using ferric chloride aqueous solution, the resist is stripped by using sodium hydroxide aqueous solution, and chromium film 306 is removed by etching using potassium ferricyanide aqueous solution. A pattern of the capacitor electrode 310 was formed (see FIG. 18A). Next, 20 μm of an alkali developing resist PER-20 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) to be the etching resist 311 is applied to the first capacitor electrode 310 side of the substrate (see FIG. 18B). After prebaking at 15 ° C. for 15 minutes, the desired negative pattern was exposed, dried at 130 ° C. for 30 minutes, and developed with an aqueous sodium carbonate solution to form an etching resist 311 on the first capacitor electrode 310 (FIG. 18C). reference). Subsequently, the PZT thin film 301 is etched away at 20 ° C. using a thin film etchant (1), and the ruthenium thin film 302 is etched away using a ruthenium etching solution REC-01 (trade name, manufactured by Kanto Chemical Co., Ltd.) The etching resist 311 was peeled off with an aqueous sodium hydroxide solution (see FIG. 18D) (see FIG. 18E). A dry film resist H-9040 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on this substrate, and a desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Subsequently, the unnecessary copper foil 303, the unnecessary copper foil 305 and the plated copper 309 thereon are removed by etching with an aqueous ferric chloride solution, and then the etching resist is stripped with an aqueous sodium hydroxide solution to form the copper foil 303. A circuit pattern including the second capacitor electrode 312 was formed to produce a circuit board (see FIG. 19A).
Using this circuit board, it was then multilayered by the same process as in Experimental Example C-1 to obtain a multilayer wiring board with a built-in capacitor.
Experimental Example C-8
The surface of the copper foil 303 of the capacitor-embedded multilayer wiring board material C-1 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. Via a 100 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) serving as an insulating resin base material 304 on the surface of the copper foil 303, a copper foil 5GTS-18 (Furukawa Circuit Foil Co., Ltd.) Company, product name) were arranged and laminated and integrated under press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes (see FIG. 17A). Further, a 0.05 μm chromium film 306 was formed on the surface of the PZT thin film 301 by DC sputtering. Next, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper foil 305 of the substrate, a desired negative pattern is exposed and developed with an aqueous sodium carbonate solution, and an etching resist. Formed. Next, unnecessary copper foil was removed by etching using a ferric chloride aqueous solution to form a φ0.1 mm window hole 307 at a desired location, and the resist was peeled off with a sodium hydroxide aqueous solution (FIG. 17B). )reference). Subsequently, using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation at the location of the window hole 307, a laser hole 308 was drilled under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (see FIG. 17C). ). Thereafter, the resin residue carbonized by ultrasonic cleaning and an alkaline permanganate solution was removed, and after application of the catalyst and adhesion promotion, electroless copper plating was performed to form a 0.5 μm copper thin film on both surfaces of the substrate. Further, electrolytic copper plating was performed on the surface of the substrate to form a metal layer made of plated copper 309 for electrically connecting the inner circuit conductor and the conductive layer on the substrate surface (see FIG. 17D). Subsequently, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the substrate, and a desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Further, after removing unnecessary plated copper 309 by etching using ferric chloride aqueous solution, the resist is stripped by using sodium hydroxide aqueous solution, and chromium film 306 is removed by etching using potassium ferricyanide aqueous solution. A pattern of the capacitor electrode 310 was formed (see FIG. 18A). Next, 12 μm of a solvent developing resist AZ9245 (trade name, manufactured by Clariant Japan Co., Ltd.) that becomes the etching resist 311 is applied to the first capacitor electrode 310 side of the substrate (see FIG. 18B) at 110 ° C. After prebaking for 10 minutes, the desired positive pattern was exposed, dried at 120 ° C. for 10 minutes, and developed with an AZ400K developer (trade name, manufactured by Clariant Japan Co., Ltd.) to form an etching resist 311 (FIG. 18C). Followed by 20% ammonium bifluoride (NH ₄ F / HF) aqueous solution is used to etch away PZT thin film 301 at 20 ° C., and ruthenium thin film 302 is etched away using ruthenium etchant REC-01 (trade name, manufactured by Kanto Chemical Co., Ltd.) (FIG. 3). The etching resist 311 was peeled off with an AZ remover 700 (trade name, manufactured by Clariant Japan Co., Ltd.) (see FIG. 18E). A dry film resist H-9040 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on this substrate, and a desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Subsequently, the unnecessary copper foil 303, the unnecessary copper foil 305 and the plated copper 309 thereon are removed by etching with a ferric chloride aqueous solution, and then the resist is peeled off with a sodium hydroxide aqueous solution to form the copper foil 303. A circuit pattern including the second capacitor electrode 312 was formed to produce a circuit board (see FIG. 19A).
The circuit surface of this circuit board was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (1) 35 μm thick copper foil MT35S3 (trade name) manufactured by Mitsui Mining & Smelting Co., Ltd., with copper foil 35 μm carrier, (2) 100 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) ), (3) Circuit board, (4) Filled glass epoxy prepreg GEA-679F with a thickness of 100 μm, (5) 3 μm thick copper foil MT35S3 with 35 μm carrier copper foil (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) The copper foil 314 was laminated | stacked through the insulating resin base material 313 on both surfaces of the circuit board by carrying out lamination | stacking and integration by the press conditions of temperature 170 degreeC, pressure 1.5MPa, and heating and pressurization time 60 minutes. After peeling off the carrier copper foil and cutting off the unnecessary substrate end (see FIG. 19B), a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the substrate, and desired. The negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Next, unnecessary copper foil 314 was removed by etching using a ferric chloride aqueous solution to form a window hole with a diameter of 0.15 mm at a desired location.
Using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation at the location of the window hole provided on the surface of the circuit board, laser drilling was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (FIG. 19 ( c)). After removing the resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution, applying a cleaning catalyst, promoting adhesion, and then performing electroless copper plating to form an electroless copper plating layer of about 20 μm on the laser hole inner wall and the copper foil surface did. An etching resist is formed using dry film resist H-9030 (manufactured by Hitachi Chemical Co., Ltd., trade name) on necessary places such as pads and circuit patterns on the surface of the circuit board, and unnecessary copper is removed by etching. An outer layer circuit formed of the foil 314 and the plated copper 315 was formed (see FIG. 19D). Solder resist PSR-4000 AUS5 (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name) was applied to the surface of the circuit board by a roll coater at 30 μm, dried, exposed and developed to form a solder resist 316 at a desired location. Thereafter, 3 μm electroless nickel plating and 0.1 μm electroless gold plating (Ni / Au plating 17) were formed on the surface layer of the exposed portion of the outer circuit pattern to obtain a multilayer wiring board with a built-in capacitor (FIG. 19 (e) )reference).
Experimental Example C-9
The surface of the copper foil 303 of the capacitor-embedded multilayer wiring board material C-1 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. Via a 100 μm thick glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) serving as an insulating resin base material 304 on the surface of the copper foil 303, a copper foil 5GTS-18 (Furukawa Circuit Foil Co., Ltd.) Company, product name) were arranged and laminated and integrated under press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes (see FIG. 17A). Further, a 0.05 μm chromium film 306 was formed on the surface of the PZT thin film 301 by DC sputtering. Next, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the copper foil 305 of the substrate, a desired negative pattern is exposed and developed with an aqueous sodium carbonate solution, and an etching resist. Formed. Next, unnecessary copper foil was removed by etching using a ferric chloride aqueous solution to form a φ0.1 mm window hole 307 at a desired location, and the resist was peeled off with a sodium hydroxide aqueous solution (FIG. 17B). )reference). Subsequently, using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation at the location of the window hole 307, a laser hole 308 was drilled under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 (see FIG. 17C). ). Thereafter, the resin residue carbonized by ultrasonic cleaning and an alkaline permanganate solution was removed, and after application of the catalyst and adhesion promotion, electroless copper plating was performed to form a 0.5 μm copper thin film on both surfaces of the substrate. Further, electrolytic copper plating was performed on the surface of the substrate to form a metal layer made of plated copper 309 for electrically connecting the inner circuit conductor and the conductive layer on the substrate surface (see FIG. 17D). Subsequently, a dry film resist H-9030 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the surface of the substrate, and a desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Further, after removing unnecessary plated copper 309 by etching using ferric chloride aqueous solution, the resist is stripped by using sodium hydroxide aqueous solution, and chromium film 306 is removed by etching using potassium ferricyanide aqueous solution. A pattern of the capacitor electrode 310 was formed (see FIG. 18A). Next, 12 μm of a solvent developing resist AZ9245 (trade name, manufactured by Clariant Japan Co., Ltd.) to be the etching resist 311 is applied to the first capacitor electrode 310 side of the substrate (see FIG. 18B), and 10 ° C. at 10 ° C. After prebaking, the desired positive pattern is exposed, dried at 120 ° C. for 10 minutes, and developed with an AZ400K developer (trade name, manufactured by Clariant Japan Co., Ltd.) to form an etching resist 311 (see FIG. 18C). ). Next, CF ₄ After the PZT thin film 301 and the ruthenium thin film 302 are removed by etching by the RIE method using gas (see FIG. 18D), the etching resist 311 is peeled off with an AZ remover 700 (trade name, manufactured by Clariant Japan Co., Ltd.) ( (See FIG. 18 (e)). A dry film resist H-9040 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on this substrate, and a desired negative pattern was exposed and developed with an aqueous sodium carbonate solution to form an etching resist. Subsequently, the unnecessary copper foil 303, the unnecessary copper foil 305 and the plated copper 309 thereon are removed by etching with a ferric chloride aqueous solution, and then the resist is peeled off with a sodium hydroxide aqueous solution to form the copper foil 303. A circuit pattern including the second capacitor electrode 312 was formed to produce a circuit board (see FIG. 19A).
Using this circuit board, a multilayer wiring board with a built-in capacitor was obtained by the same process as in Experimental Example C-8 (see FIG. 19 (e)).
In Experimental Examples C-1 to C-7, no etching residue or resist peeling was observed on any of the substrates during the etching of the thin film, and the patterning property was good. Next, the capacitor capacity was measured. Capacitor capacity is impedance probe 4291B (Agilent Technology Co., Ltd., trade name) via 50Ω coaxial cable SUCOFLEX104 / 100 (SUHNER, trade name), high-frequency signal measurement probe MICROPROBE ACP50 (GSG250, Cascade, trade name) ) Was used. The electrode size of the capacitor was 1 mm □, and the capacity of 1 GHz was measured. The results are shown in Table 3.

As shown in Table 3, the variations in the capacitor capacity of the multilayer wiring boards with built-in capacitors produced in Experimental Examples C-1 to C-7 are all less than ± 10%, and uniform and good capacitors can be produced. did it. This is the same variation as the experimental examples C-8 to C-9, and even if the experimental examples C-1 to C-7 are used, the multilayer wiring with a built-in capacitor having the same accuracy as the experimental examples C-8 to C-9 is obtained. It turns out that it is obtained. Moreover, conventional CF ₄ RIE method using gas (Experimental example C-9) and 20% ammonium bifluoride (NH ₄ Unlike the F.HF) aqueous solution (Experimental Example C-8), etc., as described above, it is a wet etching method using an alkali developing type resist, so that it can be easily applied to the conventional printed wiring board process. This is possible, and is excellent in terms of workability and economy.
(Example D)
Capacitor built-in multilayer wiring board material D-1
Titanium tetraisopropoxide, zircon tetratertiary butoxide, dipivaloylmethane lead complex, and nitrogen dioxide were used on the surface of rolled copper foil M-BNH-18 (product name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 18 μm. A PZT (lead zirconate titanate) thin film having a thickness of 0.5 μm was formed by microwave plasma CVD under the condition of a substrate temperature of 350 ° C. In this way, a capacitor built-in multilayer wiring board material D-1 in which the PZT thin film 101 (dielectric thin film) was provided on one surface of the copper foil 102 (metal foil A) was obtained (FIG. 1A).
Capacitor built-in multilayer wiring board material D-2
A 0.2 μm ruthenium thin film was formed on the surface of a rolled copper foil M-BNH-18 having a thickness of 18 μm (trade name, manufactured by Mitsui Metal Mining Co., Ltd.) by a DC sputtering method. Furthermore, the thickness of the substrate is 0.5 μm under the condition of a substrate temperature of 350 ° C. by microwave plasma CVD using titanium tetraisopropoxide, zircon tetratertiary butoxide, dipivaloylmethane lead complex and nitrogen dioxide. A PZT (lead zirconate titanate) thin film was formed. In this way, a capacitor built-in multilayer wiring board material D-2 in which the PZT thin film 101 (dielectric thin film) was provided on one side of the copper foil 102 (metal foil A) via the ruthenium thin film 103 was obtained (FIG. 1 (b)).
Capacitor built-in multilayer wiring board material D-3
A 0.2 μm ruthenium thin film was formed on the surface of a rolled copper foil M-BNH-18 having a thickness of 18 μm (trade name, manufactured by Mitsui Metal Mining Co., Ltd.) by a DC sputtering method. Further, a ferroelectric thin film forming material PZT (Kanto Chemical Co., Ltd., trade name) was applied to the surface and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, and then a heat treatment was performed at a temperature of 350 ° C. for 1 hour to form a PZT thin film having a thickness of 0.5 μm. In this way, a capacitor built-in multilayer wiring board material (3) in which the PZT thin film 101 (dielectric thin film) was provided on one side of the copper foil 102 (metal foil A) via the ruthenium thin film 103 was obtained (FIG. 1 (b)).
Example D-1
The surface of the copper foil 402 (metal foil A) of the capacitor built-in multilayer wiring board material D-1 is roughened with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 20A). A glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm and serving as an insulating resin base material 404 (insulating layer) is formed on the surface of the copper foil 402 of the capacitor built-in multilayer wiring board material. , 12μm thick copper foil 405 (metal foil B) GTS-12 (Furukawa Circuit Foil Co., Ltd., trade name), laminated at a temperature of 180 ° C., pressure of 1.5 MPa, heating and pressing time of 60 minutes. To obtain a substrate (FIG. 20B). Next, a desired etching resist was formed on both surfaces of this substrate, and unnecessary copper foil was removed by etching using a ferric chloride aqueous solution to form a window hole 405 'having a diameter of 0.15 mm at a desired location ( FIG. 20 (c)). Subsequently, using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation at the position of the window hole 405 ′, the laser hole 406 is opened by laser irradiation under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and the number of shots of 4 times, and ultrasonic cleaning is performed. And the resin residue carbonized with the alkaline permanganate solution was removed (FIG. 20D). Further, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 (dielectric thin film) by DC sputtering. Thereafter, a catalyst imparting treatment using a catalyst imparting agent (Neoganth 843, manufactured by Atotech Japan Co., Ltd., trade name) and an adhesion promoter (Neoganth WA, manufactured by Atotech Japan Co., Ltd., trade name) were used on both sides of the substrate. After performing adhesion promoting treatment, electroless copper plating is performed to form a 0.5 μm copper thin film, and further, a 20 μm metal layer is formed on both sides of the substrate by electrolytic copper plating, and a metal layer made of plated copper 408 is formed. (FIG. 20 (e)). A desired etching resist is formed on the surface of the substrate, unnecessary plated copper 408 is etched away using a ferric chloride aqueous solution, and the exposed chromium thin film 407 is etched away using a potassium ferricyanide aqueous solution. A pattern of the capacitor electrode 409 was formed (FIG. 20F). Subsequently, a resist having a desired pattern is formed and CF ₄ The PZT thin film 401 was removed by etching by RIE using gas to form a capacitor dielectric 401 '(FIG. 20 (g)). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402, the copper foil 405, and the plated copper 408 are removed by etching using a ferric chloride aqueous solution, and the second capacitor electrode 410 is removed. A circuit pattern including the circuit board was formed to produce a circuit board (FIG. 20H).
The circuit surface of this circuit board was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (1) Copper foil MT35S3 with a thickness of 3 μm with 35 μm carrier copper foil (trade name) manufactured by Mitsui Mining & Smelting Co., Ltd. (2) Glass epoxy prepreg GEA-679F with a filler of 100 μm thickness to be an insulating resin base material 412 (Hitachi Chemical) Kogyo Co., Ltd., trade name), (3) circuit board, (4) 100 μm thick glass epoxy prepreg GEA-679F filled with filler, and (5) 3 μm thick copper foil with 35 μm carrier copper foil MT35S3 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) was stacked in this order, and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. After peeling off the carrier copper foil and cutting unnecessary substrate edges, a desired etching resist is formed on the surface of this substrate, and unnecessary copper foil is removed by etching using a ferric chloride aqueous solution, to a desired location. A window hole with a diameter of 0.15 mm was formed.
Laser drilling was performed at a window hole provided on the surface of the substrate using an ML505GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation under conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of four. After removing the resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution, applying a cleaning catalyst, promoting adhesion, and then performing electroless copper plating to form an electroless copper plating layer of about 20 μm on the laser hole inner wall and the copper foil surface did. Etching resist was formed on necessary portions such as pads and circuit patterns on the surface of the substrate, and unnecessary copper was removed by etching to form an outer layer circuit.
Solder resist PSR-4000 AUS5 (Taiyo Ink Manufacturing Co., Ltd., trade name) was applied to this substrate surface with a roll coater at 30 μm, dried, exposed and developed to form a solder resist 411 at a desired location. Thereafter, 3 μm electroless nickel plating and 0.1 μm electroless gold plating (Ni—Au plating 420) were formed on the outer layer circuit pattern exposed portion surface layer to obtain a multilayer wiring board with a built-in capacitor (FIG. 20 (i)). )).
Example D-2
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 21 (a)). On the surface of the copper foil 402 of this multilayer wiring board material with a built-in capacitor, through a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404, a thickness of 12 μm. Copper foil 5GTS-12 (Furukawa Circuit Foil Co., Ltd., trade name) was placed and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate (FIG. 21 ( b)). Next, a desired etching resist was formed on both surfaces of this substrate, and unnecessary copper foil was removed by etching using a ferric chloride aqueous solution to form a window hole 405 'having a diameter of 0.15 mm at a desired location ( FIG. 21 (c)). Subsequently, using a ML505GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation at the position of the window hole 405 ′, laser irradiation was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 times to open a laser hole 406, and an ultrasonic wave Washing and resin residue carbonized with the alkaline permanganate solution were removed (FIG. 21 (d)). Further, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 by DC sputtering. Thereafter, a catalyst is applied to both surfaces of the substrate, electroless copper plating is performed after adhesion is promoted, a 0.5 μm copper thin film is formed, and a 20 μm metal layer is formed on both surfaces of the substrate by electrolytic copper plating. A layer was formed (FIG. 21 (e)). A desired etching resist is formed on the surface of the substrate, unnecessary portions of the plated copper 408 are etched away using an aqueous ferric chloride solution, and the exposed chromium thin film 407 is etched away using an aqueous potassium ferricyanide solution. One capacitor electrode 409 pattern was formed (FIG. 21F). Subsequently, a resist having a desired pattern is formed and CF ₄ Unnecessary portions of the PZT thin film 401 and the ruthenium thin film 403 were etched away by RIE using gas to form a capacitor dielectric 401 ′ (FIG. 21 (g)). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402, the copper foil 405, and the plated copper 408 are removed by etching using a ferric chloride aqueous solution, and the second capacitor electrode 410 is removed. A circuit pattern including the circuit board was formed to produce a circuit board (FIG. 21H). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 21 (i)).
Example D-3
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-2 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 22 (a)). 35 μm carrier copper is formed on the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor via a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404. A copper foil 5MT35M3 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 3 μm with a foil was arranged, and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate. (FIG. 22B). Next, after the carrier copper foil is manually peeled off, a laser is used on the surface of the copper foil 405 of the substrate under the conditions of an output power of 30 mJ, a pulse width of 15 μs, and a number of shots of 6 using a Mitsubishi Electric Corporation ML505GT type carbon dioxide laser. Drilling was performed to produce a laser hole 406 having a diameter of 0.15 mm. Thereafter, the resin residue carbonized with ultrasonic cleaning and an alkaline permanganate solution was removed (FIG. 22C). Further, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 by DC sputtering. Thereafter, a catalyst is applied to both surfaces of the substrate, electroless copper plating is performed after adhesion is promoted, a 0.5 μm copper thin film is formed, and a 20 μm metal layer is formed on both surfaces of the substrate by electrolytic copper plating. A layer was formed (FIG. 22 (d)). A desired etching resist is formed on the surface of the substrate, an unnecessary portion of the metal layer made of plated copper 408 is etched away using an aqueous ferric chloride solution, and the exposed chromium thin film 407 is etched away using an aqueous potassium ferricyanide solution. Thus, a pattern of the first capacitor electrode 409 was formed (FIG. 22E). Subsequently, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ F.HF) aqueous solution was used to etch away unnecessary portions of the PZT thin film 401, and the PZT thin film was patterned to form a capacitor dielectric 401 '(FIG. 22 (f)). Subsequently, the exposed ruthenium thin film 403 was removed by etching using a ruthenium etching solution REC-01 (Kanto Chemical Co., Inc., trade name) (FIG. 22 (g)). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402, the copper foil 405, and the plated copper 408 are removed by etching using a ferric chloride aqueous solution, and the second capacitor electrode 410 is removed. A circuit pattern including the circuit board was formed to produce a circuit board (FIG. 22H). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 22 (i)).
Example D-4
The surface of the copper foil 402 of the capacitor-embedded multilayer wiring board material C-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 23 (a)). 35 μm carrier copper is formed on the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor via a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404. A copper foil 5MT35S3 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 3 μm with a foil was disposed, and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate. (FIG. 23 (b)). In this prepreg, a polyethylene terephthalate (PET) film having a thickness of 25 μm is pasted on both sides with a hot press at a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes, and then drilled at a desired location. After conducting the above, a conductive paste 13AE1650 (Tatsuta System Electronics Co., Ltd., trade name) in which copper powder is dispersed in a thermosetting resin is filled by screen printing, and then the PET film on the surface is peeled off. Using. Next, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 by DC sputtering, and then a metal layer made of 20 μm plated copper 408 was formed on both surfaces of the substrate by electrolytic copper plating (FIG. 23 ( c)). A desired etching resist is formed on the surface of the substrate, an unnecessary portion of the metal layer made of plated copper 408 is etched away using an aqueous ferric chloride solution, and the exposed chromium thin film 7 is etched away using an aqueous potassium ferricyanide solution. Thus, a pattern of the first capacitor electrode 409 was formed (FIG. 23D). Subsequently, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ An unnecessary portion of the PZT thin film 401 was etched away using an aqueous solution of F.HF), and the PZT thin film was patterned to form a capacitor dielectric 401 '(FIG. 23E). Subsequently, the exposed ruthenium thin film 403 was removed by etching using a ruthenium etching solution REC-01 (Kanto Chemical Co., Ltd., trade name) (FIG. 23 (f)). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402, the copper foil 405, and the plated copper 408 are removed by etching using a ferric chloride aqueous solution, and the second capacitor electrode 410 is removed. A circuit board including the substrate was formed to produce a circuit board (FIG. 23G). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 23 (h)).
Example D-5
Except for replacing the conductive paste that fills the holes in the prepreg to be laminated with the capacitor built-in multilayer wiring board material with a nano paste (Harima Kasei Co., Ltd., trade name) that is metalized by chemical reaction. A multilayer wiring board with a built-in capacitor was obtained by the same process as in Example D-4.
Example D-6
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a multi-layer adhesion pretreatment ( FIG. 24 (a)). 35 μm carrier copper is formed on the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor via a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404. A copper foil 5MT35S3 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 3 μm with a foil was disposed, and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate. (FIG. 24B). Next, a desired etching resist is formed on the surface of the copper foil 405 of the substrate from which the carrier copper foil has been peeled off, and unnecessary copper foil is removed by etching using a ferric chloride aqueous solution. A window hole 405 ′ was formed (FIG. 24C). Subsequently, using a ML505GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation at the position of the window hole 405 ′, laser irradiation was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 times to open a laser hole 406, and an ultrasonic wave Washing and resin residue carbonized with the alkaline permanganate solution were removed (FIG. 24 (d)). Further, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 by DC sputtering. Thereafter, a catalyst was applied to both surfaces of the substrate, and after the adhesion was promoted, electroless copper plating was performed to form a 0.5 μm copper thin film 19. The 0.05 μm chromium thin film 407 and the 0.5 μm copper thin film 419 thus formed form a base metal layer (a metal layer having a thickness of 0.1 to 5 μm) of the semi-additive method. Desired plating resists 414 were formed on both surfaces of this substrate, and copper electroplating was performed to form a conductor pattern made of plated copper 415 to be a circuit in a portion including the first capacitor electrode 409 having a thickness of 20 μm and the laser hole 406. (FIG. 24 (e)). After the plating resist 414 was removed, unnecessary portions of the 0.5 μm copper thin film 419 and unnecessary portions of the 0.05 μm chromium thin film 407 on both surfaces of the substrate were removed by etching to form a pattern of the first capacitor electrode 409. At this time, a 3 μm thick copper foil 405 was also patterned to form a circuit (FIG. 24F). Subsequently, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ F.HF) aqueous solution was used to etch away unnecessary portions of the PZT thin film 401, and the PZT thin film 401 was patterned to form a capacitor dielectric 401 '(FIG. 24G). Subsequently, the exposed ruthenium thin film 403 was removed by etching using a ruthenium etching solution REC-01 (Kanto Chemical Co., Inc., trade name) (FIG. 24H). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402 are removed by etching using an aqueous ferric chloride solution to form a circuit pattern including the second capacitor electrode 410. A circuit board was produced (FIG. 24 (i)). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 24J).
Example D-7
The surface of the copper foil 402 of the capacitor-embedded multilayer wiring board material C-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 25 (a)). 35 μm carrier copper is formed on the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor via a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404. A copper foil 5MT35M3 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 3 μm with a foil was arranged, and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate. (FIG. 25 (b)). After the carrier copper foil is peeled off manually, laser drilling is performed using an ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation under the conditions of an output power of 30 mJ, a pulse width of 15 μs, and a shot number of 6 times, and a laser hole of φ0.15 mm 406 was produced. Thereafter, the resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution was removed (FIG. 25 (c)). Further, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 by DC sputtering. Further, after applying the catalyst to both surfaces of this substrate and promoting adhesion, electroless copper plating was performed to form a copper thin film 419 having a thickness of 0.5 μm. The 0.05 μm chromium thin film 407 and the 0.5 μm copper thin film 419 thus formed form a base metal layer (a metal layer having a thickness of 0.1 to 5 μm) of the semi-additive method. A desired plating resist 414 is formed on the surface of this substrate, and copper electroplating is performed to form a conductor pattern made of plated copper 415 to be a circuit of a portion including the first capacitor electrode 409 and the laser hole 406 having a thickness of 20 μm. (FIG. 25 (d)). After removing the plating resist 414, the exposed portions of the 0.5 μm copper thin film 419 and the 0.05 μm chromium thin film 407 exposed on the substrate surface are removed by etching, and the portion including the first capacitor electrode 409 and the laser hole 406 is removed. A circuit pattern was formed. At this time, a 3 μm thick copper foil 405 was also patterned to form a circuit (FIG. 25E). Subsequently, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ The PZT thin film 401 was etched away using an aqueous solution of (F · HF) and the PZT thin film 401 was patterned to form a capacitor dielectric 401 ′ (FIG. 25 (f)). Thereafter, the exposed portion of the ruthenium thin film 403 was removed by etching using a ruthenium etching solution REC-01 (Kanto Chemical Co., Ltd., trade name) (FIG. 25 (g)). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402 are removed by etching using an aqueous ferric chloride solution to form a circuit pattern including the second capacitor electrode 410. A circuit board was produced (FIG. 25 (h)). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 25 (i)).
Example D-8
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 26 (a)). On the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor, a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be an insulating resin base material 404 is used. Copper foil 5GTS-18 (Furukawa Circuit Foil Co., Ltd., trade name) was placed and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate (FIG. 26 ( b)). In this prepreg, a polyethylene terephthalate (PET) film having a thickness of 25 μm is pasted on both sides with a hot press at a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes, and then drilled at a desired location. After conducting the above, a conductive paste 13AE1650 (Tatsuta System Electronics Co., Ltd., trade name) in which copper powder is dispersed in a thermosetting resin is filled by screen printing, and then the PET film on the surface is peeled off. Using. Next, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 by DC sputtering. Then, after applying a catalyst to both surfaces of the substrate and promoting adhesion, electroless copper plating was performed to form a 0.5 μm copper thin film 419. The 0.05 μm chromium thin film 407 and the 0.5 μm copper thin film 419 thus formed form a base metal layer (a metal layer having a thickness of 0.1 to 5 μm) of the semi-additive method. Thereafter, a desired plating resist 414 was formed on both surfaces of the substrate, and electrolytic copper plating was performed to form a conductor pattern to be the first capacitor electrode 409 having a thickness of 20 μm (FIG. 26C). After removing the plating resist 414, the exposed 0.5 μm copper thin film 419 on the substrate surface is etched away with a ferric chloride aqueous solution, and the exposed 0.05 μm chromium thin film 407 is etched away with an aqueous potassium ferricyanide solution. Then, a pattern of the first capacitor electrode 409 was formed (FIG. 26D). Subsequently, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ An unnecessary portion of the PZT thin film 401 was etched away using an aqueous solution of (F · HF), and the PZT thin film 401 was patterned to form a capacitor dielectric 401 ′ (FIG. 26E). Subsequently, the exposed ruthenium thin film 403 was removed by etching using a ruthenium etching solution REC-01 (Kanto Chemical Co., Ltd., trade name) (FIG. 26 (f)). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402 and the copper foil 405 are removed by etching using a ferric chloride aqueous solution, so that a circuit pattern including the second capacitor electrode 410 is obtained. To form a circuit board (FIG. 26G). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 26 (h)).
Example D-9
Except for replacing the conductive paste that fills the holes in the prepreg to be laminated with the capacitor built-in multilayer wiring board material with a nano paste (Harima Kasei Co., Ltd., trade name) that is metalized by chemical reaction. A capacitor built-in multilayer wiring board was obtained by the same process as in Example D-8.
Example D-10
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 27 (a)). On the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor, a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be an insulating resin base material 404 is used. Copper foil 5GTS-18 (Furukawa Circuit Foil Co., Ltd., trade name) was placed and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate (FIG. 27 ( b)). In this prepreg, a polyethylene terephthalate (PET) film having a thickness of 25 μm is pasted on both sides with a hot press at a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes, and then drilled at a desired location. After conducting the above, a conductive paste AE1650 (Tatsuta System Electronics Co., Ltd., trade name) in which copper powder is dispersed in a thermosetting resin is filled by screen printing, and then the PET film on the surface is peeled off. Using. Next, nanopaste (Harima Kasei Co., Ltd., trade name), which is a conductive paste that is metallized by a chemical reaction, is printed at a desired location on the surface of the PZT thin film 401 with a thickness of 40 μm. Then, baking was performed at a temperature of 200 ° C. for 1 hour, and the conductive paste was metallized to form a pattern of the first capacitor electrode 416 (FIG. 27C). Subsequently, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ F.HF) aqueous solution is used to etch away unnecessary portions of the PZT thin film 401 and patterning of the PZT thin film to form a capacitor dielectric 401 ', followed by ruthenium etchant REC-01 (Kanto Chemical Co., Ltd., trade name) ) To remove the exposed portion of the ruthenium thin film 403 (FIG. 27D). Next, a desired etching resist is formed on the surface of the substrate, and unnecessary portions of the copper foil 402 and the copper foil 405 are removed by etching using a ferric chloride aqueous solution, so that a circuit pattern including the second capacitor electrode 410 is obtained. To form a circuit board (FIG. 27E). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 27 (f)).
Example D-11
Except for replacing the conductive paste that fills the holes in the prepreg to be laminated with the capacitor built-in multilayer wiring board material with a nano paste (Harima Kasei Co., Ltd., trade name) that is metalized by chemical reaction. A capacitor built-in multilayer wiring board was obtained by the same process as in Example D-10.
Example D-12
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 28 (a)). On the surface of the copper foil 402 of this multilayer wiring board material with a built-in capacitor, through a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404, a thickness of 12 μm. Copper foil 5GTS-12 (Furukawa Circuit Foil Co., Ltd., trade name) was placed and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate (FIG. 28 ( b)). Next, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ F.HF) A PZT thin film 401 is etched away using an aqueous solution, and the PZT thin film is patterned to form a capacitor dielectric 401 '. Then, a ruthenium etching solution REC-01 (Kanto Chemical Co., Ltd., trade name) is used. The ruthenium thin film 403 was removed by etching (FIG. 28C). Desired etching resists were formed on both surfaces of the substrate, and unnecessary portions of the copper foil 405 were removed by etching using a ferric chloride aqueous solution to form a window hole 405 ′ having a diameter of 0.15 mm at the desired location (FIG. 28 (d)). Subsequently, using a ML505GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation at the position of the window hole 405 ′, laser irradiation was performed under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 4 times to open a laser hole 406, and an ultrasonic wave Washing and resin residue carbonized with the alkaline permanganate solution were removed (FIG. 28 (e)). Further, a 0.05 μm chromium thin film 407 was formed on the surface of the substrate on the capacitor dielectric 401 ′ side by a DC sputtering method. Thereafter, on both surfaces of the substrate, after applying a catalyst and promoting adhesion, electroless copper plating is performed to form a 0.5 μm copper thin film, and a 20 μm metal layer is further formed thereon by electrolytic copper plating. A metal layer was formed (FIG. 28 (f)). A desired etching resist is formed on the surface of the substrate, unnecessary portions of the plated copper 408 and the copper foil 405 are etched away using a ferric chloride aqueous solution, and the exposed chromium thin film 407 is etched away using a potassium ferricyanide aqueous solution. Then, the exposed copper foil 402 was removed by etching using an aqueous ferric chloride solution to form a circuit pattern including the first capacitor electrode 409 and the second capacitor electrode 410 (FIG. 28 (g)). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 28 (h)).
Example D-13
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 29 (a)). 35 μm carrier copper is formed on the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor via a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404. A copper foil 5MT35M3 (trade name, manufactured by Mitsui Mining & Smelting Co., Ltd.) having a thickness of 3 μm with a foil was arranged, and a substrate was obtained by laminating and integrating under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. (FIG. 29 (b)). Next, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ F.HF) A PZT thin film 401 is etched away using an aqueous solution, and the PZT thin film is patterned to form a capacitor dielectric 401 '. Then, a ruthenium etching solution REC-01 (Kanto Chemical Co., Ltd., trade name) is used. Then, the exposed portion of the ruthenium thin film 403 was removed by etching (FIG. 29C). After the carrier copper foil is peeled off manually, a predetermined surface of the copper foil 405 is irradiated with a laser under the conditions of an output power of 30 mJ, a pulse width of 15 μs and a shot number of 6 using a ML505GT type carbon dioxide laser manufactured by Mitsubishi Electric Corporation. A laser hole 406 with a diameter of 0.15 mm was produced. Thereafter, the resin residue carbonized by ultrasonic cleaning and alkaline permanganate solution was removed (FIG. 29 (d)). Further, a 0.05 μm chromium thin film 407 was formed by DC sputtering on the surface of the substrate on which the capacitor dielectric 401 ′ was formed. Thereafter, a catalyst is applied to both sides of the substrate, electroless copper plating is performed after adhesion is promoted, a 0.5 μm copper thin film is formed, a 20 μm metal layer is further formed thereon by electrolytic copper plating, and a metal made of plated copper 408 A layer was formed (FIG. 29 (e)). A desired etching resist is formed on the surface of the substrate, unnecessary portions of the plated copper 408 and the copper foil 405 are etched away using a ferric chloride aqueous solution, and the exposed chromium thin film 407 is etched away using a potassium ferricyanide aqueous solution. Then, the exposed copper foil 402 was removed by etching using a ferric chloride aqueous solution, thereby forming a circuit pattern including the first capacitor electrode 409 and the second capacitor electrode 410 (FIG. 29 (f)). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 29 (g)).
Example D-14
The surface of the copper foil 402 of the capacitor built-in multilayer wiring board material D-3 was subjected to a roughening treatment with an organic acid microetching agent CZ-8100B (trade name, manufactured by MEC Co., Ltd.) as a pretreatment for multilayering adhesion. (FIG. 30 (a)). 35 μm carrier copper is formed on the surface of the copper foil 402 of the multilayer wiring board material with a built-in capacitor via a glass epoxy prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 μm to be the insulating resin base material 404. A copper foil 5MT3553 (Mitsui Mining Co., Ltd., trade name) having a thickness of 3 μm with a foil was arranged, and laminated and integrated under press conditions of a temperature of 180 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to obtain a substrate (FIG. 30 (b)). In this prepreg, a polyethylene terephthalate (PET) film having a thickness of 25 μm is pasted on both sides with a hot press under conditions of a temperature of 100 ° C., a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes, and then a drill hole is drilled at a desired location. After conducting the above, a conductive paste AE1650 (Tatsuta System Electronics Co., Ltd., trade name) in which copper powder is dispersed in a thermosetting resin is filled by screen printing, and then the PET film on the surface is peeled off. Using.
Next, a resist having a desired pattern is formed, and 20% ammonium bifluoride (NH ₄ F.HF) A PZT thin film 401 is etched away using an aqueous solution, and the PZT thin film is patterned to form a capacitor dielectric 401 '. Then, a ruthenium etching solution REC-01 (Kanto Chemical Co., Ltd., trade name) is used. Then, the exposed portion of the ruthenium thin film 403 was removed by etching (FIG. 30C). Further, a 0.05 μm chromium thin film 407 is formed on the surface side of the capacitor dielectric 401 ′ of the substrate by DC sputtering, and after application of the catalyst and adhesion promotion, electroless copper plating is performed to form a 0.5 μm copper thin film. Formed. Further, a metal layer made of plated copper 408 having a thickness of 20 μm was formed on both surfaces of the substrate by electrolytic copper plating (FIG. 30D). A desired etching resist is formed on the surface of the substrate, unnecessary portions of the plated copper 408 and the copper foil 405 are etched away using a ferric chloride aqueous solution, and the exposed chromium thin film 7 is etched away using a potassium ferricyanide aqueous solution. Further, the exposed copper foil 402 was removed by etching using a ferric chloride aqueous solution, thereby forming a circuit pattern including the first capacitor electrode 409 and the second capacitor electrode 410 (FIG. 30E). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 30 (f)).
Example D-15
Except for replacing the conductive paste that fills the holes in the prepreg to be laminated with the capacitor built-in multilayer wiring board material with a nano paste (Harima Kasei Co., Ltd., trade name) that is metalized by chemical reaction. A capacitor built-in multilayer wiring board was obtained by the same process as in Example D-14.
Comparative Example D-1
A double-sided circuit board (FIG. 31 (a)) having a plate thickness of 0.2 mm having conductor holes for connecting circuit patterns on both sides (filled with hole filling resin 418) was prepared. A ruthenium thin film 403 having a thickness of 0.2 μm was formed on one surface of this substrate by DC sputtering. A resist having a desired pattern was formed, and the ruthenium thin film 403 other than that on the circuit was etched away by RIE to form a circuit pattern including the second capacitor electrode 421 (FIG. 31B). Further, a ferroelectric thin film forming material PZT (Kanto Chemical Co., Ltd., trade name) was applied to the surface of the substrate, and prebaked at a temperature of 150 ° C. for 30 minutes. Coating and pre-baking were further repeated 5 times, followed by heat treatment at a temperature of 250 ° C. for 1 hour to form a PZT thin film 401 having a thickness of 0.5 μm (FIG. 31C). Further, a 0.05 μm chromium thin film 407 was formed on the surface of the PZT thin film 401 by DC sputtering. Further, a metal layer made of 20 μm-plated copper 408 was formed on the surface by electrolytic copper plating (FIG. 31 (d)). A desired etching resist is formed on the surface of the substrate, unnecessary portions of the plated copper 408 are etched away using a ferric chloride aqueous solution, and the exposed chromium thin film 407 is etched away using a potassium ferricyanide aqueous solution. A circuit board was produced by forming a pattern of one capacitor electrode 422 (FIG. 31E). Subsequent processing of the multilayer wiring board obtained a capacitor built-in multilayer wiring board by the same process as in Example D-1 (FIG. 31F).
For the multilayer wiring boards with a built-in capacitor obtained in Examples D-1 to D-15 and Comparative Example D-1, the thickness of the dielectric, the relative dielectric constant, and the capacitance of the capacitor were measured. Each measuring method is the same as described above. The measurement results are shown in Table 4 below.

Each of Examples D-1 to D-15 was a capacitor characterized in that a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm was provided on the surface of the metal foil. This is a capacitor built-in board manufactured using a built-in multilayer wiring board material. Variations in the capacitance of the produced capacitors were all less than ± 10%, and uniform and good capacitors could be produced.
In addition, since the comparative example is a capacitor built-in substrate in which a dielectric thin film is formed on the surface of the substrate on which the metal layer is patterned, the variation in the film thickness is large, and as a result, the variation in the capacitor capacity is as large as 54% at maximum. It was.
Those skilled in the art will appreciate that the foregoing is the preferred embodiment of the invention and that many changes and modifications can be made without departing from the spirit and scope of the invention.

Claims

A material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a thickness of 0.05 to 2 μm is provided on the surface of a metal foil.

The dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, barium strontium titanate, titanium It is a film made of any one of lead zirconate acid, lead magnesium niobate-lead titanate, a solid solution containing any two or more of these, or a laminate containing any two or more of these. The material for a multilayer wiring board with a built-in capacitor according to claim 1.

One or more selected from the group consisting of platinum, gold, silver, palladium, ruthenium, and iridium as the metal that forms the copper oxide protective film on the surface on which the metal foil is formed and the dielectric thin film is formed The material for a multilayer wiring board with a built-in capacitor according to claim 1, wherein the metal film is provided.

The metal foil is made of copper, and one or more metal films selected from the group consisting of chromium, molybdenum, titanium, and nickel are provided as a metal that forms a stable self-oxidation film on the surface thereof. The material for a multilayer wiring board with a built-in capacitor according to claim 1 or 2.

The material for a multilayer wiring board with a built-in capacitor according to any one of claims 1 to 4, wherein the surface roughness of the metal foil is 0.01 to 0.5 µm.

A method for producing a material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by a vacuum deposition method.

A method for producing a material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by an ion plating method.

A material for a multilayer wiring board with a built-in capacitor, wherein a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is formed on a surface of a metal foil by a CVD (Chemical Vapor Deposition) method. Production method.

A method for producing a capacitor-embedded multilayer wiring board material, comprising: forming a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm on a surface of a metal foil by a sputtering method.

A method for producing a capacitor built-in multilayer wiring board material, comprising forming a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm on a surface of a metal foil by a sol-gel method.

A roll-shaped metal foil is used as the metal foil, and the dielectric thin film is formed while continuously moving the metal foil in a heating furnace whose temperature is controlled to be constant. The manufacturing method of the multilayer wiring board material with a built-in capacitor | condenser in any one of.

The dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, barium strontium titanate, titanium It is a film made of any one of lead zirconate acid, lead magnesium niobate-lead titanate, a solid solution containing any two or more of these, or a laminate containing any two or more of these. A method for producing a capacitor-embedded multilayer wiring board material according to any one of claims 6 to 11.

One or more selected from the group consisting of platinum, gold, silver, palladium, ruthenium, and iridium as a metal that forms an oxidation protection film of copper on the surface on which the metal foil is formed of a copper and the dielectric thin film is formed. 13. The method for producing a capacitor built-in multilayer wiring board material according to claim 6, further comprising a metal film.

The metal foil is made of copper, and one or more metal films selected from the group consisting of chromium, molybdenum, titanium, and nickel are provided as a metal that forms a stable self-oxidation film on the surface thereof. The manufacturing method of the capacitor built-in multilayer wiring board material according to any one of claims 6 to 12.

The method for producing a material for a multilayer wiring board with a built-in capacitor according to any one of claims 6 to 14, wherein the surface roughness of the metal foil is 0.01 to 0.5 µm.

A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. :
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) forming a 10-50 μm metal layer on the surface of the dielectric thin film;
3) forming a desired first capacitor electrode by etching away leaving any portion of the metal layer;
4) a step of etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film to form a desired capacitor dielectric; and 5) of the metal foil appearing after removing the dielectric thin film A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step of forming a conductive pattern including a desired second capacitor electrode by etching away leaving at least an arbitrary portion including a capacitor dielectric.

17. The multilayer wiring board with a built-in capacitor according to claim 16, wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. Manufacturing method.

A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. :
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) forming a metal layer of 0.1 to 5 μm on the surface of the dielectric thin film;
3) forming a metal plating resist leaving an arbitrary portion including the first capacitor electrode;
4) forming a 10-50 μm first capacitor electrode by metal plating;
5) removing the metal plating resist;
6) a step of etching away a 0.1 to 5 μm metal layer formed on the surface of the dielectric thin film;
7) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
8) A step of forming a conductive pattern including a desired second capacitor electrode by removing the dielectric thin film by etching, leaving at least an arbitrary portion including the capacitor dielectric, of the metal layer that appears after removing the dielectric thin film. The manufacturing method of the multilayer wiring board with a built-in capacitor.

19. The multilayer wiring board with a built-in capacitor according to claim 18, wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. Manufacturing method.

20. The method for producing a multilayer wiring board with a built-in capacitor according to claim 18, wherein the metal plating contains at least one metal selected from the group consisting of copper, silver, tin, nickel, and zinc.

A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. :
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) forming a desired first capacitor electrode by forming a 10-50 μm metal layer on an arbitrary portion of the surface of the dielectric thin film using a conductive paste that is metallized by chemical reaction;
3) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
4) A step of forming a conductor pattern including a desired second capacitor electrode by removing the dielectric thin film by etching and leaving at least an arbitrary portion including the capacitor dielectric of the metal foil that has appeared after removing the dielectric thin film. A method of manufacturing a multilayer wiring board with a built-in capacitor.

The metal particles of the conductive paste that are metallized by a chemical reaction include at least one metal selected from the group consisting of gold, platinum, silver, copper, palladium, and ruthenium, and the average particle size thereof is The method for producing a multilayer wiring board with a built-in capacitor according to claim 21, wherein the thickness is 0.1 to 10 nm.

A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. :
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) etching away leaving any portion of the dielectric thin film to form the desired capacitor dielectric;
3) forming a 10 to 50 μm metal layer on the substrate surface on which the capacitor dielectric is formed;
4) having a step of forming an arbitrary conductive pattern electrically insulated from the desired first capacitor electrode, the second capacitor electrode, and the capacitor electrode by etching away leaving any portion of the metal layer; A method of manufacturing a multilayer wiring board with a built-in capacitor.

A metal foil surface of a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil, and a substrate having a conductor circuit The prepreg laminated through the insulating material is provided with a through hole of an insulating material at an arbitrary position, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler. The manufacturing method of the multilayer wiring board with a built-in capacitor | condenser in any one of -23.

A metal foil surface of a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil, and a substrate having a conductor circuit The prepreg laminated through the insulating material is provided with a through hole of an insulating material at an arbitrary position, and the through hole is filled with a conductive paste that is metallized by a chemical reaction. The manufacturing method of the multilayer wiring board with a built-in capacitor | condenser in any one of -23.

A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. :
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) forming a 10-50 μm metal layer on the surface of the dielectric thin film;
3) forming a desired first capacitor electrode by etching away leaving any portion of the metal layer;
4) forming a desired capacitor dielectric by etching away leaving any portion of the dielectric thin film including at least the first capacitor electrode;
5) A step of exposing an insulating layer of the cured prepreg by etching and removing an arbitrary portion of the metal foil that appears after removing the dielectric thin film;
6) removing the insulating layer exposed by laser irradiation, forming a hole, and exposing the inner conductive circuit;
7) forming a metal layer of 0.1 to 5 μm on the substrate surface;
8) a step of forming a plating resist except for an arbitrary portion including a hole;
9) A step of forming a metal layer of 10 to 50 μm on the substrate surface other than the place where the plating resist is formed and electrically connecting the circuit patterns between the layers;
10) a step of etching away a 0.1 to 5 μm metal layer formed on the substrate surface;
11) A multilayer wiring with a built-in capacitor, including a step of forming a conductive pattern including a desired second capacitor electrode by etching and removing an arbitrary portion including at least a capacitor dielectric and a hole made into a conductor. A manufacturing method of a board.

27. The multilayer wiring board with a built-in capacitor according to claim 26, wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. Manufacturing method.

A method for producing a capacitor built-in multilayer wiring board using a capacitor built-in multilayer wiring board material in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. ,
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) forming a metal layer of 0.1 to 5 μm on the surface of the dielectric thin film;
3) forming a metal plating resist leaving an arbitrary portion including the first capacitor electrode;
4) forming a 10-50 μm first capacitor electrode by metal plating;
5) removing the metal plating resist;
6) a step of etching away a 0.1 to 5 μm metal layer formed on the surface of the dielectric thin film;
7) forming a desired capacitor dielectric by etching away leaving any portion of the dielectric thin film including at least the first capacitor electrode;
8) a step of exposing an insulating layer of the cured prepreg by etching and removing an arbitrary portion of the metal foil that appears by removing the dielectric thin film;
9) removing the insulating layer exposed by laser irradiation to form a hole, and exposing the inner conductive circuit;
10) forming a metal layer of 0.1 to 5 μm on the substrate surface;
11) A step of forming a plating resist except for an arbitrary portion including a hole;
12) a step of forming a metal layer of 10 to 50 μm on the substrate surface other than the place where the plating resist is formed and electrically connecting the circuit patterns between the layers;
13) etching and removing a 0.1 to 5 μm metal layer formed on the substrate surface;
14) A multilayer wiring with a built-in capacitor, comprising a step of forming a conductive pattern including a desired second capacitor electrode by etching and removing an arbitrary portion including at least a capacitor dielectric and a hole made into a conductor. A manufacturing method of a board.

29. The multilayer wiring board with a built-in capacitor according to claim 28, wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. Manufacturing method.

30. The method of manufacturing a multilayer wiring board with a built-in capacitor according to claim 28 or 29, wherein the metal plating includes at least one metal selected from the group consisting of copper, silver, tin, nickel, and zinc.

A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. :
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) forming a desired first capacitor electrode by forming a 10-50 μm metal layer on an arbitrary portion of the surface of the dielectric thin film using a conductive paste that is metallized by chemical reaction;
3) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
4) a step of exposing an insulating layer of the cured prepreg by etching and removing an arbitrary portion of the metal foil that appears after removing the dielectric thin film;
5) removing the insulating layer exposed by laser irradiation to form a hole, and exposing the inner conductive circuit;
6) forming a metal layer of 0.1 to 5 μm on the substrate surface;
7) a step of forming a plating resist except for an arbitrary portion including a hole;
8) A step of forming a metal layer of 10 to 50 μm on the substrate surface other than the place where the plating resist is formed and electrically connecting the circuit patterns between the layers;
9) etching and removing a 0.1 to 5 μm metal layer formed on the substrate surface;
10) A multilayer wiring with a built-in capacitor, comprising a step of forming a conductive pattern including a desired second capacitor electrode by etching and removing an arbitrary portion including at least a capacitor dielectric and a hole made into a conductor. A manufacturing method of a board.

The metal particles of the conductive paste that are metallized by a chemical reaction include at least one metal selected from the group consisting of gold, platinum, silver, copper, palladium, and ruthenium, and the average particle size thereof is 32. The method of manufacturing a multilayer wiring board with a built-in capacitor according to claim 31, wherein the thickness is 0.1 to 10 nm.

A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on a surface of a metal foil. :
1) a step of laminating a substrate having a conductor circuit on a surface of a metal foil of a multilayer wiring board material with a built-in capacitor via a prepreg;
2) forming a desired capacitor dielectric by etching away leaving any portion of the dielectric thin film;
3) a step of exposing an insulating layer of the cured prepreg by etching and removing an arbitrary portion of the metal layer that appears by removing the dielectric thin film;
4) removing the insulating layer exposed by laser irradiation, forming a hole, and exposing the inner conductive circuit;
5) forming a 10-50 μm metal layer on the substrate surface on which the capacitor dielectric is formed and the surface in the hole;
6) A multilayer wiring with a built-in capacitor, characterized by having a step of forming a conductive pattern including a desired second capacitor electrode by etching and removing an arbitrary portion including at least a capacitor dielectric and a hole made into a conductor. A manufacturing method of a board.

Conductor laminated via a prepreg on the surface of the metal foil of the capacitor built-in multilayer wiring board material having a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm provided on the surface of the metal foil 17. The substrate having a circuit, wherein the substrate has two or more conductor layers, and the circuit pattern of the adjacent conductor layer is a substrate connected by a hole formed as a conductor at an arbitrary position. A method for manufacturing a multilayer wiring board with a built-in capacitor according to any one of -33.

35. The capacitor built-in multilayer according to any one of claims 16 to 34, wherein a method of etching and removing the dielectric thin film is any one of an ion beam etching method, an RIE (Reactive Ion Etching) method, and a solution etching method. A method for manufacturing a wiring board.

36. The method of manufacturing a multilayer wiring board with a built-in capacitor according to any one of claims 16 to 35, wherein the second capacitor electrode is a ground layer or a power supply layer of the multilayer wiring board.

37. The method of manufacturing a multilayer wiring board with a built-in capacitor according to any one of claims 16 to 36, wherein the insulating material of the substrate is made of resin and glass woven fabric or glass nonwoven fabric.

The multilayer wiring board with a built-in capacitor according to any one of claims 16 to 37, wherein the resin used for the insulating material of the substrate is a thermosetting resin and has a glass transition temperature of 170 ° C or higher. Manufacturing method.

Dielectric having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm on the surface of the substrate having via holes connecting the conductor layers inside the substrate and having a smooth metal layer on the surface A substrate for a multilayer wiring board with a built-in capacitor, characterized by forming a thin film.

40. The multilayer wiring board substrate with a built-in capacitor according to claim 39, wherein the via holes are electrically connected by metal plating.

40. The multilayer wiring board substrate with a built-in capacitor according to claim 39, wherein the via holes are electrically connected by a conductive paste made of a metal filler and a resin.

The substrate for a multilayer wiring board with a built-in capacitor according to claim 39 or 41, wherein the via hole is electrically connected by a conductive paste that is metallized by a chemical reaction.

The dielectric thin film is any one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, or these 43. A multilayer wiring board with a built-in capacitor according to any one of claims 39 to 42, wherein the multilayer wiring board is a film comprising two or more kinds of solid solutions containing any of the above, or two or more kinds of laminated bodies containing any of these. Substrate.

44. The method according to claim 39, wherein the dielectric thin film is formed by any one of a vacuum deposition method, an ion plating method, a CVD (Chemical Vapor Deposition) method, a sputtering method, and a sol-gel method. The board for multilayer wiring boards with a built-in capacitor described in 1.

45. The substrate for a multilayer wiring board with a built-in capacitor according to any one of claims 39 to 44, wherein a substrate temperature at the time of forming the dielectric thin film is 25 ° C to 350 ° C.

46. The substrate for a multilayer wiring board with a built-in capacitor according to any one of claims 39 to 45, wherein the insulating material of the substrate is made of resin and glass woven fabric or glass nonwoven fabric.

The built-in capacitor according to any one of claims 39 to 46, wherein the resin used for the insulating material of the substrate is a thermosetting resin and has a glass transition temperature of 170 ° C or higher. Multi-layer circuit board.

The metal layer is made of copper, and one or more metal films selected from the group consisting of platinum, gold, silver, palladium, ruthenium and iridium are provided on the surface of the metal as a copper oxide protective film. 48. The substrate for a multilayer wiring board with a built-in capacitor according to any one of claims 39 to 47.

The metal layer is made of copper, and at least one metal film selected from the group consisting of chromium, molybdenum, titanium, and nickel is provided as a metal that forms a stable self-oxidation film on the surface of the metal layer. 48. The substrate for a multilayer wiring board with a built-in capacitor according to any one of claims 39 to 47.

50. The substrate for a multilayer wiring board with a built-in capacitor according to any one of claims 39 to 49, wherein a surface roughness of the metal layer is 0.01 to 0.5 [mu] m.

A method for producing a multilayer wiring board with a built-in capacitor using the capacitor built-in multilayer wiring board substrate according to any one of claims 39 to 50 as an inner layer board,
1) forming a 10-50 μm metal layer on the surface of the dielectric thin film;
2) forming a desired first capacitor electrode by etching away leaving any portion of the metal layer;
3) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
And 4) a step of forming a conductor pattern including a desired second capacitor electrode by etching and removing at least an arbitrary portion including the capacitor dielectric of the metal layer which appears after removing the dielectric thin film. A method of manufacturing a multilayer wiring board with a built-in capacitor.

52. The multilayer wiring with a built-in capacitor according to claim 51, wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. A manufacturing method of a board.

A method for producing a multilayer wiring board with a built-in capacitor using the capacitor built-in multilayer wiring board substrate according to any one of claims 39 to 50 as an inner layer board,
1) forming a metal layer of 0.1 to 5 μm on the surface of the dielectric thin film;
2) forming a metal plating resist leaving any portion including the first capacitor electrode;
3) forming a 10-50 μm first capacitor electrode by metal plating;
4) removing the metal plating resist;
5) a step of etching away the 0.1 to 5 μm metal layer formed on the surface of the dielectric thin film;
6) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
7) A step of forming a conductor pattern including a desired second capacitor electrode by removing the dielectric thin film by etching, leaving at least an arbitrary portion including the capacitor dielectric, of the metal layer appearing. A method of manufacturing a multilayer wiring board with a built-in capacitor.

54. The multilayer wiring board with a built-in capacitor according to claim 53, wherein the metal layer formed on the surface of the dielectric thin film includes at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel. Manufacturing method.

The manufacturing method of a multilayer wiring board with a built-in capacitor according to claim 53 or 54, wherein the metal plating includes at least one metal selected from the group consisting of copper, silver, tin, nickel, and zinc. Method.

A method for producing a multilayer wiring board with a built-in capacitor using the capacitor built-in multilayer wiring board substrate according to any one of claims 39 to 50 as an inner layer board,
1) forming a desired first capacitor electrode by forming a 10 to 50 μm metal layer on an arbitrary portion of the surface of the dielectric thin film using a conductive paste that is metallized by chemical reaction; ,
2) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
And 3) a step of forming a conductor pattern including a desired second capacitor electrode by removing the dielectric thin film by etching, leaving at least an arbitrary portion including the capacitor dielectric, of the metal layer that appears after removal of the dielectric thin film. The manufacturing method of the multilayer wiring board with a built-in capacitor.

The metal particles of the conductive paste that is metallized by a chemical reaction contains at least one metal selected from the group consisting of gold, platinum, silver, copper, palladium, ruthenium, and the average particle size is 57. The method of manufacturing a multilayer wiring board with a built-in capacitor according to claim 56, wherein the thickness is 0.1 to 10 nm.

A method for producing a multilayer wiring board with a built-in capacitor using the capacitor built-in multilayer wiring board substrate according to any one of claims 39 to 50 as an inner layer board,
1) forming a desired capacitor dielectric by etching away leaving any portion of the dielectric thin film;
2) forming a 10-50 μm metal layer on the substrate surface on which the capacitor dielectric is formed;
3) having a step of forming an arbitrary conductive pattern electrically insulated from the desired first capacitor electrode, the second capacitor electrode, and the capacitor electrode by etching and removing an arbitrary portion of the metal layer; A method of manufacturing a multilayer wiring board with a built-in capacitor.

59. The capacitor built-in according to any one of claims 51 to 58, wherein a method of etching and removing the dielectric thin film is any one of an ion beam etching method, an RIE (Reactive Ion Etching) method, and a solution etching method. A method of manufacturing a multilayer wiring board.

60. The method of manufacturing a multilayer wiring board with a built-in capacitor according to any one of claims 51 to 59, wherein the second capacitor electrode is a ground layer or a power supply layer of the multilayer wiring board.

A multilayer wiring board having a plurality of insulating layers, a plurality of conductor layers, and a conductive via hole that electrically connects the conductor layers, and a relative dielectric constant of at least one insulating layer is 20 to 2000; And it is a dielectric thin film with a film thickness of 0.1-1 μm, and is a multilayer wiring board with a built-in capacitor provided with an electrode facing the insulating layer,
1) The pattern of the conductor layer forming the first capacitor electrode all forms the capacitor electrode,
2) The projection surface of the dielectric thin film includes the projection surface of the first capacitor electrode,
3) A multilayer wiring board with a built-in capacitor, wherein the conductive layer forming the second capacitor electrode has a second capacitor electrode and at least one pattern electrically insulated from the electrode.

A multilayer wiring board having a plurality of insulating layers, a plurality of conductor layers, and a conductive via hole that electrically connects the conductor layers, and a relative dielectric constant of at least one insulating layer is 20 to 2000; And it is a dielectric thin film with a film thickness of 0.1-1 μm, and is a multilayer wiring board with a built-in capacitor provided with an electrode facing the insulating layer,
1) having a first capacitor electrode included in the projection surface of the dielectric thin film that forms the dielectric of the capacitor;
2) A multilayer wiring board with a built-in capacitor, wherein a conductor layer that forms the first capacitor electrode is electrically connected to the second capacitor electrode at all ends of the dielectric thin film.

63. The multilayer wiring board with a built-in capacitor according to claim 61, wherein the second capacitor electrode is a ground layer or a power supply layer of the multilayer wiring board.

Dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, or any of these 64. A multilayer wiring board with a built-in capacitor according to any one of claims 61 to 63, wherein the multilayer wiring board includes two or more kinds of solid solutions containing or a film made of two or more kinds of laminated bodies containing any of these. .

65. The capacitor built-in multilayer wiring board according to any one of claims 61 to 64, wherein the insulating material of the substrate is made of resin and glass woven fabric or glass nonwoven fabric.

66. The multilayer capacitor with a built-in capacitor according to claim 61, wherein the resin used for the insulating material of the substrate is a thermosetting resin and has a glass transition temperature of 170 ° C. or higher. Wiring board.

The second capacitor electrode is made of copper, and at least one metal layer selected from the group consisting of platinum, gold, silver, palladium, ruthenium, iridium, chromium, molybdenum, titanium, and nickel is formed on the surface thereof. The multilayer wiring board with a built-in capacitor according to any one of claims 61 to 66, wherein the multilayer wiring board has a built-in capacitor.

68. The multilayer wiring board with a built-in capacitor according to claim 61, wherein the second capacitor electrode has a surface roughness of 0.01 to 0.5 [mu] m.

61. The first capacitor electrode includes at least one metal layer selected from the group consisting of copper, silver, tin, nickel, zinc, chromium, molybdenum, titanium, and nickel. 68. A multilayer wiring board with a built-in capacitor according to any one of 68.

The first capacitor electrode is made of a conductive paste metallized by a chemical reaction, and the metal is at least one selected from the group consisting of platinum, gold, silver, copper, tin, palladium, and ruthenium. 69. The capacitor built-in multilayer wiring board according to any one of claims 61 to 68, comprising:

71. A semiconductor device, wherein a semiconductor chip is mounted on the capacitor built-in multilayer wiring board according to claim 61.

Insulating material such that the metal foil is in contact with the insulating material, the material for a multilayer wiring board with a built-in capacitor having a dielectric thin film with a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm provided on one side of the metal foil A method of manufacturing a multilayer wiring board with a built-in capacitor using a substrate provided on at least one side of
1) forming a metal layer serving as a capacitor electrode at a predetermined position on the dielectric thin film on the substrate surface;
2) forming an etching resist on at least the metal layer on the substrate surface;
3) wet etching the dielectric thin film with an etchant containing a chelating agent and hydrogen peroxide;
4) A method for producing a multilayer wiring board with a built-in capacitor, comprising a step of removing an etching resist after wet etching.

The chelating agent concentration of the etchant is 0.001 to 0.5 mol / l, the hydrogen peroxide concentration is 1 to 50 wt%, and the pH of the etchant is in the range of 2 to 7. The method for producing a multilayer wiring board with a built-in capacitor according to claim 72.

The chelating agent is at least one selected from the group consisting of ethylenediaminetetraacetic acid (EDTA), hydroxyethyliminodiacetic acid (HIDA), iminodiacetic acid (IDA), dihydroxyethylglycine (DHEG), and alkali salts thereof. The method for producing a multilayer wiring board with a built-in capacitor according to claim 72 or 73.

Insulating material such that the metal foil is in contact with the insulating material, the material for a multilayer wiring board with a built-in capacitor having a dielectric thin film with a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm provided on one side of the metal foil A method of manufacturing a multilayer wiring board with a built-in capacitor using a substrate provided on at least one side of
1) forming a metal layer serving as a capacitor electrode at a predetermined position on the dielectric thin film on the substrate surface;
2) forming an etching resist on at least the metal layer on the substrate surface;
3) wet etching the dielectric thin film with an etchant containing at least one acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid and acetic acid and hydrogen peroxide;
4) A method for producing a multilayer wiring board with a built-in capacitor, comprising a step of removing an etching resist after wet etching.

The method for producing a multilayer wiring board with a built-in capacitor according to claim 75, wherein the acid concentration of the etchant is 1 to 30 wt% and the hydrogen peroxide concentration is 1 to 50 wt%.

77. The method for producing a multilayer wiring board with a built-in capacitor according to any one of claims 72 to 76, wherein a photosensitive dry film is used as an etching resist.

78. The film thickness of the photosensitive dry film is 1 to 3 times the thickness of the metal layer serving as a capacitor electrode protected from wet etching by an etching resist formed by the photosensitive dry film. The manufacturing method of the multilayer wiring board with a built-in capacitor | condenser described.

The method for producing a multilayer wiring board with a built-in capacitor according to any one of claims 72 to 78, wherein the wet etching of the dielectric thin film is performed with an etchant having a liquid temperature of 20 to 45 ° C.

Dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate and lead zirconate, or any of these 80. The method for producing a multilayer wiring board with a built-in capacitor according to any one of claims 72 to 79, which is a film made of a solid solution containing any two or more of them or a laminate containing any two or more of these.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) A step of laminating a metal foil B on a surface of a metal foil A of a capacitor built-in multilayer wiring board material via an insulating material to form a substrate;
2) A step of etching and removing an arbitrary portion of the metal foil B to expose the insulating layer formed of the insulating material;
3) A step of removing the exposed insulating layer by laser irradiation to form a hole and exposing the metal foil A;
4) forming a metal layer on both surfaces of the substrate surface including the inside of the hole;
5) a step of forming a first capacitor electrode pattern of an arbitrary shape from a metal layer on a dielectric thin film of a capacitor-embedded multilayer wiring board material by etching;
6) forming a capacitor dielectric of any shape including the first capacitor electrode pattern from the exposed dielectric thin film by etching;
7) Production of a multilayer wiring board with a built-in capacitor, comprising a step of forming a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A that appears after removing the dielectric thin film. Method.

82. The method of manufacturing a multilayer wiring board with a built-in capacitor according to claim 81, wherein in the etching step of 5) or 7), a circuit having an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated. To manufacture a multilayer wiring board with a built-in capacitor.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) A step of laminating a metal foil B on a surface of a metal foil A of a capacitor built-in multilayer wiring board material via an insulating material to form a substrate;
2) A step of exposing the metal foil A by removing the metal foil B and the insulating layer formed of the insulating material at the same time by irradiating a laser on an arbitrary portion of the metal foil B to form a hole;
3) forming a metal layer on both surfaces of the substrate surface including the inside of the hole;
4) a step of forming a first capacitor electrode pattern having an arbitrary shape from a metal layer on a dielectric thin film of a capacitor-embedded multilayer wiring board material by etching;
5) forming a capacitor dielectric of any shape including the first capacitor electrode pattern from the exposed dielectric thin film by etching;
6) Manufacture of a multilayer wiring board with a built-in capacitor, comprising a step of etching a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern from the metal foil A that appears after removing the dielectric thin film. Method.

84. The method of manufacturing a multilayer wiring board with a built-in capacitor according to claim 83, wherein in the etching step of 4) or 6), a circuit having an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated. To manufacture a multilayer wiring board with a built-in capacitor.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) Insulating material in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor built-in multilayer wiring board material, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler A step of laminating the metal foil B through the substrate to form a substrate;
2) forming a metal layer on at least the dielectric thin film side of the substrate surface;
3) forming a first capacitor electrode pattern of an arbitrary shape from a metal layer on the dielectric thin film of the capacitor-embedded multilayer wiring board material by etching;
4) forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern from the exposed dielectric thin film by etching;
5) Manufacture of a multilayer wiring board with a built-in capacitor, comprising a step of etching a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern on the metal foil A that appears after removing the dielectric thin film. Method.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) Insulating material in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor and the through hole is filled with a conductive paste that is metallized by a chemical reaction A step of laminating the metal foil B through the substrate to form a substrate;
2) forming a metal layer on at least the dielectric thin film side of the substrate surface;
3) forming a first capacitor electrode pattern of an arbitrary shape from a metal layer on the dielectric thin film of the capacitor-embedded multilayer wiring board material by etching;
4) forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern from the exposed dielectric thin film by etching;
5) Manufacture of a multilayer wiring board with a built-in capacitor, comprising a step of etching a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern from the metal foil A that appears after removing the dielectric thin film. Method.

89. The method of manufacturing a multilayer wiring board with a built-in capacitor according to claim 85 or 86, wherein in the etching step of 3) or 5), a circuit having an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated. A method for producing a multilayer wiring board with a built-in capacitor.

The step of forming at least one other metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel between the dielectric thin film and the metal layer is included. 87. A method for producing a multilayer wiring board with a built-in capacitor according to any one of 87.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) A step of laminating a metal foil B on a surface of a metal foil A of a capacitor built-in multilayer wiring board material via an insulating material to form a substrate;
2) A step of etching and removing an arbitrary portion of the metal foil B to expose the insulating layer formed of the insulating material;
3) removing the insulating layer exposed by laser irradiation to form a hole and exposing the metal foil A;
4) forming a metal layer of 0.1 to 5 μm on both sides of the substrate including the inside of the hole;
5) A step of forming a metal plating resist on the substrate surface leaving an arbitrary portion including a portion to be a first capacitor electrode and a hole portion;
6) A step of forming a conductor pattern on the portion including the hole and the portion to be the first capacitor electrode by metal plating;
7) removing the metal plating resist;
8) a step of etching away a 0.1 to 5 μm metal layer exposed on the substrate surface;
9) forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern from the exposed dielectric thin film by etching;
10) forming a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern by etching from the metal foil A that appears after removing the dielectric thin film;
11) A method for producing a multilayer wiring board with a built-in capacitor, comprising the step of forming a circuit by etching the exposed metal foil B.

On one side of the metal foil A, the relative dielectric constant is 10 to 2000 and the film thickness is 0.05 to 2. A method of manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor provided with a dielectric thin film of μm,
1) A step of laminating a metal foil B on a surface of a metal foil A of a capacitor built-in multilayer wiring board material via an insulating material to form a substrate;
2) A step of exposing the metal foil A by exposing the metal foil B to an arbitrary portion of the metal foil B by simultaneously removing the metal foil B and the insulating layer formed of the insulating material to form a hole;
3) forming a metal layer of 0.1 to 5 μm on both sides of the substrate including the inside of the hole;
4) A step of forming a metal plating resist on the substrate surface leaving an arbitrary portion including a portion to become the first capacitor electrode and a hole portion;
5) A step of forming a conductor pattern on the portion including the hole and the portion to be the first capacitor electrode by metal plating;
6) removing the metal plating resist;
7) a step of etching away a 0.1 to 5 μm metal layer exposed on the substrate surface;
8) forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern by etching from the exposed dielectric thin film;
9) forming a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern from the metal foil A that appears after removing the dielectric thin film;
10) A method for producing a multilayer wiring board with a built-in capacitor, comprising the step of forming a circuit by etching the exposed metal foil B.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) A prepreg in which a through hole is provided at an arbitrary location on the surface of the metal foil A of the capacitor wiring multilayer wiring board material and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler. A step of laminating metal foil B to form a substrate,
2) forming a metal layer of 0.1 to 5 μm on the surface of at least the dielectric thin film side of the substrate;
3) forming a metal plating resist on the substrate surface leaving an arbitrary portion including a portion to be the first capacitor electrode;
4) A step of forming a conductor pattern in a portion including a portion that becomes the first capacitor electrode by metal plating;
5) removing the metal plating resist;
6) a step of etching away a 0.1 to 5 μm metal layer exposed on the substrate surface;
7) forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern by etching from the exposed dielectric thin film;
8) A second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern is formed by etching from the metal foil A that appears after removing the dielectric thin film, and a circuit is formed by etching the exposed metal foil B. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) A prepreg filled with a conductive paste in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor wiring multilayer board material and the through hole is metallized by a chemical reaction. A step of laminating metal foil B to form a substrate,
2) forming a metal layer of 0.1 to 5 μm on the surface of at least the dielectric thin film side of the substrate;
3) forming a metal plating resist on the substrate surface leaving an arbitrary portion including a portion to be the first capacitor electrode;
4) A step of forming a conductor pattern in a portion including a portion that becomes the first capacitor electrode by metal plating;
5) removing the metal plating resist;
6) a step of etching away a 0.1 to 5 μm metal layer exposed on the substrate surface;
7) forming a capacitor dielectric having an arbitrary shape including the first capacitor electrode pattern by etching from the exposed dielectric thin film;
8) A second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern is formed by etching from the metal foil A that appears after removing the dielectric thin film, and a circuit is formed by etching the exposed metal foil B. A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising a step.

The metal layer of 0.1 to 5 μm formed on at least the surface of the dielectric thin film is (1) at least one metal layer selected from the group consisting of chromium, molybdenum, titanium and nickel, or (2) copper Or at least one metal layer selected from the group consisting of silver, tin, nickel and zinc, or (3) at least one metal layer selected from the group consisting of chromium, molybdenum, titanium and nickel 95. A method of manufacturing a multilayer wiring board with a built-in capacitor according to any one of claims 89 to 92, comprising: and at least one metal layer selected from the group consisting of copper, silver, tin, nickel, and zinc. .

94. The capacitor according to claim 89, wherein the conductive pattern formed by metal plating contains at least one metal selected from the group consisting of copper, silver, tin, nickel, and zinc. Manufacturing method of built-in multilayer wiring board.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) Insulating material in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor built-in multilayer wiring board material, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler A step of laminating the metal foil B through the substrate to form a substrate;
2) a step of forming a desired first capacitor electrode by forming a metal layer on an arbitrary portion of the surface of the dielectric thin film using a conductive paste that is metallized by a chemical reaction;
3) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
4) A second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern is formed by etching from the metal foil A that appears after removing the dielectric thin film, and a circuit is formed by etching the exposed metal foil B. A process for producing a multilayer wiring board with a built-in capacitor, comprising a step.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) Insulating material in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor and the through hole is filled with a conductive paste that is metallized by a chemical reaction A step of laminating the metal foil B through the substrate to form a substrate;
2) a step of forming a desired first capacitor electrode by forming a metal layer on an arbitrary portion of the surface of the dielectric thin film using a conductive paste that is metallized by a chemical reaction;
3) forming a desired capacitor dielectric by etching away leaving any portion including at least the first capacitor electrode of the dielectric thin film;
4) A second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern is formed by etching from the metal foil A that appears after removing the dielectric thin film, and a circuit is formed by etching the exposed metal foil B. A process for producing a multilayer wiring board with a built-in capacitor, comprising a step.

A method for manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil A. And
1) a step of laminating a metal foil B on a surface of a metal foil A of a capacitor-embedded multilayer wiring board material with an insulating material to form a substrate;
2) Etching away leaving any portion of the dielectric thin film to form the desired capacitor dielectric;
3) etching and removing an arbitrary portion of the metal foil B to expose the insulating layer formed of the insulating material;
4) removing the insulating layer exposed by laser irradiation to form a hole and exposing the metal foil A;
5) forming a metal layer on both surfaces of the substrate surface including the inside of the hole;
6) A multilayer wiring board with a built-in capacitor, which includes a step of forming a desired first capacitor electrode and a second capacitor electrode by etching and removing an arbitrary portion of the metal layer and the metal foil A. Manufacturing method.

A method for manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on the surface of the metal foil A. And
1) A step of laminating a metal foil B on a surface of a metal foil A of a capacitor built-in multilayer wiring board material via an insulating material to form a substrate;
2) Etching away leaving any portion of the dielectric thin film to form the desired capacitor dielectric;
3) A step of exposing the metal foil A by exposing the metal foil B and the insulating layer formed from the insulating material by simultaneously irradiating a laser beam to an arbitrary portion of the metal foil B, thereby forming a hole;
4) forming a metal layer on both surfaces of the substrate surface including the inside of the hole;
5) A multilayer wiring board with a built-in capacitor, which includes a step of forming a desired first capacitor electrode and a second capacitor electrode by etching and removing an arbitrary portion of the metal layer and the metal foil A. Manufacturing method.

A method for manufacturing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) Insulating material in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the capacitor built-in multilayer wiring board material, and the through hole is filled with a conductive paste containing a thermosetting resin and a metal filler A step of laminating the metal foil B through the substrate to form a substrate;
2) Etching away leaving any portion of the dielectric thin film to form the desired capacitor dielectric;
3) forming a metal layer on at least the surface of the substrate having the capacitor dielectric;
4) A multilayer wiring board with a built-in capacitor, which includes a step of forming a desired first capacitor electrode and a second capacitor electrode by etching and removing the metal layer and an arbitrary portion of the metal foil A. Manufacturing method.

A method for producing a multilayer wiring board with a built-in capacitor using a material for a multilayer wiring board with a built-in capacitor, in which a dielectric thin film having a relative dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 μm is provided on one side of the metal foil A. And
1) Insulating material in which a through hole is provided at an arbitrary position on the surface of the metal foil A of the multilayer wiring board material with a built-in capacitor and the through hole is filled with a conductive paste that is metallized by a chemical reaction A step of laminating the metal foil B through the substrate to form a substrate;
2) Etching away leaving any portion of the dielectric thin film to form the desired capacitor dielectric;
3) forming a metal layer on at least the surface of the substrate having the capacitor dielectric;
4) A multilayer wiring board with a built-in capacitor, which includes a step of forming a desired first capacitor electrode and a second capacitor electrode by etching and removing the metal layer and an arbitrary portion of the metal foil A. Manufacturing method.

The conductive paste that is metallized by a chemical reaction includes at least one metal particle selected from the group consisting of gold, platinum, silver, copper, palladium, and ruthenium, and the average particle diameter of the metal particles 100. The method for producing a multilayer wiring board with a built-in capacitor according to claim 86, 92, 95, 96 or 100, wherein the thickness is 0.1 to 10 nm.

102. The multilayer wiring with a built-in capacitor according to any one of claims 81 to 101, wherein a method of etching and removing the dielectric thin film is any one of an ion beam etching method, an RIE (Reactive Ion Etching) method, and a solution etching method. A manufacturing method of a board.

The method for producing a multilayer wiring board with a built-in capacitor according to any one of claims 81 to 102, wherein the second capacitor electrode is a ground layer or a power supply layer of the multilayer wiring board.

The method for producing a multilayer wiring board with a built-in capacitor according to any one of claims 81 to 103, wherein the insulating material used for forming the insulating layer of the substrate is a prepreg made of resin and glass woven fabric or glass nonwoven fabric.

The insulating material used for forming the insulating layer of the substrate is a prepreg containing a thermosetting resin as a resin, and the glass transition temperature of the thermosetting resin is 170 ° C or higher. The manufacturing method of the multilayer wiring board with a built-in capacitor | condenser in any one of 81-104.

Dielectric thin film is barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, bismuth titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, barium strontium titanate, titanate Capacitor built-in multilayer wiring which is a film made of any one of lead zirconate and magnesium niobate-lead titanate, a solid solution containing any two or more of these, or a laminate containing any two or more of these The method for manufacturing a multilayer wiring board with a built-in capacitor according to any one of claims 81 to 105, wherein a board material is used.

One or more selected from the group consisting of platinum, gold, silver, palladium, ruthenium, and iridium as the metal that forms the copper oxide protective film on the surface on which the metal foil A is made of copper and the dielectric thin film is formed. The method for producing a multilayer wiring board with a built-in capacitor according to any one of claims 81 to 106, wherein a material for the multilayer wiring board with a built-in capacitor provided with a metal film is used.

One or more metal films selected from the group consisting of chromium, molybdenum, titanium, and nickel are used as the metal that forms a stable self-oxidation film on the surface on which the metal foil A is made of copper and the dielectric thin film is formed. The method for manufacturing a multilayer wiring board with a built-in capacitor according to any one of claims 81 to 106, wherein the provided material for a multilayer wiring board with a built-in capacitor is used.

109. A capacitor built-in multilayer wiring board material having a surface roughness of 0.01 to 0.5 [mu] m on the surface of the metal foil A on which the dielectric thin film is formed is used. Manufacturing method for multilayer wiring boards with built-in capacitors.