TWI251536B

TWI251536B - Material for multilayer printed circuit board with built-in capacitor, substrate for multilayer printed circuit board, multilayer printed circuit board and methods for producing those

Info

Publication number: TWI251536B
Application number: TW93107141A
Authority: TW
Inventors: Yasushi Shimada; Yuusuke Kondou; Ken Madarame; Kazuhisa Otsuka; Yuichi Shimayama
Original assignee: Hitachi Chemical Co Ltd
Priority date: 2003-03-20
Filing date: 2004-03-17
Publication date: 2006-03-21
Also published as: TW200424059A; JPWO2004084597A1; WO2004084597A1; JP4192946B2

Abstract

The present invention relates to material for a multilayer printed circuit board with built-in capacitor having a dielectric thin film having a relative dielectric constant of 10-2,000 and a thickness of 0.05-2 mum formed on a surface of a metal foil, a substrate for a multilayer printed circuit board, a multilayer printed circuit board, and methods for producing them. The present invention provides a multilayer printed circuit board with built-in capacitor which is excellent in high-density wiring and economical efficiency.

Description

1251536 (1) 玖、發明說明【發明所屬之技術領域】本發明係關於內設電容器之多層配線板用材料、多層配線板用基板及多層配線板與這些的製造方法。【先前技術】1251536 (1) Technical Field of the Invention The present invention relates to a material for a multilayer wiring board in which a capacitor is provided, a substrate for a multilayer wiring board, and a multilayer wiring board, and a method for manufacturing the same. [Prior Art]

近年來，電子機器對於小型化及高機能化之要求逐臼增加。隨著機器之高機能化，載置之以半導體晶片及電容器爲首之被動元件等電子構件點數亦增加，傳統之高密度化技術已極爲難以對應小型化。因此，以更具效率之以安裝爲目的而將載置構件之一部份內設於配線板內部之內設化更爲必要。In recent years, the demand for miniaturization and high performance of electronic devices has increased. With the high performance of the machine, the number of electronic components such as passive components such as semiconductor chips and capacitors has increased, and the conventional high-density technology has been extremely difficult to cope with miniaturization. Therefore, it is more necessary to provide a part of the mounting member in the inside of the wiring board for the purpose of mounting more efficiently.

內設於多層配線板之電容器之容量，爲數百p F〜數 //F電平，需要500pF/mm2以上之電容密度。電容器之介電質，有採用樹脂及高介電常數無機塡料之合成材料之方法、及採用無機薄膜材料之方法。爲了形成高電容密度之電容器，1)採用高電容率之介電質、及2)採用厚度較薄之介電質係有效之方法。以前者之合成材料而言，1 ) 因爲樹脂本身之介電常數相對較低故高介電常數化有其限度、及2 )技術上要形成漏洩電流且膜厚爲數// m電平之絶緣膜極爲困難，故難以獲得5 0 0PF/mm2以上之電容密度之電容器。因此，爲了獲得5 00PF/mm2以上之電容密度之電容器，必須利用膜厚可以數// m以下形成之無機薄膜。利用樹脂之多層配線板當中，薄膜電容器之內設化手 -6- 1251536 (2) 法有利用第4頁、、第1圖號公報之 (日本特本特開平用這些手之介電質然而 226844 f 拉至任意 ’電路圖，曰本特意位置之效益。其 8-213758 獨立之電: 【發明內: 本發〜2000且電容器之基板、及依據 CVD法之方法（日本特開平5-191〇53號公報之第1圖；日本特開平5-226844號公報之第4頁 )、利用濺鍍法之方法（日本特開2 0 0 2 - 2 5 2 2 9 7 第6頁、第]圖）、或利用溶膠-凝膠法之方法開平8-2 1 3 754號公報之第12頁、第21圖；日 8 -2 1 3 7 5 8號公報之第14頁、第21圖）等。利法’可在利用樹脂之多層配線板中形成膜厚較薄薄膜。 ’日本特開平5 - 1 9 1 05 3號公報及日本特開平5_ E公報揭示之手法，因爲無法針對電容器電極以位置來形成圖案，故高密度配線化有其限度。又案上難以控制以形成薄膜爲目的之薄膜厚度。又開2002-252297號公報揭示之手法時，以拉至任方式來形成圖案之步驟會十分複雜，故不具經濟次，日本特開平8-213754號公報及日本特開平號公報揭示之手法時，難以在同一平面上形成源圖案。明係關於具有在金屬箔表面配設著電容率爲10 膜厚爲0.05〜2//m之介電質薄膜之特徵之內設多層配線板用材料、內設電容器之多層配線板用內設電容器之多層配線板之製造方法。本發明實施形態，可提供膜層均一之電容誤差較 -7- (3) 1251536 小之內設電容器之多層配線板。 A、本發明係和以下之實施形態相關。 (1 ) 一種內設電容器之多層配線板用材料，其特徵爲，金屬箔表面配設著電容率爲10〜2000且膜厚爲〇.〇5 〜之介電質薄膜。 (2 )如（1 )之內設電容器之多層配線板用材料，其特徵爲，介電質薄膜係由駄酸鋇、鈦酸緦、駄酸錦、欽酸鎂、鈦酸鉛、鈦酸鉍、二氧化鈦、锆酸鋇、銷酸鈣、鉻酸鉛、鈦酸鋇緦、锆鈦酸鉛、鎂鈮酸鉛-鈦酸鉛之其中任一種、或含有其中任2種以上之固溶體、或含有其中任2種以上之積層體所構成之膜。 (3 )如（1 )及（2 )之內設電容器之多層配線板用材料，其特徵爲，金屬箔係由銅所構成，且形成介電質薄膜之面上配設著金屬膜，前述金屬膜係銅之氧化保護覆膜，形成前述銅之氧化保護覆膜之金屬係從白金、金、銀、鈀、釕、以及銥所構成之群組所選取之1種以上。 (4 )如（1 )及（2 )之內設電容器之多層配線板用材料，其特徵爲，金屬箔係由銅所構成，且其表面配設著金屬膜，前述金屬膜係安定之自氧化覆膜，形成前述安定之自氧化覆膜之金屬係從鉻、鉬、鈦、以及鎳所構成之群組所選取之1種以上。 (5)如（1)〜（4)之其中任一項之內設電容器之多層配線板用材料，其特徵爲，金屬箔表面粗糙度爲0· 01 〜0.5 // m 〇 -8 - (4) 1251536 (6 ) —種內設電容器之多層配線板用材料之製造方法，其特徵爲，利用真空蒸鍍法在金屬箔表面形成電容率爲10〜2000且膜厚爲〇·05〜介電質薄膜。 (7 ) —種內設電容器之多層配線板用材料之製造方法，其特徵爲，利用離子鍍法在金屬箔表面形成電容率爲 10〜2000且膜厚爲〇·〇5〜2# m之介電質薄膜。The capacity of the capacitor built in the multilayer wiring board is several hundred p F to several //F level, and a capacitance density of 500 pF/mm 2 or more is required. The dielectric of the capacitor includes a method of using a synthetic material of a resin and a high dielectric constant inorganic tantalum, and a method of using an inorganic thin film material. In order to form a capacitor with a high capacitance density, 1) a dielectric material having a high permittivity, and 2) a method using a dielectric material having a relatively small thickness. In the former synthetic materials, 1) because the dielectric constant of the resin itself is relatively low, the high dielectric constant has its limit, and 2) the leakage current is technically formed and the film thickness is several m/m level. Since the insulating film is extremely difficult, it is difficult to obtain a capacitor having a capacitance density of 500 PF/mm 2 or more. Therefore, in order to obtain a capacitor having a capacitance density of 500 PF/mm2 or more, it is necessary to use an inorganic thin film which can be formed in a film thickness of / m or less. Among the multilayer wiring boards using resin, the internal capacitor of the film capacitor is -6- 1251536 (2). The method of using the 4th, 1st, and 1st drawings (Japanese Tebend Kaiping uses these hand dielectrics) 226844 f Pull to any 'circuit diagram, the benefit of this special position. Its 8-213758 independent power: [Invention: This is ~2000 and the substrate of the capacitor, and the method according to CVD method (Japanese special Kaiping 5-191〇) Japanese Patent Laid-Open No. Hei 5-226844 (page 4) and method using sputtering method (Japanese Patent Laid-Open No. 2 0 0 2 - 2 5 2 2 9 7 6th, pp.) Or, by the method of the sol-gel method, Kaiping No. 8-2 1 3 754, page 12, 21; day 8 -2 1 3 7 5 8 of the 14th, 21st, etc.) . The method can form a film having a thin film thickness in a multilayer wiring board using a resin. In the technique disclosed in Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. Hei. Further, it is difficult to control the film thickness for the purpose of forming a film. When the method disclosed in the publication No. 2002-252297 is opened, the step of forming a pattern by pulling the method is very complicated, and therefore, there is no economic time, and the method disclosed in Japanese Laid-Open Patent Publication No. 8-213754 and Japanese Patent Laid-Open Publication No. It is difficult to form a source pattern on the same plane. In the case of a dielectric film having a dielectric constant of 10 to a thickness of 0.05 to 2/m on the surface of a metal foil, a material for a multilayer wiring board and a built-in capacitor for a multilayer wiring board are provided. A method of manufacturing a multilayer wiring board of a capacitor. According to the embodiment of the present invention, it is possible to provide a multilayer wiring board having a capacitor having a uniform capacitance error of less than -7-(3) 1251536. A. The present invention relates to the following embodiments. (1) A material for a multilayer wiring board in which a capacitor is provided, wherein a surface of the metal foil is provided with a dielectric film having a permittivity of 10 to 2,000 and a film thickness of 〇. (2) A material for a multilayer wiring board having a capacitor as set forth in (1), characterized in that the dielectric film is made of bismuth ruthenate, strontium titanate, bismuth ruthenate, magnesium citrate, lead titanate, and titanic acid. Any one of cerium, titanium dioxide, cerium zirconate, calcium hydride, lead chromate, barium titanate, lead zirconate titanate, lead magnesium citrate-lead titanate, or a solid solution containing two or more of them Or a film comprising any two or more of the laminates. (3) A material for a multilayer wiring board having a capacitor provided in (1) and (2), wherein the metal foil is made of copper, and a metal film is disposed on a surface on which the dielectric film is formed, The metal film is an oxidized protective film of copper, and the metal forming the oxidized protective film of the copper is one or more selected from the group consisting of platinum, gold, silver, palladium, rhodium, and iridium. (4) A material for a multilayer wiring board having a capacitor provided in (1) and (2), wherein the metal foil is made of copper, and a metal film is disposed on a surface thereof, and the metal film is stabilized The oxide film is one or more selected from the group consisting of chromium, molybdenum, titanium, and nickel. (5) A material for a multilayer wiring board having a capacitor built in any one of (1) to (4), characterized in that the surface roughness of the metal foil is 0·01 ～ 0.5 // m 〇 -8 - ( 4) 1251536 (6) A method for producing a material for a multilayer wiring board in which a capacitor is built, characterized in that a capacitance ratio of 10 to 2000 is formed on the surface of the metal foil by a vacuum evaporation method, and the film thickness is 〇·05~ Electrochemical film. (7) A method for producing a material for a multilayer wiring board in which a capacitor is provided, characterized in that a permittivity of 10 to 2000 is formed on the surface of the metal foil by ion plating, and the film thickness is 〇·〇5 to 2# m Dielectric film.

(8 ) —種內設電容器之多層配線板用材料之製造方法，其特徵爲，利用 CVD ( Chemical Vapor Deposition) 法在金屬箱表面形成電容率爲10〜2000且膜厚爲0.05〜2 //ni之介電質薄膜。 (9 ) 一種內設電容器之多層配線板用材料之製造方法，其特徵爲，利用濺鍍法在金屬箔表面形成電容率爲 10〜2000且膜厚爲0.05〜2// m之介電質薄膜。(8) A method for producing a material for a multilayer wiring board in which a capacitor is provided, characterized in that a capacitance ratio of 10 to 2000 and a film thickness of 0.05 to 2 are formed on a surface of a metal case by a CVD (Chemical Vapor Deposition) method. Ni dielectric film. (9) A method for producing a material for a multilayer wiring board in which a capacitor is provided, characterized in that a dielectric material having a permittivity of 10 to 2,000 and a film thickness of 0.05 to 2/m is formed on the surface of the metal foil by sputtering. film.

(1 〇 ) —種內設電容器之多層配線板用材料之製造方法，其特徵爲，利用溶膠-凝膠法在金屬箔表面形成電容率爲10〜2000且膜厚爲0.05〜2//m之介電質薄膜。 (1 1 )如（6 )〜（1 0 )之其中任一項之內設電容器之多層配線板材料之製造方法，其特徵爲，利用滾筒狀金屬箔且在定溫管理之加熱爐內連續移動金屬箔來形成介電質薄膜。 (1 2 )如（6 )〜（1 1 )之其中任一項之內設電容器之多層配線板用材料之製造方法，其特徵爲，介電質薄膜係由鈦酸鋇、鈦酸緦、鈦酸鈣、鈦酸鎂、鈦酸鉛、鈦酸鉍、二氧化鈦、锆酸鋇、銷酸鈣、鉻酸鉛、鈦酸鋇緦、鉻鈦 -9- (5) 1251536 酸鉛、鎂鈮酸鉛-鈦酸鉛之其中任〜種、或含有其中任2 種以上之固溶體、或含有其中任2種以上之積層體所構成之膜。 (1 3 )如（6 )〜（U )之其中任一項之內設電容器之多層配線板用材料之製造方法，其特徵爲，金屬箔係由銅所構成，且形成介電質薄膜之面上配設著金屬膜，前述金屬膜係銅之氧化保護覆膜，形成前述銅之氧化保護覆膜之金屬係從白金、金、銀、鈀、釕、以及銥所構成之群組所選取之1種以上。 (14) 如（6)〜（12)之其中任一項之內設電容器之多層配線板用材料之製造方法，其特徵爲，金屬箔係由銅所構成，且其表面配設著金屬膜，前述金屬膜係安定之自氧化覆膜，形成前述安定之自氧化覆膜之金屬係從鉻、鉬、鈦、以及鎳所構成之群組所選取之1種以上。 (15) 如（6)〜（14)之其中任一項之內設電容器之多層配線板用材料之製造方法，其特徵爲，金屬箔表面粗糙度爲〇·〇1〜0.5// m。 (1 6 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔表面配設著電容率爲1〇〜2000且膜厚爲0.05 〜2 # m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2 )用以在介電質薄膜表面形成1 〇〜5 0 // m 之金屬層之步驟；3)以保留該金屬層之任意部份之方式 -10- 1251536 (6) 進行蝕刻除去，形成期望之電容器電極1之步驟；4 )以保留至少含有介電質薄膜之電容器電極1之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及 5 )以保留至少含有除去介電質薄膜所露出之金屬層之電容器介電質之任意部份之方式進行鈾刻除去，形成含有期望之電容器電極2之導體圖案之步驟。 (1 7 )如（1 6 )之內設電容器之多層配線板之製造方法，其特徵爲，形成於介電質薄膜表面上之金屬層至少含有從鉻、鉬、鈦、以及鎳所構成之群組所選取之1種以上之金屬層。 (1 8 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔表面配設著電容率爲10〜2000且膜厚爲0.05 〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2)用以在介電質薄膜表面形成0.1〜5#m 之金屬層之步驟；3 )以保留含有電容器電極1之任意部份之方式，形成金屬電鍍抗蝕層之步驟；4 )用以利用金屬電鍍形成10〜50/im之電容器電極1之步驟；5)用以除去金屬電鍍抗蝕層之步驟；6 )用以蝕刻除去形成於介電質薄膜表面之0.1〜5//m之金屬層之步驟；7)以保留至少含有介電質薄膜之電容器電極1之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及8 ) 以保留至少含有除去介電質薄膜所露出之金屬層之電容器 -11- (7) 1251536 介電質之任意部份之方式進行蝕刻除去，形成含有期望之電容器電極2之導體圖案之步驟。 (1 9 )如（1 8 )之內設電容器之多層配線板之製造方法’其特徵爲，形成於介電質薄膜表面上之金屬層至少含有從鉻、鋁、鈦、以及鎳所構成之群組所選取之1種以上之金屬層。 (2 0 )如（1 8 )及（1 9 )之內設電容器之多層配線板之製造方法，其特徵爲，金屬電鍍至少含有從銅、銀、錫、鎳、以及鋅所構成之群組所選取之1種以上之金屬。 (2 1 ) —種內設電容器之多層配線板之製造方法，係採用傘屬箔表面配設著電容率爲10〜2000且膜厚爲〇.〇5 〜2 V m之介電質薄膜之內設電容器之多層配線板用材料 ’其特徵爲，具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2 )在介電質薄膜表面之任意部份，以利用化學反應實施金屬化之導電性糊形成1 〇〜5 0 // m之金屬層來形成期望之電容器電極1之步驟；3)以保留至少含有介電質薄膜之電容器電極1之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及4 )以保留至少含有除去介電質薄膜所露出之金屬層之電容器介電質之任意部份之方式進行蝕刻除去，形成含有期望之電容器電極2之導體圖案之步驟。 (22 )如（2 1 )之內設電容器之多層配線板之製造方法’其特徵爲，利用化學反應實施金屬化之導電性糊之金 -12- (8) 1251536 屬粒子至少含有從金、白金、銀、銅、鈀、以及釕所構成之群組所選取之1種以上之金屬’且其平均粒徑爲0 ·1〜 1 Onm 〇 (2 3 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔表面配設著電容率爲10〜2000且膜厚爲〇。〇5 〜2 μ m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2 )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3 )用以在形成電容器介電質之基板表面形成1〇〜50//m之金屬層之步驟；以及4 )以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之與電容器電極1、電容器電極2 、及電容器電極爲電性絶緣之任意導體圖案之步驟。 (24)如（16)〜（23)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，在利用金屬箔表面配設著電容率爲10〜2000且膜厚爲〇.〇5〜2//m之介電質薄膜之內設電容器之多層配線板用材料之金屬箔面、及具有導體電路之基板實施積層之半固化片之任意部位上，配設絶緣材料之貫穿孔’且該貫穿孔以含有熱硬化性樹脂及金屬塡料之導電性糊實施充塡。 (25 )如（16)〜（23 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，在利用金屬箔表面配設著電容率爲10〜2〇〇〇且膜厚爲〇.05〜2//m之介電質 (9) 1251536 薄膜之內設電容器之多層配線板用材料之金屬箔面、及具有導體電路之基板貫®也積層之半固化片之任思部位上’配設絶緣材料之貫穿孔’且該貫穿孔以利用化學反應實施金屬化之導電性糊實施充塡。 (2 6 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔表面配設著電容率爲10〜2000且膜厚爲〇·〇5 〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2)在介電質薄膜表面形成10〜50//m之金屬層之步驟；3 )以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之電容器電極1之步驟；4 )以保留至少含有介電質薄膜之電容器電極1之任意部份之方式進行鈾刻除去，形成期望之電容器介電質之步驟；5 )用以蝕刻除去因除去介電質薄膜而露出之任意部位，而使硬化之半固化片之絶緣層露出之步驟；6 )利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟； 7 )用以在該基板表面形成〇 . 1〜5 // m之金屬層之步驟；8 )用以在含有孔之任意部位以外之部位上形成電鍍抗蝕層之步驟；9 )在形成電鍍抗蝕層之部位以外之基板表面形成1 0〜5 0 // m之金屬層，用以電性連結層間之電路圖案之步驟；1 0 )用以對形成於基板表面上之0. 1〜5 // m之金屬層實施蝕刻除去之步驟；以及1 1 )以至少保留含有電容器介電質、及導體化之孔在內之任意部份之方式進行蝕 -14- (10) 1251536 %除去，形成期望之含有電容器電極2之導體圖案之步驟〇 (27 )如（26 )之內設電容器之多層配線板之製造方 & ’其特徵爲，形成於介電質薄膜表面之金屬層至少含有從銘、鉬、鈦、以及鎳所構成之群組所選取之1種以上之金屬層。 (2 8 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔表面配設著電容率爲10〜2000且膜厚爲0.05 〜2Vm之介電質薄膜之內設電容器之多層配線板用材料 ’其特徵爲，具有·· 1 )用以在內設電容器之多層配線板材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2)用以在介電質薄膜表面形成〇·1〜5//m t金屬層之步驟；3)以保留含有電容器電極1之任意部份之方式，形成金屬電鍍抗蝕層之步驟；4 )用以利用金屬電鏟形成10〜50//m之電容器電極1之步驟；5)用以除去金屬電鍍抗蝕層之步驟；6 )用以蝕刻除去形成於介電質薄膜表面之0.1〜5//m之金屬層之步驟；7)以保留至少含有介電質薄膜之電容器電極1之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；8 )用以蝕刻除去因除去介電質薄膜而露出之任意部位，而使硬化之半固化片之絶緣層露出之步驟；9 )利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟； 1 0 )用以在該基板表面形成〇 · 1〜5 // ηι之金屬層之步驟； 1 1 )用以在含有孔之任意部位以外之部位上形成電鍍抗鈾 -15- (11) 1251536 層之步驟；1 2 )在形成電鍍抗蝕層之部位以外之基板表面形成1 0〜5 0 // m之金屬層，用以電性連結層間之電路圖案之步驟；1 3 )用以對形成於基板表面上之〇 · 1〜5 // m之金屬層實施蝕刻除去之步驟；以及1 4 )以至少保留含有電容器介電質、及導體化之孔在內之任意部份之方式進行蝕刻除去，形成期望之含有電容器電極2之導體圖案之步驟。 (29 )如（28 )之內設電容器之多層配線板之製造方法’其特徵爲，形成於介電質薄膜表面上之金屬層至少含有從鉻、鉬、鈦、以及鎳所構成之群組所選取之1種以上之金屬層。 (30 )如（28 )及（29 )記載之內設電容器之多層配線板之製造方法，其特徵爲，金屬電鍍至少含有從銅、銀、錫、鎳、以及鋅所構成之群組所選取之1種以上之金屬〇 (3 1 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔表面配設著電容率爲10〜2000且膜厚爲0.05 〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2 )在介電質薄膜表面之任意部份上，以利用化學反應實施金屬化之導電性糊形成1 0〜5 0 // m之金屬層，來形成期望之電容器電極1之步驟；3 )以保留至少含有介電質薄膜之電容器電極1之任意部份之方式進行 -16- (12) 1251536 蝕刻除去，形成期望之電容器介電質之步驟；4 )用以刻除去因除去介電質薄膜而露出之任意部位，而使硬化半固化片之絶緣層露出之步驟；5 )利用雷射照射除去出之絶緣層來形成孔，而露出內層之導體電路之步驟； )在該基板表面形成0.1〜5//m之金屬層之步驟；7) 以在含有孔之任意部位以外之部位上形成電鍍抗蝕層之驟；8 )在形成電鍍抗蝕層之部位以外之基板表面形成〜5 0 // m之金屬層，用以電性連結層間之電路圖案之步 ;9 )用以蝕刻除去形成於基板表面之〇 . 1〜5 // m之金層之步驟；以及1 〇 )以至少保留含有電容器介電質、導體化之孔在內之任意部份之方式進行蝕刻除去，形成望之含有電容器電極2之導體圖案之步驟。 (3 2 )如（3 1 )之內設電容器之多層配線板之製造法，其特徵爲，利用化學反應實施金屬化之導電性糊之屬粒子至少含有從金、白金、銀、銅、鈀、以及釕所構之群組所選取之1種以上之金屬，且其平均粒徑爲〇 · 1 1 0 nm 〇 (3 3 ) —種內設電容器之多層配線板之製造方法，採用金屬箔表面配設著電容率爲1〇〜2〇〇〇且膜厚爲〇· 〜2 // m之介電質薄膜之內設電容器之多層配線板用材，其特徵爲，具有：1 )用以在內設電容器之多層配線用材料之金屬箔面上，利用半固化片積層具有導體電路基板之步驟；2 )以保留介電質薄膜任意部份之方式進蝕刻除去，形成期望之電容器介電質之步驟；3 )用以 •17- (13) 1251536 刻除去因除去介電質薄膜而露出之任意部位，而使硬化之半固化片之絶緣層露出之步驟；4 )利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟；5 )在形成電容器介電質之基板表面、及孔內之表面形成 1 0〜5 0 // m之金屬層之步驟；以及6 )以至少保留含有電容器介電質、及導體化之孔在內之任意部份之方式進行蝕刻除去，形成期望之含有電容器電極2之導體圖案之步驟〇 (3 4 )如（1 6 )〜（3 3 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，利用半固化片積層於金屬箱表面配設著電容率爲10〜2000且膜厚爲0.05〜2 // m之介電質薄膜之內設電容器之多層配線板用材料之金屬箔面之具有導體電路之基板，係基板之導體層爲2層以上且其隣接之導體層之電路圖案係在任意部位利用導體化之孔進行連結之基板。(1) A method for producing a material for a multilayer wiring board in which a capacitor is provided, characterized in that a sol-gel method is used to form a permittivity of 10 to 2,000 on a surface of a metal foil and a film thickness of 0.05 to 2//m. Dielectric film. (1) The method for producing a multilayer wiring board material having a capacitor provided in any one of (6) to (10), characterized in that the sheet-shaped metal foil is continuously used in a heating furnace of constant temperature management The metal foil is moved to form a dielectric film. (1) The method for producing a material for a multilayer wiring board in which a capacitor is provided in any one of (6) to (1), wherein the dielectric film is made of barium titanate or barium titanate. Calcium titanate, magnesium titanate, lead titanate, barium titanate, titanium dioxide, barium zirconate, calcium pinchate, lead chromate, barium titanate, chromium titanium-9- (5) 1251536 lead acid, magnesium citrate Any one of lead-titanate lead or a solid solution containing two or more of them, or a laminate comprising two or more of them. (1) The method for producing a material for a multilayer wiring board in which a capacitor is provided in any one of (6) to (U), characterized in that the metal foil is made of copper and forms a dielectric film. A metal film is disposed on the surface, and the metal film is an oxidized protective film of copper, and the metal forming the oxidized protective film of copper is selected from the group consisting of platinum, gold, silver, palladium, rhodium, and iridium. One or more of them. (14) A method for producing a material for a multilayer wiring board in which a capacitor is provided in any one of (6) to (12), characterized in that the metal foil is made of copper and a metal film is provided on the surface thereof. The metal film is a self-oxidizing film which is stable, and the metal which forms the stable self-oxidizing film is one or more selected from the group consisting of chromium, molybdenum, titanium, and nickel. (15) A method for producing a material for a multilayer wiring board in which a capacitor is provided in any one of (6) to (14), characterized in that the surface roughness of the metal foil is 〇·〇1 to 0.5//m. (1 6 ) A method for manufacturing a multilayer wiring board in which a capacitor is provided is a capacitor provided on a surface of a metal foil with a dielectric constant of 1 〇 to 2000 and a film thickness of 0.05 〜2 # m The material for a multilayer wiring board is characterized in that: 1) a step of laminating a substrate having a conductor circuit by using a prepreg for a metal foil surface of a material for a multilayer wiring board on which a capacitor is provided; a step of forming a metal layer of 1 〇~5 0 // m on the surface of the electroless thin film; 3) etching away by retaining any part of the metal layer -10- 1251536 (6) to form a desired capacitor electrode 1 Step; 4) performing etching removal to retain a desired capacitor dielectric by retaining any portion of the capacitor electrode 1 containing at least the dielectric film; and 5) exposing to expose at least the dielectric film removed The uranium engraving is performed in a manner that any portion of the capacitor dielectric of the metal layer is removed to form a conductor pattern containing the desired capacitor electrode 2. (17) A method of manufacturing a multilayer wiring board having a capacitor as set forth in (16), characterized in that the metal layer formed on the surface of the dielectric film contains at least chromium, molybdenum, titanium, and nickel. One or more metal layers selected by the group. (1) A method for manufacturing a multilayer wiring board in which a capacitor is provided is a capacitor provided on a surface of a metal foil with a dielectric film having a permittivity of 10 to 2000 and a film thickness of 0.05 to 2 // m The material for a multilayer wiring board is characterized in that: 1) a step of laminating a substrate having a conductor circuit by using a prepreg for a metal foil surface of a material for a multilayer wiring board on which a capacitor is provided; a step of forming a metal layer of 0.1 to 5 #m on the surface of the electroless thin film; 3) a step of forming a metal plating resist layer in such a manner as to retain any portion of the capacitor electrode 1; 4) forming a 10~ by metal plating a step of 50/im of the capacitor electrode 1; 5) a step of removing the metal plating resist layer; 6) a step of etching away the metal layer formed on the surface of the dielectric film by 0.1 to 5//m; a step of etching to remove any portion of the capacitor electrode 1 containing at least the dielectric film to form a desired capacitor dielectric; and 8) retaining at least a metal layer exposed by the dielectric film removed Capacitor-11- (7) 1251536 Any step of etching the dielectric material to form a conductor pattern containing the desired capacitor electrode 2. (1) A method of manufacturing a multilayer wiring board having a capacitor provided in (1), wherein the metal layer formed on the surface of the dielectric film contains at least chromium, aluminum, titanium, and nickel. One or more metal layers selected by the group. (20) A method of manufacturing a multilayer wiring board having capacitors in (1 8 ) and (1 9), characterized in that the metal plating includes at least a group consisting of copper, silver, tin, nickel, and zinc One or more metals selected. (2 1 ) A method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a surface of the umbrella foil is provided with a dielectric film having a permittivity of 10 to 2000 and a film thickness of 〇. 5 to 2 V m A material for a multilayer wiring board in which a capacitor is provided is characterized in that: 1) a step of laminating a substrate having a conductor circuit with a prepreg for a metal foil surface of a material for a multilayer wiring board on which a capacitor is provided; 2) Any part of the surface of the dielectric film, a metal layer formed by chemical reaction to form a metal layer of 1 〇~5 0 // m to form a desired capacitor electrode 1; 3) to retain at least a dielectric layer a step of etching away any portion of the capacitor electrode 1 of the dielectric film to form a desired capacitor dielectric; and 4) retaining a capacitor dielectric containing at least a metal layer exposed by removing the dielectric film The step of etching is performed in any part to form a conductor pattern containing the desired capacitor electrode 2. (22) A method for producing a multilayer wiring board in which a capacitor is provided in (2 1), characterized in that a gold-based conductive paste of a metallized conductive paste by a chemical reaction contains at least gold, a metal of one or more selected from the group consisting of platinum, silver, copper, palladium, and rhodium, and having an average particle diameter of 0·1 to 1 Onm 〇 (2 3 ) - a multilayer wiring board with a capacitor built therein The manufacturing method is such that the surface of the metal foil is provided with a permittivity of 10 to 2,000 and a film thickness of 〇. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 5 to 2 μm, which is characterized in that: 1) a prepreg is used on a metal foil surface of a material for a multilayer wiring board on which a capacitor is provided. a step of laminating a substrate having a conductor circuit; 2) a step of etching away any portion of the dielectric film to form a desired capacitor dielectric; and 3) a substrate surface for forming a capacitor dielectric a step of forming a metal layer of 1 〇 50 50 / / m; and 4) etching and removing any part of the metal layer to form a desired electrical connection with the capacitor electrode 1, the capacitor electrode 2, and the capacitor electrode The step of insulating any conductor pattern. (24) A method of producing a multilayer wiring board having a capacitor provided in any one of (16) to (23), characterized in that the surface area of the metal foil is set to have a permittivity of 10 to 2,000 and a film thickness of 〇.〇5~2//m dielectric film is provided with a capacitor on the metal foil surface of the material for the multilayer wiring board, and a portion of the prepreg in which the substrate having the conductor circuit is laminated, and the insulating material is provided. The hole 'and the through hole is filled with a conductive paste containing a thermosetting resin and a metal tantalum. (25) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (16) to (23), characterized in that the surface ratio of the metal foil is 10 to 2 〇〇〇 and The dielectric thickness of the film is 〇.05~2//m (9) 1251536 The metal foil surface of the material for the multilayer wiring board with the capacitor built in the film, and the prepreg with the conductor circuit are also laminated. The through hole of the insulating material is disposed on the portion, and the through hole is filled with a conductive paste which is metallized by a chemical reaction. (2 6 ) A method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a surface of a metal foil is provided with a dielectric film having a permittivity of 10 to 2,000 and a film thickness of 〇·〇5 to 2 // m A material for a multilayer wiring board in which a capacitor is provided, comprising: 1) a step of laminating a substrate having a conductor circuit by using a prepreg for a metal foil surface of a material for a multilayer wiring board on which a capacitor is provided; 2) a step of forming a metal layer of 10 to 50 / / m on the surface of the dielectric film; 3) etching to remove any portion of the metal layer to form a desired capacitor electrode 1; 4) retaining at least a step of removing any portion of the capacitor electrode 1 of the dielectric film to form a desired capacitor dielectric; 5) etching to remove any portion exposed by removing the dielectric film, thereby hardening The step of exposing the insulating layer of the prepreg; 6) removing the exposed insulating layer by laser irradiation to form a hole, and exposing the inner layer of the conductor circuit; 7) forming a surface on the surface of the substrate. 1~5 // m a step of a layer; 8) a step of forming a plating resist on a portion other than the portion containing the hole; 9) forming a surface of the substrate other than the portion where the plating resist is formed, 10 to 5 0 // m a metal layer for electrically connecting the circuit patterns between the layers; 10) a step of etching removing the metal layer formed on the surface of the substrate by 0.1 to 5 // m; and 1 1 ) The step 〇(27) of removing the conductor pattern containing the capacitor electrode 2 is performed by removing at least any portion including the capacitor dielectric and the conductor hole. (26) A manufacturer of a multilayer wiring board having a capacitor therein, characterized in that the metal layer formed on the surface of the dielectric film contains at least a group selected from the group consisting of: ingot, molybdenum, titanium, and nickel. More than one metal layer. (2) A method for manufacturing a multilayer wiring board in which a capacitor is provided, which is a multilayer wiring in which a capacitor having a dielectric constant of 10 to 2000 and a film thickness of 0.05 to 2 Vm is provided on a surface of a metal foil. The material for a board is characterized by having a step of using a prepreg to laminate a substrate having a conductor circuit on a metal foil surface of a multilayer wiring board material of a capacitor, and 2) for using a dielectric film a step of forming a 金属·1~5//mt metal layer on the surface; 3) a step of forming a metal plating resist layer in such a manner as to retain any portion of the capacitor electrode 1; 4) forming a metal shovel 10~ a step of 50//m of the capacitor electrode 1; 5) a step of removing the metal plating resist layer; 6) a step of etching away the metal layer formed on the surface of the dielectric film by 0.1 to 5//m; 7) performing etching removal to retain a desired capacitor dielectric by retaining any portion of the capacitor electrode 1 containing at least a dielectric film; 8) etching to remove any exposed by removing the dielectric film Part of the hardening half a step of exposing the insulating layer of the chemical sheet; 9) removing the exposed insulating layer by laser irradiation to form a hole, and exposing the inner layer of the conductor circuit; 10) for forming a 〇·1~5 on the surface of the substrate / ηι metal layer step; 1 1) a step of forming a layer of electroplating anti-uranium-15-(11) 1251536 on a portion other than the hole; 1 2) outside the portion where the electroplated resist layer is formed The surface of the substrate is formed with a metal layer of 10 to 5 0 // m for electrically connecting the circuit patterns between the layers; and 1 3 ) for the metal of 〇·1 to 5 // m formed on the surface of the substrate The step of performing etching removal on the layer; and the step of etching to remove at least any portion including the capacitor dielectric and the via hole to form a desired conductor pattern of the capacitor electrode 2. (29) A method of manufacturing a multilayer wiring board having a capacitor as set forth in (28) characterized in that the metal layer formed on the surface of the dielectric film contains at least a group consisting of chromium, molybdenum, titanium, and nickel. One or more metal layers selected. (30) A method of producing a multilayer wiring board having a capacitor as described in (28) and (29), characterized in that the metal plating is at least selected from the group consisting of copper, silver, tin, nickel, and zinc. One or more kinds of metal ruthenium (3 1 ) - a method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a surface of the metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 0.05 to 2 // m A material for a multilayer wiring board in which a capacitor is provided in an electric film, comprising: 1) a step of laminating a substrate having a conductor circuit by using a prepreg for a metal foil surface of a material for a multilayer wiring board on which a capacitor is provided 2) a step of forming a desired metal capacitor layer 1 by forming a metal layer of a conductive paste formed by a chemical reaction on a surface of the dielectric film to form a desired capacitor electrode 1; a step of -16-(12) 1251536 etching removal to retain a desired capacitor dielectric by retaining any portion of the capacitor electrode 1 containing at least a dielectric film; 4) for removing the dielectric The film is exposed a step of exposing the insulating layer of the hardened prepreg; 5) a step of forming a hole by removing the insulating layer by laser irradiation to expose the conductor circuit of the inner layer; ) forming 0.1 to 5// on the surface of the substrate a step of forming a metal layer of m; 7) forming a plating resist layer on a portion other than the portion containing the hole; 8) forming a surface of the substrate other than the portion where the plating resist layer is formed. a metal layer for electrically connecting the circuit patterns between the layers; 9) a step of etching away the gold layer formed on the surface of the substrate: 1 to 5 // m; and 1 〇) to retain at least the capacitor containing The step of forming a conductor pattern including the capacitor electrode 2 is performed by etching away any portion of the dielectric or the conductor hole. (3) A method for producing a multilayer wiring board in which a capacitor is provided in (3), characterized in that the genus of the conductive paste which is metallized by a chemical reaction contains at least gold, platinum, silver, copper, palladium. And a method of manufacturing a multilayer wiring board in which a capacitor having a size of one or more selected from the group consisting of 〇·1 1 0 nm 3(3 3 ) A multilayer wiring board material having a capacitor having a capacitance of 1 〇 2 〇〇〇 and a film thickness of 〇· 〜 2 // m is provided on the surface, and is characterized in that: 1) a step of forming a conductor circuit substrate by using a prepreg layer on a metal foil surface of a multilayer wiring material having a capacitor; 2) etching and removing any portion of the dielectric film to form a desired capacitor dielectric; Step; 3) removing the insulating layer of the cured prepreg by removing any portion exposed by removing the dielectric film, and removing the exposed insulating layer by laser irradiation; To form a hole and expose it a step of a conductor circuit; 5) a step of forming a metal layer of 10 to 50 // m on a surface of the substrate on which the capacitor dielectric is formed, and a surface in the hole; and 6) to retain at least a capacitor dielectric, Etching and removing the conductor pattern including the capacitor electrode 2 in a desired manner, and forming a desired conductor pattern including the capacitor electrode 2, such as (1 6 ) to (3 3 ) A method for manufacturing a multilayer wiring board with a built-in capacitor, characterized in that a capacitor having a dielectric film having a permittivity of 10 to 2000 and a film thickness of 0.05 to 2 // m is disposed on the surface of the metal case by using a prepreg layer. The substrate having the conductor circuit on the metal foil surface of the material for the multilayer wiring board, the conductor layer of the base substrate is two or more layers, and the circuit pattern of the adjacent conductor layer is a substrate that is connected to each other by a conductor hole.

(35)如（16)〜（34)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，鈾刻除去介電質薄膜之方法係離子束触刻法、RIE ( Reactive Ion Etching) 法、或溶液蝕刻法之其中任一種方法。 (3 6 )如（1 6 )〜（3 5 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，電容器電極2係多層配線板之接地層或電源層。 (37)如（16)〜（36)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，基板之絶緣材料係 -18- (14) 1251536 由樹脂、及玻璃織布或玻璃不織布所構成。 (3 8 )如（1 6 )〜（3 7 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，基板之絶緣材料所使用之樹脂係熱硬化性樹脂，其玻璃轉移點溫度爲1 7〇 t 以上。 B、此外，本發明係和以下之實施形態相關。 (1 ) 一種內設電容器之多層配線板用基板，其特徵爲，基板內部具有用以連結導體層間之通孔，且具有表面平滑之金屬層之基板表面上，形成電容率爲10〜2〇〇〇且膜厚爲0.05〜2//m之介電質薄膜。 (2 )如（1 )之內設電容器之多層配線板用基板，其特徵爲，利用金屬電鏟將用以連結導體層間之通孔電性連結至基板內部。 (3 )如（1 )之內設電容器之多層配線板用基板，其特徵爲，利用由金屬粉及樹脂所構成之導電性糊將用以連結導體層間之通孔電性連結至基板內部。 (4 )如（1 )或（3 )之內設電容器之多層配線板用基板，其特徵爲，利用以化學反應實施金屬化之導電性糊將用以連結導體層間之通孔電性連結至基板內部。 (5 )如（1 )至（4 )之其中任一項之內設電容器之多層配線板用基板’其特徵爲，介電質薄膜係由鈦酸鋇、鈦酸緦、鈦酸鈣、鈦酸鎂、鈦酸鉛、鈦酸鉍、二氧化鈦、鉻酸鋇、鉻酸鈣、锆酸鉛之其中任一種、或含有其中任2 種以上之固溶體、或含有其中任2種以上之積層體所構成 -19- (15) 1251536 之膜。 (6 )如（1 )至（5 )之其中任一項之內設電容器之多層配線板用基板，其特徵爲，介電質薄膜之形成方法係真空蒸鍍法、離子鍍法、CVD ( ChemlCal Vap〇1(35) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (16) to (34), characterized in that the method of removing the dielectric film by uranium is ion beam lithography, RIE ( Any of the Reactive Ion Etching methods or solution etching methods. (3) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (1) to (35), characterized in that the capacitor electrode 2 is a ground layer or a power supply layer of a plurality of wiring boards. (37) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (16) to (36), characterized in that the insulating material of the substrate is -18-(14) 1251536 made of resin and glass woven. Cloth or glass non-woven fabric. (3) The method for producing a multilayer wiring board in which a capacitor is provided in any one of (1) to (37), characterized in that the resin-based thermosetting resin used for the insulating material of the substrate The glass transition point temperature is above 17 〇t. B. Further, the present invention relates to the following embodiments. (1) A substrate for a multilayer wiring board in which a capacitor is provided, wherein a substrate having a through hole between the conductor layers and having a metal layer having a smooth surface has a permittivity of 10 to 2 〇. A dielectric film having a film thickness of 0.05 to 2/m. (2) A substrate for a multilayer wiring board in which a capacitor is provided in (1), wherein a through hole for connecting the conductor layers is electrically connected to the inside of the substrate by a metal shovel. (3) A substrate for a multilayer wiring board in which a capacitor is provided in (1), wherein a conductive paste made of a metal powder and a resin is electrically connected to a via hole for connecting the conductor layers to the inside of the substrate. (4) The substrate for a multilayer wiring board in which a capacitor is provided in (1) or (3), characterized in that the via hole for connecting the conductor layers is electrically connected to the conductive paste which is metallized by a chemical reaction to Inside the substrate. (5) The substrate for a multilayer wiring board in which a capacitor is provided in any one of (1) to (4), characterized in that the dielectric film is made of barium titanate, barium titanate, calcium titanate, titanium Any one of magnesium sulfate, lead titanate, barium titanate, titanium dioxide, barium chromate, calcium chromate, and lead zirconate, or a solid solution containing two or more of them, or a laminate of two or more of them The body constitutes the membrane of -19- (15) 1251536. (6) The substrate for a multilayer wiring board having a capacitor provided in any one of (1) to (5), wherein the method of forming the dielectric film is vacuum evaporation, ion plating, CVD ( ChemlCal Vap〇1

Deposition)法、濺鍍法、以及溶膠-凝膠法之其中任一種〇 (7) 如（1)至（6)之其中任一項之內設電容器之多層配線板用基板，其特徵爲，介電質薄膜形成時之基板溫度爲2 5 °C〜3 5 0 °C。 (8) 如（1)至（7)之其中任一項之內設電谷器之多層配線板用基板，其特徵爲’基板之絶緣材料係由樹脂、及玻璃織布或玻璃不織布所構成。 (9) 如（1)至（8)之其中任一項之內設電容器之多層配線板用基板，其特徵爲’基板之絶緣材料所使用之樹脂係熱硬化性樹脂，其玻璃轉移點溫度爲1 7 0 °C以上。 (10) 如（1)至（9)之其中任一項之內設電容器之多層配線板用基板，其特徵爲，基板表面之金屬層係由銅所構成，且其表面上配設著銅之氧化保護覆膜，形成前述銅之氧化保護覆膜之金屬係從白金、金、銀、鈀、釕、以及銥所構成之群組所選取之1種以上。 (1 1 )如（1 )至（9 )之其中任一項之內設電容器之多層配線板用基板，基板表面之金屬層係由銅所構成，且其表面配設著金屬膜，前述金屬膜係安定之自氧化覆膜，形成前述安定之自氧化覆膜之金屬係從鉻、鉬、鈦、以及 -20- (16) 1251536 鎳所構成之群組所選取之至少1種以上。 (12)如（1)至（11)之其中任一項之內設電容器之多層配線板用基板’其特徵爲，基板表面之金屬層之表面粗糙度爲0.0 1〜0.5〆m。 (1 3 ) —種內設電容器之多層配線板之製造方法，係採用將如（1 )至（1 2 )之其中任一項之內設電容器之多層配線板用基板當做內層板使用，其特徵爲，具有：1 ) 在介電質薄膜表面形成10〜50//m之金屬層之步驟；2) 以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極之步驟；3)以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；4 )以保留至少含有除去介電質薄膜所露出之金屬層之電容器介電質之任意部份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (1 4 )如（1 3 )之內設電容器之多層配線板之製造方法，其特徵爲，形成於介電質薄膜表面上之金屬層至少含有從鉻、鉬、鈦、以及鎳所構成之群組所選取之1種以上之金屬層。 (1 5 ) —種內設電容器之多層配線板之製造方法，係採用將（1)至（12)之其中任一項之內設電容器之多層配線板用基板當做內層板使用，其特徵爲，具有：i )用以在介電質薄膜表面形成〇 · 1〜5 # m之金屬層之步驟.2 )以保留含有第1電容器電極之任意部份之方式形成金屬 -21 - (17) 1251536 電鍍抗蝕層之步驟；3 )利用金屬電鍍形成i 〇〜5 〇 " m之第1電容器電極之步驟；4 )用以除去金屬電鍍抗蝕層之步驟；5 )用以触刻除去形成於介電質薄膜表面之〇 .丨〜5 V m之金屬層之步驟；6 )以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及7 )以保留至少含有除去介電質薄膜所露出之金屬層之電容器介電質之任意部份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (1 6 )如（1 5 )之內設電容器之多層配線板之製造方法，其特徵爲，形成於介電質薄膜表面上之金屬層至少含有從鉻、鉬、鈦、以及鎳所構成之群組所選取之1種以上之金屬層。 (1 7 )如（1 5 )或（1 6 )之內設電容器之多層配線板之製造方法，其特徵爲，金屬電鍍至少含有從銅、銀、錫、鎳、以及鋅所構成之群組所選取之1種以上之金屬。 (1 8 ) —種內設電容器之多層配線板之製造方法，係採用將（1)至（12)之其中任一項之內設電容器之多層配線板用基板當做內層板使用，其特徵爲’具有：1 )在介電質薄膜表面之任意部份，以利用化學反應實施金屬化之導電性糊形成1 0〜5 0 // m之金屬層來形成期望之第1 電容器電極之步驟；2)以保留至少含有介電質薄膜之第 1電容器電極之任意部份之方式進行蝕刻除去’形成期望之電容器介電質之步驟；以及3 )以保留至少含有除去介 -22- (18) 1251536 電質薄膜所露出之金屬層之電容器介電質之任意部份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (1 9 )如（1 8 )之內設電容器之多層配線板之製造方法，其特徵爲，利用化學反應實施金屬化之導電性糊之金屬粒子至少含有從金、白金、銀、銅、鈀、以及釕所構成之群組所選取之1種以上之金屬，且其平均粒徑爲0.1〜 1 0 nm。 (20 ) —種內設電容器之多層配線板之製造方法，係採用將如（1 )至（1 2 )之其中任一項之內設電容器之多層配線板用基板當做內層板使用，其特徵爲，具有：1 ) 以保留介電質薄膜之任意部份之方式進行鈾刻除去，形成期望之電容器介電質之步驟；2)在形成電容器介電質之基板表面上形成1 〇〜5 0 // m之金屬層之步驟；以及3 )以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極、第2電容器電極、及電容器電極爲電性絶緣之任意導體圖案之步驟。 (2 1 )如（1 3 )至（2 0 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，蝕刻除去介電質薄月旲之方法係離子束触刻法、RIE( Reactive Ion Etching) 法、或溶液鈾刻法之其中任一種方法。 (22)如（13)至（21)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，第2電容器電極係多層配線板之接地層或電源/罾。 -23- (19) 1251536A substrate for a multilayer wiring board in which a capacitor is provided in any one of (1) to (6), characterized in that: The substrate temperature at the time of forming the dielectric film is 25 ° C to 3 50 ° C. (8) The substrate for a multilayer wiring board of the electric grid device according to any one of (1) to (7), wherein the insulating material of the substrate is composed of a resin, a glass woven fabric or a glass non-woven fabric. . (9) The substrate for a multilayer wiring board in which a capacitor is provided in any one of (1) to (8), characterized in that the resin-based thermosetting resin used for the insulating material of the substrate has a glass transition point temperature It is above 1 70 °C. (10) The substrate for a multilayer wiring board in which a capacitor is provided in any one of (1) to (9), wherein the metal layer on the surface of the substrate is made of copper, and copper is provided on the surface thereof. The oxidized protective film is one or more selected from the group consisting of platinum, gold, silver, palladium, rhodium, and iridium. (1) The substrate for a multilayer wiring board in which a capacitor is provided in any one of (1) to (9), wherein the metal layer on the surface of the substrate is made of copper, and a metal film is disposed on the surface thereof, and the metal is The membrane-stabilized auto-oxidation coating forms at least one selected from the group consisting of chromium, molybdenum, titanium, and -20-(16) 1251536 nickel. (12) A substrate for a multilayer wiring board having a capacitor built in any one of (1) to (11), characterized in that the surface roughness of the metal layer on the surface of the substrate is 0.01 to 0.5 〆m. (1 3) The method for manufacturing a multilayer wiring board in which a capacitor is provided is used as an inner layer board using a substrate for a multilayer wiring board having a capacitor provided in any one of (1) to (1). The method has the following steps: 1) forming a metal layer of 10 to 50//m on the surface of the dielectric film; 2) etching and removing any part of the metal layer to form a desired first capacitor a step of an electrode; 3) etching to remove any portion of the first capacitor electrode containing at least a dielectric film to form a desired capacitor dielectric; 4) retaining at least a dielectric-removing film The step of etching and removing any portion of the capacitor dielectric of the exposed metal layer to form a conductor pattern containing the desired second capacitor electrode. (1) A method of manufacturing a multilayer wiring board having a capacitor provided in (13), wherein the metal layer formed on the surface of the dielectric film contains at least chromium, molybdenum, titanium, and nickel. One or more metal layers selected by the group. (1) A method for manufacturing a multilayer wiring board in which a capacitor is provided, which is characterized in that a substrate for a multilayer wiring board in which a capacitor is provided in any one of (1) to (12) is used as an inner layer board, and the characteristics thereof are used. For example, there are: i) a step of forming a metal layer of 〇·1~5 #m on the surface of the dielectric film. 2) forming a metal 21 - (17) in such a manner as to retain any portion of the electrode of the first capacitor. 1251536 step of plating the resist layer; 3) step of forming the first capacitor electrode of i 〇〜5 〇" m by metal plating; 4) step of removing the metal plating resist layer; 5) for engraving a step of removing a metal layer formed on the surface of the dielectric film, and removing 65% of the first capacitor electrode containing the dielectric film to form a desired portion a step of capacitor dielectric; and 7) etching and removing away any portion of the capacitor dielectric containing at least the metal layer removed from the dielectric film to form a conductor pattern containing the desired second capacitor electrode The steps. (16) A method of manufacturing a multilayer wiring board having a capacitor as set forth in (15), characterized in that the metal layer formed on the surface of the dielectric film contains at least chromium, molybdenum, titanium, and nickel. One or more metal layers selected by the group. (1) A method of manufacturing a multilayer wiring board having a capacitor provided in (1 5 ) or (16), characterized in that the metal plating contains at least a group consisting of copper, silver, tin, nickel, and zinc. One or more metals selected. (1) A method for manufacturing a multilayer wiring board in which a capacitor is provided, which is characterized in that the substrate for a multilayer wiring board in which a capacitor is provided in any one of (1) to (12) is used as an inner layer board, and the characteristics thereof are used. A step of forming a desired first capacitor electrode by forming a metal layer of a conductive paste by chemical reaction to form a desired first capacitor electrode for any portion of the surface of the dielectric film by 'having: 1 2) etching to remove any portion of the first capacitor electrode containing at least the dielectric film to remove 'forming a desired capacitor dielectric; and 3) to retain at least the removal of the dielectric - 22 1251536 The step of etching to remove any portion of the capacitor dielectric of the metal layer exposed by the dielectric film to form a conductor pattern containing the desired second capacitor electrode. (1) A method for producing a multilayer wiring board in which a capacitor is provided in (1), characterized in that the metal particles of the conductive paste which are metallized by a chemical reaction contain at least gold, platinum, silver, copper, palladium. And one or more metals selected from the group consisting of 钌, and having an average particle diameter of 0.1 to 10 nm. (20) A method of manufacturing a multilayer wiring board in which a capacitor is provided, which is used as an inner layer board using a substrate for a multilayer wiring board having a capacitor provided in any one of (1) to (1) The method has the following steps: 1) performing uranium engraving in a manner of retaining any portion of the dielectric film to form a desired capacitor dielectric; and 2) forming a 〇 on the surface of the substrate on which the capacitor dielectric is formed. a step of a metal layer of 5 0 // m; and 3) etching and removing away any part of the metal layer to form a desired first capacitor electrode, a second capacitor electrode, and a capacitor electrode electrically insulated The step of any conductor pattern. (2) A method of manufacturing a multilayer wiring board having a capacitor built in any one of (1 3) to (20), characterized in that the method of etching and removing the dielectric thin moon is ion beam tracing Method, RIE (Reactive Ion Etching) method, or solution uranium engraving method. (22) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (13) to (21), characterized in that the second capacitor electrode is a ground layer or a power source/turn of the multilayer wiring board. -23- (19) 1251536

(2 3 ) —種內設電容器之多層配線板，係具有複數絶緣層、複數導體層、以及用以實施前述導體層之電性連結之導體化之通孔，其介電質薄膜係至少1層之絶緣層之電容率爲 20〜2000且膜厚爲 0.1〜1/im，且具有和絶緣層相對之電極，其特徵爲，1)形成第1電容器電極之導體層圖案可形成全部電容器之電極，2 )介電質薄膜之投影面包含第1電容器電極之投影面，3)形成第2電容器電極之導體層上，具有第2電容器電極、及與該電極爲電性絶緣之至少1個圖案。(2 3) A multi-layer wiring board having a capacitor, a plurality of insulating layers, a plurality of conductor layers, and a via hole for electrically connecting the conductor layers, wherein the dielectric film is at least 1 The insulating layer of the layer has a permittivity of 20 to 2000 and a film thickness of 0.1 to 1/im, and has an electrode opposite to the insulating layer, wherein 1) the conductor layer pattern forming the first capacitor electrode can form all of the capacitors. The electrode 2) the projection surface of the dielectric film includes a projection surface of the first capacitor electrode, and 3) the conductor layer forming the second capacitor electrode has a second capacitor electrode and at least one electrically insulated from the electrode pattern.

(24 ) —種內設電容器之多層配線板，係具有複數絶緣層、複數導體層、以及用以實施前述導體層之電性連結之導體化之通孔，其介電質薄膜之至少1層之絶緣層之電容率爲20〜2000且膜厚爲〇·1〜l//m，且具有和絶緣層相對之電極，其特徵爲’〗）具有位於形成電容器之介電質之介電質薄膜投影面之內之第1電容器電極，2)介電質薄膜之端部所有形成第1電容器電極之導體層皆電性連結至第2電容器電極。 (25 )如（23 )或（24 )之內設電容器之多層配線板，其特徵爲，第2電容器電極係多層配線板之接地層或電源層 (2 6 )如（2 3 )至（2 5 )之其中任一項之內設電容器之多層配線板，其特徵爲’介電質薄膜係由鈦酸鋇、鈦酸緦、鈦酸鈣、鈦酸鎂、鈦酸鉛、鈦酸鉍、二氧化鈦、鍩酸鋇、鉻酸鈣、i告酸鉛之其中任一種、或含有其中任2種以 -24- (20) 1251536 上之固溶體、或含有其中任2種以上之積層體所構成之膜〇 (27) 如（23)至（26)之其中任一項之內設電容器之多層配線板，其特徵爲，基板之絶緣材料係由樹脂、及玻璃織布或玻璃不織布所構成。 (28) 如（23)至（27)之其中任一項之內設電容器之多層配線板，其特徵爲，基板之絶緣材料所使用之樹脂係熱硬化性樹脂，其玻璃轉移點溫度爲1 7〇 °C以上。 (29) 如（23)至（28)之其中任一項之內設電容器之多層配線板，其特徵爲，第2電容器電極銅所構成’ 且其表面含有從白金、金、銀、鈀、釕、銥、鉻、鉬、鈦、以及鎳所構成之群組所選取之至少1種以上之金屬層。 (30) 如（23)至（29)之其中任一項之內設電容器之多層配線板，其特徵爲，第2電容器電極之表面粗糙度爲 0.01 〜0.5// m。 (31) 如（23)至（30)之其中任一項之內設電容器之多層配線板，其特徵爲，第1電容器電極含有從銅、銀、錫、鎳、鋅、鉻、鉬、鈦、以及鎳所構成之群組所選取之至少1種以上之金屬層。 (32) 如（23)至（30)之其中任一項之內設電容器之多層配線板，其特徵爲，第1電容器電極係由利用化學反應實施金屬化之導電性糊所構成，其金屬含有從白金、金、銀、銅、錫、鈀、以及釕所構成之群組所選取至少1 種以上之金屬。 -25- (21) 1251536 (33) —種半導體裝置，其特徵爲，將半導體晶片載 ®於如（23)至（32)之其中任一項之內設電容器之多層配線板上。 C、此外’本發明係和以下之實施形態相關。 (1 ) 一種內設電容器之多層配線板之製造方法，係採用將金屬箔單面配設著電容率爲10〜2000且膜厚爲〇· 05〜2//m之介電質薄膜之內設電容器之多層配線板用材料以金屬箔接觸絶緣材料之方式配設於絶緣材料之至少單面上之基板，其特徵爲，具有：1)用以在基板表面之介電質薄膜上之特定位置上形成當做電容器電極使用之金屬層之步驟；2)至少在基板表面之前述金屬層上形成鈾刻抗蝕層之步驟；3 )利用含有鉗合劑及過氧化氫之蝕刻劑，實施介電質薄膜之濕蝕刻之步驟；以及4 )在濕蝕刻後除去蝕刻抗蝕層之步驟。 (2 )如（1 )之內設電容器之多層配線板之製造方法，其特徵爲，蝕刻劑之鉗合劑濃度爲 0.001〜0.5m〇 1/1，且過氧化氫濃度爲1〜5 0 wt %，且蝕刻劑之P H爲2〜7之範圍。 (3 )如（1 )或（2 )之內設電容器之多層配線板之製造方法，其特徵爲，鉗合劑係從乙烯二胺四醋酸（ EDTA)、羥乙基醯亞胺基（HIDA)、醯亞胺基二醋酸（ IDA )、二羥乙基甘氨酸（DHEG )、以及這些鹼鹽所構成之群組所選取之至少1種。 (4 ) 一種內設電容器之多層配線板之製造方法，係 -26- (22) I251536 採用將金屬箔單面配設著電容率爲10〜2000且膜厚爲 Q · G 5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料以金屬箔接觸絶緣材料之方式配設於絶緣材料之至少單面上之基板，其特徵爲，具有：1 )用以在基板表面之介電質薄膜上之特定位置上形成當做電容器電極使用之金屬層之步驟；2)至少在基板表面之前述金屬層上形成倉虫刻抗蝕層之步驟；3 )利用含有從硫酸、鹽酸、磷酸 '硝酸、及醋酸所構成之群組所選取之至少1種酸、以及過氧化氫之蝕刻劑層，實施介電質薄膜之濕鈾刻之步驟；以及 4 )在濕蝕刻後除去蝕刻抗蝕層之步驟。 (5 )如（4 )之內設電容器之多層配線板之製造方法，其特徵爲，蝕刻劑之酸濃度爲1〜3 〇wt%，且過氧化氫濃度爲1〜50wt%。 (6)如（1)〜（5)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲’蝕刻抗鈾層係使用感光性乾薄膜。 (7 )如（6 )之內設電容器之多層配線板之製造方法，其特徵爲，感光性乾薄膜之膜厚，爲利用由感光性乾薄膜所形成之餓刻抗鈾層而不會貫施濕鈾刻之當做電谷器電極使用之金屬層之厚度的1〜3倍。 (8) 如（1)〜（7)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲’介電質薄膜之濕蝕刻係以液溫爲2 0〜4 5 °C之蝕刻劑實施。 (9) 如（1)〜（8)之其中任一項之內設電容器之 -27- (23) 1251536 多層鋇、鈦、其中體所採用 0.05 材料用材來形除去用雷出之層之質薄圖案容器及7 有電如（爲，配線板之製造方法，其特徵爲，介電質薄膜係由鈦酸鈦酸緦、鈦酸鈣、鈦酸鎂、鈦酸鉛、鈦酸鉍、二氧化鉻酸鋇、锆酸鈣、以及锆酸鉛之其中任一種、或含有任2種以上之固溶體、或含有其中任2種以上之積層構成之膜。 D、此外，本發明係和以下之實施形態相關。 (1 ) 一種內設電容器之多層配線板之製造方法，係金屬箔A單面配設著電容率爲1〇〜2000且膜厚爲〜2 // m之介電質薄膜之內設電容器之多層配線板用 ’其特徵爲，具有：1 )在內設電容器之多層配線板料之金屬箔A面利用絶緣材料實施金屬箔B之積層成基板之步驟；2 )實施金屬范B之任意部位之飽刻 ’使上述絶緣材料形成之絶緣層露出之步驟；3 )利射照射除去露出之絶緣層來形成孔而使金屬箔A露步驟·，4)在含孔內在內之基板表面之兩面形成金屬步驟；5 )對內設電容器之多層配線板用材料之介電膜上之金屬層以蝕刻形成任意形狀之電容器電極A 之步驟；6 )對露出之介電質薄膜以蝕刻形成含有電電極A圖案之任意形狀之電容器介電質之步驟；以 )對除去介電質薄膜而露出之金屬箔A以蝕刻形成含容器介電質圖案之任意形狀之電容器電極B之步驟。 (2 ) —種內設電容器之多層配線板之製造方法，係 1 )之內設電容器之多層配線板之製造方法，其特徵 5 )或7 )之蝕刻步驟中，在基板之積層著金屬箔b -28- 1251536 (24) 之面上形成任意形狀之電路。 (3 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔A單面配設著電容率爲1〇〜2〇〇〇且膜厚爲 0.0 5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )對金屬箔B之任意部位實施雷射照射，同時除去金屬箔B、及上述絶緣材料所形成之絶緣層來形成孔，而使金屬箔A露出之步驟；3)在含孔內在內之基板表面之兩面形成金屬層之步驟；4)對內設電容器之多層配線板用材料之介電質薄膜上之金屬層以蝕刻形成任意形狀之電容器電極A圖案之步驟；5 )對露出之介電質薄膜以触刻形成含有電容器電極A圖案之任意形狀之電容器介電質之步驟；以及6)對除去介電質薄膜而露出之金屬泊A以餓刻形成含有電容器介電質圖案之任意形狀之電容器電極B之步驟。 (4 ) 一種內設電容器之多層配線板之製造方法，係如（3 )之內設電容器之多層配線板之製造方法，其特徵爲，4)或6)之蝕刻步驟中，在基板之積層著金屬箔b 之面上形成任意形狀之電路。 (5 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔A單面配設著電容率爲1〇〜2000且膜厚爲 0.0 5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料’其特徵爲，具有：i )在內設電容器之多層配線板 >29- (25) 1251536(24) A multilayer wiring board in which a capacitor is provided, which has a plurality of insulating layers, a plurality of conductor layers, and a via hole for electrically connecting the conductor layers, and at least one layer of the dielectric film The insulating layer has a permittivity of 20 to 2000 and a film thickness of 〇·1 to l//m, and has an electrode opposite to the insulating layer, which is characterized by having a dielectric located in a dielectric forming a capacitor. The first capacitor electrode in the film projection surface, and 2) the conductor layer forming the first capacitor electrode at the end of the dielectric film are electrically connected to the second capacitor electrode. (25) A multilayer wiring board having a capacitor provided in (23) or (24), characterized in that the second capacitor electrode is a ground layer or a power supply layer (26) of the multilayer wiring board such as (2 3 ) to (2) 5) A multilayer wiring board having a capacitor therein, characterized in that the dielectric film is made of barium titanate, barium titanate, calcium titanate, magnesium titanate, lead titanate, barium titanate, Any one of titanium dioxide, barium strontium silicate, calcium chromate, and lead acid, or a solid solution of any two of them, -24-(20) 1251536, or a laminate containing two or more of them The laminated film of the capacitor is provided in any one of (23) to (26), wherein the insulating material of the substrate is made of resin, glass woven fabric or glass non-woven fabric. . (28) A multilayer wiring board having a capacitor provided in any one of (23) to (27), wherein the resin-based thermosetting resin used for the insulating material of the substrate has a glass transition point temperature of 1 7〇°C or more. (29) A multilayer wiring board having a capacitor built in any one of (23) to (28), characterized in that the second capacitor electrode is made of copper and the surface thereof contains platinum, gold, silver, palladium, At least one metal layer selected from the group consisting of ruthenium, osmium, chromium, molybdenum, titanium, and nickel. (30) A multilayer wiring board having a capacitor provided in any one of (23) to (29), wherein the second capacitor electrode has a surface roughness of 0.01 to 0.5/m. (31) A multilayer wiring board having a capacitor provided in any one of (23) to (30), characterized in that the first capacitor electrode contains copper, silver, tin, nickel, zinc, chromium, molybdenum, titanium And at least one metal layer selected from the group consisting of nickel. (32) A multilayer wiring board having a capacitor provided in any one of (23) to (30), wherein the first capacitor electrode is made of a conductive paste which is metallized by a chemical reaction, and the metal It contains at least one metal selected from the group consisting of platinum, gold, silver, copper, tin, palladium, and rhodium. Further, a semiconductor device is mounted on a multilayer wiring board in which a capacitor is provided in any one of (23) to (32). C. Further, the present invention relates to the following embodiments. (1) A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein a metal foil is disposed on one side of a dielectric film having a permittivity of 10 to 2,000 and a film thickness of 〇·05 to 2//m. The material for the multilayer wiring board of the capacitor is disposed on the substrate on at least one side of the insulating material in such a manner that the metal foil contacts the insulating material, and has the following features: 1) specificity on the dielectric film on the surface of the substrate a step of forming a metal layer as a capacitor electrode at a position; 2) a step of forming a uranium-etched resist layer on at least the metal layer on the surface of the substrate; 3) performing a dielectric using an etchant containing a chelating agent and hydrogen peroxide a step of wet etching the thin film; and 4) a step of removing the etching resist after the wet etching. (2) A method of manufacturing a multilayer wiring board having a capacitor as set forth in (1), characterized in that the concentration of the etchant is 0.001 to 0.5 m〇1/1, and the hydrogen peroxide concentration is 1 to 50 wt. %, and the pH of the etchant is in the range of 2 to 7. (3) A method of producing a multilayer wiring board having a capacitor as set forth in (1) or (2), characterized in that the chelating agent is derived from ethylenediaminetetraacetic acid (EDTA) or hydroxyethyl quinone imine (HIDA). At least one selected from the group consisting of quinone iminodiacetic acid (IDA), dihydroxyethylglycine (DHEG), and these alkali salts. (4) A method for manufacturing a multilayer wiring board with a built-in capacitor, -26-(22) I251536, which is provided with a single-sided metal foil with a permittivity of 10 to 2000 and a film thickness of Q · G 5 to 2 // a material for a multi-layer wiring board in which a capacitor is provided with a metal foil in contact with an insulating material, and a substrate disposed on at least one surface of the insulating material, wherein: 1) for the surface of the substrate a step of forming a metal layer as a capacitor electrode at a specific position on the dielectric film; 2) a step of forming a barrier layer on at least the metal layer on the surface of the substrate; 3) utilizing a sulfuric acid, a hydrochloric acid And at least one acid selected from the group consisting of phosphoric acid and nitric acid, and an etchant layer of hydrogen peroxide, a step of performing a wet uranium engraving of the dielectric film; and 4) removing the etching after the wet etching The step of the resist layer. (5) A method of producing a multilayer wiring board having a capacitor as set forth in (4), characterized in that the acid concentration of the etchant is 1 to 3 Å by weight, and the hydrogen peroxide concentration is 1 to 50% by weight. (6) A method of producing a multilayer wiring board having a capacitor provided in any one of (1) to (5), characterized in that the etch-resistant uranium layer is a photosensitive dry film. (7) A method of producing a multilayer wiring board having a capacitor as set forth in (6), characterized in that the film thickness of the photosensitive dry film is such that the hungry anti-uranium layer formed by the photosensitive dry film does not pass through The wet uranium is engraved as 1 to 3 times the thickness of the metal layer used for the electrode of the electric grid. (8) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (1) to (7), characterized in that the wet etching of the dielectric film is performed at a liquid temperature of 20 to 4 5 ° The etchant of C is implemented. (9) If any of the capacitors in any of (1) to (8) is provided with -27-(23) 1251536 multi-layer tantalum, titanium, and 0.05 material used in the body, the material of the layer is removed. The thin pattern container and 7 have electricity (for, the manufacturing method of the wiring board, characterized in that the dielectric film is made of barium titanate titanate, calcium titanate, magnesium titanate, lead titanate, barium titanate, two Any one of ruthenium chromite, calcium zirconate, and lead zirconate, or a solid solution containing two or more of them, or a film comprising two or more of them. D. Further, the present invention is The following embodiments are related to each other. (1) A method of manufacturing a multilayer wiring board with a capacitor provided with a dielectric material having a capacitance of 1 〇 to 2000 and a film thickness of 〜2 // m on one side of the metal foil A The multilayer wiring board in which a capacitor is provided in the film is characterized in that: 1) a step of laminating the metal foil B into a substrate by using an insulating material on the surface of the metal foil A of the multilayer wiring sheet of the capacitor; 2) The saturation of any part of the metal body B is made to insulate the above insulating material a step of exposing the layer; 3) removing the exposed insulating layer by laser irradiation to form a hole to expose the metal foil A, and 4) forming a metal step on both sides of the surface of the substrate including the hole; 5) forming a capacitor a step of etching a metal layer on a dielectric film of a material for a multilayer wiring board to form a capacitor electrode A of any shape; 6) etching a dielectric film of the exposed dielectric film to form a capacitor dielectric having an arbitrary shape of the electrode A pattern a step of: forming a capacitor electrode B having an arbitrary shape including a dielectric pattern of the container by etching the metal foil A exposed by removing the dielectric film. (2) A method of manufacturing a multilayer wiring board in which a capacitor is provided, in a method of manufacturing a multilayer wiring board in which a capacitor is provided, wherein in the etching step of the feature 5) or 7), a metal foil is laminated on the substrate A circuit of any shape is formed on the surface of b -28- 1251536 (24). (3) A method for manufacturing a multilayer wiring board in which a capacitor is provided is a dielectric layer having a capacitance of 1 〇 2 〇〇〇 and a film thickness of 0.0 5 〜 2 // m on one side of the metal foil A A material for a multilayer wiring board in which a capacitor is provided in a film, which is characterized in that: 1) a step of forming a substrate by laminating a metal foil B with an insulating material on a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided 2) performing laser irradiation on any part of the metal foil B, removing the metal foil B and the insulating layer formed by the above insulating material to form a hole, and exposing the metal foil A; 3) in the hole a step of forming a metal layer on both sides of the substrate surface; 4) a step of etching a metal layer on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed to form a capacitor electrode A pattern of an arbitrary shape; 5) exposing a dielectric film is formed by engraving a capacitor dielectric having an arbitrary shape including a capacitor electrode A pattern; and 6) forming a capacitor dielectric pattern by starving the metal poise A exposed by removing the dielectric film. Arbitrarily The step of forming capacitor electrode B. (4) A method of manufacturing a multilayer wiring board with a capacitor built therein, which is a method for manufacturing a multilayer wiring board having a capacitor provided in (3), characterized in that in the etching step of 4) or 6), lamination on a substrate A circuit of any shape is formed on the surface of the metal foil b. (5) A method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a metal film A is provided with a dielectric film having a permittivity of 1 〇 to 2000 and a film thickness of 0.0 5 to 2 // m on one side. A material for a multilayer wiring board having a built-in capacitor, which is characterized by having: i) a multilayer wiring board having a capacitor built therein> 29-(25) 1251536

用材料之金屬箔 A面之任意部位配設貫穿孔，且以含有熱硬化性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B積層來形成基板之步驟；2 )在基板表面之至少介電質薄膜側形成金屬層之步驟；3 )對內設電容器之多層配線板用材料之介電質薄膜上之金屬層以蝕刻形成任意形狀之電容器電極A圖案之步驟；4 )對露出之介電質薄膜以鈾刻形成含有電容器電極 A圖案之任意形狀之電容器介電質之步驟；以及5 )對除去介電質薄膜而露出之金屬箔A以蝕刻形成含有電容器介電質圖案之任意之形狀之電容器電極B之步驟。A step of forming a through hole by arranging a through hole at any portion of the metal foil A surface of the material, and filling the through hole with a conductive paste containing a thermosetting resin and a metal material, and forming a substrate by laminating the metal foil B with an insulating material 2) a step of forming a metal layer on at least the dielectric film side of the substrate surface; 3) etching a metal layer on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed to form an arbitrary shape of the capacitor electrode A pattern a step of: forming a capacitor dielectric having an arbitrary shape of a capacitor electrode A pattern by uranium engraving on the exposed dielectric film; and 5) etching the metal foil A exposed by removing the dielectric film The step of capacitor electrode B having any shape of a capacitor dielectric pattern.

(6 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔A單面配設著電容率爲10〜2000且膜厚爲 0.0 5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔 A面之任意部位配設貫穿孔，且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )在基板表面之至少介電質薄膜側形成金屬層之步驟；3 )對內設電容器之多層配線板用材料之介電質薄膜上之金屬層以蝕刻形成任意形狀之電容器電極A圖案之步驟；4 )對露出之介電質薄膜以鈾刻形成含有電容器電極A圖案之任意形狀之電容器介電質之步驟；以及5 )對除去介電質薄膜而露出之金屬箔A以鈾刻形成含有電容器介電質圖案之任意形狀之電容器電極B之步驟。 -30- (26) 1251536 (7 ) —種內設電容器之多層配線板之製造方法’係如（5 )或（6 )之內設電容器之多層配線板之製造方法’ 其特徵爲，3 )或5 )之蝕刻步驟中，在基板之積層著金屬箔B之面上形成任意形狀之電路。 (8 )如（1 )〜（7 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，具有在上述介電質薄膜及上述金屬層間形成由鉻、鉬、鈦、以及鎳所構成之群組所選取之至少1種之其他金屬層之步驟。 (9 ) 一種內設電容器之多層配線板之製造方法，係採用金屬箔A單面配設著電容率爲1〇〜2000且膜厚爲〇· 05〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )實施金屬箔B之任意部位之蝕刻除去，使上述絶緣材料形成之絶緣層露出之步驟；3 )利用雷射照射除去露出之絶緣層來形成孔，而使金屬范 A 露出之步驟；4)在含有孔內之基板之兩面形成〇.1〜5 从m之金屬層之步驟；5)以保留電容器電極a部份、及含有孔部之任意部份之方式，在基板表面上形成金屬電鍍抗蝕層之步驟；6 )利用金屬電鍍在含有上述電容器電極 A部份及孔部之部份形成導體圖案之步驟；7 )用以除去金屬電鍍抗蝕層之步驟；8 )用以蝕刻除去露出基板表面之Q.1〜5//m之金屬層之步驟；9)對露出之介電質薄膜以蝕刻形成含有電容器電極A圖案之任意形狀之電容器 -31 - (27) 1251536 介電質之步驟；10)對除去介電質薄膜而露出之金屬箔A 以蝕刻形成含有電容器介電質圖案之任意形狀之電容器電極B之步驟；以及1 1 )對露出之金屬箔B實施蝕刻而形成電路之步驟。 (1 〇 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔 A單面配設著電容率爲10〜2000且膜厚爲〇· 05〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：i )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )對金屬箔B之任意部位實施雷射照射，同時除去金屬箔B、及由上述絶緣材料所形成之絶緣層來形成孔，而使金屬箔A露出之步驟；3 )在含孔內在內之基板兩面形成0.1〜5//m之金屬層之步驟；4)以保留電容器電極A部份、及含有孔部之任意部份之方式，在基板表面上形成金屬電鍍抗鈾層之步驟；5 )利用金屬電鍍在含有上述電容器電極A部份及孔部之部份形成導體圖案之步驟；6 )用以除去金屬電鍍抗蝕層之步驟；7 )用以蝕刻除去露出基板表面之〜5//m之金屬層之步驟；8 )對露出之介電質薄膜以蝕刻形成含有電容器電極 A圖案之任意形狀之電容器介電質之步驟；9 )對除去介電質薄膜而露出之金屬箔A以蝕刻形成含有電容器介電質圖案之任意形狀之電容器電極B之步驟；以及1 0 )對露出之金屬箔B實施鈾刻而形成電路之步驟。 (1 1 ) 一種內設電容器之多層配線板之製造方法，係 -32- 1251536 (28) 採用金屬箔A單面配設著電容率爲10〜2000且膜厚爲 0.0 5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以含有熱硬化性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用半固化片實施金屬箔B之積層來形成基板之步驟；2) 在基板之至少介電質薄膜側之表面形成〇 . 1〜5 // m之金屬層之步驟；3 )以保留含有電容器電極A部份之任意部份之方式，在基板表面上形成金屬電鍍抗蝕層之步驟；4) 利用金屬電鍍在含有電容器電極 A部份之部份形成導體圖案之步驟；5 )用以除去金屬電鍍抗蝕層之步驟；6 )用以蝕刻除去露出基板表面之0 . 1〜5 // m之金屬層之步驟； 7 )對露出之介電質薄膜以蝕刻形成含有電容器電極A圖案之任意形狀之電容器介電質之步驟；以及8 )對除去介電質薄膜而露出之金屬箔 A以鈾刻形成含有電容器介電質圖案之任意形狀之電容器電極B，並對露出之金屬箔B 實施蝕刻而形成電路之步驟。 (1 2 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔 A單面配設著電容率爲10〜2000且膜厚爲〇 . 〇 5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔’且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔’並利用半固化片實施金屬箔B之積層來形成基板之步驟；2 )在基 -33- (29) 1251536 板之至少介電質薄膜側之表面形成〇 . 1〜5 // m之金屬層之步驟；3 )以保留含有電容器電極A部份之任意部份之方式，在基板表面上形成金屬電鍍抗蝕層之步驟；4 )利用金屬電鍍在含有電容器電極 A部份之部份形成導體圖案之步驟；5 )用以除去金屬電鍍抗鈾層之步驟；6 )用以鈾刻除去露出基板表面之0.1〜5//m之金屬層之步驟；7) 對露出之介電質薄膜以蝕刻形成含有電容器電極A圖案之任意形狀之電容器介電質之步驟；以及8 )對除去介電質薄膜而露出之金屬箔 A以鈾刻形成含有電容器介電質圖案之任意形狀之電容器電極B，並對露出之金屬箔B實施蝕刻而形成電路之步驟。 (13) 如（9)〜（12)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，至少形成於介電質薄膜表面之0.1〜5//m之金屬層含有：從絡、鉬、鈦、及鎳所構成之群組所選取之至少1種之金屬層、或從銅、銀、錫、鎳、及鋅所構成之群組所選取之至少1種之金屬層、或從鉻、鉬、鈦、及鎳所構成之群組所選取之至少1種之金屬層；以及從銅、銀、錫、鎳、及鋅所構成之群組所選取之至少1種之金屬層。 (14) 如（9)〜（13)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲’利用金屬電鍍形成之導體圖案含有從銅、銀、錫、鎳、以及鋅所構成之群組所選取之至少1種以上之金屬。 (15) 一*種內設電容器之多層配線板之製造方法’係 -34- (30) 1251536 採用金屬箔A單面配設著電容率爲ι〇〜2000且膜厚爲 ϋ·ΰ5〜之介電質薄膜之內設電容器之多層配線板用材料’其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以含有熱硬化性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 ) 在介電質薄膜表面之任意部份以利用化學反應實施金屬化之導電性糊形成金屬層，用以形成期望之電容器電極A 之步驟；3)以保留介電質薄膜之至少含有電容器電極A 之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及4 )對除去介電質薄膜而露出之金屬箔A 以餓刻形成含有電容器介電質圖案之任意形狀之電容器電極B ’並對露出之金屬箔B實施蝕刻而形成電路之步驟。 (1 6 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔 Α單面配設著電容率爲10〜2000且膜厚爲〇·〇5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料’其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔 A面之任意部位配設貫穿孔，且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )在介電質薄膜表面之任意部份以利用化學反應實施金屬化之導電性糊形成金屬層，用以形成期望之電容器電極A之步驟；3 )以保留介電質薄膜之至少含有電容器電極A之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之 -35- (31) 1251536 步驟；以及4 )對除去介電質薄膜而露出之金屬箔A以蝕刻形成含有電容器介電質圖案之任意形狀之電容器電極B ’並對露出之金屬箔B實施鈾刻而形成電路之步驟。(6) A method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a metal foil A is disposed on one side of a dielectric film having a permittivity of 10 to 2,000 and a film thickness of 0.05 to 2 // m The material for a multilayer wiring board of a capacitor is characterized in that: 1) a through hole is formed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and the metallization is performed by a chemical reaction. a step of filling the through hole and forming a substrate by laminating the metal foil B with an insulating material; 2) forming a metal layer on at least the dielectric film side of the substrate surface; 3) multilayering the capacitor a step of etching a metal layer on a dielectric film of a material for a wiring board to form a capacitor electrode A pattern of an arbitrary shape; 4) forming a capacitor of any shape including a capacitor electrode A pattern by uranium etching on the exposed dielectric film And a step of forming a capacitor electrode B having an arbitrary shape of a capacitor dielectric pattern by uranium engraving on the metal foil A exposed by removing the dielectric film. -30- (26) 1251536 (7) A method of manufacturing a multilayer wiring board in which a capacitor is built is a manufacturing method of a multilayer wiring board in which a capacitor is provided in (5) or (6), characterized in that 3) Or in the etching step of 5), a circuit of an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated. (8) The method for producing a multilayer wiring board having a capacitor provided in any one of (1) to (7), characterized in that the method comprises forming chromium, molybdenum and titanium between the dielectric film and the metal layer. And the step of at least one other metal layer selected by the group consisting of nickel. (9) A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein a metal foil A is provided with a dielectric film having a permittivity of 1 〇 to 2000 and a film thickness of 〇· 05 〜2 // m on one side A material for a multilayer wiring board in which a capacitor is provided, comprising: 1) a step of forming a substrate by laminating a metal foil B with an insulating material on a surface of a metal foil A of a material for a multilayer wiring board in which a capacitor is provided; 2) a step of performing etching removal of any portion of the metal foil B to expose the insulating layer formed of the insulating material; 3) a step of removing the exposed insulating layer by laser irradiation to form a hole to expose the metal A; 4) a step of forming a metal layer of 〇.1~5 from m on both sides of the substrate containing the hole; 5) forming a metal plating resist on the surface of the substrate by retaining a portion of the capacitor electrode a and containing any portion of the hole portion a step of etching a layer; 6) a step of forming a conductor pattern on a portion containing the electrode A portion and the hole portion of the capacitor electrode by using metal plating; 7) a step of removing the metal plating resist layer; 8) etching for removing the exposed portion Q of the substrate surface a step of a metal layer of .1 to 5//m; 9) a step of etching a dielectric film of the exposed shape to form a capacitor-31 - (27) 1251536 dielectric having an arbitrary shape of the capacitor electrode A; 10) a step of etching the metal foil A exposed by removing the dielectric film to form a capacitor electrode B having an arbitrary shape including a capacitor dielectric pattern; and 1) a step of etching the exposed metal foil B to form a circuit. (1 〇) — A method for manufacturing a multilayer wiring board with a built-in capacitor, which is provided with a dielectric film having a permittivity of 10 to 2000 and a film thickness of 〇· 05 to 2 // m on one side of the metal foil A. A material for a multilayer wiring board having a capacitor, comprising: i) a step of forming a substrate by laminating a metal foil B with an insulating material on a surface of a metal foil A of a material for a multilayer wiring board in which a capacitor is provided; a step of performing laser irradiation on any portion of the metal foil B, removing the metal foil B and the insulating layer formed by the insulating material to form a hole, and exposing the metal foil A; 3) in the hole a step of forming a metal layer of 0.1 to 5//m on both sides of the substrate; 4) a step of forming a metal plated anti-uranium layer on the surface of the substrate by retaining a portion of the capacitor electrode A and containing any portion of the hole portion; a step of forming a conductor pattern by metal plating on a portion including the capacitor electrode A portion and the hole portion; 6) a step of removing the metal plating resist layer; and 7) etching for removing the surface of the exposed substrate; /m metal layer step; 8) a step of etching a dielectric film having an arbitrary shape of a capacitor electrode A pattern by etching the exposed dielectric film; 9) etching the metal foil A exposed by removing the dielectric film to form a capacitor dielectric pattern a step of capacitor electrode B of any shape; and 10) a step of forming a circuit by performing uranium engraving on the exposed metal foil B. (1 1 ) A method for manufacturing a multilayer wiring board with a built-in capacitor, which is a -32-1215336 (28), a metal foil A is provided with a single-sided capacitance ratio of 10 to 2000 and a film thickness of 0.0 5 to 2 // m The material for a multilayer wiring board in which a capacitor is provided in the dielectric film is characterized in that: 1) a through hole is provided in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and A conductive paste of a thermosetting resin and a metal crucible is filled in the through hole, and a step of forming a substrate by laminating the metal foil B with a prepreg; 2) forming a crucible on a surface of at least the dielectric film side of the substrate. a step of a metal layer of ~5 // m; 3) a step of forming a metal plating resist on the surface of the substrate in such a manner as to retain any portion of the capacitor electrode A; 4) using a metal plating in the electrode containing the capacitor a step of forming a conductor pattern in part A; 5) a step of removing a metal plating resist; and 6) a step of etching to remove a metal layer of 0.1 to 5 // m of the exposed substrate surface; ) forming an exposed dielectric film by etching a capacitor dielectric having any shape of a capacitor electrode A pattern; and 8) forming a capacitor electrode B of any shape containing a capacitor dielectric pattern by uranium etching of the metal foil A exposed by removing the dielectric film The step of etching the exposed metal foil B to form a circuit. (1 2 ) A method for manufacturing a multilayer wiring board in which a capacitor is provided is a dielectric material having a permittivity of 10 to 2000 and a film thickness of 〇 5 〜 2 // m on one side of the metal foil A. A material for a multilayer wiring board in which a capacitor is provided in a film, which is characterized in that: 1) a through hole ' is disposed at any portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided, and a metal is chemically reacted The conductive paste is filled in the through-holes and the step of forming a substrate by using a prepreg to form a substrate; and 2) forming a crucible on the surface of at least the dielectric film side of the base-33-(29) 1251536. a step of a metal layer of 1 to 5 // m; 3) a step of forming a metal plating resist on the surface of the substrate in such a manner as to retain any portion of the capacitor electrode A; 4) using a metal plating in the capacitor a step of forming a conductor pattern on a portion of the electrode A; 5) a step of removing the metal-plated anti-uranium layer; and 6) a step of removing the metal layer of 0.1 to 5 //m from the surface of the substrate by uranium engraving; The exposed dielectric film is etched to form a capacitor dielectric of any shape of the capacitor electrode A pattern; and 8) forming a capacitor electrode B of any shape containing a capacitor dielectric pattern by uranium etching of the metal foil A exposed by removing the dielectric film The exposed metal foil B is etched to form a circuit. (13) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (9) to (12), characterized in that at least a metal layer of 0.1 to 5/m is formed on a surface of the dielectric film And comprising: at least one metal layer selected from the group consisting of complex, molybdenum, titanium, and nickel, or at least one selected from the group consisting of copper, silver, tin, nickel, and zinc a metal layer, or at least one metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel; and at least one selected from the group consisting of copper, silver, tin, nickel, and zinc Metal layer of the species. (14) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (9) to (13), characterized in that the conductor pattern formed by metal plating contains copper, silver, tin, nickel, and At least one metal selected from the group consisting of zinc. (15) A method for manufacturing a multilayer wiring board with a built-in capacitor 'System-34- (30) 1251536 A metal foil A is provided with a single-sided capacitance ratio of ι〇 to 2000 and a film thickness of ϋ·ΰ5~ A material for a multilayer wiring board in which a capacitor is provided in a dielectric film is characterized in that: 1) a through hole is provided in any portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided, and contains heat a conductive paste of a curable resin and a metal crucible is filled in the through hole, and a step of forming a substrate by laminating the metal foil B with an insulating material; 2) performing a chemical reaction on any portion of the surface of the dielectric film The metallized conductive paste forms a metal layer for forming a desired capacitor electrode A; 3) etching is removed by retaining at least any portion of the capacitor electrode A containing the capacitor electrode to form a desired capacitor dielectric And a step of forming a capacitor electrode B' of any shape including a capacitor dielectric pattern by starving the metal foil A exposed by removing the dielectric film and etching the exposed metal foil B The steps to form a circuit. (1) A method for manufacturing a multilayer wiring board in which a capacitor is provided is a dielectric material having a permittivity of 10 to 2000 and a film thickness of 〜·〇5 to 2 // m on one side of a metal foil. A material for a multilayer wiring board in which a capacitor is provided in the film is characterized in that: 1) a through hole is formed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and the metal is chemically reacted. The conductive paste is filled in the through hole, and the step of forming the substrate by laminating the metal foil B with an insulating material; and 2) conducting the metallized conductive paste on any part of the surface of the dielectric film by chemical reaction Forming a metal layer to form a desired capacitor electrode A; 3) etching away the remaining portion of the dielectric film containing at least any portion of the capacitor electrode A to form a desired capacitor dielectric -35- (31) 1251536 steps; and 4) etching the metal foil A exposed by removing the dielectric film to form a capacitor electrode B' of any shape including a capacitor dielectric pattern and performing uranium engraving on the exposed metal foil B And the steps to form a circuit.

(1 7 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔 A表面配設著電容率爲10〜2000且膜厚爲〇·〇5〜2// m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層而形成基板之步驟；2 )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3 )實施金屬箔B之任意部位之蝕刻除去，使上述絶緣材料形成之絶緣層露出之步驟；4 )利用雷射照射除去露出之絶緣層來形成孔，而使金屬箔A露出之步驟；5 )在含孔內在內之基板表面之兩面形成金屬層之步驟；6)以保留該金屬層及金屬箔A之任意部份之方式進行蝕刻除去，形成期望之電容器電極A及電容器電極B之步驟。(1 7) A method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a dielectric film having a capacitance of 10 to 2000 and a film thickness of 〇·〇5 to 2//m is disposed on the surface of the metal foil A A material for a multilayer wiring board having a capacitor therein, comprising: 1) a step of forming a substrate by laminating a metal foil B with an insulating material on a surface of a metal foil A of a material for a multilayer wiring board on which a capacitor is provided; a step of etching to remove any portion of the dielectric film to form a desired capacitor dielectric; 3) performing etching removal of any portion of the metal foil B to expose the insulating layer formed of the insulating material Step; 4) a step of removing the exposed insulating layer by laser irradiation to form a hole to expose the metal foil A; 5) a step of forming a metal layer on both sides of the surface of the substrate including the hole; 6) retaining the metal The layer and the metal foil A are etched and removed to form a desired capacitor electrode A and capacitor electrode B.

(1 8 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔A表面配設著電容率爲10〜2000且膜厚爲〇 . 0 5〜2 μ m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3 )對金屬箔B之任意部位實施雷射照射，同時除去金屬箔 -36- (32) 1251536 B '及上述絶緣材料所形成之絶緣層來形成孔，而使金屬 A露出之步驟；4)在含孔內在內之基板表面之兩面形成&屬層之步驟；以及5 )以保留該金屬層及金屬箔A之任意部份之方式進行蝕刻除去，形成期望之電容器電極A 及電容器電極B之步驟。 (1 9 ) 一種內設電容器之多層配線板之製造方法，係採用金屬箔 A單面配設著電容率爲10〜2000且膜厚爲 α·〇5〜之介電質薄膜之內設電容器之多層配線板用材料’其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以含有熱硬化性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 ) 以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3)在基板之至少具有電容器介電質之表面形成金屬層之步驟；以及4)以保留該金屬層及金屬箔A之任意部份之方式進行蝕刻除去，形成期望之電容器電極A及電容器電極B之步驟。 (20 ) —種內設電容器之多層配線板之製造方法，係採用金屬箔 A單面配設著電容率爲1〇〜2000且膜厚爲 0 · 0 5〜2 // m之介電質薄膜之內設電容器之多層配線板用材料，其特徵爲，具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )以保 •37- (33) 1251536 留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3)在基板之至少具有電容器介電質之表面形成金屬層之步驟；以及4 )以保留該金屬層及金屬箔A之任意部份之方式進行蝕刻除去，形成期望之電容器電極A及電容器電極B之步驟。 (21) 如（6) 、 (12) 、 (15) 、 (16)、或（20 )之內設電容器之多層配線板之製造方法，其特徵爲，利用化學反應實施金屬化之導電性糊含有從金、白金、銀、銅、鈀、以及釕所構成之群組所選取之至少1種以上之金屬粒子，且其金屬粒子之平均粒徑爲0.1〜10nm。 (22) 如（1)〜（21)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，蝕刻除去介電質薄膜之方法係離子束蝕刻法、RIE ( R e a c t i v e I ο η E t c h i n g ) 法、或溶液蝕刻法之其中任一種方法。 (23) 如（1)〜（22)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，電容器電極B係多層配線板之接地層或電源層。 (24 )如（1 )〜（23 )之其中任一項之內設電容器之多層配線板之製造方法’其特徵爲，基板之絶緣層之形成上所使用之絶緣材料係由樹脂、及玻璃織布或玻璃不織布所構成之半固化片。 (25)如（1)〜之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，基板之絶緣層之形成上所使用之絶緣材料，係含有之樹脂爲熱硬化性樹脂之 -38- (34) 1251536 半固化片，該熱硬化性樹脂之玻璃轉移點溫度爲1 70°C以上。 (2 6 )如（1 )〜（2 5 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，採用介電質薄膜係由鈦酸鋇、鈦酸緦、鈦酸鈣、鈦酸鎂、鈦酸鉛、鈦酸鉍、二氧化鈦、鉻酸鋇、銷酸鈣、鉻酸鉛、鈦酸鋇緦、鉻鈦酸鉛、以及鎂鈮酸鉛-鈦酸鉛之其中任一種、或含有其中任 2種以上之固溶體、或含有其中任2種以上之積層體所構成之膜之內設電容器之多層配線板用材料。 (27 )如（1 )〜（26 )之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，採用金屬箔A係由銅所構成，且形成介電質薄膜之面上配設著銅之氧化保護覆膜，形成前述銅之氧化保護覆膜之金屬係從白金、金、銀、鈀、釕、以及銥所構成之群組所選取之1種以上之內設電容器之多層配線板用材料。 (28) 如（1)〜（26)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，採用金屬箔 A係由銅所構成，且形成介電質薄膜之面上配設著安定之自氧化覆膜，形成前述安定之自氧化覆膜之金屬係從鉻、鉬、鈦、以及鎳所構成之群組所選取之1種以上之內設電容器之多層配線板用材料。 (29) 如（1)〜（28)之其中任一項之內設電容器之多層配線板之製造方法，其特徵爲，採用金屬箔A之形成介電質薄膜之面之表面粗糙度爲0.01〜0.5//m之內 -39 - (35) 1251536 設電容器之多層配線板用材_斗。本說明書所示之內容，係和日本國特許出願2 0 0 3 -077695 (出願日 2003 年 3 月 20 日）、2003-078324(出願日2 0 0 3年3月2 0日）、2 〇〇 3 _ 3 6 8 8 5 7 (出願日2 0 0 3年 10月29日）、以及2003-376604(出願日2003年11月 6日）所含主題相關者，前述諸文件皆屬本說明書之一部份。(1 8 ) A method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a surface of the metal foil A is provided with a dielectric film having a permittivity of 10 to 2000 and a film thickness of 5 0.5 5 2 μm. A material for a multilayer wiring board in which a capacitor is provided, comprising: 1) a step of forming a substrate by laminating a metal foil B with an insulating material on a surface of a metal foil A of a material for a multilayer wiring board in which a capacitor is provided; 2) Etching to remove any portion of the dielectric film to form a desired capacitor dielectric; 3) performing laser irradiation on any portion of the metal foil B while removing the metal foil -36- (32) 1251536 B 'and the insulating layer formed by the insulating material to form a hole to expose the metal A; 4) a step of forming a & genus layer on both sides of the substrate surface including the hole; and 5) to retain the The metal layer and any part of the metal foil A are etched and removed to form a desired capacitor electrode A and capacitor electrode B. (1) A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein a metal capacitor A is provided with a capacitor having a dielectric constant of 10 to 2000 and a dielectric film having a thickness of α·〇5~ The material for a multilayer wiring board is characterized in that: 1) a through hole is formed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and the thermosetting resin and the metal material are contained. a conductive paste is filled in the through hole, and a step of forming a substrate by laminating the metal foil B with an insulating material; 2) etching is removed by retaining any portion of the dielectric film to form a desired capacitor dielectric a step of forming a metal layer on a surface of the substrate having at least a capacitor dielectric; and 4) etching and removing the metal layer and any portion of the metal foil A to form a desired capacitor electrode A And the step of capacitor electrode B. (20) A method for manufacturing a multilayer wiring board in which a capacitor is provided, wherein a dielectric material having a permittivity of 1 〇 to 2000 and a film thickness of 0·0 5 to 2 // m is disposed on one side of the metal foil A A material for a multilayer wiring board in which a capacitor is provided in a film, comprising: 1) a through hole is formed in any portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided, and a metal is chemically reacted The conductive paste is filled in the through hole, and the step of forming the substrate by laminating the metal foil B with an insulating material; 2) the method of retaining any part of the dielectric film by the protection of 37-(33) 1251536 a step of etching to form a desired capacitor dielectric; 3) a step of forming a metal layer on a surface of the substrate having at least a capacitor dielectric; and 4) a manner of retaining the metal layer and any portion of the metal foil A The etching is performed to remove the desired capacitor electrode A and capacitor electrode B. (21) A method of manufacturing a multilayer wiring board having a capacitor provided in (6), (12), (15), (16), or (20), characterized in that the conductive paste is metallized by a chemical reaction At least one metal particle selected from the group consisting of gold, platinum, silver, copper, palladium, and rhodium is contained, and the average particle diameter of the metal particles is 0.1 to 10 nm. (22) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (1) to (21), characterized in that the method of etching and removing the dielectric film is ion beam etching, RIE (R eactive Any of the methods of I ο η E tching ) or solution etching. (23) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (1) to (22), characterized in that the capacitor electrode B is a ground layer or a power supply layer of a plurality of wiring boards. (24) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (1) to (23) characterized in that the insulating material used for forming the insulating layer of the substrate is made of a resin and a glass. A prepreg composed of a woven or glass non-woven fabric. (25) A method of producing a multilayer wiring board having a capacitor provided in any one of (1) to (1), wherein the insulating material used for forming the insulating layer of the substrate is thermosetting. Resin -38- (34) 1251536 Prepreg, the thermosetting resin has a glass transition point temperature of 1 70 ° C or higher. (2) The method for producing a multilayer wiring board having a capacitor provided in any one of (1) to (25), characterized in that the dielectric film is made of barium titanate, barium titanate, titanium Calcium acid, magnesium titanate, lead titanate, barium titanate, titanium dioxide, barium chromate, calcium pinchate, lead chromate, barium titanate, lead chromite titanate, lead magnesium citrate-lead titanate Any of them, or a material for a multilayer wiring board in which a capacitor including two or more of them is contained, or a capacitor including a laminate of two or more of them is provided. (27) A method of producing a multilayer wiring board having a capacitor provided in any one of (1) to (26), characterized in that the metal foil A is made of copper and the surface of the dielectric film is formed. An oxide protective film of copper is disposed thereon, and the metal forming the oxidized protective film of copper is one or more types of capacitors selected from the group consisting of platinum, gold, silver, palladium, rhodium, and iridium. The material for the multilayer wiring board. (28) A method of producing a multilayer wiring board having a capacitor provided in any one of (1) to (26), characterized in that the metal foil A is made of copper and the surface of the dielectric film is formed. A multilayer wiring board in which one or more types of internal capacitors selected from the group consisting of chromium, molybdenum, titanium, and nickel are formed by a stable self-oxidizing coating film. Use materials. (29) A method of manufacturing a multilayer wiring board having a capacitor provided in any one of (1) to (28), characterized in that the surface roughness of the surface on which the dielectric film is formed using the metal foil A is 0.01 ~0.5//m -39 - (35) 1251536 Capacitor multilayer wiring board material _ bucket. The contents shown in this manual are related to the Japanese license 2 0 0 3 -077695 (the date of March 20, 2003), 2003-078324 (the date of March 20, 2003), 2 〇〇3 _ 3 6 8 8 5 7 (when the wish date is October 29, 2003), and 2003-376604 (the date of the wish day, November 6, 2003), the above-mentioned documents are the present specification. One part.

【實施方式】 (內設電容器之多層配線板用材料）本發明之一實施形態，係關於金屬箔表面配設著電容率爲10〜2000且膜厚爲0.05〜2//m之介電質薄膜之內設電容器之多層配線板用材料。此多層配線板用材料時，因係在金屬箔表面形成介電質薄膜，故很容易得到均一膜厚之介電質薄膜，且電容器容量之誤差會較小。[Embodiment] (Material for multilayer wiring board in which a capacitor is provided) According to an embodiment of the present invention, a dielectric material having a permittivity of 10 to 2,000 and a film thickness of 0.05 to 2/m is disposed on the surface of the metal foil. A material for a multilayer wiring board in which a capacitor is provided in a film. In the case of the material for a multilayer wiring board, since a dielectric film is formed on the surface of the metal foil, a dielectric film having a uniform film thickness can be easily obtained, and the error in the capacity of the capacitor is small.

爲了確保絶緣性且抑制漏洩電流，介電質薄膜之膜厚應爲0 · 0 5 // m以上，0 · 1 // m以上更佳。又，若考慮經濟效益，則以2 // m以下之膜厚爲佳，1 // m以下更佳。因此，膜厚應爲〇 · 0 5〜2 // m，0 · 1〜1 // m更佳。爲了得到 5 00pF/mm2以上之電容密度，必要電容率在膜厚爲〇.〇5 // m時應爲2 · 9以上、0.1 // m時應爲5 · 7以上、1 // m時應爲5 7以上、2 // m時應爲1 1 3以上。因此，若採用電容率爲2.9〜1 1 3之薄膜介電質，則〇 · 〇 5〜2 // m之膜厚可形成5 0 Op F/mm2之薄膜電容器。然而，薄膜介電質之電容率 -40- (36) 1251536 愈局’則對內設電容器之小型化愈有利，故以1 0〜2 Ο Ο Ο 爲佳，20〜2000更佳。此處之電容率係指25 °C之溫度管理環境下依據IPC-65 0 2.5.5.2以1 MHz之頻率檢測到之値 °又’膜厚之値係利用如掃描型電子顯微鏡之可觀察低於〇·〇5//ηι之厚度之裝置觀察形成電極之電容器之剖面所得〇介電質薄膜若能形成電容率爲10〜2000且膜厚爲〇· 05〜2 // m之介電質薄膜則有任何限制，然而，應採用由鈦酸鋇、鈦酸總、鈦酸錦、鈦酸鎂、欽酸鉛、鈦酸鉍、二氧化鈦、銷酸鋇、鉻酸鈣、锆酸鉛、鈦酸鋇鋸、鉻鈦酸鉛、以及鎂鈮酸鉛-鈦酸鉛等之介電質所構成之膜。此時，亦可使用2種以上之固溶體及積層體。一般而言，具有鈣鈦礦晶形結構之金屬氧化物具有高電容率係大家所知，故十分適合。金屬箔則例如銅箔、銀箔、錫箔、鎳箔、以及鋅箔。其中，若考慮電性特性及經濟效益，則以銅箔爲佳。金屬箔之厚度以1 〇〜5 0 // m爲佳。使用銅箔時，銅箔表面應配設當做銅之氧化保護覆膜使用之金屬層、及/或用以形成安定之自氧化覆膜之金屬層。這些覆膜之厚度應爲0.1 〜3 μ m。當做銅之氧化保護覆膜使用之金屬層，應爲白金、金、銀、钯、釘、以及銥等之金屬fe。金屬箱使用銅范時，若直接在銅表面形成金屬氧化物之介電質薄膜，則金屬氧化物會對銅供應氧而在界面產生氧化銅，故會降低密合性 -41 - 1251536 (37) 。因此，應形成可阻隔金屬氧化物供應之氧且可確保與銅之密合性之氧化保護覆膜。形成自氧化覆膜之金屬層應爲鉻、鉬、鈦、以及鎳等之金屬膜。金屬箔使用銅箔時，可能因爲氧化銅之產生而降低密合性，故應形成可阻隔金屬氧化物之介電質薄膜供應之氧且可確保與銅之密合性之自氧化覆膜。金屬箔表面粗糙度應爲〇·〇1〜〇.5//m。介電質薄膜之厚度如前面所述，應爲〇·〇5〜2//m，0.1〜l//m更佳。形成介電質薄膜之基板之表面粗糙度至少必須低於介電質薄膜之厚度，爲了確保漏洩電流等之絶緣膜之信賴性，應爲低於介電質薄膜之厚度之50%。因此，雖然可以爲0.025 〜0.5 // m之表面粗糙度，然而，爲了確保信賴性，表面粗糙度應爲〇 · 〇 1〜〇 . 5 // m。此處，表面粗糙度係指以掃描型顯微鏡觀察表面所得之任意十點之凹凸差之平均値。在金屬箔上形成介電質薄膜之方法亦可採用例如真空蒸鍍法、離子鍍法、CVD ( Chemical Vapor Deposition) 法、濺鍍法、或溶膠-凝膠法。真空蒸鑛法係在1.3 X l(T4Pa以下之高真空中實施薄膜材料之加熱蒸鍍，使該蒸發粒子附著於基板上而形成介電質薄膜之技術。離子鍍法則係爲了提高真空蒸鍍膜對基板之附著強度，而實施蒸發粒子之離子化並利用電場加速後使其附著於基板上並形成介電質薄膜之技術。CVD法係使含有用以形成薄膜之元素之鹵化物、硫化物、氫化物、以及有機金屬化合物等在高溫中或電漿中實施熱分解· -42- (38) 1251536 氧化·還原·聚合或氣相化學反應等後，使薄膜組成附著於基板上而形成介電質薄膜之技術。濺鍍法係對目標物照射離子，使濺鍍蒸發之目標物質附著於基板上而形成介電質薄膜之技術。溶膠-凝膠法係將含有用以形成薄膜之元素之溶膠溶液塗布於基板上，利用縮合反應實施凝膠化後，再實施高溫退火而形成介電質薄膜之技術。在金屬箔表面形成介電質薄膜時，應使用滾筒狀金屬箔且使金屬箔在定溫管理之加熱爐內連續移動之情形下形成介電質薄膜。連續處理不但可形成均一品質之介電質薄膜，亦具有較佳之經濟效益。 (內設電容器之多層配線板用基板）其次，本發明之一實施形態，係關於基板內部具有用以連結導體層間之通孔，且在具有平滑表面之金屬層之基板表面形成電容率爲10〜2000且膜厚爲0.05〜2//m之介電質薄膜之內設電容器之多層配線板用基板。依據此實施形態，因使用基板內部具有通孔之基板，與電容器電極連結之配線圖案可以任意設計。又’因係在 g B平滑之金屬層表面形成介電質薄膜，故很容易得到均一膜厚之介電質薄膜，且電容器容量之誤差亦較小。金屬層以銅爲佳，銅箔表面應配設氧化保護覆膜及/ 或自氧化覆膜來防止銅之氧化。介電質薄膜可利用和內設電容器之多層配線板用材料所使用之介電質薄膜相同者，以和前述相同之方法形成。 -43- (39) 1251536 利用通孔之導體層間之連結可利用金屬電鍍或導電性糊實施。金屬電鍍可利用銅 '銀、鎳、鋅、及錫等之金屬、或前述之合金。利用金屬電鍍之層間之連結方法亦可利用1 )以鑽床或雷射在張貼金屬之積層板上形成貫穿孔’ 2 ) 附與電鍍觸媒，3 )實施較薄之無電電鍍，4 )實施較厚之電鍍，5 )將熱硬化性孔充塡樹脂充塡至貫穿孔，6 )實施熱硬化性孔充塡樹脂之硬化，7 )實施以基板表面平滑化爲目的之硏磨，8 )附與電鍍觸媒，9 )實施較薄之無電電鍍，1 0 )實施較厚之電鍍之方法。較厚之電鍍亦可以爲較厚之無電電鍍。導電性糊可以爲由金屬塡料及樹脂所構成之導電性糊、或利用化學反應實施金屬化之導電性糊。由金屬塡料（金屬粉）及樹脂所構成之導電性糊以金屬塡料及熱硬化性樹脂所構成者爲佳。金屬塡料例如銀、銅、錫、鉢、或其合金等。其粒徑爲0.5〜10//m。熱硬化性樹脂例如酚樹脂、環氧樹脂、以及氰酸酯樹脂等。導電性糊中之金屬塡料含有量應爲60〜80體積％。由熱硬化性樹脂及金屬塡料所構成之導電性糊可使用市販品之 DD PASTE ( TATSUTA SYSTEM ELECTRONICS 公司製、商品名稱）、DOTITE (藤倉化成株式會社製、商品名稱 )、以及 UNIMEC CONDUCTIVE PASTE ( NAMICS 公司製、商品名稱）等。利用化學反應貫施金屬化之導電性糊相對於由熱硬化 -44 - (40) 1251536 性樹脂及金屬塡料所構成之導電性糊，因爲體電阻率，故電性特性較有利。此種導電性糊例如由微細金屬、分散劑、以及溶劑所構成之糊。該導電性糊中之金子含有量應爲60〜80重量％。利用化學反應實施金之導電性糊之金屬粒子爲例如、金、白金、銀、銅、以及釕等。其平均粒徑爲0 . 1〜1 〇 nm。此導電性糊因用分散劑保護利用氣體中蒸發法所形成之極微金屬粒故在室溫下會呈現和液體大致相同之舉動，可利用印塗布、以及浸漬等來形成電路等。又，若加熱至一定 (15〇〜200°C )，則會因爲補足物質之活性化、及除散劑等之化學反應而使微細金屬粒子間互相接觸，而熔合及熔接，而具有形成金屬化之電性傳導體之性質積層爲目的之加熱加壓時之溫度，亦即，爲了以未達屬熔點之溫度實施金屬化，應採用0.1〜lOnm之金屬來提高反應活性。又，爲了抑制與氧之反應，應採用氧化之金屬之金、白金、銀、銅、鈀、以及釕等金屬。此種利用化學反應實施金屬化之導電性糊可以 NANO PASTE ( HARIMA CHEMICALS，INC.製、商品 )等之市販品，然而，並未限定爲此。利用導電性糊之層間連結方法係可含有1 )以鑽雷射在絶緣層之半固化片上形成貫穿孔之步驟、2 ) 電性糊充塡至貫穿孔之步驟、以及3 )以金屬箔夾住施加壓加熱並進行硬化之步驟。加熱溫度應爲25 t产 °C。因爲超過3 5 0 °C時，一般樹脂會產生熱分解。較低粒子屬粒屬化鈀、係利子，刷、溫度去分加速。以到金粒子不易粒子採用名稱床或將導，實 -350 (41) 1251536 利用金屬電鍍及導電性糊之其中之一實施層間連結時 ’亦不限定爲2層基板，3層以上之基板亦可利用金屬實施基板內部之用以連結導體層間之通孔之電性連結。基板使用之絶緣材料應由樹脂、及玻璃織布或玻璃不織布所構成。因爲基板之加熱處理而處於高溫下時，亦必須能確保基板之剛性。因此，使用由樹脂、及玻璃織布或玻璃不織布所構成之絶緣材料優於只由樹脂及無機塡料所構成之絶緣材料、或由樹脂及纖維素或合成樹脂等紙所構成之絶緣材料等。又，亦可利用高耐熱性之氟樹脂、聚醚醚酮等之熱可塑性樹脂、或聚醯亞胺及聚醯胺醯亞胺等之熱硬化性樹脂之薄板，然而，經濟效益較差。織布或不織布之材質只要在高溫下具有高剛性，亦即，只要爲彈性模量較高者，就沒有特別限制，亦可使用D玻璃、E玻璃、及S玻璃等。基板之絶緣材料使用之樹脂係熱硬化性樹脂，其玻璃轉移點溫度應爲1 7 (TC以上。使用由熱硬化性樹脂、及玻璃織布或玻璃不織布所構成之絶緣材料之基板，具有良好之加工性及經濟效益。又，因爲玻璃轉移點溫度爲1 7 0 °C 以上’可抑制形成介電質薄膜時之熱所導致之劣化。玻璃轉移點溫度爲1 7 0 °C以上之熱硬化性樹脂例如環氧樹脂、變性聚醯亞胺樹脂、變性三氮雜苯樹脂、變性聚氧化二甲苯樹脂、變性聚二苯醚樹脂、以及變性氰酸酯酯樹脂等，然而，不受限於此。使用環氧樹脂之基板材料可使用 MCL-E-679、MCL-E-679F (以上爲日立化成工業株式會 (42) 1251536In order to ensure insulation and suppress leakage current, the film thickness of the dielectric film should be 0 · 0 5 / m or more, more preferably 0 · 1 / m or more. Further, in consideration of economic benefits, a film thickness of 2 // m or less is preferable, and 1 / m or less is more preferable. Therefore, the film thickness should be 〇 · 0 5~2 // m, 0 · 1~1 // m is better. In order to obtain a capacitance density of 500 kPa/mm2 or more, the necessary permittivity should be 2 · 9 or more and 0.1 · 5 m when the film thickness is 〇.〇5 // m. It should be 1 1 3 or more when it is 5 7 or more and 2 // m. Therefore, if a film dielectric having a capacitance of 2.9 to 1 1 3 is used, a film thickness of 〇 · 〇 5 to 2 // m can be formed into a film capacitor of 50 Op F/mm 2 . However, the permittivity of the film dielectric is -40-(36) 1251536, which is more advantageous for miniaturization of the built-in capacitor, so it is preferable to use 10 to 2 Ο Ο ,, and 20 to 2000 is preferable. The permittivity here refers to the temperature at 25 °C in accordance with IPC-65 0 2.5.5.2 detected at a frequency of 1 MHz, and the thickness of the film is as low as observable by scanning electron microscopy.装置〇〇 5 / / ηι thickness of the device to observe the cross-section of the capacitor forming the electrode obtained 〇 dielectric film can form a dielectric constant of 10~2000 and a film thickness of 〇· 05~2 // m There are any restrictions on the film. However, it should be made of barium titanate, total titanate, titanate, magnesium titanate, lead acid, barium titanate, titanium dioxide, barium strontium, calcium chromate, lead zirconate, titanium. A film composed of a dielectric such as a strontium saw, a lead chromate titanate, and a lead magnesium niobate-lead titanate. In this case, two or more kinds of solid solution and laminate may be used. In general, a metal oxide having a crystal structure of a perovskite has a high permittivity and is well known. Metal foils are, for example, copper foil, silver foil, tin foil, nickel foil, and zinc foil. Among them, in consideration of electrical characteristics and economic benefits, copper foil is preferred. The thickness of the metal foil is preferably 1 〇 to 5 0 // m. When copper foil is used, the surface of the copper foil shall be provided with a metal layer used as an oxidized protective film for copper and/or a metal layer for forming a stable auto-oxidation film. These films should have a thickness of 0.1 to 3 μm. The metal layer used as the oxidized protective coating for copper shall be metal such as platinum, gold, silver, palladium, nails, and tantalum. When a copper box is used, if a dielectric film of a metal oxide is formed directly on the surface of the copper, the metal oxide will supply oxygen to the copper and cause copper oxide at the interface, thereby lowering the adhesion -41 - 1251536 (37 ). Therefore, an oxidative protective film which can block the supply of oxygen to the metal oxide and ensure adhesion to copper should be formed. The metal layer forming the self-oxidation film should be a metal film of chromium, molybdenum, titanium, or nickel. When a copper foil is used for the metal foil, the adhesion may be lowered by the occurrence of copper oxide. Therefore, an oxygen-containing film which can block the oxygen supplied to the dielectric film of the metal oxide and which can secure the adhesion to copper should be formed. The surface roughness of the metal foil should be 〇·〇1~〇.5//m. The thickness of the dielectric film should be 〇·〇5 to 2//m, more preferably 0.1 to l//m, as described above. The surface roughness of the substrate on which the dielectric film is formed must be at least lower than the thickness of the dielectric film, and should be 50% lower than the thickness of the dielectric film in order to ensure the reliability of the insulating film such as leakage current. Therefore, although it is possible to have a surface roughness of 0.025 to 0.5 // m, however, in order to ensure reliability, the surface roughness should be 〇 · 〇 1 to 〇 . 5 // m. Here, the surface roughness refers to the average enthalpy of the unevenness of any ten points obtained by observing the surface with a scanning microscope. The method of forming a dielectric film on the metal foil may be, for example, a vacuum evaporation method, an ion plating method, a CVD (Chemical Vapor Deposition) method, a sputtering method, or a sol-gel method. The vacuum evaporation method is a technique in which a vapor deposition of a film material is performed in a high vacuum of T4Pa or less to adhere the evaporated particles to a substrate to form a dielectric film. The ion plating method is for improving the vacuum evaporation film. A technique of ionizing evaporating particles and accelerating an electric field to adhere to a substrate to form a dielectric thin film on the adhesion strength of the substrate. The CVD method is to form a halide or a sulfide containing an element for forming a thin film. , hydride, and organometallic compounds are thermally decomposed in high temperature or in the plasma. -42- (38) 1251536 Oxidation, reduction, polymerization, gas phase chemical reaction, etc., and then the film composition is attached to the substrate to form a medium. Electro-chemical film technology. Sputtering is a technique in which a target substance is irradiated with ions to cause a target material to be evaporated and adhered to a substrate to form a dielectric film. The sol-gel method will contain an element for forming a film. The sol solution is applied onto a substrate, and gelation is carried out by a condensation reaction, followed by high-temperature annealing to form a dielectric film. Forming a dielectric on the surface of the metal foil In the case of a film, a dielectric film should be formed by using a roll-shaped metal foil and continuously moving the metal foil in a heating furnace controlled by a constant temperature. The continuous treatment can form a uniform quality dielectric film and has a better economy. (Embodiment of Multilayer Wiring Board with Capacitor) Next, an embodiment of the present invention has a permittivity in which a via hole is formed in the substrate to connect the via holes between the conductor layers, and a metal layer having a smooth surface is formed on the surface of the substrate. A substrate for a multilayer wiring board having a capacitor of 10 to 2000 and a film thickness of 0.05 to 2//m. According to this embodiment, a substrate having a through hole in the substrate is used, and the capacitor electrode is connected thereto. The wiring pattern can be arbitrarily designed. Also, since a dielectric film is formed on the surface of the smooth metal layer of g B, it is easy to obtain a dielectric film having a uniform film thickness, and the error of the capacitor capacity is small. Preferably, the surface of the copper foil should be provided with an oxidized protective film and/or an auto-oxidized film to prevent oxidation of the copper. The dielectric film can be used and built-in capacitors. The dielectric film used for the wiring board material is the same as that described above. -43- (39) 1251536 The connection between the conductor layers of the via holes can be performed by metal plating or conductive paste. A metal such as copper 'silver, nickel, zinc, and tin, or an alloy of the foregoing is used. The method of joining between layers by metal plating may also be used to form a through hole '2 by a drill press or a laser on a laminated metal plate. Attached to the plating catalyst, 3) implement thinner electroless plating, 4) implement thicker plating, 5) fill the through hole with the thermosetting hole filling resin, and 6) implement the thermosetting hole filling resin Hardening, 7) performing honing for the purpose of smoothing the surface of the substrate, 8) attaching to the plating catalyst, 9) performing thinner electroless plating, and 10) performing a thicker plating method. Thicker plating can also be thicker electroless plating. The conductive paste may be a conductive paste composed of a metal tantalum or a resin or a conductive paste which is metallized by a chemical reaction. The conductive paste composed of the metal tantalum (metal powder) and the resin is preferably composed of a metal coating and a thermosetting resin. Metallic materials such as silver, copper, tin, antimony, or alloys thereof. Its particle size is 0.5 to 10 / / m. A thermosetting resin such as a phenol resin, an epoxy resin, a cyanate resin or the like. The content of the metal tantalum in the conductive paste should be 60 to 80% by volume. For the conductive paste which consists of a thermosetting resin and a metal material, DD PASTE (TATSUTA SYSTEM ELECTRONICS, product name), DOTITE (made by Fujikura Kasei Co., Ltd., trade name), and UNIMEC CONDUCTIVE PASTE ( NAMICS company system, product name), etc. The conductive paste which is chemically reacted and chemically bonded to the conductive paste composed of the thermosetting -44 - (40) 1251536 resin and the metal tantalum is advantageous in electrical properties because of the volume resistivity. Such a conductive paste is, for example, a paste composed of a fine metal, a dispersant, and a solvent. The metal content in the conductive paste should be 60 to 80% by weight. The metal particles of the conductive paste of the gold which are chemically reacted are, for example, gold, platinum, silver, copper, and ruthenium. The average particle diameter is 0.1 to 1 〇 nm. This conductive paste protects the extremely fine metal particles formed by the evaporation method in the gas by the dispersing agent, so that it exhibits substantially the same behavior as the liquid at room temperature, and can form a circuit by printing, dipping, or the like. In addition, when heated to a certain level (15 〇 to 200 ° C), the fine metal particles come into contact with each other due to the activation of the complementary substance and the chemical reaction of the dispersing agent, and are fused and welded to form a metallization. The nature of the electrical conductor is the temperature at which the laminate is heated and pressurized, that is, in order to carry out the metallization at a temperature that does not reach the melting point, a metal of 0.1 to 1 nm is used to increase the reactivity. Further, in order to suppress the reaction with oxygen, metals such as gold, platinum, silver, copper, palladium, and rhodium of oxidized metal should be used. Such a conductive paste which is metallized by a chemical reaction may be a commercial product such as NANO PASTE (manufactured by HARIMA CHEMICALS, INC.), however, it is not limited thereto. The interlayer bonding method using the conductive paste may include 1) a step of forming a through hole by drilling a laser on the prepreg of the insulating layer, 2) a step of charging the electrical paste to the through hole, and 3) clamping with a metal foil A step of applying pressure heating and hardening is applied. The heating temperature should be 25 t °C. Because it exceeds 305 °C, the resin generally undergoes thermal decomposition. The lower particles are granulated palladium, philosophies, brush, and temperature de-acceleration. When the gold particles are not easily used, the name of the bed or the guide is used. When the layer is connected to one of the metal plating and the conductive paste, it is not limited to a two-layer substrate, and the substrate of three or more layers is also The metal can be electrically connected to the through hole between the conductor layers in the substrate. The insulating material used for the substrate should be composed of resin, glass woven fabric or glass non-woven fabric. It is also necessary to ensure the rigidity of the substrate when the substrate is subjected to heat treatment at a high temperature. Therefore, the use of an insulating material composed of a resin, a glass woven fabric or a glass non-woven fabric is preferable to an insulating material composed of only a resin and an inorganic coating material, or an insulating material composed of a resin and a paper such as cellulose or synthetic resin. . Further, a thermoplastic resin such as a fluororesin or a polyetheretherketone having high heat resistance, or a thin plate of a thermosetting resin such as polyamidimide or polyamidoximine may be used, but the economic efficiency is inferior. The material of the woven fabric or the non-woven fabric is not particularly limited as long as it has a high modulus of elasticity at high temperatures, that is, D glass, E glass, and S glass can be used. The resin-based thermosetting resin used for the insulating material of the substrate has a glass transition point temperature of 17 (TC or more. A substrate made of a thermosetting resin and an insulating material composed of a glass woven fabric or a glass non-woven fabric has a good The processability and economic benefits. Moreover, because the glass transition point temperature is above 170 °C, it can suppress the deterioration caused by the heat when forming the dielectric film. The glass transition point temperature is above 70 °C. a curable resin such as an epoxy resin, a denatured polyimide resin, a denatured triazabenzene resin, a denatured polyoxyxylene resin, a denatured polydiphenyl ether resin, and a denatured cyanate ester resin, etc., however, are not limited Here, MCL-E-679 and MCL-E-679F can be used as the substrate material for epoxy resin (the above is Hitachi Chemical Industry Co., Ltd. (42) 1251536

社製、商品名稱）、R- 1 7 5 5、R-1 5 1 5 (以上爲松下電工株式會社製、商品名稱）、ELC-47 8 1 ( SUMINOTO BAKE LITE CO·，LTD 製、商品名稱）、以及 CS-3665、 CS- 3 3 6 5 S、CS- 3 2 8 7 (以上爲利昌工業株式會社製、商品名稱）等市販品。又’使用變性聚醯亞胺樹脂之銅箔基板可使用MCL-1-671 (日立化成工業株式會社製 '商品名稱 )、以及R-4 7 05 (松下電工株式會社製、商品名稱）等市販品。又’使用變性三氮雜苯樹脂之銅箔基板可使用 CCL-830、CCL-832、CCL-832HS (以上爲三菱氣體化學株式會社製、商品名稱）等市販品。又，使用變性聚二苯醚樹脂之銅箔基板可使用C S · 3 3 7 6 B (利昌工業株式會社製、商品名稱）、TLC-W- 5 96 ( KYOCERA CHEMICAL CORPORATION製、商品名稱）等市販品。對應上述各銅 S β #層化絶緣材料（半固化片）亦可利用各廠商之市販品。 (內设電谷器之多層配線板） (¾設《 $器之多層配線板亦可利用上述內設電容器之多層配線板用材料，利用絶緣層在該銅箔面實施具有導體電路之基板之積層，並形成電容器、以及使銅箔及導體圖 $形成導通來進行製造。又，內設電容器之多層配線板亦 W M i： @ @設電容器之多層配線板用基板形成電容器來進ίτ製造°其次’亦可在上述內設電容器之多層配線板用材料之金S箱（以下稱爲金屬箔a。）上利用絶緣層實施 -47- (43) 1251536 金屬箔（以下稱爲金屬范B。）之積層，並形成電容器及使金屬箔A及金屬箔B形成導通來進行製造。以卞針對其進行說明。 (第1電容器電極之形成）在基板表面之介電質薄膜上形成電容器電極（以下稱爲第1電容器電極。）。第1電容器電極之厚度應爲10〜50//m。低於i0//m 時，若要進一步在電極1之外層形成絶緣層而設置當做電極之引線圖案使用之非貫穿孔時，若採用雷射加工，則介電質薄膜下之金屬層會受損，而有容易破損之問題。又，超過5 0 // m時，以蝕刻形成電極圖案時之加工精度可能會變差。在介電質薄膜之特定位置上形成第1電容器電極之方法有在介電質薄膜之全面形成金屬層後再利用蝕刻形成之方法（第1方法）、形成電鍍抗蝕層後再實施金屬電鍍之方法（第2方法）、以及利用導電性糊實施印刷之方法（第3方法）等。第1方法亦可含有：利用金屬電鍍或濺鍍形成1 0〜 5 0 # m之金屬層之步驟、及蝕刻除去任意部位之步驟。可以成爲第1電容器電極之金屬層有各種金屬，然而，若考慮電性特性及經濟效益，則以銅爲佳。金屬層使用銅時，爲了防止介電質薄膜之氧移動所導致之銅之氧化，金屬層應進一步含有鉻、鉬、鈦、或鎳等，或者，在金屬層及介 -48- (44) 1251536 電質薄膜間配設鉻、鉬、鈦、或鎳等成爲自氧化覆膜之金屬層。第2方法含有：在介電質薄膜之表面形成0.1〜5//m 之金屬層之步驟；以保留含有第1電容器電極之任意部份之方式形成金屬電鍍抗蝕層之步驟；利用金屬電鍍形成 1 0〜5 0 // m之第1電容器電極之步驟；用以蝕刻除去金屬電鍍抗蝕層之步驟；以及用以蝕刻除去形成於介電質薄膜表面之〇·1〜5//m之金屬層之步驟。0.1〜5//m之金屬層可以採用各種金屬，然而，若考慮電性特性及經濟效益，則以銅爲佳。使用銅之時，爲了防止銅之氧化，0.1〜5 // m之金屬層間應配設用以形成自氧化性覆膜之金屬層。形成自氧化性覆膜之金屬層應爲鉻、鉬、鈦、以及鎳等之金屬層。利用金屬電鍍形成之10〜50//m之金屬層，若考慮電性特性及經濟效益，則應含有銅、銀、錫、鎳、或鋅。電鍍抗蝕層可使用例如PHOTEC H-93 3 0 (商品名稱、曰立化成工業株式會社製）。電鍍抗蝕層之蝕刻液及 0.1〜5 # m之金屬層之蝕刻液可使用眾所皆知之物。第3方法係亦可以含有在介電質薄膜之用以形成第1 電容器電極之任意部位上，印刷利用化學反應實施金屬化之導電性糊並實施硬化之步驟。又，亦可在含有成爲第1 電容器電極之部位之部份印刷導電性糊，並蝕刻不必要部位而形成第1電容器電極。利用化學反應實施金屬化之導電性糊可使用內設電容器之多層配線板用基板可使用之前述導電性糊，尤其是，金屬粒子之平均粒徑以0 . 1〜1 〇nm -49- (45) 1251536 爲佳。應用利用化學反應實施金屬化之導電性糊，無需使用處理步驟較多之電鍍處理即可形成第1電容器電極，而可減少內設電容器之多層配線板之製造日數。 (電容器介電質之形成）以保留成爲電容器介電質之部位之方式蝕刻除去前述內設電容器之多層配線板用材料或基板之介電質薄膜，可形成電容器介電質。倉虫刻除去之方法例如離子束餓刻法、RIE ( R e a c t i v e I 〇 η E t c h i n g )法、或濕鈾刻法。離子束蝕刻法係利用電場將氬等惰性氣體之離子實施加速後，將其照射至基板用以除去介電質薄膜之技術。 RIE法係在減壓強電場下產生氟系氣體等反應性之氣體電漿，並利用其除去介電質薄膜之技術。濕蝕刻法係利用可溶解蝕刻溶液（触刻劑）等之介電質之蝕刻溶液（蝕刻劑）來除去介電質薄膜之技術。蝕刻劑可使用眾所熟知之物，例如，含有氟酸之溶液、含有氨及過氧化氫之水溶液、以及含有EDTA、氨、及過氧化氫之水溶液等。然而，氟酸因反應性高而具有危險性。含有氨及過氧化氫之水溶液、以及含有EDTA、氨、及過氧化氫之水溶液係鹼性。因此，利用蝕刻實施圖案化時，蝕刻抗蝕層必須使用耐鹼性之抗蝕層，亦即，必須使用橡膠系抗蝕層等。此種抗蝕層之顯像液及剝離液因爲需要特殊藥品及溶劑，故需要專用設備。因此，亦可使用如下所示2 -50- (46) 1251536 種使用蝕刻劑之方法來實施介電質薄膜之蝕刻。Co., Ltd., product name), R- 1 7 5 5, R-1 5 1 5 (The above is a product name of Matsushita Electric Works Co., Ltd.), ELC-47 8 1 (manufactured by SUMINOTO BAKE LITE CO., LTD, product name ), as well as CS-3665, CS- 3 3 6 5 S, CS- 3 2 8 7 (above, manufactured by Lee Chang Industrial Co., Ltd., trade name). In the case of a copper foil substrate using a denatured polyimide resin, MCL-1-671 (a product name manufactured by Hitachi Chemical Co., Ltd.) and R-4 7 05 (a product name by Matsushita Electric Works Co., Ltd.) can be used. Product. Further, a commercially available product such as CCL-830, CCL-832, or CCL-832HS (above, Mitsubishi Gas Chemical Co., Ltd., trade name) can be used as the copper foil substrate using the denatured triazine resin. In addition, as a copper foil substrate using a denatured polydiphenyl ether resin, a commercially available product such as CS · 3 3 7 6 B (manufactured by Lichang Industrial Co., Ltd.) and TLC-W-5596 (manufactured by KYOCERA CHEMICAL CORPORATION) can be used. Product. Corresponding to each of the above copper S β #layered insulating materials (prepreg), it is also possible to use commercial products of various manufacturers. (Multilayer wiring board with built-in electric grid) (3⁄4) The multilayer wiring board of the device can also use the material for the multilayer wiring board with the built-in capacitor described above, and the substrate with the conductor circuit is implemented on the copper foil surface by the insulating layer. The layer is formed, and a capacitor is formed, and the copper foil and the conductor pattern are formed to be electrically connected. Further, the multilayer wiring board in which the capacitor is provided is also formed by a capacitor for forming a capacitor for the multilayer wiring board of the capacitor. In the next step, a metal foil (hereinafter referred to as a metal foil a) may be used for the metal S-box (hereinafter referred to as a metal foil a) of a material for a multilayer wiring board in which a capacitor is provided. The laminate is formed by forming a capacitor and forming the capacitor and the metal foil A and the metal foil B. The formation of the capacitor electrode is performed on the dielectric film on the surface of the substrate (the formation of the first capacitor electrode). Hereinafter, it is referred to as a first capacitor electrode.) The thickness of the first capacitor electrode should be 10 to 50/m. When it is lower than i0//m, if an insulating layer is further formed on the outer layer of the electrode 1, it is set as the electricity. When the lead pattern is used in a non-through hole, if the laser processing is used, the metal layer under the dielectric film may be damaged, and there is a problem that it is easily broken. Further, when it exceeds 50 // m, the electrode is formed by etching. The processing accuracy may be deteriorated in the pattern. The method of forming the first capacitor electrode at a specific position of the dielectric film may be a method in which a metal layer is formed on the entire surface of the dielectric film and then formed by etching (first method), A method of forming a plating resist, a method of performing metal plating (second method), a method of performing printing by a conductive paste (third method), etc. The first method may further include: forming a layer by metal plating or sputtering. The step of removing the metal layer of 〜50, and the step of removing any portion by etching. The metal layer of the first capacitor electrode may have various metals. However, in consideration of electrical properties and economic benefits, copper is preferred. When copper is used in the layer, in order to prevent oxidation of copper caused by oxygen movement of the dielectric film, the metal layer should further contain chromium, molybdenum, titanium, or nickel, or the like, or in the metal layer and the -48-(44) 1 251536 is provided with a metal layer which is an auto-oxidation film such as chromium, molybdenum, titanium or nickel. The second method comprises the steps of: forming a metal layer of 0.1 to 5//m on the surface of the dielectric film; a step of forming a metal plating resist layer in such a manner as to retain any portion of the first capacitor electrode; a step of forming a first capacitor electrode of 10 to 50 // m by metal plating; and etching to remove the metal plating resist a step of layering; and a step of etching to remove a metal layer of 〇·1~5//m formed on the surface of the dielectric film. The metal layer of 0.1~5//m can be made of various metals, however, if electricity is considered For the characteristics and economic benefits, copper is preferred. When copper is used, in order to prevent oxidation of copper, a metal layer for forming an auto-oxidizing film should be disposed between the metal layers of 0.1 to 5 // m. The metal layer forming the autoxidisable film should be a metal layer such as chromium, molybdenum, titanium, or nickel. A metal layer of 10 to 50/m formed by metal plating should contain copper, silver, tin, nickel, or zinc in consideration of electrical properties and economic efficiency. For the electroplating resist layer, for example, PHOTEC H-93 3 0 (trade name, manufactured by Toray Chemical Industry Co., Ltd.) can be used. An etching solution for plating an anticorrosive layer and an etching solution for a metal layer of 0.1 to 5 m can be used. The third method may include a step of printing and curing the conductive paste which is metallized by a chemical reaction at any portion of the dielectric film for forming the first capacitor electrode. Further, the conductive paste may be printed on a portion including the portion to be the first capacitor electrode, and the unnecessary portion may be etched to form the first capacitor electrode. The conductive paste which is metallized by a chemical reaction can use the above-mentioned conductive paste which can be used for a substrate for a multilayer wiring board in which a capacitor is provided, and in particular, the average particle diameter of the metal particles is 0.1 to 1 〇nm -49- ( 45) 1251536 is preferred. By applying a metallized conductive paste by a chemical reaction, it is possible to form the first capacitor electrode without using a plating process having a large number of processing steps, and it is possible to reduce the number of manufacturing days of the multilayer wiring board in which the capacitor is built. (Formation of Capacitor Dielectric) A capacitor dielectric can be formed by etching away a dielectric thin film for a multilayer wiring board or a substrate of the built-in capacitor so as to remain a portion of the capacitor dielectric. Methods for removing insects, such as ion beam starving, RIE (R e a c t i v e I 〇 η E t c h i n g ), or wet uranium engraving. The ion beam etching method is a technique in which an ion of an inert gas such as argon is accelerated by an electric field and then irradiated onto a substrate to remove a dielectric thin film. The RIE method is a technique in which a reactive gas plasma such as a fluorine-based gas is generated under a reduced electric field and a dielectric thin film is removed. The wet etching method is a technique of removing a dielectric thin film by using an etching solution (etching agent) which dissolves a dielectric such as an etching solution (touching agent). As the etchant, well-known materials such as a solution containing fluoric acid, an aqueous solution containing ammonia and hydrogen peroxide, and an aqueous solution containing EDTA, ammonia, and hydrogen peroxide, and the like can be used. However, hydrofluoric acid is dangerous due to its high reactivity. An aqueous solution containing ammonia and hydrogen peroxide, and an aqueous solution containing EDTA, ammonia, and hydrogen peroxide are alkaline. Therefore, when patterning by etching, it is necessary to use an alkali-resistant resist layer for etching the resist layer, that is, a rubber-based resist layer or the like must be used. Since the developing solution and the stripping solution of such a resist layer require special medicines and solvents, special equipment is required. Therefore, etching of the dielectric film can also be carried out by using an etchant as shown in the following 2 - 50 - ( 46 ) 1251536 .

2種方法係使用含有鉗合劑及過氧化氫之蝕刻劑之方法（第1方法）、及使用含有從硫酸、鹽酸、磷酸、硝酸、以及醋酸所構成之群組所選取之至少1種酸及過氧化氫之鈾刻劑之方法（第2方法）。第1及第2方法實施之介電質薄膜之蝕刻係濕飽刻，其生產性優於乾處理之蝕刻。又，因爲亦可對應大型基板，故較爲經濟。此外，因爲使用通常光刻處理所使用之鹼性顯像型蝕刻抗蝕層，故無需專用設備，亦無需使用特殊之藥液，而較爲便宜且以良好效率實施薄膜圖案化。The two methods are a method using a chelating agent containing a chelating agent and hydrogen peroxide (the first method), and using at least one acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid, and acetic acid, and Method for uranium encapsulation of hydrogen peroxide (second method). The etching of the dielectric film by the first and second methods is wet-saturated, and its productivity is superior to that of the dry process. Moreover, since it can also correspond to a large substrate, it is economical. Further, since the alkaline development type etching resist layer used in the usual photolithography process is used, no special equipment is required, and it is not necessary to use a special chemical liquid, and it is relatively inexpensive and the film patterning is performed with good efficiency.

第1方法時，介電質薄膜之蝕刻劑係使用含有鉗合劑及過氧化氫者，通常，蝕刻劑爲水溶液。因爲未使用氟酸而以含有鉗合劑及過氧化氫之水溶液實施介電質薄膜之蝕刻，藥液之處理上更爲容易也可降低危險性。又，鉗合劑及過氧化氫係通常之印刷配線板製造處理所使用者’使用時不會產生新的重大負擔。蝕刻劑之鉗合劑濃度應爲 0.001〜0.5mol/l。介電質薄@旲之触刻時’最少需要 0.001mol/l，至限度濃度〇·5ηιο1/1爲止之範圍內可任意設定。最好爲〇 · 1〜0 · 3 m ο 1 /1 ’因爲可以獲得具有安定性良好之鈾刻率。又，過氧化氫濃度應爲1〜5 0 wt%。此範圍內可以任意設定過氧化氫濃度來調整蝕刻率。爲了獲得使用上之最低容許蝕刻率，至少需要1 w t%之過氧化氫’至藥液之處理性不會形成問題之5 0 wt %爲止之範圍內可任意設定。最好爲20〜3 Owt% ’因爲可獲得適當之蝕刻率’且 -51 - (47) 1251536 1濃度之管理上亦較爲容易。前述實施濃度管理之蝕刻劑係酸性鈾刻劑，蝕刻劑之pH應管理在2〜7之範圍內。又’亦可利用緩衝液將pH調整至鹼性側，然而，此時必須使用耐鹼性之蝕刻抗蝕層，而耐鹼性抗蝕層通常需要專用設備及藥液◦因此，基於前述理由，最好使蝕刻劑之 p Η位於2〜7之範圍內。本發明所使用之鉗合劑應爲從乙烯二胺四醋酸（ E D T A ) 、hydroxyethylimino diacetic acid ( HIDA )、 imino diacetic acid ( IDA ) 、dihydroxy ethyl glycine ( DHEG )、以及其鹼鹽之群組所選取之至少1種鉗合劑。前述鉗合劑因係水溶性，故無需使用NH4OH、NaOH等之鹼性溶液。因爲有利於取得前述酸性蝕刻劑，且抗蝕層之選擇更爲容易，故亦可降低藥液成本。第2方法使用之介電質薄膜之蝕刻劑係含有從硫酸、鹽酸、磷酸、硝酸、及醋酸所構成之群組所選取之酸、以及過氧化氫，通常爲水溶液。因爲前述酸亦使用於通常之配線板製造上，故處理上較氟酸更爲容易。利用含有前述酸及過氧化氫之水溶液很容易即可實施介電質薄膜之蝕刻〇蝕刻劑之從硫酸、鹽酸、磷酸、硝酸、以及醋酸所構成之群組所選取之至少1種酸之濃度應爲1〜30wt%。濃度愈高鈾刻率可能會愈高，然而，藥液之處理會較爲困難。因此，濃度應以30wt%爲上限。又，爲了獲得使用上之最低容許飩刻率，應爲lwt %以上。最好爲5〜30 wt%，不 (48) 1251536 但處理性佳，且可獲得適當之蝕刻率。又，藥液之處理亦較爲容易，而可得到優良之蝕刻率。In the first method, the etchant for the dielectric film is a device containing a chelating agent and hydrogen peroxide. Usually, the etchant is an aqueous solution. Since the etching of the dielectric film is carried out in an aqueous solution containing a chelating agent and hydrogen peroxide without using hydrofluoric acid, the treatment of the chemical liquid is easier and the risk can be reduced. Further, the user of the conventional printed wiring board manufacturing process of the tongs and hydrogen peroxide system does not generate a significant new burden when used. The concentration of the etchant should be 0.001 to 0.5 mol/l. When the dielectric material is thin, the 触旲触 ’ ’ ’ ’ ’ ’ ’ ’ 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 It is preferable to be 〇 1 to 0 · 3 m ο 1 /1 ’ because it is possible to obtain a uranium engraving rate with good stability. Further, the hydrogen peroxide concentration should be 1 to 50% by weight. The hydrogen peroxide concentration can be arbitrarily set within this range to adjust the etching rate. In order to obtain the lowest allowable etching rate for use, at least 1 w% of hydrogen peroxide is required to be arbitrarily set within a range of 50% by weight which does not cause a problem. It is preferable that the concentration is 20 to 3 Owt% ’ because the appropriate etching rate can be obtained and the concentration of -51 - (47) 1251536 1 is also relatively easy. The etchant for performing the concentration management described above is an acidic uranium engraving agent, and the pH of the etchant should be managed within the range of 2 to 7. In addition, the pH can be adjusted to the alkaline side by using a buffer. However, an alkaline-resistant etching resist must be used at this time, and the alkaline-resistant resist usually requires special equipment and liquid chemicals. Therefore, for the above reasons. Preferably, the p Η of the etchant is in the range of 2 to 7. The chelating agent used in the present invention should be selected from the group consisting of ethylenediaminetetraacetic acid (EDTA), hydroxyethylimino diacetic acid (HIDA), imino diacetic acid (IDA), dihydroxy ethyl glycine (DHEG), and an alkali salt thereof. At least 1 type of chelating agent. Since the above-mentioned chelating agent is water-soluble, it is not necessary to use an alkaline solution such as NH4OH or NaOH. Since it is advantageous to obtain the aforementioned acidic etchant and the selection of the resist layer is easier, the cost of the chemical solution can also be reduced. The etchant for the dielectric film used in the second method contains an acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid, and acetic acid, and hydrogen peroxide, usually an aqueous solution. Since the aforementioned acid is also used in the manufacture of a conventional wiring board, it is easier to handle than hydrofluoric acid. The concentration of at least one acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid, and acetic acid can be easily performed by using an aqueous solution containing the foregoing acid and hydrogen peroxide. It should be 1 to 30% by weight. The higher the concentration, the higher the uranium engraving rate may be. However, the treatment of the liquid is more difficult. Therefore, the concentration should be limited to 30% by weight. Further, in order to obtain the minimum allowable etching rate in use, it should be 1 wt% or more. It is preferably 5 to 30 wt%, not (48) 1251536, but it is excellent in handleability and an appropriate etching rate can be obtained. Moreover, the treatment of the chemical liquid is also relatively easy, and an excellent etching rate can be obtained.

第1及第2方法，只要在至少形成於基板表面之特定位置上之當做電容器電極使用之金屬層上形成飩刻抗_層即可。蝕刻抗蝕層可使用市販之感光性乾薄膜及鹼性顯像型抗蝕墨水等，然而，以感光性乾薄膜爲佳。感光性乾薄膜係最常被應用於於印刷配線板製造處理之抗蝕材料。不但可以低成本形成抗蝕層，作業性亦極佳。使用之蝕刻抗蝕層並無特別限制，例如，FX140 ( DUPONT MRC DRYFILM LTD. Μ、商品名稱）、ΝΙΤ240 ( NICHIGO-MORTON CO·，LTD.製、商品名稱）、以及H-9040 (日立化成工業株式會社製、商品名稱）等。又，市販之鹼性顯像型抗蝕墨水如 PER-20(TAIYO INK MFG. CO.，LTD.製、商品名稱）等。在基板表面之當做電容器電極之金屬層上、及介電質薄膜上形成蝕刻抗蝕層，燒上電路圖案並進行顯像。又，顯像上，可使用碳酸鈉水溶液，蝕刻抗蝕層之剝離則使用氫氧化鈉水溶液，環境負擔較小係其特徵。又，亦可以網板印染等利用墨水狀蝕刻抗蝕劑只在當做電容器電極使用之金屬層上形成蝕刻抗蝕層。使用感光性乾薄膜時，其膜厚應爲當做電容器電極使用之金屬層之厚度的1〜3倍。其厚度小於其保護之金屬層之厚度時，金屬層及被蝕刻層表面之段差的充塡性會較差而出現空隙，容易導致蝕刻不良。又，若超過3倍，則飩刻性會降低而難以實現圖案之微細化。最好爲金屬層之 -53- 1251536 (49) 2〜3倍。2〜3倍時，對段差會有良好追隨性，且可具有良好之鈾刻性。第1及第2方法係在20〜45 °C執行介電質薄膜之蝕刻之內設:電谷器之多層配線板之製造方法◦低於2 0 °C時 ’倉虫刻率會顯著降低故蝕刻上需要較多時間而不符經濟效益。又’超過4 5 °C時，抗蝕層之密合性會降低而易導致倉虫刻不良。因此，蝕刻溫度應爲2 0〜4 5 °C。最好爲2 0〜 3 0 °C ’不但可兼具良好之蝕刻率及抗蝕層之密合性，且可改善作業性及廢料率。介電質薄膜及第i電容器電極之間，應配設當做前述之氧化保護覆膜或自氧化覆膜使用之金屬層。可以使用和內設電容器之多層配線板用材料所使用者相同之物。 (第2電容器電極之形成）以保留任意部份對前述之內設電容器之多層配線板用材*料或內設電容器之多層配線板用基板所含有之金屬箔或金屬層進行蝕刻，可得到電容器電極（第2電容器電極） °蝕刻係採用眾所皆知之方法。第2電容器電極之形成上，可以和第1電容器電極同胃形成、亦可以在形成第1電容器電極之後再形成。尤其是’若第2電容器電極和第1電容器電極同時形成，不但可簡化製造處理步驟、減少製造日數，尙具有經濟效益。 &時’形成電容器介電質並在其上形成當做第1電容器電使用之金屬層後，同時實施第1及第2電容器電極之蝕 -54- (50) 1251536 刻。第2電容器電極和多層配線板之接地層或電源層爲共用時，應將第2電容器電極尙做接地層或電源層之層應用。一般而言，接地層或電源層之圖案面積會大於配線圖案。本發明中製作之電容器電極之面積方面，形成介電質薄膜時實施覆蓋於基板表面之金屬層之圖案化所形成之第2 電容器電極之面積，會大於形成於介電質薄膜上之第1電容器電極之面積，故第2電容器電極適合當做接地層或電源層來使用。 (第2電容器電極、及具有導體電路之基板之導體之連結）本發明之一實施形態之利用內設電容器之多層配線板用材料製造電容器內層多層配線板時，亦利用絶緣層將具有導體電路之基板積層於內設電容器之多層層配線板用材料之銅箔面上。此種電容器內層多層配線板時，第2電容器電極及導體電路之連結上，可以利用除去絶緣層再以電解電鍍進行連結（第1方法），亦可以利用預先將導電性糊充塡至貫穿孔之絶緣層來進行連結（第2方法）。第1方法係在形成第1及第2電容器電極及電容器介電質後，亦可含有：利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟；用以在該基板表面形成0. 1〜5 // m之金屬層之步驟·；用以在含有孔之任意部位以外之部位上形成電鍍抗蝕層之步驟；在形成電鍍抗蝕層之部位以外之基板表面形成1 〇〜5 0 // m之金屬層，用 -55- (51) 1251536 以電性連結層間之電路圖案之步驟；蝕刻除去形成於基板表面之〇·1〜5//m之金屬層之步驟；以及以保留至少含有電容器介電質及導體化之孔任意部份之方式實施触刻除去之步驟。金屬層及電鍍抗蝕層等可使用和第1電容器電極所使用者相同之物。第2方法亦可具有：利用鑽床或雷射在當做絶緣層使用之半固化片等絶緣材料上形成貫穿孔之步驟、及利用網板印染等將利用化學反應實施金屬化導電性糊充塡至貫穿孔之步驟。導電性糊可使用和前述之內設電容器之多層配列用基板所使用之導電性糊相同之物。本發明之一實施形態之利用內設電容器之多層配線板用基板製造內設電容器之多層配線板時，因爲基板內部具有用以連結導體層間之通孔，故無需特別實施導通。本發明之一實施形態之利用內設電容器之多層配線板用材料製造電容器內層多層配線板時，可利用絶緣層將金屬箔B積層於內設電容器之多層層配線板用材料之銅箔面上。此種電容器內層多層配線板時，亦可在除去絶緣層及金屬箔B並形成孔後，再在孔內形成金屬層來進行連結（第1方法），亦可以利用預先將導電性糊充塡至貫穿孔之絶緣層來進行連結（第2方法）。第1方法時，絶緣層之除去可利用雷射，金屬箔B之除去可利用雷射或鈾刻。利用雷射同時除去金屬箔；B及絶緣層並形成孔時，不但可簡化製造處理步驟、減少製造日數’尙具有經濟效益。可採用此種製造方法之金屬箔B時 -56 - (52) 1251536 ，應實施以容易吸收雷射光之能量爲目的之處理。銅箔時 ’此種處理以氧化銅處理、微蝕刻處理、以及粗化電鍍處理等表面粗化處理較爲有效，其表面粗糙度應爲0. 1〜3 β m。低於〇 . 1 // m時，因無法充分吸收雷射光而使加工性變差，超過3 // m時，則加工精度會較差。又，銅箔之厚度應爲1〜1 8 // m。低於1 // m之銅箔的處理性會較差 ’超過1 8 // m之銅箔的加工性會較差。又，除了銅表面之粗化處理以外，尙可在表面配設鎳等易吸收雷射光之金屬層。形成此種金屬層或基板表面之金屬層之方法，例如 ’濺鍍法、無電電鍍法、以及電解電鍍法及前述方法之組合之方法。其次，可利用在形成之孔形成金屬層，使金屬箔B及金屬箔A (電容器電極）形成電性連結。此電性連結可利用例如電解電鍍或導電性糊來實施。第1方法含有：在含孔內在內之基板兩面形成0.1〜5// m之金屬層之步驟；以保留含有孔部之任意部份之方式在基板表面上形成金屬電鍍抗蝕層之步驟；利用金屬電鍍在含有孔部之部份形成導體圖案之步驟；用以除去不必要之金屬電鍍抗蝕層之步驟 ;以及用以除去形成於不必要部份之0 . 1〜5 // m之金屬層之步驟。金屬層及電鍍抗蝕層等可使用和第1電容器電極所使用者相同之物。又’在內設電容器之多層配線板用材料之介電質薄膜上形成金屬層2之前，若在含有孔之基板表面之兩面形成金屬層，則應同時形成孔內之金屬層、及當做第1電容器 -57- (53) 1251536 電極使用之金屬層。金屬層之形成上，亦可具有：在含有孔內在內之基板兩面形成0 · 1〜5 μ m之金屬層之步驟；以保留含有孔部之任意邰份之方式在基板表面形成金屬電鍍抗蝕層之步驟；利用金屬電鍍在含有孔部之部份形成導體圖案之步驟；用以除去金屬電鍍抗蝕層之步驟；以及鈾刻除去露出於基板表面之0.1〜5//m之金屬層之步驟。又，金屬箔B及金屬箔A (電容器電極）之電性連結亦可利用前面說明之導電性糊實施。第2方法亦可具有：以鑽床或雷射在當做絶緣層使用之半固化片等絶緣材料上形成貫穿孔之步驟；及利用網板印染等，將利用化學反應實施金屬化之導電性糊充塡至貫穿孔之步驟。導電性糊係和前述內設電容器之多層配列用基板所使用之導電性糊相同。本發明在必要時，可在基板之兩面或單面進一步利用絶緣層形成1層以上之電路層，而得到3層以上之內設電容器之多層配線板。本發明之一實施形態之內設電容器之多層配線板，形成第1電容器電極之導體層圖案可形成全部電容器之電極，介電質薄膜之投影面包含第！電容器電極之投影面，形成第2電容器電極之導體層上，具有第2電容器電極、及與該電極爲電性絶緣之至少1個圖案。本發明之一實施形態之利用這些製造方法製作之內設電容器之多層配線板時，形成第1電容器電極之金屬層圖案之下部，存在著用以形成第2電容器電極之金屬圖案。 -58- (54) 1251536 因此，若在用以形成第1電容器電極之金屬層上形成配線圖案，則用以形成第2電容器電極之金屬層間會產生寄生電容，而會有電性信號傳送特性變差之問題，故最好避免。因此，配線圖案應設置於第2電容器電極之金屬層。又，本發明之一實施形態之利用這些製造方法製作之內設電容器之多層配線板時，亦可1 )具有位於形成電容器之介電質之介電質薄膜投影面之內之第1電容器電極， 2)介電質薄膜端部之用以形成全部第1電容器電極之導體層電性連結於第2電容器電極。如此，可成爲不但可簡化製造處理步驟、減少製造日數，尙可具有良好經濟效益之內設電容器之多層配線板。本發明之一實施形態之利用這些製造方法製作之內設電容器之多層配線板時，亦可載置半導體晶片。因爲電容器係內設於基板上，不但可減少載置構件，尙可提供小型之半導體裝置。內設電容器之多層配線板之製造方法具體說明如下。以下之製造方法係利用金屬箔表面配設著電容率爲 10〜2000且膜厚爲0.05〜2// m之介電質薄膜之內設電容器之多層配線板用材料之內設電容器之多層配線板之製造方法具體實例。 (a-1 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2)在介電質薄膜表面形成1〇〜5〇//m之金屬層之步驟；3 )以保留該金屬層之任意部份之方式進行蝕 -59- (55) 1251536 刻除去，形成期望之第1電容器電極之步驟；4 )以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及5 )以保留除去介電質薄膜而露出之金屬箔之至少含有電容器介電質之任意部份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (a-2 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2)用以在介電質薄膜表面形成〇.1〜5//m之金屬層之步驟；3 )以保留含有第1電容器電極之任意部份之方式形成金屬電鍍抗蝕層之步驟；4 )利用金屬電鍍形成10〜50//m之第1電容器電極之步驟；5)用以除去金屬電鍍抗蝕層之步驟；6 )蝕刻除去形成於介電質薄膜表面之0.1〜5// m之金屬層之步驟；7)以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行鈾刻除去，形成期望之電容器介電質之步驟；以及8 )以保留除去介電質薄膜而露出之至少含有電容器介電質之任意部份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖条之步驟。 (a- 3 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2 )在介電質薄膜表面之任意部份，以利用化學反應實施金屬化之導電性糊形成1 〇〜5 0 // m之金屬層來形成期望之第1電容器電極之步驟；3 )以保留至少含 -60- (56) 1251536 有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及4 )以保留除去介電質薄膜而露出之至少含有電容器介電質之任意部份之方式進行飩刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (a-4 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2 )以保留介電質溥膜之任思部份之方式進丫了蝕刻除去，形成期望之電容器介電質之步驟；3 )在形成電容器介電質之基板表面上形成10〜50// m之金屬層之步驟；以及4)以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極、第2電容器電極、及電容器電極爲電性絶緣之任意導體圖案之步驟。 (a- 5 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2)在介電質薄膜表面形成1〇〜50//m之金屬層之步驟；3 )以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極之步驟；4 )以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；5 )用以蝕刻除去因除去介電質薄膜而露出之任意部位，而使硬化之半固化片之絶緣層露出之步驟；6 )利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟 ;7)在其基板表面形成0.1〜5// m之金屬層之步驟；8) -61 - (57) 1251536 用以在含有孔之任意部位以外之部位上形成電鍍抗蝕層之步驟；9 )在形成電鍍抗蝕層之部位以外之基板表面形成 1 〇〜5 0 // m之金屬層，用以電性連結層間之電路圖案之步驟；1 〇 )用以對形成於基板表面上之〇 . 1〜5 // m之金屬層實施蝕刻除去之步驟；以及1 1 )以至少保留含有電容器介電質、及導體化之孔在內之任意部份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (a- 6 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2)用以在介電質薄膜表面形成0.1〜5//m之金屬層之步驟；3)以保留含有第1電容器電極之任意部份之方式形成金屬電鍍抗蝕層之步驟；4 )利用金屬電鍍形成10〜50//m之第1電容器電極之步驟；5)用以除去金屬電鍍抗蝕層之步驟；6 )用以蝕刻除去形成於介電質薄膜表面之0.1〜5//m之金屬層之步驟；7)以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；8 )用以蝕刻除去因除去介電質薄膜而露出之任意部位，而使硬化之半固化片之絶緣層露出之步驟；9 )利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟；1 0 )在其基板表面形成0.1〜5//m之金屬層之步驟；11)用以在含有孔之任意部位以外之部位上形成電鑛抗蝕層之步驟；1 2 )在形成電鍍抗蝕層之部位以外之基板表面形成 1 0〜5 0 m之金屬層，用以電性連結層間之電路圖案之步 -62- 1251536 (58) 驟；1 3 )用以對形成於基板表面上之Ο . 1〜5 // m之金屬層實施蝕刻除去之步驟；以及1 4 )以至少保留含有電容器介電質、及導體化之孔在內之任意部份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (a- 7 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基板之步驟；2 )在介電質薄膜表面之任意部份以利用化學反應實施金屬化之導電性糊形成1 0〜5 0 // m之金屬層來形成期望之第1電容器電極之步驟；3)以保留至少含有介電質薄膜之第i電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；4 )用以蝕刻除去因除去介電質薄膜而露出之任意部位，而使硬化之半固化片之絶緣層露出之步驟；5 )利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟；6 )在其基板表面形成0.1〜5//m之金屬層之步驟；7)在含有孔之任意部位以外之部份形成電鍍抗蝕層之步驟；8 )在形成電鍍抗蝕層之部位以外之基板表面形成1 0〜5 0 // m 之金屬層，用以電性連結層間之電路圖案之步驟；9 )蝕刻除去形成於基板表面上之0.1〜5 // m之金屬層之步驟；以及1 〇 )以至少保留含有電容器介電質、及導體化之孔在內之任意部份之方式進行蝕刻除去，形成含有期望之第 2電容器電極之導體圖案之步驟。 (a- 8 )具有：1 )用以在內設電容器之多層配線板用材料之金屬箔面上，利用半固化片積層具有導體電路之基 -63- (59) 1251536 板之步驟；2 )以保留介電質薄膜任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3 )用以蝕刻除去因除去介電質薄膜而露出之任意部位，而使硬化之半固化片之絶緣層露出之步驟；4 )利用雷射照射除去露出之絶緣層來形成孔，而露出內層之導體電路之步驟；5 ) 在形成電容器介電質之基板表面、及孔內之表面形成10 〜50//m之金屬層之步驟；以及6)以至少保留含有電容器介電質、及導體化之孔在內之任意部份之方式進行鈾刻除去’形成含有期望之第2電容器電極之導體圖案之步驟〇以下之製造方法，係將基板內部具有用以連結導體層間之通孔、且在具有平滑表面之金屬層之基板表面上配設著電容率爲1〇〜2000且形成膜厚爲0.05〜2//m之介電質薄膜之內設電容器之多層配線板用基板當做內層板使用之內設電容器之多層配線板之製造方法之具體實例。 (b-Ι)具有：1)在介電質薄膜表面形成1〇〜5〇/im 之金屬層之步驟；（2 )以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極之步驟；3 )以保留介電質薄膜之至少含有第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟以及4 )以保留至少含有除去介電質薄膜所露出之金屬層之電容器介電質之任意部份之方式進行鈾刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (b-2)具有：1)在介電質薄膜表面形成Q.1〜5//m - 64 - 1251536 (60) 之金屬層之步驟；2)以保留含有第1電容器電極之任意部份之方式形成金屬電鍍抗蝕層之步驟；3 )利用金屬電鑛形成1 0〜5 0 /i m之第1電容器電極之步驟；4 )用以除去金屬電鍍抗鈾層之步驟；5 )用以蝕刻除去形成於介電負薄膜表面之〇·1〜5//m之金屬層之步驟；6)以保留至少含有介電質薄膜之第i電容器電極之任意部份之方式進行飽刻除去’形成期望之電容器介電質之步驟；以及7 ) 以保留至少含有除去介電質薄膜所露出之金屬層之電容器力電&之任意邰份之方式進行蝕刻除去，形成含有期望之第2電容器電極之導體圖案之步驟。 (b-3 )具有：1 )在介電質薄膜表面之任意部份以利用化學反應實施金屬化之導電性糊形成〗〇〜5 〇 # m之金屬層來形成期望之第1電容器電極之步驟；2)以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及3 ) 以保留至少含有除去介電質薄膜所露出之金屬層之電容器介電質之任意部份之方式進行蝕刻除去，形成含有期望之弟2電谷窃電極之導體圖案之步驟；之內設電容器之多層配線板之製造方法。 (b-4 )具有：i )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；2 ) 在形成電容器介電質之基板表面上形成10〜50// m之金屬層之步驟；以及3 )以保留該金屬層之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極、第2電容器 -65- Ϊ251536 (61) 電極、及電容器電極爲電性絶緣之任意導體圖案之步驟。以下之製造方法係採用將金屬箔單面配設著電容率爲 10〜2000且膜厚爲〇.〇5〜2m之介電質薄膜之內設電容器之多層配線板用材料以金屬箔接觸絶緣材料之方式配設於絶緣材料之至少單面上之基板內設電容器之多層配線板之製造方法之具體實例。 (c- 1 )具有：1 )用以在基板表面之介電質薄膜上之特定位置上形成當做電容器電極使用之金屬層之步驟；2 )至少在基板表面之前述金屬層上形成鈾刻抗鈾層之步驟 ;3 )利用含有鉗合劑及過氧化氫之蝕刻劑，實施介電質薄膜之濕蝕刻之步驟；以及4 )在濕蝕刻後除去蝕刻抗蝕層之步驟。 (c-2)具有：1)用以在基板表面之介電質薄膜上之特定位置上形成當做電容器電極使用之金屬層之步驟；2 )至少在基板表面之前述金屬層上形成蝕刻抗蝕層之步驟 ;3 )利用含有從硫酸、鹽酸、磷酸、硝酸、及醋酸所構成之群組所選取之至少1種酸、以及過氧化氫之蝕刻劑，實施介電質薄膜之濕蝕刻之步驟；以及4 )在濕蝕刻後除去蝕刻抗蝕層之步驟。以下之製造方法係採用金屬箔A單面配設著電容率爲1〇〜2000且膜厚爲0.05〜2/i m之介電質薄膜之內設電容器之多層配線板用材料之具體實例。 (d_ 1 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A靣利用絶緣材料實施金屬箔B之積層來形成 -66- 1251536 (62) 基板之步驟；2 )實施金屬箱B之任意部位之鈾刻除去，使上述絶緣材料形成之絶緣層露出之步驟；3 )利用雷射照射除去露出之絶緣層來形成孔而使金屬箔A露出之步驟，4)在含孔內在內之基板表面之兩面形成金屬層之步驟；5 )對內設電容器之多層配線板用材料之介電質薄膜上之金屬層以蝕刻形成任意形狀之第1電容器電極圖案之步驟；6 )對露出之介電質薄膜以蝕刻形成含有第1電容器電極圖案之任意形狀之電容器介電質之步驟；7 )對除去介電質薄膜而露出之金屬箔A以蝕刻形成含有電容器介電質圖案之任意形狀之第2電容器電極之步驟。 (d-2 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )對金屬箱B之任意部位實施雷射照射，同時除去金屬箔B、及上述絶緣材料所形成之絶緣層來形成孔，而使金屬箔A露出之步驟；3)在含孔內在內之基板表面之兩面形成金屬層之步驟；4)對內設電容器之多層配線板用材料之介電質薄膜上之金屬層以蝕刻形成任意形狀之第1電容器電極圖案之步驟；5)對露出之介電質薄膜以鈾刻形成含有第1電容器電極圖案之任意形狀之電容器介電質之步驟；以及6)對除去介電質薄膜而露出之金屬箔A以飩刻形成含有電容器介電質圖案之任意形狀之第2電容器電極之步驟。 (d-3 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以含有熱硬化 •67- (63) 1251536 性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )在基板表面之至少介電質薄膜側形成金屬層之步驟；3 )對內設電容器之多層配線板用材料之介電質薄膜上之金屬層以會虫刻形成任意形狀之第1電容器電極圖案之步驟；4 )對露出之介電質薄膜以蝕刻形成含有第1電容器電極圖案之任意形狀之電容器介電質之步驟；以及5)對除去介電質薄膜而露出之金屬箔A以蝕刻形成含有電容器介電質圖案之任意形狀之第2電容器電極之步驟。 (d-4 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )在基板表面之至少介電質薄膜側形成金屬層之步驟；3 )對內設電容器之多層配線板用材料之介電質薄膜上之金屬層以蝕刻形成任意形狀之第1電容器電極圖案之步驟；4)對露出之介電質薄膜以蝕刻形成含有第1電容器電極圖案之任意形狀之電容器介電質之步驟；以及5 )對除去介電質薄膜而錯出之金屬泊 A以触刻形成含有電谷益介電質圖案之任意形狀之第2電容器電極之步驟。 (d- 5 )具有：i )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )實施金屬箔B之任意部位之蝕刻除去，使上述絶緣材料形成之絶緣層露出之步驟；3 )利用雷射 -68- 1251536 (64) 照射除去露出之絶緣層來形成孔，而使金屬箔A露出之步驟；4 )在含有孔內在內之基板兩面形成〇 · 1〜5 // m之金屬層之步驟；5 )以保留當做第1電容器電極使用之部份、及含有孔部之任意部份之方式，在基板表面上形成金屬電鑛抗鈾層之步驟；6 )利用金屬電鍍在當做上述第^ 電容器電極使用之部份、及含有孔部之部份形成導體_ _ 之步驟；7 )用以除去金屬電鍍抗蝕層之步驟；8 )用以倉虫刻除去露出基板表面之〇·1〜5//m之金屬層之步驟；9彳對露出之介電質薄膜以鈾刻形成含有第1電容器電極圖_ 之任意形狀之電容器介電質之步驟；10)對除去介電質_ 膜而露出之金屬箔A以蝕刻形成含有電容器介電質圖案之任意形狀之第2電容器電極之步驟；以及；l丨）對露$ 之金屬箔B進行蝕刻而形成電路之步驟。 (d-6 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔b之積層來形成基板之步驟；2 )對金屬范B之任意部位實施雷射照射，同時除去金屬箔B、及上述絶緣材料所形成之絶緣層來形成孔，而使金屬箔A露出之步驟；3)在含有孔內在內之基板兩面形成〇·1〜5//m之金屬層之步驟；4)以保留當做第1電容器電極使用之部份、及含有孔部之任意部份之方式’在基板表面上形成金屬電鑛抗蝕層之步驟；5 )利用金屬電鍍在當做上述第1電容器電極使用之部份、及含有孔邰之部份形成導體圖案之步驟；6 )用以除去金屬電鍍抗鈾層之步驟；7 )蝕刻除去從基板表面露出之〇 . i〜5 -69- (65) 1251536 M m之金屬層之步驟；8 )對露出之介電質薄膜以蝕刻形成含有第1電容器電極圖案之任意形狀之電容器介電質之步驟；9 )對除去介電質薄膜而露出之金屬箔A形成含有電容器介電質圖案之任意形狀之第2電容器電極之步驟；以及1 〇 )對露出之金屬箔B實施蝕刻而形成電路之步驟In the first and second methods, the etching resist layer may be formed on the metal layer used as the capacitor electrode at at least a specific position formed on the surface of the substrate. As the etching resist layer, a commercially available photosensitive dry film, an alkali developing type resist ink or the like can be used. However, a photosensitive dry film is preferred. Photosensitive dry film is most commonly used as a resist material for printed wiring board manufacturing processes. Not only can the resist layer be formed at low cost, but also workability is excellent. The etching resist layer to be used is not particularly limited, and, for example, FX140 (DUPONT MRC DRYFILM LTD. Μ, trade name), ΝΙΤ240 (manufactured by NICHIGO-MORTON CO., LTD., trade name), and H-9040 (Hitachi Chemical Industry Co., Ltd.) Co., Ltd., product name), etc. Further, the alkaline-type resist ink of the market is PER-20 (manufactured by TAIYO INK MFG. CO., LTD., trade name). An etching resist is formed on the metal layer of the surface of the substrate as a capacitor electrode and on the dielectric film, and the circuit pattern is burned and developed. Further, in the development, an aqueous sodium carbonate solution can be used, and the etching of the etching resist layer is carried out using an aqueous sodium hydroxide solution, and the environmental burden is small. Further, it is also possible to form an etching resist layer on the metal layer used as the electrode of the capacitor by using an ink-like etching resist such as screen printing. When a photosensitive dry film is used, the film thickness should be 1 to 3 times the thickness of the metal layer used as the capacitor electrode. When the thickness is smaller than the thickness of the metal layer to be protected, the gap between the metal layer and the surface of the layer to be etched is poor, and voids are formed, which may cause etching failure. Moreover, when it exceeds three times, the engraving property will fall and it will become difficult to refine a pattern. Preferably, the metal layer is -53-1215536 (49) 2 to 3 times. When it is 2 to 3 times, it will have good followability to the step and can have good uranium engraving. The first and second methods are performed in the etching of the dielectric film at 20 to 45 ° C. The manufacturing method of the multilayer wiring board of the electric grid is less than 20 ° C. Therefore, it takes more time to etch and it is not economical. Further, when the temperature exceeds 45 ° C, the adhesion of the resist layer is lowered to cause a bad burn. Therefore, the etching temperature should be 20 to 4 5 °C. It is preferable that it has a good etching rate and adhesion of the resist layer, and the workability and the scrap rate can be improved. A metal layer used as the above-described oxidized protective film or self-oxidizing film should be disposed between the dielectric film and the i-th capacitor electrode. It is possible to use the same material as that of the material for the multilayer wiring board in which the capacitor is built. (Formation of the second capacitor electrode) The capacitor is obtained by etching a metal foil or a metal layer contained in the multilayer wiring board material or the multilayer wiring board substrate in which the capacitor is built in any part. The electrode (second capacitor electrode) ° etching is a well-known method. The second capacitor electrode may be formed in the same stomach as the first capacitor electrode or may be formed after the first capacitor electrode is formed. In particular, when the second capacitor electrode and the first capacitor electrode are simultaneously formed, the manufacturing process step can be simplified and the number of manufacturing days can be reduced, which is economical. When the capacitor dielectric is formed and the metal layer used as the first capacitor is formed thereon, the first and second capacitor electrodes are simultaneously etched -54-(50) 1251536. When the grounding layer or the power supply layer of the second capacitor electrode and the multilayer wiring board are used in common, the second capacitor electrode should be applied as a layer of a ground layer or a power supply layer. In general, the pattern area of the ground plane or power plane will be larger than the wiring pattern. In the area of the capacitor electrode produced in the present invention, the area of the second capacitor electrode formed by patterning the metal layer covering the surface of the substrate when forming the dielectric film is larger than the first layer formed on the dielectric film. Since the area of the capacitor electrode is such that the second capacitor electrode is suitable for use as a ground layer or a power supply layer. (Coupling of the second capacitor electrode and the conductor of the substrate having the conductor circuit) When the capacitor inner layer multilayer wiring board is manufactured using the material for the multilayer wiring board in which the capacitor is provided in the embodiment of the present invention, the insulating layer is also used to have the conductor The substrate of the circuit is laminated on the copper foil surface of the material for the multilayer wiring board in which the capacitor is provided. In the case of such a multilayer wiring board having a capacitor inner layer, the connection between the second capacitor electrode and the conductor circuit can be connected by electrolytic plating by removing the insulating layer (first method), or the conductive paste can be filled in advance. The insulating layer of the hole is connected (the second method). In the first method, after forming the first and second capacitor electrodes and the capacitor dielectric, the step of removing the exposed insulating layer by laser irradiation to form a hole to expose the conductor circuit of the inner layer may be included; a step of forming a metal layer of 0.1 to 5 // m on the surface of the substrate; a step of forming a plating resist layer on a portion other than the portion containing the hole; and a substrate other than a portion where the plating resist layer is formed Forming a metal layer of 1 〇~5 0 // m on the surface, and electrically connecting the circuit patterns between the layers with -55-(51) 1251536; etching and removing the metal formed on the surface of the substrate by 1~5//m a step of layering; and performing a step of removing the etch by retaining at least any portion of the capacitor dielectric and the via of the conductor. The metal layer, the plating resist, or the like can be used in the same manner as the user of the first capacitor electrode. The second method may further include a step of forming a through hole by using a drill press or a laser on an insulating material such as a prepreg used as an insulating layer, and filling a through-hole with a metallized conductive paste by a chemical reaction using a screen printing or the like. The steps. As the conductive paste, the same thing as the conductive paste used for the multilayer arrangement substrate of the capacitor described above can be used. In the multilayer wiring board in which the capacitor is mounted on the substrate for the multilayer wiring board in which the capacitor is provided in the embodiment of the present invention, since the substrate has a through hole for connecting the conductor layers, it is not necessary to perform conduction. When a capacitor inner layer multilayer wiring board is manufactured using a material for a multilayer wiring board in which a capacitor is built in the embodiment of the present invention, the metal foil B can be laminated on the copper foil surface of the multilayer wiring board material in which the capacitor is provided by the insulating layer. on. In the case of such a multilayer wiring board having a capacitor inner layer, after the insulating layer and the metal foil B are removed and a hole is formed, a metal layer may be formed in the hole to be connected (first method), and the conductive paste may be charged in advance. The insulating layer is connected to the through hole to be connected (the second method). In the first method, the removal of the insulating layer can be performed by laser, and the removal of the metal foil B can be performed by laser or uranium engraving. When the metal foil is removed simultaneously by the laser; B and the insulating layer are formed into holes, not only the manufacturing process step can be simplified, but also the number of manufacturing days can be reduced. When the metal foil B of such a manufacturing method can be used, -56 - (52) 1251536, a treatment for easily absorbing the energy of the laser light should be performed. 1〜3 β m。 The surface roughness of the surface roughness of 0. 1~3 β m. When it is lower than 〇 1 1 m, the processing property is deteriorated because the laser light cannot be sufficiently absorbed. If it exceeds 3 // m, the machining accuracy will be poor. Also, the thickness of the copper foil should be 1 to 18 // m. Copper foils of less than 1 // m will be less handleable. 'The processing of copper foils exceeding 1 8 // m will be poor. Further, in addition to the roughening treatment of the copper surface, a metal layer such as nickel which is apt to absorb laser light can be disposed on the surface. A method of forming such a metal layer or a metal layer on the surface of the substrate, for example, a sputtering method, an electroless plating method, and an electrolytic plating method and a combination of the foregoing methods. Next, a metal layer can be formed in the formed hole to electrically connect the metal foil B and the metal foil A (capacitor electrode). This electrical connection can be carried out, for example, by electrolytic plating or conductive paste. The first method comprises the steps of: forming a metal layer of 0.1 to 5 / / m on both sides of the substrate including the hole; and forming a metal plating resist on the surface of the substrate in such a manner as to retain any portion of the hole; a step of forming a conductor pattern in a portion containing a hole portion by metal plating; a step of removing an unnecessary metal plating resist layer; and removing a portion formed in an unnecessary portion of 0.1 to 5 // m The step of the metal layer. The metal layer, the plating resist, or the like can be used in the same manner as the user of the first capacitor electrode. Further, before the metal layer 2 is formed on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed, if a metal layer is formed on both surfaces of the substrate surface including the hole, the metal layer in the hole should be simultaneously formed, and 1 capacitor -57- (53) 1251536 The metal layer used for the electrode. The metal layer may also have a step of forming a metal layer of 0·1~5 μm on both sides of the substrate including the hole; forming a metal plating resist on the surface of the substrate by retaining any portion containing the hole portion a step of etching a layer; forming a conductor pattern in a portion containing the hole portion by metal plating; a step of removing the metal plating resist layer; and removing a metal layer of 0.1 to 5//m exposed on the surface of the substrate by uranium etching The steps. Further, the electrical connection between the metal foil B and the metal foil A (capacitor electrode) can also be carried out by using the conductive paste described above. The second method may further include a step of forming a through hole by using a drill press or a laser on an insulating material such as a prepreg used as an insulating layer; and filling the conductive paste metallized by a chemical reaction with a screen printing or the like to The step of the through hole. The conductive paste is the same as the conductive paste used for the multilayer arrangement substrate of the built-in capacitor. In the present invention, if necessary, a circuit layer of one or more layers can be formed by using an insulating layer on both sides or one side of the substrate, and a multilayer wiring board having three or more internal capacitors can be obtained. In the multilayer wiring board in which the capacitor is provided in the embodiment of the present invention, the conductor layer pattern of the first capacitor electrode can form an electrode of all the capacitors, and the projection surface of the dielectric film includes the first! The projection surface of the capacitor electrode has a second capacitor electrode and at least one pattern electrically insulated from the electrode layer formed on the second capacitor electrode. In the multilayer wiring board in which the capacitor is formed by the above-described manufacturing method according to the embodiment of the present invention, a metal pattern for forming the second capacitor electrode is formed under the metal layer pattern of the first capacitor electrode. -58- (54) 1251536 Therefore, if a wiring pattern is formed on the metal layer for forming the first capacitor electrode, parasitic capacitance is generated between the metal layers for forming the second capacitor electrode, and electrical signal transmission characteristics are generated. It is better to avoid the problem of deterioration. Therefore, the wiring pattern should be provided on the metal layer of the second capacitor electrode. Further, in the multilayer wiring board in which the capacitor is formed by the manufacturing method according to the embodiment of the present invention, the first capacitor electrode having the dielectric film projection surface of the dielectric material forming the capacitor may be used. 2) The conductor layer for forming all of the first capacitor electrodes at the end of the dielectric film is electrically connected to the second capacitor electrode. Thus, it is possible to provide a multilayer wiring board in which a capacitor can be provided not only by simplifying the manufacturing process steps, reducing the number of manufacturing days, but also having good economic efficiency. In the case of the multilayer wiring board in which the capacitor is fabricated by the above-described manufacturing method according to an embodiment of the present invention, the semiconductor wafer may be placed. Since the capacitor is provided on the substrate, not only the mounting member can be reduced, but also a small semiconductor device can be provided. A method of manufacturing a multilayer wiring board in which a capacitor is provided will be specifically described below. The following manufacturing method is a multilayer wiring in which a capacitor is provided in a material for a multilayer wiring board in which a capacitor having a dielectric constant of 10 to 2,000 and a film thickness of 0.05 to 2/m is disposed on the surface of the metal foil. Specific examples of the manufacturing method of the board. (a-1) has: 1) a step of laminating a substrate having a conductor circuit using a prepreg on a metal foil surface of a material for a multilayer wiring board having a built-in capacitor; 2) forming a layer on the surface of the dielectric film. a step of a metal layer of 5 Å/m; 3) a step of removing etch-59-(55) 1251536 by leaving any portion of the metal layer to form a desired first capacitor electrode; 4) a step of etching to remove any portion of the first capacitor electrode of the dielectric film to form a desired capacitor dielectric; and 5) containing at least a capacitor of the metal foil exposed to remove the dielectric film The step of etching to remove any portion of the dielectric material to form a conductor pattern containing the desired second capacitor electrode. (a-2) has: 1) a step of laminating a substrate having a conductor circuit with a prepreg for a metal foil surface of a material for a multilayer wiring board having a built-in capacitor; and 2) forming a crucible on the surface of the dielectric film. a step of a metal layer of .1 to 5//m; 3) a step of forming a metal plating resist layer in such a manner as to retain any portion of the electrode of the first capacitor; 4) forming a layer of 10 to 50/m by metal plating a step of the first capacitor electrode; 5) a step of removing the metal plating resist layer; 6) a step of etching away the metal layer formed on the surface of the dielectric film by 0.1 to 5 // m; 7) retaining at least a step of removing the uranium engraving to form a desired capacitor dielectric by any portion of the first capacitor electrode of the dielectric film; and 8) exposing at least the capacitor dielectric by leaving the dielectric film removed The step of etching is performed in any part to form a conductor strip containing the desired second capacitor electrode. (a-3) has: 1) a step of laminating a substrate having a conductor circuit using a prepreg on a metal foil surface of a material for a multilayer wiring board having a built-in capacitor; and 2) any portion on the surface of the dielectric film a step of forming a desired first capacitor electrode by forming a metal layer of a conductive paste by a chemical reaction to form a metal layer of 1 〇~5 0 // m; 3) retaining at least -60-(56) 1251536 a portion of the first capacitor electrode of the electroless thin film is etched and removed to form a desired capacitor dielectric; and 4) any portion of the capacitor dielectric exposed to remove the dielectric thin film In the form of a portion, the step of removing the conductor pattern containing the desired second capacitor electrode is carried out. (a-4) has: 1) a step of laminating a substrate having a conductor circuit using a prepreg on a metal foil surface of a material for a multilayer wiring board of a built-in capacitor; 2) thinking of retaining a dielectric film Part of the method is the step of etching to remove the desired capacitor dielectric; 3) the step of forming a metal layer of 10 to 50 / / m on the surface of the substrate on which the capacitor dielectric is formed; and 4) to retain The portion of the metal layer is etched and removed to form a desired first capacitor electrode, a second capacitor electrode, and a capacitor electrode that is electrically insulated from any conductor pattern. (a-5) has: 1) a step of laminating a substrate having a conductor circuit by using a prepreg on a metal foil surface of a material for a multilayer wiring board having a built-in capacitor; 2) forming a layer on the surface of the dielectric film. a step of a metal layer of 50/m; 3) a step of etching to remove any portion of the metal layer to form a desired first capacitor electrode; and 4) retaining a first portion containing at least a dielectric film a step of etching away any portion of the capacitor electrode to form a desired capacitor dielectric; 5) etching away any portion exposed by removing the dielectric film, and exposing the insulating layer of the cured prepreg Step; 6) a step of removing the exposed insulating layer by laser irradiation to form a hole to expose the conductor circuit of the inner layer; 7) a step of forming a metal layer of 0.1 to 5 // m on the surface of the substrate; 8) -61 - (57) 1251536 a step for forming an electroplated resist layer on a portion other than the portion containing the hole; 9) forming a metal of 1 〇 to 50 ε m on the surface of the substrate other than the portion where the electroplated resist layer is formed Layer, used for electricity a step of connecting circuit patterns between layers; 1) a step of etching removing a metal layer of 〜. 1 to 5 // m formed on a surface of the substrate; and 1 1) retaining at least a capacitor dielectric, The step of etching and removing any portion including the conductor hole to form a conductor pattern containing the desired second capacitor electrode. (a-6) has: 1) a step of laminating a substrate having a conductor circuit using a prepreg for a metal foil surface of a material for a multilayer wiring board having a built-in capacitor; 2) forming 0.1 on a surface of the dielectric film. a step of forming a metal layer of 〜5//m; 3) a step of forming a metal plating resist layer in such a manner as to retain any portion of the first capacitor electrode; 4) forming a first layer of 10 to 50/m by metal plating a step of a capacitor electrode; 5) a step of removing a metal plating resist; 6) a step of etching away a metal layer of 0.1 to 5//m formed on the surface of the dielectric film; 7) retaining at least a step of etching away any portion of the first capacitor electrode of the dielectric film to form a desired capacitor dielectric; and 8) etching and removing any portion exposed by removing the dielectric film to harden a step of exposing the insulating layer of the prepreg; 9) removing the exposed insulating layer by laser irradiation to form a hole to expose the conductor circuit of the inner layer; 10) forming a metal of 0.1 to 5//m on the surface of the substrate Step of the layer; 11) a step of forming an electric ore resist layer on a portion other than any portion of the hole; 1) forming a metal layer of 10 to 50 m on the surface of the substrate other than the portion where the plating resist layer is formed, for electrically connecting the interlayer The circuit pattern step-62- 1251536 (58) step; 1 3) the step of etching to remove the metal layer formed on the surface of the substrate: 1~5 // m; and 1 4) to retain at least The step of etching and removing any portion including the capacitor dielectric and the via hole to form a desired conductor pattern of the second capacitor electrode. (a-7) has: 1) a step of laminating a substrate having a conductor circuit with a prepreg for a metal foil surface of a material for a multilayer wiring board having a built-in capacitor; 2) any portion of the surface of the dielectric film a step of forming a desired first capacitor electrode by forming a metal layer of a conductive paste by a chemical reaction to form a metal layer of 10 to 50 // m; and 3) retaining an ith capacitor electrode containing at least a dielectric film a step of etching away any part of the capacitor to form a desired capacitor dielectric; 4) a step of etching away any portion exposed by removing the dielectric film to expose the insulating layer of the cured prepreg; a step of removing the exposed insulating layer by laser irradiation to form a hole to expose the conductor circuit of the inner layer; 6) a step of forming a metal layer of 0.1 to 5//m on the surface of the substrate; 7) arbitrarily containing a hole a step of forming a plating resist layer other than the portion; 8) forming a metal layer of 10 to 50 // m on the surface of the substrate other than the portion where the plating resist layer is formed, for electrically connecting the circuit patterns between the layers step 9) a step of etching away a metal layer of 0.1 to 5 // m formed on the surface of the substrate; and 1 〇) by retaining at least any portion including the dielectric of the capacitor and the hole of the conductor The etching is removed to form a conductor pattern containing the desired second capacitor electrode. (a-8) has: 1) a metal foil surface of a material for a multilayer wiring board having a built-in capacitor, a step of laminating a substrate having a conductor circuit with a prepreg-63-(59) 1251536 board; 2) to retain a step of etching away any portion of the dielectric film to form a desired capacitor dielectric; 3) etching away any portion exposed by removing the dielectric film, thereby exposing the insulating layer of the cured prepreg a step of: 4) removing the exposed insulating layer by laser irradiation to form a hole to expose the inner conductor circuit; 5) forming a surface of the substrate on which the capacitor dielectric is formed, and a surface in the hole to form 10 to 50/ a step of a metal layer of /m; and 6) performing uranium engraving in such a manner as to retain at least any portion including the capacitor dielectric and the via of the conductor to form a conductor pattern containing the desired second capacitor electrode Step 〇 The following manufacturing method has a capacitance ratio of 1 〇 to 2000 in a substrate having a through hole between the conductor layers and a metal layer having a smooth surface. Thickness of multilayer wiring board equipped with a capacitor dielectric film of 0.05~2 // m as a specific example of the method for manufacturing a multilayer wiring board using the features of the inner plate of the capacitor with the substrate. (b-Ι) has: 1) a step of forming a metal layer of 1 〇 5 〇 / im on the surface of the dielectric film; (2) etching and removing by leaving any part of the metal layer to form a desired a step of the first capacitor electrode; 3) a step of removing the dielectric film by at least containing any portion of the first capacitor electrode to form a desired capacitor dielectric; and 4) retaining at least the removal medium The step of removing the conductor pattern containing the desired second capacitor electrode by performing uranium engraving on the portion of the capacitor dielectric of the metal layer exposed by the electroless thin film. (b-2) has: 1) a step of forming a metal layer of Q.1~5//m - 64 - 1251536 (60) on the surface of the dielectric film; 2) retaining any part of the electrode containing the first capacitor a step of forming a metal plating resist layer; 3) a step of forming a first capacitor electrode of 10 to 50 μm using metal oxide; 4) a step of removing a metal plating uranium layer; 5) Etching removes the metal layer formed on the surface of the dielectric negative film by 〇1 to 5//m; 6) satisfactorily removing the portion of the ith capacitor electrode containing at least the dielectric film. a step of forming a desired capacitor dielectric; and 7) etching and removing by removing any of the capacitors of the metal layer exposed by removing the dielectric film to form a desired second capacitor The step of the conductor pattern of the electrode. (b-3) has: 1) forming a desired first capacitor electrode by forming a metal layer of a conductive paste formed by chemical reaction in any part of the surface of the dielectric film to form a desired first capacitor electrode Step; 2) performing etching removal to retain a desired capacitor dielectric by retaining any portion of the first capacitor electrode containing at least the dielectric film; and 3) retaining at least the dielectric-removing film A step of etching to remove a conductor pattern of a desired dielectric layer of the exposed metal layer to form a conductor pattern containing a desired electrode, and a method of manufacturing a multilayer wiring board having a capacitor therein. (b-4) has: i) a step of etching to remove any portion of the dielectric film to form a desired capacitor dielectric; 2) forming a 10~ on the surface of the substrate on which the capacitor dielectric is formed a step of 50/m metal layer; and 3) etching and removing any part of the metal layer to form a desired first capacitor electrode, second capacitor -65-Ϊ251536 (61) electrode, and capacitor The electrode is a step of electrically insulating any conductor pattern. The following manufacturing method uses a metal foil to be insulatively provided with a material for a multilayer wiring board in which a capacitor having a dielectric constant of 10 to 2000 and a film thickness of 〇. 5 to 2 m is provided on one side of the metal foil. A specific example of a method of manufacturing a multilayer wiring board in which a capacitor is disposed in a substrate on at least one side of an insulating material. (c-1) has: 1) a step of forming a metal layer used as a capacitor electrode at a specific position on a dielectric film on the surface of the substrate; 2) forming an uranium engraving resistance on at least the aforementioned metal layer on the surface of the substrate a step of uranium layer; 3) performing a wet etching step of the dielectric film using an etchant containing a chelating agent and hydrogen peroxide; and 4) removing the etching resist layer after the wet etching. (c-2) having: 1) a step of forming a metal layer used as a capacitor electrode at a specific position on a dielectric film on the surface of the substrate; 2) forming an etching resist on at least the aforementioned metal layer on the surface of the substrate a step of layering; 3) performing a wet etching step of the dielectric film by using an etchant containing at least one acid selected from the group consisting of sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid, and acetic acid, and an etchant of hydrogen peroxide And 4) the step of removing the etching resist after the wet etching. The following manufacturing method is a specific example of a material for a multilayer wiring board in which a capacitor having a dielectric constant of 1 〇 to 2000 and a film thickness of 0.05 to 2/i m is disposed on one side of the metal foil A. (d-1) has: 1) a metal foil A of a material for a multilayer wiring board having a built-in capacitor; a step of forming a metal foil B by an insulating material to form a -66-1215336 (62) substrate; 2) implementing a metal case The step of removing the uranium in any part of B to expose the insulating layer formed by the insulating material; 3) removing the exposed insulating layer by laser irradiation to form a hole to expose the metal foil A, and 4) in the hole containing a step of forming a metal layer on both sides of the surface of the substrate; 5) a step of etching a metal layer on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed to form a first capacitor electrode pattern of an arbitrary shape; 6) The exposed dielectric film is etched to form a capacitor dielectric having an arbitrary shape of the first capacitor electrode pattern; 7) the metal foil A exposed to remove the dielectric film is etched to form a capacitor dielectric pattern The step of the second capacitor electrode of any shape. (d-2) has the steps of: 1) forming a substrate by laminating a metal foil B with an insulating material on the surface of the metal foil A of the material for the multilayer wiring board in which the capacitor is provided; 2) performing lightning on any part of the metal case B a step of irradiating, simultaneously removing the metal foil B and the insulating layer formed by the insulating material to form a hole to expose the metal foil A; and 3) forming a metal layer on both sides of the surface of the substrate including the hole; a step of etching a metal layer on a dielectric film of a material for a multilayer wiring board in which a capacitor is formed to form a first capacitor electrode pattern of an arbitrary shape; and 5) forming a first dielectric layer of the exposed dielectric film with uranium engraving a step of forming a capacitor dielectric of an arbitrary shape of the capacitor electrode pattern; and 6) a step of forming a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern by etching the metal foil A exposed by removing the dielectric film. (d-3) has: 1) a through hole is provided in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and contains a thermosetting material 67-(63) 1251536 resin and metal coating material a conductive paste is filled in the through hole, and a step of forming a substrate by laminating the metal foil B with an insulating material; 2) a step of forming a metal layer on at least the dielectric film side of the substrate surface; 3) a capacitor is provided The metal layer on the dielectric film of the material for the multilayer wiring board is a step of forming a first capacitor electrode pattern of an arbitrary shape; 4) etching the exposed dielectric film to form a pattern containing the first capacitor electrode a step of forming a capacitor dielectric of an arbitrary shape; and 5) a step of etching the metal foil A exposed by removing the dielectric film to form a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern. (d-4) has: 1) a through hole is disposed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and the through hole is filled with a conductive paste which is metallized by a chemical reaction. a step of forming a substrate by laminating a metal foil B with an insulating material; 2) a step of forming a metal layer on at least a dielectric film side of the substrate surface; 3) a dielectric material for a material for a multilayer wiring board having a capacitor built therein a step of etching a metal layer on the film to form a first capacitor electrode pattern of an arbitrary shape; 4) a step of etching the exposed dielectric film to form a capacitor dielectric having an arbitrary shape of the first capacitor electrode pattern; and 5 A step of forming a second capacitor electrode having an arbitrary shape including an electric valley dielectric pattern by a metal poise A which is removed by removing the dielectric film. (d-5): (i) a step of forming a substrate by laminating a metal foil B with an insulating material on the surface of the metal foil A of the material for the multilayer wiring board in which the capacitor is provided; 2) performing etching of an arbitrary portion of the metal foil B Removing the step of exposing the insulating layer formed of the insulating material; 3) irradiating the exposed insulating layer with laser-68-1252936 (64) to form a hole to expose the metal foil A; 4) containing the hole a step of forming a metal layer of 〇·1 to 5 // m on both sides of the substrate; 5) forming on the surface of the substrate by retaining the portion used as the first capacitor electrode and containing any portion of the hole portion a step of resisting the uranium layer of the metal ore; 6) a step of forming a conductor __ by using metal plating as a part of the above-mentioned capacitor electrode and a portion containing the hole portion; 7) for removing the metal plating resist layer Step; 8) a step of removing the metal layer of 〇·1~5//m exposed on the surface of the substrate; 9彳 forming the first capacitor electrode with the uranium engraved on the exposed dielectric film Steps for capacitor dielectric of any shape 10) a step of etching the metal foil A exposed by removing the dielectric film to form a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern; and; 丨) etching the metal foil B of the exposed material The steps to form a circuit. (d-6) has the steps of: 1) forming a substrate by laminating a metal foil b with an insulating material on the surface of the metal foil A of the material for the multilayer wiring board in which the capacitor is provided; 2) performing lightning on any part of the metal body B Irradiation, simultaneous removal of the metal foil B, and the insulating layer formed by the insulating material to form a hole to expose the metal foil A; 3) forming a 〇·1~5//m on both sides of the substrate including the hole a step of forming a metal layer; 4) using a metal electroplating resist layer on the surface of the substrate in a manner of retaining the portion used as the first capacitor electrode and containing any portion of the hole portion; a step of forming a conductor pattern as a portion of the first capacitor electrode and a portion containing the aperture; 6) a step of removing the metal plating uranium layer; and 7) etching to remove the surface exposed from the substrate. 〜5 -69- (65) 1251536 M m metal layer step; 8) a step of etching the exposed dielectric film to form a capacitor dielectric having any shape of the first capacitor electrode pattern; 9) removing Dielectric film and exposed gold a step of forming a second capacitor electrode having an arbitrary shape of a capacitor dielectric pattern, and a step of forming an electric circuit by etching the exposed metal foil B

C (d-7 )具有：1 )在內設電容器之多層配線板用材料之金屬箔 A面之任意部位配設貫穿孔，且以含有熱硬化性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )在基板之至少介電質薄膜側之表面形成0.1〜5// m之金屬層之步驟；3 )以保留當做第1電容器電極使用之部份之任意部份之方式，在基板表面上形成金屬電鍍抗鈾層之步驟；4 )利用金屬電鍍在含有當做第1電容器電極使用之部份之部份形成導體圖案之步驟；5 )用以除去金屬電鍍抗蝕層之步驟；6 )鈾刻除去從基板表面露出之〇 . 1〜5 // m之金屬層之步驟；7 )對露出之介電質薄膜以蝕刻形成含有第 1電容器電極圖案之任意形狀之電容器介電質之步驟；以及8 )對除去介電質薄膜而露出之金屬箔A，以鈾刻形成含有電容器介電質圖案之任意形狀之第2電容器電極，對露出之金屬箔B實施蝕刻而形成電路之步驟。 (d-8 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔，並利用絶緣材料 -70- 1251536 (66) 實施金屬箔B之積層來形成基板之步驟；2)在基板之至少介電質薄膜側之表面形成0 . 1〜5 // m之金屬層之步驟； 3 )以保留當做第1電容器電極使用之部份之任意部份之方式，在基板表面上形成金屬電鍍抗鈾層之步驟；4 )利用金屬電鍍在含有當做第1電容器電極使用之部份之部份形成導體圖案之步驟；5 )用以除去金屬電鍍抗鈾層之步驟；6)用以触刻除去露出基板表面之〇.1〜5//m之金屬層之步驟；7 )對露出之介電質薄膜以蝕刻形成含有第1 電容器電極圖案之任意形狀之電容器介電質之步驟；以及 8 )對除去介電質薄膜而露出之金屬箔A，以蝕刻形成含有電容器介電質圖案之任意形狀之第2電容器電極，對露出之金屬箔B實施蝕刻而形成電路之步驟。 (d-9 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以含有熱硬化性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )在介電質薄膜之表面之任意部份，以利用化學反應實施金屬化之導電性糊形成金屬層來形成期望之第1電容器電極之步驟 ;3 )以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；以及4 )對除去介電質薄膜而露出之金屬箔A，以鈾刻形成含有電容器介電質圖案之任意形狀之第2電容器電極，對露出之金屬箔B實施蝕刻而形成電路之步驟。 (d- 1 0 )具有：1 )在內設電容器之多層配線板用材 -71 - (67) 1251536 料之金屬箔A面之任意部位配設貫穿孔，且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B積層來形成基板之步驟；2 )在介電質薄膜之表面之任意部份，以利用化學反應實施金屬化之導電性糊形成金屬層來形成期望之第1電容器電極之步驟；3 )以保留至少含有介電質薄膜之第1電容器電極之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟 ;以及4 )對除去介電質薄膜而露出之金屬箔A，以蝕刻形成含有電容器介電質圖案之任意形狀之第2電容器電極，對露出之金屬箔B實施蝕刻而形成電路之步驟。 (d -1 1 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面利用絶緣材料實施金屬箔B之積層而形成基板之步驟；2 )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3 )實施金屬箔B之任意部位之蝕刻除去，使上述絶緣材料形成之絶緣層露出之步驟；4 )利用雷射照射除去露出之絶緣層來形成孔，而使金屬箔A露出之步驟；5)在含孔內在內之基板表面之兩面形成金屬層之步驟；以及6)以保留該金屬層及金屬箔A之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極及第2電容器電極之步驟。 (d -1 2 )具有：1 )在內設電容器之多層配線板用材料之金屬箱A面利用絶緣材料實施金屬箔b之積層來形成基板之步驟；2 )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3 )對 -72- 1251536 (68) 金屬箔B之任意部位實施雷射照射，同時除去金屬箔B、及由上述絶緣材料所形成之絶緣層並形成孔，而使金屬箔 A露出之步驟；4)在含孔內在內之基板表面之兩面形成金屬層之步驟；以及5 )以保留該金屬層及金屬箔A之任意部份之方式進行蝕刻除去，形成期望之第1電容器電極及第2電容器電極之步驟。 (d-1 3 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以含有熱硬化性樹脂及金屬塡料之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3)在基板之至少具有電容器介電質之表面形成金屬層之步驟；以及4)以保留該金屬層及金屬范A之任意部份之方式進行鈾刻除去，形成期望之第1電容器電極及第2電容器電極之步驟。 (d- 1 4 )具有：1 )在內設電容器之多層配線板用材料之金屬箔A面之任意部位配設貫穿孔，且以利用化學反應實施金屬化之導電性糊充塡該貫穿孔，並利用絶緣材料實施金屬箔B之積層來形成基板之步驟；2 )以保留介電質薄膜之任意部份之方式進行蝕刻除去，形成期望之電容器介電質之步驟；3)在基板之至少具有電容器介電質之表面形成金屬層之步驟；以及4)以保留該金屬層及金屬箔A之任意部份之方式進行蝕刻除去，形成期望之第j 電容器電極及第2電容器電極之步驟。 -73- (69) 1251536 以下，參照圖面，針對本發明實施例進行更具體之說明。 (實施例A ) 內設電容器之多層配線板用材料A- 1 在銅箔102之厚度爲35//m之壓延銅箔M-BNH-18( 三井金屬鑛業株式會社製、商品名稱）之表面，以採用四異丙氧基鈦、四第三丁氧基锆、二-三甲基乙醯甲烷鉛錯合物、以及二氧化氮之微波電漿CVD，在基材溫度爲350 t之條件下，形成厚度爲0.5 // m之PZT (鉻鈦酸鉛）薄膜 1 0 1 (圖 1 ( a ))。內設電容器之多層配線板用材料A-2C (d-7) has: 1) a through hole is formed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and is filled with a conductive paste containing a thermosetting resin and a metal material. a step of forming a substrate by using a laminate of the metal foil B with an insulating material; 2) a step of forming a metal layer of 0.1 to 5/m on the surface of at least the dielectric film side of the substrate; 3) a step of forming a metal-plated anti-uranium layer on the surface of the substrate as a part of the portion of the first capacitor electrode; 4) forming a conductor by using metal plating on a portion containing the portion used as the first capacitor electrode a step of patterning; 5) a step of removing the metal plating resist layer; 6) a step of removing the metal layer exposed from the surface of the substrate by uranium etching; 1) exposing the dielectric film a step of forming a capacitor dielectric having an arbitrary shape of the first capacitor electrode pattern by etching; and 8) forming a metal foil A exposed by removing the dielectric film, and forming an arbitrary shape including a capacitor dielectric pattern by uranium engraving Second capacitor The electrode is a step of etching the exposed metal foil B to form a circuit. (d-8) has: 1) a through hole is disposed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and the through hole is filled with a conductive paste which is metallized by a chemical reaction, And using the insulating material -70- 1251536 (66) to carry out the step of forming a substrate of the metal foil B; 2) forming a metal layer of 0.1 to 5 // m on the surface of at least the dielectric film side of the substrate 3) a step of forming a metal-plated anti-uranium layer on the surface of the substrate by retaining any portion of the portion used as the first capacitor electrode; 4) using metal plating to contain the portion used as the first capacitor electrode a step of forming a conductor pattern; 5) a step of removing the metal-plated anti-uranium layer; 6) a step of removing the metal layer of the surface of the substrate exposed to expose the surface of the substrate; 7) a step of etching the dielectric film to form a capacitor dielectric having an arbitrary shape of the first capacitor electrode pattern; and 8) forming a capacitor-containing dielectric by etching the metal foil A exposed by removing the dielectric film The arbitrary shape of the pattern 2 Capacitor electrode, the step of etching the exposed metal foil B to form a circuit. (d-9): 1) a through hole is formed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and is filled with a conductive paste containing a thermosetting resin and a metal material. a step of forming a substrate by forming a laminate of the metal foil B with an insulating material; 2) forming a metal layer by using a conductive paste formed by chemical reaction at any portion of the surface of the dielectric film to form a desired a step of the first capacitor electrode; 3) a step of etching away any portion of the first capacitor electrode containing at least the dielectric film to form a desired capacitor dielectric; and 4) removing the dielectric The metal foil A exposed by the thin film is formed by etching a second capacitor electrode having an arbitrary shape of a capacitor dielectric pattern by uranium etching, and etching the exposed metal foil B to form an electric circuit. (d-1 0 ) has: 1) a through-hole is provided in any portion of the metal foil A surface of the multilayer wiring board material-71 - (67) 1251536 which is provided with a capacitor, and the metallization is performed by a chemical reaction. a paste filled with the through hole, and a metal foil B layer is formed by an insulating material to form a substrate; 2) a metal paste is formed on the surface of the dielectric film by a chemical reaction to form a metal a step of forming a desired first capacitor electrode; 3) performing etching removal to retain a desired capacitor dielectric by retaining any portion of the first capacitor electrode containing at least a dielectric film; and 4) The metal foil A exposed by removing the dielectric film is etched to form a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern, and the exposed metal foil B is etched to form a circuit. (d -1 1 ) has: 1) a step of forming a substrate by laminating a metal foil B with an insulating material on the surface of the metal foil A of the material for the multilayer wiring board in which the capacitor is provided; 2) arbitrarily retaining the dielectric film Part of the method of etching to remove the desired capacitor dielectric; 3) performing etching removal of any portion of the metal foil B to expose the insulating layer formed by the insulating material; 4) removing by laser irradiation a step of exposing the insulating layer to form a hole to expose the metal foil A; 5) a step of forming a metal layer on both sides of the surface of the substrate including the hole; and 6) retaining the metal layer and any part of the metal foil A The step of etching is performed to form a desired first capacitor electrode and second capacitor electrode. (d -1 2 ) has: 1) a step of forming a substrate by laminating a metal foil b with an insulating material on the surface of the metal case A of the material for the multilayer wiring board in which the capacitor is provided; 2) arbitrarily retaining the dielectric film a part of the method of etching to remove the desired capacitor dielectric; 3) performing laser irradiation on any part of the -72-1252336 (68) metal foil B, while removing the metal foil B, and the above insulating material a step of forming an insulating layer to form a hole to expose the metal foil A; 4) a step of forming a metal layer on both sides of the surface of the substrate including the hole; and 5) retaining the metal layer and the metal foil A Part of the method is performed by etching to remove the desired first capacitor electrode and second capacitor electrode. (d-1 3 ) has: 1) a through hole is formed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and is filled with a conductive paste containing a thermosetting resin and a metal crucible; The through hole, and the step of forming a substrate by laminating the metal foil B with an insulating material; 2) the step of etching away by retaining any portion of the dielectric film to form a desired capacitor dielectric; 3) a step of forming a metal layer on a surface of the substrate having at least a capacitor dielectric; and 4) performing uranium engraving to retain the metal layer and any part of the metal A to form a desired first capacitor electrode and second The steps of the capacitor electrode. (d-1 4 ) has: 1) a through hole is disposed in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided, and the conductive paste is filled with a metallization by a chemical reaction; And using the insulating material to carry out the lamination of the metal foil B to form the substrate; 2) the step of etching away any part of the dielectric film to form the desired capacitor dielectric; 3) in the substrate a step of forming a metal layer on at least a surface of the capacitor dielectric; and 4) etching and removing the metal layer and any portion of the metal foil A to form a desired j-th capacitor electrode and a second capacitor electrode . -73- (69) 1251536 Hereinafter, the embodiment of the present invention will be described more specifically with reference to the drawings. (Example A) A material for a multilayer wiring board in which a capacitor is provided, a surface of a rolled copper foil M-BNH-18 (manufactured by Mitsui Mining & Mining Co., Ltd., trade name) having a thickness of 35/m in the copper foil 102 Using microwave plasma CVD with titanium tetraisopropoxide, tetra-tertiary zirconyl zirconate, di-trimethylethyl hydrazine methane lead complex, and nitrogen dioxide at a substrate temperature of 350 t Next, a PZT (lead chromate titanate) film 1 0 1 having a thickness of 0.5 // m was formed (Fig. 1 (a)). Material A-2 for multilayer wiring board with capacitor

在銅箔102之厚度35//m之壓延銅箔M-BNH-18(三井金屬鑛業株式會社製、商品名稱）之表面，以DC濺鍍法形成0.2 μ m之釕薄膜103。此外，在其基板表面以採用四異丙氧基鈦、四第三丁氧基銷、二-三甲基乙醯甲烷鉛錯合物、以及二氧化氮之微波電漿CVD，在基材溫度爲3 5 0 T：之條件下，形成厚度爲0.5 /i m之PZT (鍩鈦酸鉛）薄膜1 〇 1 (第1圖（b ))。內設電容器之多層配線板用材料A-3 在銅箔102之厚度35//m之壓延銅箔M-BNH-18(三井金屬鑛業株式會社製、商品名稱）之表面，以DC濺鍍 -74- 1251536 (70) 法形成0.2 A m之釕薄膜1 0 3。此外，在其表面塗布強介電質薄膜形成材料ρζτ (關東化學株式會社、商品名稱），實施溫度1 5 〇°C、加熱時間3 〇分鐘之預烘焙。塗布及預烘焙再重複實施5次，其後，實施溫度3 5 0 °C、加熱時間1小時之熱處理，形成厚度〇 · 5 # m之p Z T薄膜1 〇 1 ( 第1圖（b ))。實施例A -1On the surface of a rolled copper foil M-BNH-18 (manufactured by Mitsui Mining & Mining Co., Ltd., trade name) having a thickness of 35/m of the copper foil 102, a 0.2 μm tantalum film 103 was formed by DC sputtering. In addition, on the surface of the substrate, microwave plasma CVD using titanium tetraisopropoxide, tetra-terti-butoxyspin, di-trimethylethylmethane-methane complex, and nitrogen dioxide at the substrate temperature A film of PZT (lead bismuth titanate) film 1 〇1 (Fig. 1(b)) having a thickness of 0.5 / im was formed under the condition of 3 5 0 T:. The material A-3 for the multilayer wiring board in which the capacitor is provided is on the surface of the rolled copper foil M-BNH-18 (manufactured by Mitsui Mining & Mining Co., Ltd., product name) having a thickness of 35/m of the copper foil 102, and is subjected to DC sputtering. 74- 1251536 (70) The film forms a film of 0.2 A m 1 0 3 . Further, a surface of a ferroelectric thin film forming material ρζτ (Kanto Chemical Co., Ltd., trade name) was applied to the surface thereof, and prebaking was carried out at a temperature of 15 ° C for 3 minutes. The coating and prebaking were repeated five times, and thereafter, heat treatment was carried out at a temperature of 350 ° C and a heating time of 1 hour to form a p ZT film 1 〇 1 having a thickness of 〇·5 # m (Fig. 1 (b)) . Example A-1

在內設電容器之多層配線板用材料A-2之銅箔102表面，實施利用有機酸系微蝕刻齊！i CZ-8100B ( MEC C Ο .， LTD.製、商品名稱）之粗化處理，當做多層化黏結前處理（第2圖（a))。以板厚爲0.2mm之兩面銅箔玻璃環氧積層板MCL-E-679F (日立化成工業株式會社製、商品名稱）做爲基材，在期望部位上製成導體化之連結孔1 〇 6 、及電路圖案之兩面基板1 04上，實施利用有機酸系微鈾刻劑CZ-8 100B ( MEC CO·，LTD.製、商品名稱）之粗化處理當做多層化黏結前處理後，在其一方之面，利用厚度爲 100 // m之玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱）配設厚度爲18//m之銅箱GTS-18 (FURUKAWA CIRCUIT FOIL CO.，LTD.製、商品名稱），又，在另一方之面，利用厚度爲l〇〇//m之玻璃環氧半固化片GEA-67 9F (日立化成工業株式會社製、商品名稱 )配設前述之內設電容器之多層配線板用材料，在溫度 170°C、壓力1 .5MPa、力〇熱力□壓時間60分鐘之冲壓條件 -75- (71) 1251536 下，實施積層一體化（第2圖（b ))。此處，符號105 係指電鍍銅，符號1 〇 7係指絶緣樹脂基材（半固化片硬化物）。此外，其PZT薄膜表面上以DC濺鍍法形成〇.〇5 // m之鉻薄膜1 〇 8。此外，其表面上以電性銅電鍍形成2 0 //m之金屬層1〇9(第2圖（c))。在該基板表面形成期望之蝕刻抗蝕層，使用氯化鐵水溶液蝕刻除去不必要之銅金屬層’利用鐵氰化鉀水溶液蝕刻除去銘金屬層，形成第1電容器電極圖案（第2圖（d))。接著，形成期望圖案之抗蝕層，以利用CF4氣體之RIE法，蝕刻除去PZT 薄膜及釕薄膜（第2圖（e ))。其次，在該基板表面形成期望之蝕刻抗蝕層，使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望之部位形成0 0 · 1 mm之窗孔，在窗孔之部位，利用三菱電機株式會社製ML5 05 GT型碳酸氣體雷射，以輸出功率26mJ、脈衝寬度1〇〇 // s、冲程數4次之條件實施雷射鑽孔1 1 〇 (第2圖（f))。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並附與觸媒、促進密合後，實施無電解銅電鍍，形成〇·5μπι之銅薄膜。在該基板表面形成期望之電鍍抗蝕層1 η，實施銅電鍍，形成用以電性連結內層之電路導體、及基板表面之導體層之金屬層 (第2圖（g ))。剝離電鍍抗鈾層後’鈾刻除去基板表面之0.5m之銅薄膜，其後，進一步形成期望之餓刻抗倉虫層，以氯化鐵溶液蝕刻除去不必要之銅金屬層’製成形成含有第2電容器電極之電路圖案之電路板（第2圖（h) -76- (72) 1251536In the surface of the copper foil 102 of the material A-2 for the multilayer wiring board in which the capacitor is provided, micro-etching using organic acid is performed! The roughening treatment of i CZ-8100B (MEC C Ο ., LTD., trade name) is treated as a multi-layer bonding (Fig. 2(a)). A two-sided copper foil glass epoxy laminate MCL-E-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) is used as a base material to form a conductor-forming connecting hole 1 〇 6 at a desired portion. And the roughening treatment using the organic acid-based micro-uranium engraving agent CZ-8 100B (trade name, manufactured by MEC CO., LTD.) on the two-sided substrate 1024 of the circuit pattern, and then performing multi-layer bonding pretreatment. On one side, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) with a thickness of 100 // m is used to provide a copper box GTS-18 (FURUKAWA CIRCUIT FOIL CO.) with a thickness of 18/m. In addition, the glass epoxy prepreg GEA-67 9F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 10 〇〇 / / m is disposed on the other side. The material for the multilayer wiring board with a capacitor is laminated under the stamping conditions of -170-(71) 1251536 at a temperature of 170 ° C, a pressure of 1.5 MPa, and a heat-shrinking time of 60 minutes (Fig. 2 (Fig. 2 ( b)). Here, reference numeral 105 denotes electroplated copper, and reference numeral 1 〇 7 denotes an insulating resin substrate (prepreg cured). In addition, on the surface of the PZT film, a chrome film 1 〇 8 of 〇. 5 // m was formed by DC sputtering. Further, a metal layer 1〇9 of 20 //m was formed by electroplating on the surface thereof (Fig. 2(c)). A desired etching resist layer is formed on the surface of the substrate, and an unnecessary copper metal layer is removed by etching with an aqueous solution of ferric chloride. The first metal layer is formed by etching away the metal layer with a potassium ferricyanide aqueous solution to form a first capacitor electrode pattern (Fig. 2 (d) )). Next, a resist layer of a desired pattern is formed, and the PZT thin film and the tantalum thin film are removed by etching using a CF4 gas RIE method (Fig. 2(e)). Next, a desired etching resist layer is formed on the surface of the substrate, an unnecessary copper foil is removed by etching with an aqueous solution of ferric chloride, a window of 0 0 · 1 mm is formed at a desired portion, and a Mitsubishi motor is used at a portion of the window hole. The ML5 05 GT type carbon dioxide gas laser manufactured by the company was subjected to laser drilling 1 1 条件 (Fig. 2 (f)) under the conditions of an output of 26 mJ, a pulse width of 1 〇〇//s, and a stroke number of four times. Ultrasonic cleaning and alkali permanganic acid solution were used to remove the carbonized resin residue, and the catalyst was added to promote adhesion. Electroless copper plating was performed to form a copper film of 〇·5 μm. A desired plating resist layer 1 η is formed on the surface of the substrate, and copper plating is performed to form a metal layer for electrically connecting the inner layer circuit conductor and the conductor layer on the substrate surface (Fig. 2(g)). After stripping the electroplating anti-uranium layer, the uranium engraved a copper film of 0.5 m on the surface of the substrate, and then further formed a desired hungry anti-burd layer, and the iron chloride solution was etched to remove the unnecessary copper metal layer. Circuit board containing the circuit pattern of the second capacitor electrode (Fig. 2(h) -76- (72) 1251536

在該電路板之電路表面，實施利用有機酸系微触刻劑 CZ-8100B ( MEC CO·，LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理。依據（1 )附3 5 // m載體銅箔之厚度爲3//m之銅箔MT35S3(三井金屬鑛業株式會社製、商品名稱）、（2 )厚度爲1 〇〇 // m之含塡料玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱）、（3 )電路板、（4 )當做絶緣樹脂基材1 1 2之厚度爲100//m之含塡料玻璃環氧半固化片GEA-679F、以及 (5)附35//m載體銅箔之厚度爲3//m之銅箔MT35S3 ( 三井金屬鑛業株式會社製、商品名稱）之順序，在溫度 170°C、壓力1.5MPa、力卩熱力[]壓時間60分鐘之冲壓條件下，實施積層一體化。剥離載體銅箔並切除不必要之基板端部後，在該基板表面形成期望之蝕刻抗蝕層，使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望部位形成0 0 . 1 5 m m之窗孔。The surface of the circuit board is subjected to a roughening treatment using an organic acid-based micro-touching agent CZ-8100B (manufactured by MEC CO., LTD., trade name) as a multilayer pre-bonding treatment. (1) Copper foil MT35S3 (manufactured by Mitsui Mining and Mining Co., Ltd., product name) having a thickness of 3 / / m of 3 / 5 m carrier copper foil, (2) 塡 containing a thickness of 1 〇〇 / / m A glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name), (3) a circuit board, and (4) a glass-containing glass ring having a thickness of 100/m as an insulating resin substrate 1 1 2 Oxygen prepreg GEA-679F, and (5) copper foil MT35S3 (manufactured by Mitsui Mining Co., Ltd., trade name) with a thickness of 3/m, with a thickness of 170 ° C, pressure 1.5MPa, force and heat [] Pressing time 60 minutes of stamping conditions, the implementation of laminated integration. After the carrier copper foil is peeled off and the unnecessary substrate end portion is cut off, a desired etching resist layer is formed on the surface of the substrate, and an unnecessary copper foil is removed by etching with an aqueous solution of ferric chloride to form a 0.15 mm portion at a desired portion. Window hole.

在配設於該基板表面之窗孔部位上，利用三菱電機株式會社製ML5 0 5 GT型碳酸氣體雷射，以輸出功率26m J、脈衝寬度1 〇〇 # s、冲程數4次之條件實施雷射鑽孔。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並洗淨、附與觸媒、促進密合後，實施無電解銅電鍍，在雷射孔內壁及銅箔表面形成約20//m之無電解銅電鍍層。在該基板表面之焊接點及電路圖案等必要部位形成蝕刻抗蝕層，蝕刻除去不必要之銅，形成外層電路。在該基板表面以滾筒塗布器塗布30//m之防焊漆 -77- (73) 1251536 PSR-4000 AUS5 ( TAIYO INK MFG. CO·，LTD.製、商品名稱），乾燥後，實施曝光、顯像，在期望之部位形成防焊漆層113。其後，在外層電路圖案露出部表面層形成3 A m之無電解鎳電鍍及0 · 1 // m之無電解金電鍍，得到內設電容器之多層配線板（第2圖（i ))。實施例A-2 除了將內設電容器之多層配線板用材料A-2換成內設電容器之多層配線板用材料A - 3以外，以和實施例a - 1相同之步驟得到內設電容器之多層配線板。實施例A - 3The ML5 0 5 GT-type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used to carry out the conditions of an output of 26 m J, a pulse width of 1 〇〇# s, and a stroke number of 4 times in a window portion of the surface of the substrate. Laser drilling. After removing the carbonized resin residue by ultrasonic cleaning and alkali permanganic acid solution, washing, attaching the catalyst, and promoting adhesion, electroless copper plating is performed to form about 20/ on the inner wall of the laser hole and the surface of the copper foil. /m of electroless copper plating. An etching resist layer is formed on a necessary portion such as a solder joint and a circuit pattern on the surface of the substrate, and unnecessary copper is removed by etching to form an outer layer circuit. On the surface of the substrate, a 30/m solder resist-77-(73) 1251536 PSR-4000 AUS5 (manufactured by TAIYO INK MFG. CO., LTD., trade name) was applied by a roll coater, and after drying, exposure was performed. Development, a solder resist layer 113 is formed at a desired portion. Thereafter, electroless nickel plating of 3 A m and electroless gold plating of 0·1 // m were formed on the surface layer of the exposed portion of the outer layer pattern to obtain a multilayer wiring board with a built-in capacitor (Fig. 2(i)). Example A-2 A capacitor of the built-in capacitor was obtained in the same manner as in Example a-1 except that the material A-2 for the multilayer wiring board in which the capacitor was built was replaced with the material A-3 for the multilayer wiring board in which the capacitor was built. Multilayer wiring board. Example A - 3

在內設電容器之多層配線板用材料A - 3之銅箔1 〇 2表面，實施利用有機酸系微蝕刻劑CZ-8100B ( MEC CO.， LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理（第3圖（a ))。將板厚爲0.2mm之兩面銅箔玻璃環氧積層板MCL-E-679F (日立化成工業株式會社製、商品名稱）當做基材，在期望之部位上製成導體化之連結孔、及電路圖案之兩面基板1 04上，實施利用有機酸系微蝕刻劑CZ-8 100B ( MEC C0.5 LTD.製、商品名稱）之粗化處理當做多層化黏結前處理後，其一方之面，利用當做絶緣樹脂基材107使用之厚度爲l〇〇/im之玻璃環氧半固化片 GEA-6 7 9F (日立化成工業株式會社製、商品名稱）配設厚度爲 18 β m 之銅箔 GTS-18 ( FURUKAWA CIRCUIT -78- (74) 1251536 FOILCO.，LTD.製、商品名稱），又，在另一方之面，利用當做絶緣樹脂基材1 〇 7使用之厚度爲1 Ο Ο μ m之玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱）配設前述之內設電容器之多層配線板用材料，在溫度170°C、壓力1 .5MPa、力[]熱力□壓時間60分鐘之冲壓條件下，實施積層一體化（第3圖（b ))。此處，1 〇 5係電鍍銅，106係孔充塡樹脂。此外，在其PZT薄膜1〇1表面以D C濺鍍法形成0 · 0 5 // m之鉻薄膜1 0 8。此外，對其表面附與觸媒、促進密合後，實施無電解銅電鍍，形成〇.5//m之銅薄膜。其次，在該基板表面形成期望之電鍍抗蝕層，實施銅電鍍，形成厚度爲20//m之當做第1電容器電極使用之金屬層109(第3圖（c))。剝離電鍍抗蝕層後，鈾刻除去基板表面之〇.5//m之銅薄膜及〇.05 //m之鉻薄膜，形成第1電容器電極之圖案（第3圖（d ))。接著，形成期望圖案之抗蝕層，以利用CF4氣體之 RIE法，蝕刻除去PZT薄膜及釕薄膜（第3圖（e ))。其次，在該基板表面形成期望之触刻抗餓層，使用氯化鐵水溶液鈾刻除去不必要之銅箔，在期望之部位形成0 0.1mm之窗孔，在窗孔之部位，利用三菱電機株式會社製 ML5 05 GT型碳酸氣體雷射，以輸出功率26mJ、脈衝寬度 1 00 // s、冲程數4次之條件實施雷射鑽孔1 1 〇 (第3圖（f ))。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並附與觸媒、促進密合後，實施無電解銅電鍍，形成〇. 5 μ m 之銅薄膜。在該基板表面形成期望之電鍍抗蝕層U1，實 -79- (75) 1251536 施銅電鍍，形成用以電性連結內層之電路導體、及基板表面之導體層之金屬層（第3圖（g))。剝離電鍍抗蝕層後，蝕刻除去基板表面之〇 · 5 // m之銅薄膜，其後，進_ 步形成期望之蝕刻抗蝕層，以氯化鐵溶液蝕刻除去不必g 之銅金屬層，製成形成含有第2電容器電極之電路圖案之電路板（第3圖（h ))。其後之多層配線板之加工係和實施例A- 1相同之步驟，可得到內設電容器之多層配線板 (第3圖（i ))。此處，1 1 2係絶緣樹脂基材，1 1 3係防焊漆。實施例A-4 在內設電容器之多層配線板用材料A-3之銅范表面 102，實施利用有機酸系微蝕刻劑CZ-8100B ( MEC C0.， LTD ·製、商品名稱）之粗化處理，當做多層化黏結前處理（第4圖（a ))。將板厚爲0.2mm之兩面銅箔玻璃環氧積層板MCL-E-679F (日立化成工業株式會社製、商品名稱）當做基材，在期望之部位上製成導體化之連結孔、及電路圖案之兩面基板1 04上，實施利用有機酸系微蝕刻劑CZ-8 100B ( MEC CO.，LTD·製、商品名稱）之粗化處理當做多層化黏結前處理後，其一方之面，利用當做絶緣樹脂基材107使用之厚度爲100/ζηι之玻璃環氧半固化片 GEA-6 7 9F (日立化成工業株式會社製、商品名稱）配設厚度爲 18 // m 之銅箔 GTS-1 8 ( FURUKAWA CIRCUIT FOIL CO.，LTD·製、商品名稱），又，在另一方之面，利 (76) 1251536 用當做絶緣樹脂基材107使用之厚度爲100// m之玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱）配設前述之內設電容器之多層配線板用材料，在溫度17〇°C、壓力1.5MPa、加熱加壓時間60分鐘之冲壓條件，實施積層一體化（第4圖（b ))。此處，1 〇 5係電鍍銅，1 06係孔充塡樹脂。此外，在其PZT薄膜表面之期望部位上利用網板印染印刷4 0 // m厚度之利用化學反應實施金屬化之導電性糊之 NANO PASTE ( HARIMA CHEMICALS，IN C ·製、商品名稱）後，在溫度2 0 0 °C、加熱時間1小時之條件下實施烘焙，實施導電性糊之金屬化，形成第1電容器電極之圖案（第4圖（c))。接著，形成期望圖案之抗蝕層，以利用CF4氣體之RIE法，蝕刻除去PZT薄膜及釕薄膜（第4圖（d))。其次，在該基板表面形成期望之蝕刻抗蝕層，使用氯化鐵水溶液鈾刻除去不必要之銅范，在期望之部位形成0 0.1 m m之窗孔，在窗孔之部位，利用三菱電機株式會社製ML5 0 5 GT型碳酸氣體雷射，以輸出功率2 6 mJ、脈衝寬度1 〇〇 μ s、冲程數4次之條件實施雷射鑽孔1 1 0 (第4圖（e ))。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並附與觸媒、促進密合後，實施無電解銅電鍍，形成〇 . 5 μ m之銅薄膜。在該基板表面形成期望之電鍍抗蝕層U 1，實施銅電鍍，形成用以電性連結內層之電路導體、及基板表面之導體層之金屬層（第4圖（f))。剝離電鍍抗蝕層後，蝕刻除去基板表面之〇.5//m之銅薄膜，其後，進一步形成期望 -81 - (77) 1251536 之蝕刻抗蝕層，以氯化鐵溶液蝕刻除去不必要之銅金屬層，製成形成含有第2電容器電極之電路圖案之電路板（第 4圖（g ))。其後之多層配線板之加工係和實施例A -1 相同之步驟，可得到內設電容器之多層配線板（第4圖（ h ))。此處，Π 2係絶緣樹脂基材，1 1 3係防焊漆。實施例A - 5 係使用內設電容器之多層配線板用材料A - 3，然而，蝕刻除去PZT薄膜及釕薄膜之方法並非RIE法，而係針對PZT薄膜採用20%氟化氫銨（NH4F· HF)水溶液進行蝕刻、針對釕薄膜則採用釕蝕刻液RE C - 0 1 (關東化學株式會製、商品名稱）進行蝕刻，其餘步驟則和實施例A- 1 相同，製成內設電容器之多層配線板（第2圖（i ))。The surface of the copper foil 1 〇 2 of the material A - 3 of the multilayer wiring board in which the capacitor is provided is subjected to roughening treatment using an organic acid-based microetching agent CZ-8100B (manufactured by MEC CO., LTD.). Multilayer bonding pretreatment (Fig. 3(a)). A double-sided copper foil glass epoxy laminate MCL-E-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 0.2 mm is used as a base material, and a conductor connection hole and a circuit are formed on a desired portion. On the double-sided substrate 1024 of the pattern, the roughening treatment using the organic acid-based microetching agent CZ-8 100B (trade name, manufactured by MEC C0.5 LTD.) is carried out, and the surface of the double-layered pre-bonding treatment is used. A glass epoxy prepreg GEA-6 7 9F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 10 〇〇 / im used as the insulating resin substrate 107 is provided with a copper foil GTS-18 having a thickness of 18 β m ( FURUKAWA CIRCUIT -78- (74) 1251536 FOILCO., LTD., the product name), and on the other hand, a glass epoxy having a thickness of 1 Ο Ο μm used as the insulating resin substrate 1 〇7 The prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) is equipped with a material for a multilayer wiring board in which the above-mentioned capacitor is provided, and has a temperature of 170 ° C, a pressure of 1.5 MPa, and a force [] thermal pressure time of 60 minutes. Under the stamping conditions, the integration of the layer (Fig. 3 (b)). Here, 1 〇 5 series electroplated copper, 106-series filled with resin. Further, a chromium film of 0·0 5 // m was formed by DC plating on the surface of the PZT film 1〇1. Further, after the surface was attached to the catalyst and the adhesion was promoted, electroless copper plating was performed to form a copper film of 〇.5//m. Next, a desired plating resist layer is formed on the surface of the substrate, and copper plating is performed to form a metal layer 109 which is used as a first capacitor electrode having a thickness of 20/m (Fig. 3(c)). After the plating resist was peeled off, the uranium was engraved to remove a copper film of .5/m from the surface of the substrate and a chromium film of 〇.05 //m to form a pattern of the first capacitor electrode (Fig. 3(d)). Next, a resist layer of a desired pattern is formed, and the PZT thin film and the tantalum thin film are removed by etching using a CF4 gas RIE method (Fig. 3(e)). Secondly, a desired touch-resistant anti-hungry layer is formed on the surface of the substrate, and an unnecessary copper foil is removed by using an aqueous solution of ferric chloride solution to form a window hole of 0.1 mm in a desired portion, and a Mitsubishi Electric is used in the window portion. The ML5 05 GT type carbon dioxide gas laser manufactured by the company was subjected to laser drilling 1 1 〇 (Fig. 3 (f)) under the conditions of an output of 26 mJ, a pulse width of 100 s // s, and a stroke number of four times. After the ultrasonic cleaning and the alkali permanganic acid solution were used to remove the carbonized resin slag, and the catalyst was added to promote adhesion, electroless copper plating was performed to form a copper film of 〇. 5 μm. A desired plating resist U1 is formed on the surface of the substrate, and a solid-79-(75) 1251536 copper plating is performed to form a metal layer for electrically connecting the inner layer circuit conductor and the conductor layer on the substrate surface (Fig. 3) (g)). After the plating resist is peeled off, the copper film of the surface of the substrate is etched and removed, and then a desired etching resist is formed, and the copper metal layer is removed by etching with a ferric chloride solution. A circuit board forming a circuit pattern including the second capacitor electrode is formed (Fig. 3(h)). Thereafter, the processing of the multilayer wiring board is the same as that of the embodiment A-1, and a multilayer wiring board having a built-in capacitor can be obtained (Fig. 3(i)). Here, 1 1 2 is an insulating resin substrate, and 1 1 3 is a solder resist. Example A-4 The roughening of the copper-based surface 102 of the material A-3 for a multilayer wiring board in which a capacitor is used is performed by using an organic acid-based microetching agent CZ-8100B (manufactured by MEC C0., LTD., trade name) Treatment, as a multi-layered pre-bonding treatment (Fig. 4(a)). A double-sided copper foil glass epoxy laminate MCL-E-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 0.2 mm is used as a base material, and a conductor connection hole and a circuit are formed on a desired portion. On the double-sided substrate 1024 of the pattern, the roughening treatment using the organic acid-based microetching agent CZ-8 100B (product name, manufactured by MEC CO., LTD.) is performed on the surface of the multilayered bonding process. A glass epoxy prepreg GEA-6 7 9F (manufactured by Hitachi Chemical Co., Ltd., manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100/ζηι used as the insulating resin substrate 107 is provided with a copper foil GTS-1 8 having a thickness of 18 // m ( FURUKAWA CIRCUIT FOIL CO., LTD., product name), and, on the other hand, Lee (76) 1251536 uses a glass epoxy prepreg GEA-679F having a thickness of 100/m as the insulating resin substrate 107. (The product of Hitachi Chemical Co., Ltd., the product name) is a material for a multilayer wiring board in which the above-mentioned capacitor is placed, and is laminated at a temperature of 17 ° C, a pressure of 1.5 MPa, and a pressurization time of 60 minutes. (Fig. 4 (b) )). Here, 1 〇 5 series electroplated copper, 06 06 hole filled with resin. In addition, after NANO PASTE (manufactured by HARIMA CHEMICALS, IN C., trade name) which is a metal paste conductive paste which is chemically reacted by a screen printing on a desired portion of the surface of the PZT film by a screen printing, Baking was carried out under the conditions of a temperature of 200 ° C and a heating time of 1 hour, and metallization of the conductive paste was carried out to form a pattern of the first capacitor electrode (Fig. 4 (c)). Next, a resist layer of a desired pattern is formed, and the PZT thin film and the tantalum thin film are removed by etching using a CF4 gas RIE method (Fig. 4(d)). Next, a desired etching resist layer is formed on the surface of the substrate, an unnecessary copper is removed by using an aqueous solution of ferric chloride, and a window of 0 0.1 mm is formed in a desired portion, and a Mitsubishi Electric system is used in the window portion. The company's ML5 0 5 GT type carbon dioxide gas laser was used to perform laser drilling 1 1 0 (Fig. 4 (e)) with an output of 2 6 mJ, a pulse width of 1 〇〇μ s, and a stroke number of four times. The carbonized resin residue was removed by ultrasonic cleaning and alkali permanganic acid solution, and the catalyst was bonded to the catalyst to facilitate adhesion. Electroless copper plating was performed to form a copper film of μ 5 μm. A desired plating resist U1 is formed on the surface of the substrate, and copper plating is performed to form a metal layer for electrically connecting the inner layer circuit conductor and the conductor layer on the substrate surface (Fig. 4(f)). After the plating resist is peeled off, the copper film of 〇.5//m on the surface of the substrate is etched away, and thereafter, an etching resist layer of -81 - (77) 1251536 is further formed, and etching is removed by the ferric chloride solution. The copper metal layer is formed into a circuit board (Fig. 4(g)) for forming a circuit pattern including the second capacitor electrode. Subsequent processing of the multilayer wiring board is the same as that of the embodiment A-1, and a multilayer wiring board having a built-in capacitor can be obtained (Fig. 4 (h)). Here, Π 2 is an insulating resin substrate, and 1 1 3 is a solder resist. Example A-5 uses a material A-3 for a multilayer wiring board with a built-in capacitor. However, the method of etching and removing the PZT film and the tantalum film is not the RIE method, but the 20% ammonium hydrogen fluoride (NH4F·HF) is used for the PZT film. The aqueous solution was etched, and the ruthenium film was etched using a ruthenium etching solution RE C - 0 1 (manufactured by Kanto Chemical Co., Ltd., trade name), and the remaining steps were the same as those in Example A-1 to form a multilayer wiring board with a built-in capacitor. (Fig. 2 (i)).

實施例A-6 在內設電容器之多層配線板用材料A-3之銅箔102表面，實施利用有機酸系微蝕刻劑 CZ-8 1 00B ( MEC CO.， LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理（第5圖（a))。將板厚爲0.2mm之兩面銅箔玻璃環氧積層板MCL-E-6 79F (日立化成工業株式會社製、商品名稱）當做基材，在期望之部位上製成導體化之連結孔、及電路圖案之兩面基板1 04，實施利用有機酸系微蝕刻劑 CZ-8 100B ( MEC C0.5 LTD·製、商品名稱）之粗化處理當 -82- (78) 1251536 做多層化黏結前處理後，其一方之面，利用當做絶緣樹脂基材107使用之厚度爲100#^之玻璃環氧半固化片 GEA-6 7 9F (日立化成工業株式會社製、商品名稱）配設厚度爲 18 //m 之銅箔 GTS-1 8 ( FURUKAWA CIRCUIT FOIL CO.，LTD.製、商品名稱），又，在另一方之面，利用當做絶緣樹脂基材1 〇 7使用之厚度爲1 〇〇 // m之玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱）配設前述之內設電容器之多層配線板用材料，在溫度170°C、壓力1.5MPa、加熱加壓時間60分鐘之冲壓條件，實施積層一體化（第5圖（b))。此處，105係電鍍銅，1 〇 6係孔充塡樹脂。接著，形成期望圖案之抗蝕層，以20%氟化氫銨（NH4F · HF )水溶液蝕刻除去PZT薄膜，以釕蝕刻液REC-01 (關東化學株式會製、商品名稱 )蝕刻除去釕薄膜，實施PZT薄膜之圖案化（第5圖（c ))。其次，在該基板表面形成期望之蝕刻抗鈾層，使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望之部位形成 0 0.1mm之窗孔，在窗孔之部位，利用三菱電機株式會社製ML5 0 5 GT型碳酸氣體雷射，以輸出功率26mJ '脈衝寬度1 00 // s、冲程數4次之條件實施雷射鑽孔1 1 0 (第5 圖（d ))。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣後，以DC濺鍍法形成0.05 // m之鉻薄膜108。此外，利用電性銅電鍍在其表面形成20 // m之金屬層109 (第5 圖（e))。此時，薄膜介電質層表面及雷射孔內已形成銅金屬層。在該基板表面形成期望之蝕刻抗鈾層，使用氯 -83- (79) 1251536 化鐵水彳谷液蝕刻除去不必要之銅金屬層，利用鐵氰化鉀水溶液蝕刻除去鉻金屬層，形成第1電容器電極、第2電容器電極、及其他配線圖案而製成電路板（第5圖（f)) 。其後之多層配線板之加工係和實施例A- 1相同之步驟，可得到內設電容器之多層配線板（第5圖（g ))。此處，1 1 2係絶緣樹脂基材，1 1 3係防焊漆。實施例A-7Example A-6 The organic acid-based microetching agent CZ-8 1 00B (product name, manufactured by MEC CO., LTD.) was used for the surface of the copper foil 102 of the material A-3 for the multilayer wiring board in which the capacitor was provided. The roughening treatment is performed as a multi-layered pre-bonding treatment (Fig. 5(a)). A double-sided copper foil glass epoxy laminate MCL-E-6 79F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 0.2 mm is used as a substrate, and a conductor-forming connecting hole is formed at a desired portion, and The double-sided substrate 010 of the circuit pattern is subjected to roughening treatment using an organic acid-based microetching agent CZ-8 100B (manufactured by MEC C0.5 LTD.), and -82-(78) 1251536 is used for multi-layer bonding pretreatment. Then, the thickness of the glass epoxy prepreg GEA-6 7 9F (product name, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 #^ used as the insulating resin substrate 107 is set to a thickness of 18 //m. The copper foil GTS-1 8 (manufactured by FURUKAWA CIRCUIT FOIL CO., LTD., trade name), and on the other hand, the thickness of the insulating resin substrate 1 〇7 is 1 〇〇//m. The glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) is equipped with a material for a multilayer wiring board in which the above-mentioned capacitor is provided, and is pressed at a temperature of 170 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. Conditions, implementation of laminated integration (Figure 5 (b)). Here, the 105 series electroplated copper, and the 1 〇 6 series hole filled with resin. Then, a resist layer of a desired pattern is formed, and a PZT thin film is removed by etching with a 20% aqueous solution of ammonium hydrogen fluoride (NH 4 F · HF ), and a tantalum film is removed by etching the etching liquid REC-01 (manufactured by Kanto Chemical Co., Ltd., trade name) to carry out PZT. Patterning of the film (Fig. 5(c)). Next, a desired etch-resistant uranium layer is formed on the surface of the substrate, and an unnecessary copper foil is removed by etching with an aqueous solution of ferric chloride, and a window of 0 0.1 mm is formed in a desired portion, and Mitsubishi Electric Corporation is used in the window portion. The ML5 0 5 GT type carbon dioxide gas laser was used to perform laser drilling 1 1 0 (Fig. 5 (d)) with an output power of 26 mJ 'pulse width of 1 00 // s and 4 strokes. After the carbonized resin residue was removed by ultrasonic cleaning and alkali permanganic acid solution, a chromium film 108 of 0.05 // m was formed by DC sputtering. Further, a metal layer 109 of 20 // m is formed on the surface by electroplating with copper (Fig. 5(e)). At this time, a copper metal layer is formed on the surface of the thin film dielectric layer and in the laser hole. A desired etch-resistant uranium layer is formed on the surface of the substrate, and an unnecessary copper metal layer is removed by etching with a chlorine-83-(79) 1251536 iron-iron solution, and the chromium metal layer is removed by etching with a potassium ferricyanide aqueous solution to form a first A capacitor electrode, a second capacitor electrode, and other wiring patterns are used to form a circuit board (Fig. 5(f)). Subsequent processing of the multilayer wiring board is the same as that of the embodiment A-1, and a multilayer wiring board having a built-in capacitor can be obtained (Fig. 5(g)). Here, 1 1 2 is an insulating resin substrate, and 1 1 3 is a solder resist paint. Example A-7

在內設電容器之多層配線板用材料A - 3之銅箔表面 1〇2，實施利用有機酸系微蝕刻劑CZ_8100B ( MEC C0.， LTD ·製、商品名稱）之粗化處理，當做多層化黏結前處理（第6圖（a ))。將板厚爲0.2mm之兩面銅箔玻璃環氧積層板MCL-E-679F (日立化成工業株式會社製、商品名稱）當做基材，在期望之部位上製成導體化之連結孔、及電路圖案之兩面基板1 04上，實施利用有機酸系微鈾刻劑CZ-8 100B ( MEC CO., LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理後，其一方之面，利用當做絶緣樹脂基材107使用之厚度爲之玻璃環氧半固化片 GEA-6 7 9F (日立化成工業株式會社製、商品名稱）配設厚度爲 18 // m 之銀箔 GTS-1 8 ( FURUKAWA CIRCUIT FOIL CO.，LTD.製、商品名稱），又，在另一方之面，利用當做絶緣樹脂基材1 〇 7使用之厚度爲1 0 0 # m之玻璃環氧半固化片GEA-67 9F (日立化成工業株式會社製、商品名稱）配設前述之內設電容器之多層配線板用材料’在溫 -84- (80) 1251536In the case of the copper foil surface 1〇2 of the material A-3 of the multilayer wiring board in which the capacitor is provided, the roughening treatment using the organic acid microetching agent CZ_8100B (manufactured by MEC C0., LTD.) is carried out as a multilayer. Pre-bonding treatment (Fig. 6(a)). A double-sided copper foil glass epoxy laminate MCL-E-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 0.2 mm is used as a base material, and a conductor connection hole and a circuit are formed on a desired portion. On the two-sided substrate 1024 of the pattern, a roughening treatment using an organic acid-based micro-uranium engraving agent CZ-8 100B (manufactured by MEC CO., LTD., trade name) is carried out, and the surface is treated as a multilayered pre-bonding treatment. A glass epoxy Epoxy prepreg GEA-6 7 9F (manufactured by Hitachi Chemical Co., Ltd., trade name) is used as a silver foil GTS-1 8 (FURUKAWA CIRCUIT) having a thickness of 18 // m. FOIL CO., LTD., the name of the product, and, on the other hand, a glass epoxy prepreg GEA-67 9F having a thickness of 100 ° m used as the insulating resin substrate 1 〇7 (Hitachi Chemical Co., Ltd.) Industrial Co., Ltd., product name) The material for the multilayer wiring board with the built-in capacitor described above is in the temperature -84- (80) 1251536

度1 7 0 °C、壓力1 . 5 Μ P a、加熱加壓時間6 0分鐘之冲壓條件，實施積層一體化（第6圖（b ))。此處，1 05係電鍍銅，106係孔充塡樹脂。此半固化片係利用溫度100 °C 、壓力1。5 Μ P a、加熱加壓時間1 〇分鐘之條件之熱壓在兩面貼附厚度爲25 // m之聚對苯二甲酸乙二酯（PET )之薄膜並在期望之部位實施鑽床鑽孔後，利用網板印染充塡銅糊 NF2000 ( TATSUTA SYSTEM E L E C T R Ο N I C S 公司製、商品名稱）1 16，然後再剝離表面之PET薄膜者。在該基板之PZT薄膜表面以DC濺鍍法形成0.05 // m之鉻薄膜 1 08。此外，在其表面利用電性銅電鑛形成20 // m之金屬層1 09 (第6圖（c ))。在該基板表面形成期望之蝕刻抗鈾層，使用氯化鐵水溶液蝕刻除去不必要之銅金屬層，使用鐵氰化鉀水溶液鈾刻除去鉻金屬層，形成第1電容器電極之圖案（第6圖（d))。接著，形成期望圖案之抗蝕層，以利用CF4氣體之RIE法，鈾刻除去PZT薄膜及釕薄膜（第6圖（e))。其次，在該基板表面形成期望之鈾刻抗蝕層，以氯化鐵溶液蝕刻除去不必要之銅金屬層，製成形成含有第2電容器電極之電路圖案之電路板（第 6圖（f))。其後，以和實施例A-1相同步驟進行多層配線板之加工，得到內設電容器之多層配線板（第6圖（ g ))。此處，1 1 2係絶緣樹脂基材，Π 3係防焊漆。實施例A - 8 在內設電容器之多層配線板用材料A-3之銅箔表面 -85· (81) 1251536The stamping conditions of the temperature of 1 70 ° C, the pressure of 1.5 Μ P a, and the heating and pressing time of 60 minutes were carried out to integrate the layers (Fig. 6(b)). Here, the 05 series is electroplated with copper, and the 106-series is filled with a resin. The prepreg is coated with polyethylene terephthalate (PET) having a thickness of 25 // m on both sides by hot pressing at a temperature of 100 ° C, a pressure of 1.5 Μ P a , and a heating and pressing time of 1 〇 minute. After the drilling of the drilled bed in the desired portion, the stencil-filled copper paste NF2000 (TATSUTA SYSTEM ELECTR Ο NICS, trade name) 1 16 was used to smear the PET film on the surface. A chromium film of 0.05 // m was formed by DC sputtering on the surface of the PZT film of the substrate. Further, a metal layer of 20 // m is formed on the surface thereof by using an electric copper ore (Fig. 6(c)). A desired etch-resistant uranium layer is formed on the surface of the substrate, an unnecessary copper metal layer is removed by etching with an aqueous solution of ferric chloride, and a chrome metal layer is removed by uranium ferric chloride solution to form a pattern of the first capacitor electrode (Fig. 6 (d)). Next, an anti-corrosion layer of a desired pattern is formed to remove the PZT thin film and the tantalum thin film by RIE of CF4 gas (Fig. 6(e)). Next, a desired uranium resist layer is formed on the surface of the substrate, and an unnecessary copper metal layer is removed by etching with a ferric chloride solution to form a circuit board for forming a circuit pattern including the second capacitor electrode (Fig. 6(f) ). Thereafter, the multilayer wiring board was processed in the same manner as in the example A-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 6 (g)). Here, the 1 1 2 is an insulating resin substrate, and the Π 3 is a solder resist. Embodiment A - 8 Surface of copper foil of material A-3 for multilayer wiring board with capacitor -85· (81) 1251536

102，實施利用有機酸系微蝕刻劑 CZ-8100B ( MEC CO.， LTD .製、商品名稱）之粗化處理，當做多層化黏結前處理（第7圖（a))。將板厚爲〇.2mm之兩面銅淸帳玻璃環氧積層板MCL-E-679F (日立化成工業株式會社製、商品名稱）當做基材，在期望之部位上製成導體化之連結孔、及電路圖案之兩面基板1 〇4，實施利用有機酸系微蝕刻劑CZ-8100B (MEC CO·，LTD·製 '商品名稱）之粗化處理當做多層化黏結前處理後，其一方之面，利用當做絶緣樹脂基材1 〇 7使用之厚度爲100# m之玻璃运氣半固化片 GEA-6 7 9F (日立化成工業株式會社製、商品名稱）配設厚度爲 18m 之銅箔 GTS-18 ( FURUKAWA CIRCUIT FOIL CO.，LTD.製、商品名稱），又，在另一方之面，利用當做絶緣樹脂基材1 〇 7使用之厚度爲1 〇〇 // m之玻璃環氧半固化片 GEA-67 9F (日立化成工業株式會社製、商品名稱 )配設前述之內設電容器之多層配線板用材料，以溫度 20(TC、壓力1.5MPa、力□熱力〇壓時間60分鐘之冲壓條件，實施積層一體化（第7圖（b ))。又，105係電鍍銅，106係孔充塡樹脂。此半固化片係利用溫度1〇〇 °C、壓力1.5MPa、加熱加壓時間10分鐘之條件之熱壓在兩面貼附厚度爲25/zm之聚對苯二甲酸乙二酯（PET)之薄膜並在期望之部位實施鑽床鑽孔後，利用網板印染充塡利用化學反應實施金屬化之導電性糊117之NANO PASTE ( HARIMA CHEMICALS，INC.製、商品名稱），然後再剝離表面之PET薄膜者。其後以和實施例1相同步驟實施 -86- (82) 1251536 電容器之加工及多層配線板之加工，得到內設電容器之多層配線板（第7圖（c ))。又，1 12係絶緣樹脂基材， 1 1 3係防焊漆。比較例A -1 將板厚爲〇.2mm之兩面銅箔玻璃環氧積層板MCL-E-6 7 9F (日立化成工業株式會社製、商品名稱）當做基材，利用厚度爲l〇〇//m之玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱），在期望之部位上製成導體化之連結孔、及電路圖案之4層基板之表面以DC 濺鍍法形成〇 · 2 // m之釕薄膜（第8圖（a ))。此處， 1 〇 2係銅箔，1 0 5係電鍍銅，1 〇 6係孔充塡樹脂，1 〇 7係絶緣樹脂基材。形成期望圖案之抗蝕層，以RIE法鈾刻除去釕薄膜1 〇 3，其後，使用氯化鐵水溶液蝕刻除去內層基板表面之銅金屬層，形成含有第2電容器電極之電路圖案（第 8圖（b))。此外，在其基板表面塗布強介電質薄膜形成材料P ZT (關東化學株式會製、商品名稱），實施溫度1 5 (TC、加熱時間3 0分鐘之預烘焙。再重複實施5次塗布及預烘焙，其後，實施溫度2 5 0 °C、加熱時間1小時之熱處理，形成厚度爲〇.5//m之PZT薄膜ιοί (第8圖 (c ))。此外，在該P Z T薄膜表面以D C濺鍍法形成〇 · 〇 5 // m之鉻薄膜。利用電性銅電鍍在其表面形成2 0 // m 之金屬層1〇9(第8圖（d))。在該基板表面形成期望之蝕刻抗鈾層，使用氯化鐵水溶液蝕刻除去不必要之銅金 -87- (83) 1251536 屬層，使用鐵氰化鉀水溶液蝕刻除去鉻金屬層，形成第1 電容器電極之圖案，製成電路板（第8圖（e))。其後 ’以和實施例A-1相同步驟進行多層配線板之加工，得到內設電容器之多層配線板（第8圖（f ))。此處，1 12 係絶緣樹脂基材，1 1 3係防焊漆。試驗方法如下所示。 (介電質之膜厚）介電質之膜厚係以 Focused Ion Beam System (FIB: FB-20 00A、（株）日立製作所製、商品名稱）切削形成電極之電容器，並以掃描型電子顯微鏡觀察其剖面，係夾著膜之電極及電極間之距離的5點平均値。 (電容率）電容率係在25 °C之溫度管理之環境下，依據IP C-650 2.5·5·2以1MHz之頻率檢測。 (電容器容量）電容器容量之檢測上，係採用在阻抗分析儀429 1 B ( AGILENT TECHNOLOGIES製、商品名稱）經由50Ω同軸纜線SUCOFLEX 1 04/1 00 ( SUHNER公司製、商品名稱）連結著高頻信號檢測探針MICROPROBE ACP50 ( GSG250 型、Cascade公司製、商品名稱）之檢測系統。電容器之電極尺寸爲1mm□，檢測1GHz之電容。檢測抽樣數爲5 -88- (84) 1251536 表1 1 電容率 ^膜厚（// m) 電容器容量（nF) jg小値最大値平均値最小値最大値平均値實施例 A-1 70 ^0.45 0.52 0.48 1.1 1.3 1.2 A-2 100 _0.48 0.51 0.50 1.5 1.7 1.6 A-3 100 0.48 0.51 0.50 1.5 1.7 1.6 A-4 100 _^0.48 0.51 0.50 1.5 1.7 1.6 A-5 100 _0.48 0.51 0.50 1.5 1.7 1.6 A-6 100 _0.48 0.51 0.50 1.5 1.7 1.6 A-7 100 0.48 0.51 0.50 1.5 1.7 1.6 A-8 100 _0.48 0.51 0.50 1.5 1.7 1.6 比較例A-1 80 _0.33 0.67 0.50 1.0 2.0 1.3102. The roughening treatment using the organic acid-based microetching agent CZ-8100B (manufactured by MEC CO., LTD., trade name) is carried out as a multi-layer bonding treatment (Fig. 7(a)). MCL-E-679F (manufactured by Hitachi Chemical Co., Ltd., manufactured by Hitachi Chemical Co., Ltd.), which is a two-sided copper enamel glass epoxy laminate with a thickness of 〇.2 mm, is used as a substrate, and a conductor-forming connecting hole is formed in a desired portion. And the two-sided substrate 1 〇 4 of the circuit pattern, and the roughening treatment using the organic acid-based micro etchant CZ-8100B (trade name of MEC CO·, LTD.) is performed on the surface of the multilayered pre-bonding treatment. A glass epoxy prepreg GEA-6 7 9F (manufactured by Hitachi Chemical Co., Ltd., manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100 # m used as the insulating resin substrate 1 〇7 is provided with a copper foil GTS-18 (FURUKAWA) having a thickness of 18 m. CIRCUIT FOIL CO., LTD., and the name of the product, and on the other hand, a glass epoxy prepreg GEA-67 9F having a thickness of 1 〇〇//m used as the insulating resin substrate 1 〇7 ( Hitachi Kasei Kogyo Co., Ltd., product name) The material for the multilayer wiring board in which the above-mentioned capacitor is placed, and the lamination integration is carried out at a temperature of 20 (TC, a pressure of 1.5 MPa, and a heat-compression time of 60 minutes). (Fig. 7(b)) In addition, 105 series electroplated copper, 106-series filled with resin. The prepreg is attached to a thickness of 25/zm on both sides by hot pressing at a temperature of 1 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 10 minutes. After the film of polyethylene terephthalate (PET) is drilled in a desired part, the NANO PASTE ( HARIMA CHEMICALS, INC) is used to fill the conductive paste 117 which is chemically reacted by chemical reaction. , product name, and then stripped PET film on the surface. Thereafter, in the same procedure as in Example 1, the processing of the capacitor and the processing of the multilayer wiring board were carried out to obtain the multilayer wiring of the built-in capacitor. Plate (Fig. 7(c)). Also, 1 12 series insulating resin substrate, 1 1 3 series solder resist. Comparative Example A -1 Two-sided copper foil glass epoxy laminate MCL with a thickness of 〇.2 mm -E-6 7 9F (product name, manufactured by Hitachi Chemical Co., Ltd.), as a base material, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 10 〇〇 / / m, Making a conductord connection hole at a desired portion, The surface of the four-layer substrate of the circuit pattern is formed by DC sputtering to form a film of 〇··························· 〇6-line hole-filled resin, 1 〇7-type insulating resin substrate. A resist layer of a desired pattern is formed, and the ruthenium film 1 〇3 is removed by RIE, and then the inner layer substrate is etched away using an aqueous solution of ferric chloride. The copper metal layer on the surface forms a circuit pattern including the second capacitor electrode (Fig. 8(b)). In addition, a ferroelectric thin film forming material P ZT (manufactured by Kanto Chemical Co., Ltd., trade name) was applied to the surface of the substrate, and a pre-baking at a temperature of 15 (TC, heating time of 30 minutes) was carried out. Prebaking, followed by heat treatment at a temperature of 250 ° C and a heating time of 1 hour to form a PZT film ιοί (Fig. 8 (c)) having a thickness of 〇5/m. Further, on the surface of the PZT film A chromium film of 〇·〇5 // m is formed by DC sputtering. A metal layer 1〇9 (Fig. 8(d)) of 20 0 m is formed on the surface by electroplating with copper. Forming a desired etch-resistant uranium layer, etching an unnecessary copper-gold-87-(83) 1251536 genus layer with an aqueous solution of ferric chloride, and etching the chrome-metal layer using an aqueous solution of potassium ferricyanide to form a pattern of the first capacitor electrode. A circuit board was produced (Fig. 8(e)). Thereafter, the multilayer wiring board was processed in the same manner as in the example A-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 8(f)). , 1 12 series insulating resin substrate, 1 1 3 series solder mask. The test method is as follows. (Thickness of the film thickness) The film thickness of the dielectric is cut by a Focused Ion Beam System (FIB: FB-20 00A, manufactured by Hitachi, Ltd., trade name), and the cross section is observed by a scanning electron microscope. The 5-point average 値 of the distance between the electrode and the electrode sandwiching the film. (Polarity ratio) The permittivity is measured at a frequency of 1 MHz according to IP C-650 2.5·5·2 under the temperature management environment of 25 °C. (capacitor capacity) In the detection of the capacitor capacity, the impedance analyzer 429 1 B (product name, manufactured by AGILENT TECHNOLOGIES) is connected to the high via a 50Ω coaxial cable SUCOFLEX 1 04/1 00 (product name, manufactured by SUHNER Co., Ltd.). The detection system of the frequency signal detection probe MICROPROBE ACP50 (GSG250, manufactured by Cascade), the electrode size of the capacitor is 1mm□, and the capacitance of 1GHz is detected. The number of samples tested is 5 -88- (84) 1251536 Table 1 1 Capacitance ^ film thickness (/ / m) Capacitor capacity (nF) jg less than maximum 値 average 値 minimum 値 maximum 値 average 値 Example A-1 70 ^ 0.45 0.52 0.48 1.1 1.3 1.2 A-2 100 _0.48 0.51 0.50 1.5 1. 7 1.6 A-3 100 0.48 0.51 0.50 1.5 1.7 1.6 A-4 100 _^0.48 0.51 0.50 1.5 1.7 1.6 A-5 100 _0.48 0.51 0.50 1.5 1.7 1.6 A-6 100 _0.48 0.51 0.50 1.5 1.7 1.6 A- 7 100 0.48 0.51 0.50 1.5 1.7 1.6 A-8 100 _0.48 0.51 0.50 1.5 1.7 1.6 Comparative Example A-1 80 _0.33 0.67 0.50 1.0 2.0 1.3

一 ^ ^ A-8皆採用金屬箔表面配設著電容率爲 10〜2000且膜厚爲〇〇5〜m之介電質薄膜之內設電容器之多層配線板用材料所製成之內設電容器之基板。製成之電容器容量之誤差皆低於± 1 0 %，可製成均一且良好之電容器。又’比較例A-1因係在實施金屬層圖案化之基板表面形成介電質薄膜之內設電容器之基板，膜厚誤差較大，結果，電容器容量之誤差亦爲最大之54%。依據上述實施形態，本發明可提供一種多層配線板， -89- 1251536 (85) 具有形成電容器之介電質薄膜之電容率爲20〜2000且膜厚爲0.1〜之電容誤差較小之電容器。 (實施例B ) 內層基板B -1 在銅箔厚爲3 // m、板厚爲0.2mm之兩面銅箔玻璃環氧積層板 MCL-E-679F (日立化成工業株式會社製、商品名稱）實施期望之鑽床鑽孔（直徑200 // m )。其次，實施超音波洗淨、及使用高錳酸鹼性溶液除去碳化之樹脂渣並附與觸媒、促進密合後，對該基板實施無電解銅電鍍，在鑽床鑽孔內壁及銅箔表面形成約15//m之無電解銅電鍍層204。利用以次氯酸鈉爲主成分之黑化處理、及以二甲基胺基氫化硼爲主成分之還原處理來對得到之基板表面實施粗化處理。其次，以網板印染將糊類型之熱硬化型絶緣材料 HRP-700BA ( TAIYO INK MFG. CO·，LTD.製、商品名稱）當做孔充塡樹脂203充塡至該基板之鑽床鑽孔內，以170 °C、6 0分鐘之熱處理實施硬化。以擦光刷硏磨該基板，除去多餘絶緣材料。對該基板附與觸媒、促進密合後，實施無電解銅電鍍，在基板表面形成約1 5 // m之無電解銅電鏟層，製成基板內部具有用以連結導體層間之通孔’且具有表面平滑之金屬層之基板。從掃描型電子顯微鏡觀察之影像求取之基板表面之金屬層之表面粗糙度爲 0.3//m。製成之內層基板之剖面圖如第 9圖所示。又， 2 0 2係絶緣樹脂基材，2 0 1係銅箔。 (86) 1251536 內層基板B-2 在厚度爲200 //m之玻璃環氧半固化片GEA_6 7 9F( 曰立化成王業株式會社製、商品名稱）之兩面’以溫度 1 0 0 °C、壓力1 . 5 Μ P a、力Π熱加壓時間1 〇分鐘之條件之熱壓貼附厚度爲2 5 // m之聚對苯二甲酸乙二酯（P ET )之薄膜。在該半固化片實施期望之鑽床鑽孔（直徑2 0 0 # m ) 後，利用網板印染，充塡銅糊 NF2000 ( TATSUTA SYSTEM ELECTRONICS公司製、商品名稱）2 0 5。剝離表面之PET薄膜，從兩面夾住厚度爲18//m之銅箔GTS-18 (FURUKAWA CIRCUIT FOIL CO·，LTD.製、商品名稱），在溫度1 7 〇 °C、壓力1 . 5 Μ P a、加熱加壓時間6 0分鐘之冲壓條件下實施積層一體化，製成基板內部具有用以連結導體層間之通孔，且具有表面平滑之金屬層之基板。從掃描型電子顯微鏡觀察之影像求取之基板表面之金屬層之表面粗糙度爲〇.2//m。製成之內層基板之剖面圖如第10圖所示。內層基板B - 3 在厚度爲200 /im之玻璃環氧半固化片GEA-6 79F( 曰立化成工業株式會社製、商品名稱）之兩面，以溫度 l〇〇°C、壓力1 .5MPa、力□熱力□壓時間10分鐘之條件之熱壓貼附厚度爲25 // m之聚對苯二甲酸乙二酯（PET )之薄膜。在該半固化片實施期望之鑽床鑽孔（直徑200 // m ) 後’利用網板印染，充塡利用化學反應實施金屬化之導電 -91 - (87) 1251536 性糊之 NANO PASTE ( HARIMA CHEMICALS，INC.製、商品名稱）206。剝離表面之PET薄膜，從兩面夾住厚度爲 1 8 // m 之銅箔 GTS-1 8 ( FURUKAWA CIRCUIT FOIL CO·， LTD·製、商品名稱），在溫度1 70°C、壓力1，5MPa、加熱加壓時間6 0分鐘之冲壓條件下實施積層一體化，製成基板內部具有用以連結導體層間之通孔，且具有表面平滑之金屬層之基板。從掃描型電子顯微鏡觀察之影像求取之基板表面之金屬層之表面粗f造度爲製成之內層基板之剖面圖如第1 1圖所示。實施例B -1 在內層基板B-1之基板表面以DC濺鍍法形成0.2 // m 之釕薄膜2 0 7 (第1 2圖（a ))。此外，在其基板表面上以使用四異丙氧基鈦、四第三丁氧基鍩、二-三甲基乙醯甲烷鉛錯合物、二氧化氮之微波電漿CVD，在基板溫度爲2 5 0 °C之條件下形成厚度爲0.5 // m之PZT (鍩鈦酸鉛 )薄膜208(第12圖（b))。此外，在其PZT薄膜表面以DC濺鍍法形成〇.〇5 μ m之鉻薄膜209。此外，在其表面利用電性銅電鍍形成20//m之金屬層210(第12圖（c ))° 在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液飩刻除去不必要之銅金屬層2 1 0，利用鐵氰化鉀水溶液蝕刻除去鉻金屬層2 0 9，形成第1電容器電極2 1 7之圖案（第12圖（d ))。接著，形成期望圖案之抗蝕層，以 -92- (88) 1251536 利用CF4氣體之RIE法，蝕刻除去PZT薄膜2 08及釕薄膜2 0 7 (第12圖（e ))。其次，進一步形成期望之蝕刻抗蝕層，以氯化鐵溶液蝕刻除去不必要之銅金屬層，形成含有第2電容器電極218之電路圖案，製成內設電容器之多層配線板使用之內層板2 1 9 (第1 2圖（f ))。在該內層板之電路表面利用以次氯酸鈉爲主成分之黑化處理及以二甲基胺基氫化硼爲主成分之還原處理來實施粗化處理。依據（1 )附3 5 // m載體銅箔之厚度爲3 // m 之銅箔MT3 5 S3 (三井金屬鑛業株式會社製、商品名稱）、（2)絶緣樹脂基材211之厚度爲100// m之含塡料玻璃環氧半固化片GEA-67 9F (日立化成工業株式會社製、商品名稱）、（3 )內層板2 1 9、（ 4 )絶緣樹脂基材2 1 1 之厚度爲l〇〇//m之含塡料玻璃環氧半固化片GEA-679F 、以及（5)附35//m載體銅箔之厚度爲3//m之銅箔 MT3 5 S 3 (三井金屬鑛業株式會社製、商品名稱）之順序，在溫度170 °C、壓力1.5 MPa、加熱加壓時間60分鐘之冲壓條件下實施積層一體化。剥離載體銅箔並切除不必要之基板端部後，在該基板表面形成期望之鈾刻抗蝕層，蝕刻除去不必要之銅箔，在期望之部位上形成直徑0.15mm 之窗孔。在配設於該基板表面之窗孔部位上，利用三菱電機株式會社製ML 5 0 5 GT型碳酸氣體雷射，以輸出功率26mJ、脈衝寬度]s、冲程數4次之條件實施雷射鑽孔。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並實施洗淨、 -93- (89) 1251536 附與壁及板表貪虫刻 PSR· 稱）漆層 β m 設電實施施例實施施例實施之釕布強品名觸媒、促進密合後，實施無電解銅電鍍，在雷射孔內銅箔表面形成約2 0 // m之無電解銅電鑛層。在該基面之焊接點及電路圖案等必要部位形成蝕刻抗蝕層，除去不必要之銅，形成外層電路2 1 3。在該基板表面以滾筒塗布器塗布 3 0 // m之防焊漆 4000 AUS5 ( TAIYO INK MFG. CO.，LTD.製、商品名 ’乾燥後，實施曝光、顯像，在期望之部位形成防焊 2 1 2。其後，在外層電路圖案露出部表面層形成3 之無電解鎳電鍍及0.1 // m之無電解金電鍍，得到內容器之多層配線板2 2 0 (第4圖（g ))。例B-2 除了將內層基板B-1換成內層基板B-2以外，以和實 B - 1相同之步驟，得到內設電容器之多層配線板。A ^ ^ A-8 is made of a material for a multilayer wiring board in which a capacitor having a dielectric constant of 10 to 2000 and a film thickness of 〇〇 5 to m is provided on the surface of the metal foil. The substrate of the capacitor. The capacitance of the fabricated capacitor is less than ± 10%, making it a uniform and good capacitor. Further, in Comparative Example A-1, a substrate having a capacitor formed on the surface of the substrate on which the metal layer was patterned was formed, and the film thickness error was large, and as a result, the error in the capacitor capacity was also 54% at the maximum. According to the above embodiment, the present invention can provide a multilayer wiring board, which has a capacitor having a capacitance ratio of 20 to 2000 and a film thickness of 0.1 to a capacitor having a small capacitance error of 0.1 to 1251536 (85). (Example B) Inner layer substrate B -1 Copper foil glass epoxy laminate MCL-E-679F having a copper foil thickness of 3 // m and a thickness of 0.2 mm (manufactured by Hitachi Chemical Co., Ltd., trade name ) Implement the desired drill hole drilling (200 // m diameter). Next, ultrasonic cleaning is performed, and the carbonized resin slag is removed by using a permanganic acid alkaline solution, and the catalyst is attached to the catalyst to promote adhesion. The substrate is subjected to electroless copper plating, and the inner wall and the copper foil of the drill hole are drilled. The surface forms an electroless copper plating layer 204 of about 15/m. The surface of the obtained substrate was subjected to a roughening treatment by a blackening treatment containing sodium hypochlorite as a main component and a reduction treatment mainly composed of dimethylaminoborohydride. Next, a paste-type thermosetting insulating material HRP-700BA (manufactured by TAIYO INK MFG. CO., LTD., trade name) is used as a hole filling resin 203 to be filled into the drill hole of the substrate by the screen printing and dyeing. Hardening was carried out by heat treatment at 170 ° C for 60 minutes. The substrate is honed with a brush to remove excess insulating material. After the substrate is attached to the catalyst and promotes adhesion, electroless copper plating is performed, and an electroless copper shovel layer of about 15 // m is formed on the surface of the substrate to form a through hole between the conductor layers. 'And a substrate having a smooth metal layer. The surface roughness of the metal layer on the surface of the substrate obtained from the image observed by the scanning electron microscope was 0.3/m. A cross-sectional view of the fabricated inner substrate is shown in Fig. 9. Further, 2 0 2 is an insulating resin substrate, and 2 0 1 is a copper foil. (86) 1251536 Inner substrate B-2 On both sides of the glass epoxy prepreg GEA_6 7 9F (manufactured by 曰立化成王业株式会社, trade name) with a thickness of 200 //m, at a temperature of 1 0 0 °C, pressure 1. 5 Μ P a, heat-pressurized time 1 〇 minutes of the condition of hot pressing with a thickness of 2 5 / m of polyethylene terephthalate (P ET ) film. After the desired pre-drilling hole drilling (diameter 2 0 0 #m) was carried out, the prepreg was filled with a copper paste NF2000 (manufactured by TATSUTA SYSTEM ELECTRONICS, trade name) 205. The PET film of the surface was peeled off, and the copper foil GTS-18 (manufactured by FURUKAWA CIRCUIT FOIL CO., LTD.) having a thickness of 18/m was sandwiched between the two sides at a temperature of 1 7 〇 ° C and a pressure of 1.5 Μ P a and a pressurization time of 60 minutes under heating and pressurization were carried out to form a substrate having a metal layer having a smooth surface and having a through hole between the conductor layers. The surface roughness of the metal layer on the surface of the substrate obtained from the image observed by the scanning electron microscope was 〇.2//m. A cross-sectional view of the fabricated inner substrate is shown in Fig. 10. The inner substrate B - 3 is on both sides of a glass epoxy prepreg GEA-6 79F (manufactured by Konica Chemical Co., Ltd., trade name) having a thickness of 200 / im, at a temperature of 10 ° C, a pressure of 1.5 MPa, and a force. □ Thermal compression The film of polyethylene terephthalate (PET) with a thickness of 25 // m is attached by hot pressing for 10 minutes. After the prepreg is subjected to the desired drill hole drilling (200 // m diameter), the stencil printing is used to carry out the metallization by chemical reaction. 91- (87) 1251536 NANO PASTE ( HARIMA CHEMICALS, INC ., product name) 206. The PET film on the surface was peeled off, and the copper foil GTS-1 8 (manufactured by FURUKAWA CIRCUIT FOIL CO·, LTD., manufactured under the trade name) having a thickness of 1 8 // m was sandwiched between the two sides at a temperature of 1 70 ° C and a pressure of 1,5 MPa. The laminate is laminated under the pressing conditions of 60 minutes of heating and pressing, and a substrate having a metal layer having a smooth surface and a through hole between the conductor layers is formed inside the substrate. The surface roughness of the metal layer on the surface of the substrate obtained from the image observed by the scanning electron microscope is a cross-sectional view of the inner substrate which is formed as shown in Fig. 11. Example B-1 A 0.2* m thin film 2 0 7 was formed on the surface of the substrate of the inner substrate B-1 by DC sputtering (Fig. 2 (a)). In addition, on the surface of the substrate, microwave plasma CVD using titanium tetraisopropoxide, tetradecyloxyphosphonium, di-trimethylethylmethane-methane complex, and nitrogen dioxide is used at the substrate temperature. A PZT (lead bismuth titanate) film 208 having a thickness of 0.5 // m was formed under conditions of 25 ° C (Fig. 12(b)). Further, a chrome film 209 of 〇. 5 μm was formed by DC sputtering on the surface of the PZT film. Further, a metal layer 210 of 20/m is formed by electroplating on the surface thereof (Fig. 12(c)). A desired etching resist layer is formed on the surface of the substrate, and etching is removed by using an aqueous solution of ferric chloride. The copper metal layer 210 is etched away by the potassium ferricyanide aqueous solution to remove the chromium metal layer 209, forming a pattern of the first capacitor electrode 2 17 (Fig. 12(d)). Next, a resist layer of a desired pattern is formed, and the PZT film 2 08 and the thin film 2 0 7 (Fig. 12(e)) are removed by etching using a CF4 gas RIE method at -92-(88) 1251536. Next, a desired etching resist layer is further formed, and an unnecessary copper metal layer is removed by a ferric chloride solution to form a circuit pattern including the second capacitor electrode 218, thereby forming an inner layer board for using a multilayer wiring board with a built-in capacitor. 2 1 9 (Fig. 1 2 (f)). The surface of the circuit of the inner layer is subjected to a roughening treatment by a blackening treatment containing sodium hypochlorite as a main component and a reduction treatment mainly composed of dimethylaminoborohydride. (1) A copper foil MT3 5 S3 (manufactured by Mitsui Mining and Mining Co., Ltd.) having a thickness of 3 // m of a carrier foil having a thickness of 3 // m (3), and a thickness of the insulating resin substrate 211 of 100 // m containing glass epoxy prepreg GEA-67 9F (manufactured by Hitachi Chemical Co., Ltd., trade name), (3) inner layer 2 19, (4) thickness of insulating resin substrate 2 1 1 L〇〇//m containing glass epoxy prepreg GEA-679F, and (5) 35//m carrier copper foil thickness of 3/m copper foil MT3 5 S 3 (Mitsui Metals Mining Co., Ltd. The order of the system and the product name was carried out under the conditions of a temperature of 170 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. After the carrier copper foil was peeled off and the unnecessary substrate end portion was cut, a desired uranium resist layer was formed on the surface of the substrate, the unnecessary copper foil was removed by etching, and a window hole having a diameter of 0.15 mm was formed on the desired portion. A laser drill was applied to a window hole portion of the surface of the substrate by using a ML 5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation to perform a laser drill with an output of 26 mJ, a pulse width of s, and a stroke number of four times. hole. Ultrasonic cleaning and alkali permanganic acid solution to remove carbonized resin slag and wash, -93- (89) 1251536 attached to the wall and plate table greet PSR · said) lacquer layer β m set up electricity to implement the case After the implementation of the example, the strong name of the catalyst and the adhesion are promoted, and electroless copper plating is performed to form an electroless copper electroplated layer of about 20 // m on the surface of the copper foil in the laser hole. An etching resist layer is formed on a necessary portion such as a solder joint and a circuit pattern on the base surface to remove unnecessary copper, thereby forming an outer layer circuit 2 1 3 . On the surface of the substrate, a 30 Å/m anti-welding paint 4000 AUS5 (manufactured by TAIYO INK MFG. CO., LTD., manufactured under the trade name of ', dried, exposed, developed, and formed at a desired portion) Welding 2 1 2. Thereafter, electroless nickel plating and 0.1/5 m electroless gold plating were formed on the surface layer of the exposed portion of the outer layer pattern to obtain a multilayer wiring board 2 2 0 of the inner container (Fig. 4 (g Example B-2 A multilayer wiring board with a built-in capacitor was obtained in the same procedure as the actual B-1 except that the inner substrate B-1 was replaced with the inner substrate B-2.

除了將內層基板B-1換成內層基板B-3以外，以和實 B-1相同之步驟，得到內設電容器之多層配線板。例B-4 在內層基板B - 1之基板表面以d C濺鍍法形成〇. 2 // m 薄膜207(第12圖（a))。此外，在其基板表面塗介電質薄膜形成材料PZT (關東化學株式會社製、商稱）’實施溫度1 5 0它、加熱時間3 〇分鐘之預烘焙 -94- (90) 1251536 。再重複實施5次塗布及預烘焙，其後，實施溫度2 5 0 °C 、加熱時間1小時之熱處理，形成厚度爲0.5 /z m之PZT 薄膜208 (第12圖（b))。其後，以和實施例B-1相同之步驟進行電容器之加工及多層配線板之加工，得到內設電容器之多層配線板（第12圖（g))。實施例B - 5 PZT薄膜208及釕薄膜207之蝕刻除去方法並未採用 RIE法，而係針對pZT薄膜採用20%氟化氫銨（NH4F· HF )水溶液進行蝕刻、針對釕薄膜則採用釕蝕刻液reC-0 1 (關東化學株式會製、商品名稱）進行蝕刻，其餘步驟則和實施例B-4相同，製成內設電容器之多層配線板（第 12 圖（g ))。實施例B - 6 在在內層基板B_1之基板表面以DC濺鍍法形成〇.2 // πι之釕溥膜2 0 7 (第1 3圖（a ))。此外，在其基板表面塗布強介電質薄膜形成材料ρ ΖΊΓ (關東化學株式會社製、商品名稱），實施溫度〗5 〇 t、加熱時間3 〇分鐘之預烘焙。再重複實施5次塗布及預烘焙，其後，實施溫度 25 0 °C、加熱時間1小時之熱處理，形成厚度爲〇·5 “❿之 PZT薄g旲208(第13圖（b))。此外，在其PZT薄膜表面以DC濺鍍法形成〇.〇5从m之鉻薄膜2〇9。此外，洗淨其表面並附與觸媒、促進密合後，實施無電解銅電鍍形成 -95- (91) 1251536 0.5// m之銅薄膜。在該基板之表面形成期望之電鍍抗蝕層2 1 5，實施銅電鍍，形成厚度爲20//m之當做第1電容器電極使用之金屬層2 1 4 (第1 3圖（c ))。剝離電鍍抗蝕層2 1 5後，蝕刻除去基板表面之〇 . 5 // m之銅薄膜及0 · 〇 5 // m之鉻薄膜，形成第1電容器電極217之圖案（第13圖（d))。接著，形成期望圖案之抗鈾層，利用2 0重量％氟化氫錢 (NH4F · HF )水溶液蝕亥[J除去PZT薄膜2 08，利用釕蝕刻液R E C - 0 1 (關東化學株式會社製、商品名稱）蝕刻除去釕薄膜207(第13圖（e))。其次，進一步形成期望之蝕刻抗蝕層，以氯化鐵溶液蝕刻除去不必要之銅金屬層 ’形成含有第2電容器電極218之電路圖案，製成內層板 2 1 9 (第1 3圖（f))。其後，以和實施例b -1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板 220 (第 13 圖（g))。實施例B - 7 在內層基板B-1之基板表面以DC濺鑛法形成0.2 // m 之釕薄膜207(第14圖（a))。此外，在其基板表面塗布強介電質薄膜形成材料ΡΖΤ (關東化學株式會社製、商品名稱），實施温度1 5 〇 °C、加熱時間3 0分鐘之預烘焙。再重複實施5次塗布及預烘焙，其後，實施溫度2 5 〇〇c 、加熱時間1小時之熱處理，形成厚度爲〇 . 5 μ m之P Z T γ専g旲20 8 (第1 4圖（b ))。此外，在其PZT薄膜表面之 (92) 1251536 期望部位，利用網板印染，印刷4 0 // m厚度之利用化學反應實施金屬化之導電性糊之NANO PASTE ( HARIMA CHEMICALS，INC.製、商品名稱）216後，以溫度200 °C 、加熱時間1小時之條件進行烘焙，實施導電性糊之金屬化，形成第1電容器電極217之圖案（第14圖（c))。接著，形成期望圖案之抗蝕層，利用20重量％氟化氫銨 (NH4F · HF )水溶液蝕刻除去PZT薄膜，利用釕蝕刻液 REC-01 (關東化學株式會社製、商品名稱）蝕刻除去釕薄膜（第14圖（d ))。其次，進一步形成期望之鈾刻抗蝕層，以氯化鐵溶液蝕刻除去不必要之銅金屬層，形成含有第2電容器電極218之電路圖案，製成內層板219(第 1 4圖（e ))。其後，以和實施例B -1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板220 (第 14 圖（f) ) 〇實施例B - 8 在內層基板B-1之基板表面以DC濺鍍法形成〇.2 # m 之釕薄膜207 (第15圖（a))。此外，在其基板表面塗布強介電質薄膜形成材料PZT (關東化學株式會社製、商品名稱），實施溫度1 5 0 °C、加熱時間3 0分鐘之預烘焙。再重複實施5次塗布及預烘焙，其後，實施溫度2 5 〇它、加熱時間1小時之熱處理，形成厚度爲0.5 // m之PZT 薄膜208(第15圖（b))。接著，形成期望圖案之抗蝕層，利用20重量％氟化氫銨（NH4F · HF )水溶液蝕刻除 -97- (93) 1251536 去PZT薄膜208、利用釕蝕刻液REC-01 (關東化學株式會社製、商品名稱）蝕刻除去釕薄膜，實施PZT薄膜之圖案化（第15圖（c ))。在其PZT薄膜表面以DC濺鑛法形成0 · 0 5 // m之鉻薄膜2 0 9。此外，在其表面利用電性銅電鍍形成20//m之金屬層210(第15圖（d))。在該基板表面形成期望之蝕刻抗飩層，使用氯化鐵水溶液_虫刻 _去不必要之銅金屬層，利用鐵氰化鉀水溶液蝕刻除去鉻金屬層蝕刻除去，形成第1電容器電極217、第2電容器電極2 1 8、及其他配線圖案，製成內層板2 1 9 (第1 5圖（〇 )。其後，以和實施例B - 1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板220 (第1 5圖比較例B -1 在內層基板B-1之基板表面以DC濺鍍法形成0.2//m 之釕薄膜207 (第16圖（a))。形成期望圖案之抗蝕層，以RIE法鈾刻除去釕薄膜2 0 7，其後，使用氯化鐵水溶液蝕刻除去內層基板表面之銅金屬層，形成含有第2電容器電極218之電路圖案（第16圖（b))。此外，在其基板表面塗布強介電質薄膜形成材料PZT (關東化學株式會社製、商品名稱），實施溫度1 5 (TC、加熱時間3 0分鐘之預烘焙。再重複實施5次塗布及預烘焙，其後，實施溫度25 0 °C、加熱時間1小時之熱處理，形成厚度爲0.5m 之PZT薄膜208(第16圖（c))。此外，在其ρζτ薄膜 -98- (94) 1251536 表面以D C濺鍍法形成〇 · 〇 5 // m之鉻薄膜2 Ο 9。此外，在其表面利用電性銅電鍍形成20//m之金屬層210(第16 圖（d ))。在該基板表面形成期望之蝕刻抗蝕層，使用氯化鐵水溶液蝕刻除去不必要之銅金屬層，利用鐵氰化鉀水溶液蝕刻除去鉻金屬層蝕刻除去，形成第1電容器電極 217之圖案，製成內層板219(第16圖（e))。其後，以和實施例B - 1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板220(第16圖（f))。針對以上所得到之內設電容器之多層配線板實施介電質之膜厚、電容率、及電容器容量之試驗。試驗方法和上述相同。檢測結果如表2所示。表2 電容率膜厚（// m ) 電容器容量（nF) 最小値最大値平均値最小値最大値平均値實施例 B-1 60 0.45 0.52 0.48 0.9 1.1 1.0 B-2 60 0.45 0.52 0.48 0.9 1.1 1.0 _B-3 60 0.45 0.52 0.48 0.9 1.1 1.0 B-4 80 0.48 0.51 0.50 1.2 1.4 1.3 B-5 80 0.48 0.51 0.50 1.2 1.4 1.3 B-6 80 0.48 0.51 0.50 1.2 1.4 1.3 B-7 80 0.48 0.51 0.50 1.2 1.4 1.3 B-8 80 0.48 0.51 0.50 1.2 1.4 1.3 比較例B-1 80 0.33 0.67 0.50 1.0 2.0 1.3 (95) 1251536 實施例B -1〜B - 8皆採用在基板內部具有用體層間之通孔且具有表面平滑之金屬層之基板表容率爲10〜2000且膜厚爲〇·〇5〜2// m之介電質式所製成之內設電容器之基板。製成之電容器容皆低於± 1 0 %，可製成均一且良好之電容器。又，比較例B -1因係在實施金屬層圖案化之形成介電質薄膜之內設電容器之基板’膜厚誤差果，電容器容量之誤差亦爲最大之54%。依據上述實施例，可提供內設膜厚均一、電小之電容器之內設電容器之多層配線板。 (實驗例C ) 內設電容器之多層配線板用材料C - 1 在厚度爲35/zm之壓延銅箔M-BNH-18(三業株式會社製、商品名稱）1 02之表面以DC濺 0.2//m之釕薄膜103。此外，在其表面塗布強介形成材料PZT (關東化學株式會製、商品名稱）度1 5 〇 °C、加熱時間3 0分鐘之預烘焙。再重複; 塗布及預烘焙，其後，實施溫度3 5 0。(：、加熱時之熱處理，形成厚度爲0.5 // m之P Z T薄膜1 0 ] 可製成在銅箔2(金屬箔）102之單面上利用釕配設PZT薄膜1〇1 (介電質薄膜）之內設電容器線板用材料C - 1 (參照第1圖）。以此方式得到膜之電容率爲100。以連結導面形成電薄膜之方量之誤差基板表面較大，結容誤差較井金屬鑛鍍法形成電質薄膜，實施溫實施5次間1小時 .。如此，薄膜103 之多層配之PZT薄 -100- 1251536 (96) 內設電容器之多層配線板用材料C-2 在厚度爲35//m之壓延銅箔M-BNH-18(三井金屬鑛秦株式會社製、商品名稱）1 0 2之表面以D C濺鍍法形成〇·2// m之釘薄膜103。此外，在其表面以採用四異丙氧基鈦、四第三丁氧基锆、二-三甲基乙醯甲烷鉛錯合物、以及二氧化氮之微波電漿C V D，在基材溫度爲3 5 0 °C之條件下’形成厚度爲〇. 5 // m之P Z T (锆鈦酸鉛）薄膜101，得到內設電容器之多層配線板用材料C-2。以此方式得到之PZT薄膜之電容率爲70。薄膜蝕刻劑1 混合乙烯二胺四醋酸•二鈉鹽（EDTA.2Na)、過氧化氫（H2〇2)、以及水，製成具有EDTA· 2Na 0.1mol/l 、H2〇2 30wt%之成分之pH4.0之水溶液。A multilayer wiring board with a built-in capacitor was obtained in the same procedure as that of the actual B-1 except that the inner substrate B-1 was replaced with the inner substrate B-3. Example B-4 〇. 2 // m film 207 was formed on the surface of the substrate of the inner substrate B-1 by d C sputtering (Fig. 12(a)). Further, a dielectric film forming material PZT (manufactured by Kanto Chemical Co., Ltd.) was applied to the surface of the substrate, and pre-baking -94-(90) 1251536 was carried out at a temperature of 15,000 and a heating time of 3 minutes. The coating and prebaking were repeated five times, and thereafter, heat treatment was carried out at a temperature of 250 ° C and a heating time of 1 hour to form a PZT film 208 having a thickness of 0.5 / z m (Fig. 12 (b)). Thereafter, the capacitor was processed and the multilayer wiring board was processed in the same manner as in Example B-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 12(g)). Example B-5 The etching removal method of the PZT film 208 and the ruthenium film 207 was not performed by the RIE method, but was performed by etching a pZT film with a 20% aqueous solution of ammonium hydrogen fluoride (NH4F·HF), and using a ruthenium etching solution for the ruthenium film. -0 1 (manufactured by Kanto Chemical Co., Ltd., product name) was etched, and the remaining steps were the same as in Example B-4, and a multilayer wiring board with a built-in capacitor was formed (Fig. 12 (g)). Example B - 6 On the surface of the substrate of the inner substrate B_1, a film of 〇.2 // πι was formed by DC sputtering to form a film 2 0 7 (Fig. 13 (a)). In addition, a ferroelectric thin film forming material ρ ΖΊΓ (manufactured by Kanto Chemical Co., Ltd., trade name) was applied to the surface of the substrate, and prebaking was carried out at a temperature of 5 〇 t and a heating time of 3 〇. The coating and prebaking were repeated five times, and thereafter, heat treatment was carried out at a temperature of 25 ° C and a heating time of 1 hour to form a PZT thin g 208 (Fig. 13 (b)) having a thickness of 〇·5 "❿. In addition, on the surface of the PZT film, a chromium film 2〇9 from m is formed by DC sputtering. In addition, after cleaning the surface and attaching the catalyst to promote adhesion, electroless copper plating is performed. 95-(91) 1251536 0.5//m copper film. A desired plating resist 2 15 is formed on the surface of the substrate, and copper plating is performed to form a metal having a thickness of 20/m as the first capacitor electrode. Layer 2 1 4 (Fig. 3 (c)). After peeling off the plating resist 2 1 5 , etching removes the surface of the substrate. 5 / m of copper film and 0 · 〇 5 / m of chromium film, A pattern of the first capacitor electrode 217 is formed (Fig. 13(d)). Next, an anti-uranium layer of a desired pattern is formed, and an aqueous solution of 20% by weight of hydrogen fluoride (NH4F·HF) is used to remove the PZT film 2 08. The tantalum film 207 is removed by etching with a ruthenium etching solution REC - 0 1 (trade name, manufactured by Kanto Chemical Co., Ltd.) (Fig. 13 (e)). It is desirable to etch the resist layer and etch away the unnecessary copper metal layer by the ferric chloride solution to form a circuit pattern including the second capacitor electrode 218 to form the inner layer plate 2 1 9 (Fig. 13 (f)). Thereafter, the multilayer wiring board was processed in the same manner as in the example b-1 to obtain a multilayer wiring board 220 having a built-in capacitor (Fig. 13 (g)). Example B - 7 In the inner substrate B-1 The surface of the substrate is formed by a DC sputtering method to form a film of 205 (Fig. 14 (a)). The surface of the substrate is coated with a ferroelectric thin film forming material (manufactured by Kanto Chemical Co., Ltd., trade name) The prebaking was carried out at a temperature of 15 ° C and a heating time of 30 minutes. The coating and prebaking were repeated five times, and then a heat treatment at a temperature of 25 〇〇c and a heating time of 1 hour was carried out to form a thickness of 5. 5 μ m of PZT γ専g旲20 8 (Fig. 14 (b)). In addition, on the surface of the PZT film (92) 1251536, the desired part is printed by screen printing and printed with a thickness of 40 // m NANO PASTE (manufactured by HARIMA CHEMICALS, INC., a metallized conductive paste by chemical reaction) After the product name 216, the film was baked at a temperature of 200 ° C and a heating time of 1 hour, and the conductive paste was metallized to form a pattern of the first capacitor electrode 217 (Fig. 14 (c)). In the pattern of the resist layer, the PZT film is removed by etching with a 20% by weight aqueous solution of ammonium hydrogen fluoride (NH 4 F · HF ), and the tantalum film is removed by etching with a ruthenium etching solution REC-01 (manufactured by Kanto Chemical Co., Ltd.) (Fig. 14 (d) )). Next, a desired uranium resist layer is further formed, and an unnecessary copper metal layer is removed by etching with a ferric chloride solution to form a circuit pattern including the second capacitor electrode 218, thereby forming an inner layer plate 219 (Fig. 14 (e )). Thereafter, the multilayer wiring board was processed in the same manner as in Example B-1 to obtain a multilayer wiring board 220 having a built-in capacitor (Fig. 14 (f)). Example B-8 In the inner substrate B-1 The surface of the substrate is formed by DC sputtering to form a film 207 of #2 #m (Fig. 15(a)). Further, a surface of the substrate was coated with a ferroelectric thin film forming material PZT (manufactured by Kanto Chemical Co., Ltd., trade name), and prebaked at a temperature of 150 ° C and a heating time of 30 minutes. The coating and prebaking were repeated five times, and thereafter, heat treatment was carried out at a temperature of 2 5 Torr and a heating time of 1 hour to form a PZT film 208 having a thickness of 0.5 // m (Fig. 15(b)). Then, a resist layer of a desired pattern was formed, and a PZT film 208 was removed by using a 20% by weight aqueous solution of ammonium hydrogen fluoride (NH 4 F · HF ) to remove the PZT film 208, and a ruthenium etching solution REC-01 (manufactured by Kanto Chemical Co., Ltd., The product name is etched to remove the tantalum film, and the PZT film is patterned (Fig. 15(c)). A chromium film of 0·05/m is formed on the surface of the PZT film by DC sputtering. Further, a metal layer 210 of 20 / / m was formed by electroplating on the surface thereof (Fig. 15 (d)). Forming a desired etch-resistant ruthenium layer on the surface of the substrate, using an aqueous solution of ferric chloride, removing the unnecessary copper metal layer, etching and removing the chrome metal layer by using an aqueous solution of potassium ferricyanide to form a first capacitor electrode 217, The second capacitor electrode 2 18 and other wiring patterns are formed into the inner layer plate 2 1 9 (Fig. 15 (〇). Thereafter, the processing of the multilayer wiring board is performed in the same procedure as in the embodiment B-1. A multilayer wiring board 220 having a built-in capacitor was obtained (Fig. 15 Comparative Example B-1) A ruthenium film 207 of 0.2/m was formed by DC sputtering on the surface of the substrate of the inner substrate B-1 (Fig. 16(a) The resist layer forming the desired pattern is uranium-etched by the RIE method to remove the tantalum film 20, and thereafter, the copper metal layer on the surface of the inner substrate is removed by etching with an aqueous solution of ferric chloride to form a circuit including the second capacitor electrode 218. Pattern (Fig. 16(b)). The surface of the substrate was coated with a ferroelectric thin film forming material PZT (manufactured by Kanto Chemical Co., Ltd., trade name), and a temperature of 15 (TC, heating time of 30 minutes) was carried out. Baking. Repeat 5 times of coating and pre-baking, after which, A heat treatment at a temperature of 25 ° C and a heating time of 1 hour was carried out to form a PZT film 208 having a thickness of 0.5 m (Fig. 16 (c)). Further, DC sputtering was performed on the surface of the ρ ζτ film -98-(94) 1251536. The method forms a //· 〇5 // m chrome film 2 Ο 9. In addition, a 20/m metal layer 210 is formed on the surface by electrical copper plating (Fig. 16(d)). The desired surface is formed on the substrate. The resist layer is etched, an unnecessary copper metal layer is removed by etching with an aqueous solution of ferric chloride, and the chromium metal layer is removed by etching with a potassium ferricyanide aqueous solution to remove the pattern, thereby forming a pattern of the first capacitor electrode 217, thereby forming an inner layer plate 219 ( Fig. 16(e)). Thereafter, the multilayer wiring board was processed in the same manner as in the example B-1 to obtain a multilayer wiring board 220 having a built-in capacitor (Fig. 16(f)). The multilayer wiring board with capacitors is tested for dielectric thickness, permittivity, and capacitor capacity. The test method is the same as above. The test results are shown in Table 2. Table 2 Capacitance film thickness (// m ) Capacitor Capacity (nF) Minimum 値 Maximum 値 Average 値 Minimum 値 Maximum 値Average 値 Example B-1 60 0.45 0.52 0.48 0.9 1.1 1.0 B-2 60 0.45 0.52 0.48 0.9 1.1 1.0 _B-3 60 0.45 0.52 0.48 0.9 1.1 1.0 B-4 80 0.48 0.51 0.50 1.2 1.4 1.3 B-5 80 0.48 0.51 0.50 1.2 1.4 1.3 B-6 80 0.48 0.51 0.50 1.2 1.4 1.3 B-7 80 0.48 0.51 0.50 1.2 1.4 1.3 B-8 80 0.48 0.51 0.50 1.2 1.4 1.3 Comparative Example B-1 80 0.33 0.67 0.50 1.0 2.0 1.3 (95) 1251536 Embodiments B-1 to B-8 each have a substrate having a metal layer having a through-hole between the body layers and having a smooth surface, and having a surface area of 10 to 2000 and a film thickness of 〇·〇5 to 2//m. A substrate of a capacitor built into the dielectric type. The fabricated capacitors are all less than ± 10%, making a uniform and good capacitor. Further, in Comparative Example B-1, the film thickness error of the substrate in which the capacitor was formed in the formation of the metal layer was patterned, and the error in the capacitor capacity was also 54%. According to the above embodiment, it is possible to provide a multilayer wiring board in which a capacitor having a uniform film thickness and a small capacitance is provided. (Experimental Example C) Material C - 1 for multilayer wiring board in which a capacitor is provided. On the surface of a rolled copper foil M-BNH-18 (manufactured by Sanyo Co., Ltd.) 102 having a thickness of 35/zm, DC sputtering is 0.2. /m between the film 103. Further, pre-baking was carried out on the surface thereof with a PZT (manufactured by Kanto Chemical Co., Ltd., trade name) at a temperature of 15 ° C and a heating time of 30 minutes. Repeated; coating and prebaking, after which the temperature was carried out at 350 °. (:, heat treatment during heating, forming a PZT film having a thickness of 0.5 // m 10] can be made on a single side of a copper foil 2 (metal foil) 102 by using a Z PZT film 1 〇 1 (dielectric In the film), the material for the capacitor wire plate C-1 is used (refer to Fig. 1). The permittivity of the film obtained in this way is 100. The error of the amount of the film formed by the connection of the guide surface is large, and the surface of the substrate is large. The error is compared with the well metallization plating method to form an electric film, and the temperature is carried out for 5 times for 1 hour. Thus, the multilayer of the film 103 is provided with a PZT thin-100-1226536 (96) material for the multilayer wiring board of the capacitor C- 2 A nail film 103 of 〇·2//m was formed by DC sputtering on the surface of a rolled copper foil M-BNH-18 (manufactured by Mitsui Metals, Inc., manufactured by Mitsui Chemicals, Inc.) of the thickness of 35/m. In addition, on the surface thereof, microwave plasma CVD using titanium tetraisopropoxide, tetra-tertiary zirconium zirconate, bis-trimethylethyl hydrazine methane lead complex, and nitrogen dioxide at the substrate temperature A film of PZT (lead zirconate titanate) 101 having a thickness of 〇. 5 // m was formed under the condition of 3 50 ° C, and a built-in capacitor was obtained. Material C-2 for layer wiring board. The PZT film obtained in this way has a permittivity of 70. Thin film etchant 1 mixed with ethylene diamine tetraacetic acid • disodium salt (EDTA. 2Na), hydrogen peroxide (H 2 〇 2) And water, an aqueous solution of pH 4.0 having a composition of EDTA·2Na 0.1 mol/l and H 2 〇 2 30 wt% was prepared.

薄膜蝕刻劑2 混合 imino diacetic acid(IDA) 、H2O2、以及水’ 製成具有IDA 0.1mol/l、H2〇2 30wt°/〇之成分之ρΗ2·0之水溶液。薄膜蝕刻劑3 混合乙烯二胺四醋酸•二鈉鹽（EDTA · 2Na )、 H202、以及水，製成具有 EDTA· 2Na 0.01mol/l、H2〇2 l〇wt%之成分之pH4.2之水溶液。 -101 - (97) 1251536 薄膜蝕刻劑4 混合磷酸、H2〇2、以及水，製成含有磷酸30wt%、 H202 20wt%之成分之水溶液。薄膜蝕刻劑5 混合硫酸、H2〇2、以及水，製成含有硫酸5wt%、 H202 1 Owt%之成分之水溶液。實驗例C-1 在內設電容器之多層配線板用材料c _ i之銅箔表面，實施利用有機酸系微蝕刻劑CZ-8l〇〇B ( Mec CO.，LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理。第 17圖中’銅箱係303，釘薄膜係302，PZT薄膜係301。在該銅箔3 0 3之表面利用當做絶緣樹脂基材3 〇 4 (絶緣材料）使用之厚度爲100//Π1之玻璃環氧半固化片GEA-6 7 9F (日立化成工業株式會社製、商品名稱）配設厚度爲 18// m 之銅范 5GTS-18 ( FURUKAWA CIRCUIT FOIL CO·， LTD·製、商品名稱）305，在溫度i7〇°c、壓力1.5MPa、加熱加壓時間60分鐘之冲壓條件下實施積層一體化，得到基板（參照第17圖（a))。此外，在其ρζτ薄膜301 表面以DC濺鍍法形成〇.〇5//m之鉻膜306。其次，在該基板之銅范305表面層疊乾薄膜抗飽層h-9030 (日立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗鈾層。其次， -102- 1251536 (98) 使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望之部位形成0 0.1mm之窗孔3 07，利用氫氧化鈉水溶液剝離抗蝕層（參照第2圖（b ))。接著，在窗孔3 07之部位利用三菱電機株式會社製ML5 0 5 GT型碳酸氣體雷射在輸出功率2 6mJ、脈衝寬度100 // s、冲程數4次之條件下實施雷射鑽孔3 0 8 (參照第1 7圖（c ))。其後，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並附與觸媒、促進密合後，實施無電解銅電鍍，在基板表面形成0.5//m之銅薄膜。此外，在該基板表面實施銅電鍍，形成由用以電性連結內層之電路導體及基板表面之導體層之電鍍銅309所構成之金屬層（參照第17圖（d))。接著，在該基板之表面層疊膜厚爲30//m之乾薄膜抗蝕層H-9030 (日立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗蝕層。此外，利用氯化鐵水溶液蝕刻除去不必要之電鍍銅3 0 9後，利用氫氧化鈉水溶液剝離抗蝕層，利用鐵氰化鉀水溶液鈾刻除去鉻膜306，形成第1電容器電極（金屬層）310之圖案（參照第1 8圖（a ))。其次，在該基板之第1電容器電極 3 1 〇側層疊當做蝕刻抗蝕層3 1 1使用之膜厚爲4 0 # m之乾薄膜抗蝕層H-9040 (日立化成工業株式會社製、商品名稱）（參照第18圖（b))，實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，在第1電容器電極3 1 0上形成蝕刻抗蝕層3 11 (參照第1 8圖（c ))。接著，利用薄膜蝕刻劑（1 )在20°C下蝕刻除去PZT薄膜301，利用釕蝕 -103- 1251536 (99) 刻液REC-01(關東化學株式會社製、商品名去釕薄膜3 02 (參照第1 8圖（d ))，利用氫液剝離鈾刻抗蝕層3 1 1 (參照第1 8圖（e )) 層疊乾薄膜抗鈾層H-9040 (日立化成工業株商品名稱），實施期望之負圖案之曝光並以碳實施顯像，形成蝕刻抗蝕層。接著，利用氯化刻除去不必要之銅箔3 03，蝕刻除去不必要之其上之電鍍銅3 09後，利用氫氧化鈉水溶液剝形成含有由銅箱303形成之第2電容器電極3 案，製成電路板（參照第1 9圖（a ))。在該電路板之電路表面，實施利用有機酸 CZ-8100B (MEC CO.，LTD.製、商品名稱）之當做多層化黏結前處理。依據（1 )附3 5 // m 厚度爲3//m之銅箔MT35S3(三井金屬鑛業、商品名稱）、（2)厚度爲100//m之含塡半固化片 GEA-6 79F (日立化成工業株式會社稱）、（3)電路板、（4)厚度爲100//m之環氧半固化片GEA-679F、以及（5 )附35 // 之厚度爲3/zm之銅箔MT35S3(三井金屬鑛製、商品名稱）之順序，在溫度1 7 〇 °C、壓力熱加壓時間6 0分鐘之冲壓條件下實施積層一路板之兩面上利用絶緣樹脂基材3 1 3實施銅箔。剝離載體銅箔並切除不必要之基板端部後圖（b ))，在該基板之表面層疊乾薄膜抗鈾^ 稱）蝕刻除 :氧化鈉水溶。在該基板式會社製、酸鈉水溶液鐵水溶液蝕銅箔3 0 5及離抗鈾層， 1 2之電路圖系微蝕刻劑粗化處理，載體銅箔之株式會社製料玻璃環氧製、商品名含塡料玻璃 m載體銅范業株式會社 1 .5MPa、加體化，在電 314之積層 (參照第1 9 i H-9030 ( -104- (100) 1251536 曰立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗鈾層。其次，利用氯化鐵水溶液蝕刻除去不必要之銅箔3 1 4，在期望部位形成0 0 . 1 5 m m之窗孔。在配設於該電路板表面之窗孔之部位上，利用三菱電機株式會社製ML 5 0 5 GT型碳酸氣體雷射，以輸出功率 2 6 m J、脈衝寬度1 0 0 // s、冲程數4次之條件實施雷射鑽孔3 1 0 (參照第1 9圖（c ))。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並實施洗淨、附與觸媒、促進密合後，實施無電解銅電鍍，在雷射孔內壁及銅箔表面形成約 2 0 // m之無電解電鍍銅3 1 5之層。在該電路板表面之焊接點及電路圖案等必要部位利用乾薄膜抗蝕層H-903 0 (日立化成工業株式會社製、商品名稱）形成蝕刻抗蝕層，蝕刻除去不必要之銅，形成由銅箔3 1 4及電鍍銅3 1 5形成之外層電路（參照第1 9圖（d ))。在該電路板表面以滾筒塗布器塗布30//m之防焊漆 PSR-4000 AUS5 ( TAIYO INK MFG. CO.，LTD.製•商品名稱），乾燥後，實施曝光、顯像，在期望之部位形成防焊漆層3 1 6。其後，在外層電路圖案露出部表面層形成3 //m之無電解鎳電鍍、及之無電解金電鍍（Ni/Au 電鍍3 1 7 )，得到內設電容器之多層配線板（參照第1 9 圖（e ))。實驗例C-2 -105- (101) 1251536 除了將內設電容器之多層配線板用材料C - 1換成內設電容器之多層配線板用材料c -2以外，以和實驗例C - 1相同之步驟得到內設電容器之多層配線板。實驗例C-3 除了將薄膜蝕刻劑（1 )換成薄膜蝕刻劑（2 )以外，以和實驗例C - 1相同之步驟得到內設電容器之多層配線板〇實驗例C-4 除了將薄膜蝕刻劑（1 )換成薄膜蝕刻劑（3 )、及 3 〇°C以外，以和實驗例C-1相同之步驟得到內設電容器之多層配線板。實驗例C - 5 除了將薄膜蝕刻劑（1 )換成薄膜蝕刻劑（4 )以外，以和實驗例C- 1相同之步驟得到內設電容器之多層配線板實驗例C - 6 除了將薄膜鈾刻劑（1 )換成薄膜蝕刻劑（5 )以外，以和實驗例C - 1相同之步驟得到內設電容器之多層配線板 -106- (102) 1251536 實驗例C - 7 在內設電容器之多層配線板用材料C-1之銅箔303表面，實施利用有機酸系微蝕刻劑C Z - 8 1 0 0 B ( Μ E C C Ο .， L T D ·製、商品名稱）之粗化處理，當做多層化黏結前處理。在該銅箔3 0 3表面利用當做絶緣樹脂基材3 〇4 (絶緣材料）使用之厚度爲1 0 0 μ m之玻璃環氧半固化片G E A -6 7 9F (日立化成工業株式會社製、商品名稱）配設厚度爲 1 8 // m 之銅箔 5GTS-1 8 ( FURUKAWA CIRCUIT FOIL CO.， LTD.製、商品名稱），在溫度1 70°C、壓力1 .5MPa、加熱加壓時間60分鐘之冲壓條件下實施積層一體化，得到基板（參照第1 7圖（a ))。此外，在其P Z T薄膜3 01 表面以D C濺鍍法形成〇 . 〇 5 // m之鉻膜3 0 6。其次，在該基板之銅箔3 0 5表面層疊乾薄膜抗蝕層H-903 0 (日立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗蝕層。其次，使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望之部位形成0 0 · 1 mm之窗孔3 0 7 (參照第1 7圖（b ))，利用氫氧化鈉水溶液剝離抗蝕層。接著，在窗孔3 0 7之部位利用三菱電機株式會社製ML5 05 GT型碳酸氣體雷射，以輸出功率26mJ、脈衝寬度1 〇〇 # s、冲程數4次之條件實施雷射鑽孔3 0 8 (參照第1 7圖（c ))。其後，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並附與觸媒、促進密合後，實施無電解銅電鍍，在基板之兩面形成0.5//m之銅薄膜。此外，在該基板表面實施銅電鍍，形成用以電性連結 -107- (103) 1251536 內層之電路導體、及基板表面之導體層之電鍍銅309所構成之金屬層（參照第1 7圖（d ))。接著’在該基板之表面層疊乾薄膜抗鈾層H-9030(日立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗鈾層。此外，利用氯化鐵水溶液蝕刻除去不必要之電鍍銅3 0 9後，利用氫氧化鈉水溶液剝離抗蝕層，利用鐵氰化鉀水溶液蝕刻除去鉻膜3 06 ’形成第1電容器電極310之圖案（參照第18圖（a))。其次，在該基板之第1電容器電極3 1 0側塗布20 // m當做蝕刻抗蝕層311使用之鹼性顯像型抗蝕層PER-20(TAIYO INK MFG. CO·，LTD.製、商品名稱）（參照第1 8圖（b ) )，實施1 0 、1 5分鐘之預烘焙後，實施期望之負圖案之曝光，實施130°C、30分鐘之乾燥，利用碳酸鈉水溶液實施顯像，在第1電容器電極3 1 0上形成鈾刻抗蝕層3 1 1 (參照第1 8圖（c ))。接著，利用薄膜蝕刻劑（1 )在 2 0°C下蝕刻除去PZT薄膜301，利用釕蝕刻液REC-01 ( 關東化學株式會社製、商品名稱）蝕刻除去釕薄膜3 0 2 ( 參照第1 8圖（d ))，利用氫氧化鈉水溶液剝離蝕刻抗蝕層3 1 1 (參照第1 8圖（e ))。在該基板層疊乾薄膜抗蝕層H-9〇4〇 (日立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗蝕層。接著，利用氯化鐵水溶液蝕刻除去不必要之銅箔3 0 3，蝕刻除去不必要之銅箔3 0 5及其上之電鍍銅 3 0 9後，利用氫氧化鈉水溶液剝離蝕刻抗蝕層，形成含有 -108- (104) 1251536 由銅箔303形成之第2電容器電極312之電路圖案之電路板（參照第19圖（a ))。利用該電路板，以和實驗例C -1相同之步驟實施多層化，得到內設電容器之多層配線板。實驗例C-8 在內設電容器之多層配線板用材料C-1之銅箔3 0 3表面，實施利用有機酸系微蝕刻劑 CZ-8100B ( MEC CO.， LTD.製、商品名稱）之粗化處理，當做多層化黏結前處理。在該銅箔3 03表面利用當做絶緣樹脂基材3 04使用之厚度爲ΙΟΟμπι之玻璃環氧半固化片GEA-679F(日立化成工業株式會社製、商品名稱）配設厚度爲18//m之銅 fg 5GTS-18 ( FURUKAWA CIRCUIT FOIL CO.? LTD.製、商品名稱），在溫度17〇°C、壓力1.5MPa、加熱加壓時間 60分鐘之冲壓條件下實施積層一體化，得到基板（參照第17圖（a))。此外，在其PZT薄膜301表面以DC濺鍍法形成〇 . 〇 5 // m之鉻膜3 0 6。其次，在該基板之銅箔 305表面層疊乾薄膜抗蝕層H-9030 (日立化成工業株式會社製、商品名稱）’實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗蝕層。其次，使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望之部位形成0 0.1mm 之窗孔3 0 7，利用氫氧化鈉水溶液剝離抗蝕層（第1 7圖 (B )參照）。接著’在窗孔3 07之部位利用三菱電機株式會社製ML5 0 5 GT型碳酸氣體雷射，以輸出功率26mJ、 -109- (105) 1251536 脈衝寬度1 0 0 s、冲程數4次之條件實施雷射孔3 0 8 (參照第1 7圖（c ))。其後，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並附與觸媒、促進密合後，實施無電解銅電鍍，在基板之兩面形成0.5 " m之銅薄膜。The film etchant 2 was mixed with imino diacetic acid (IDA), H2O2, and water to prepare an aqueous solution of ρΗ2·0 having a composition of IDA of 0.1 mol/l and H2〇2 of 30 wt%/〇. The film etchant 3 is mixed with ethylene diamine tetraacetic acid • disodium salt (EDTA · 2Na ), H202, and water to prepare a pH 4.2 having a composition of EDTA·2Na 0.01 mol/l and H 2 〇 2 l〇wt%. Aqueous solution. -101 - (97) 1251536 Thin film etchant 4 A phosphoric acid solution, H2 ruthenium 2, and water were mixed to prepare an aqueous solution containing 30% by weight of phosphoric acid and 20% by weight of H202. The film etchant 5 was mixed with sulfuric acid, H 2 〇 2, and water to prepare an aqueous solution containing a component of sulfuric acid of 5 wt% and H202 1 wt%. In the case of the copper foil of the material c _ i of the multilayer wiring board in which the capacitor is provided, the organic acid-based microetching agent CZ-8l〇〇B (manufactured by Mec Co., Ltd., trade name) is used. Roughening treatment, as a multi-layer pre-bonding treatment. In Fig. 17, the copper box system 303, the nail film system 302, and the PZT film system 301. A glass epoxy prepreg GEA-6 7 9F (manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100//Π1 used as the insulating resin substrate 3 〇4 (insulating material) is used as the surface of the copper foil 305. ) A copper vane 5GTS-18 (manufactured by FURUKAWA CIRCUIT FOIL CO., LTD., trade name) 305 having a thickness of 18/m is provided, and the stamping is performed at a temperature of i7〇°c, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. The laminate was integrated under the conditions to obtain a substrate (see Fig. 17 (a)). Further, a chromium film 306 of 〇.5//m was formed on the surface of the ρζτ film 301 by DC sputtering. Next, a dry film anti-saturated layer h-9030 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on the surface of the copper 305 of the substrate, and exposure to a desired negative pattern was carried out, and development was carried out with an aqueous solution of sodium carbonate to form an etching resistance. Uranium layer. Next, -102- 1251536 (98) Etching unnecessary copper foil with an aqueous solution of ferric chloride, forming a window hole of 0 0.1 mm at a desired portion, and peeling off the resist layer with an aqueous solution of sodium hydroxide (refer to Fig. 2) (b)). Then, the laser drilling of the ML5 0 5 GT type carbonic acid gas laser manufactured by Mitsubishi Electric Corporation was carried out at a portion of the window hole 3 07 under the conditions of an output of 26 mJ, a pulse width of 100 // s, and a stroke number of 4 times. 0 8 (Refer to Figure 17 (c)). Thereafter, the carbonized resin residue was removed by ultrasonic cleaning and an alkali permanganic acid solution, and the catalyst was adhered to promote adhesion. Electroless copper plating was performed to form a copper film of 0.5/m on the surface of the substrate. Further, copper plating is applied to the surface of the substrate to form a metal layer composed of electroplated copper 309 for electrically connecting the inner layer of the circuit conductor and the conductor layer on the surface of the substrate (see Fig. 17 (d)). Then, a dry film resist H-9030 (manufactured by Hitachi Chemical Co., Ltd., trade name) having a film thickness of 30/m was laminated on the surface of the substrate, and a desired negative pattern was exposed and exposed to a sodium carbonate aqueous solution. Like, an etch resist is formed. Further, after the unnecessary electroplating copper is removed by etching with an aqueous solution of ferric chloride, the resist layer is removed by an aqueous solution of sodium hydroxide, and the chromium film 306 is removed by uranium ferric chloride aqueous solution to form a first capacitor electrode (metal layer). ) 310 pattern (refer to Figure 18 (a)). Then, a dry film resist layer H-9040 having a thickness of 40 # m used as the etching resist layer 31 is laminated on the first capacitor electrode 3 1 side of the substrate (manufactured by Hitachi Chemical Co., Ltd., a product) (Refer to Fig. 18(b)), performing exposure of a desired negative pattern and developing with a sodium carbonate aqueous solution, and forming an etching resist layer 3 11 on the first capacitor electrode 3 1 0 (refer to Fig. 18) (c)). Then, the PZT film 301 was removed by etching at 20 ° C using a film etchant (1), and the etched -103 - 1251536 (99) etch liquid REC-01 (manufactured by Kanto Chemical Co., Ltd., trade name 钌钌 film 3 02 ( Referring to Fig. 18(d)), the uranium engraved resist layer 3 1 1 is removed by hydrogen liquid (refer to Fig. 18 (e)), and the dry film anti-uranium layer H-9040 (product name of Hitachi Chemical Industry Co., Ltd.) is laminated. Exposure of a desired negative pattern is performed and development is performed by carbon to form an etching resist layer. Then, unnecessary copper foil 303 is removed by chlorination, and unnecessary electroplating copper 3 09 is removed by etching, and then utilized. The sodium hydroxide aqueous solution was peeled off to form a second capacitor electrode 3 formed of a copper box 303, and a circuit board was formed (see Fig. 19 (a)). On the circuit surface of the circuit board, an organic acid CZ-8100B was used. (MEC CO., LTD., product name) as a multi-layer pre-bonding treatment. According to (1) attached 3 5 // m thickness of 3 / / copper foil MT35S3 (Mitsui Metal Mining, trade name), ( 2) 塡-containing prepreg with a thickness of 100/m, GEA-6 79F (called by Hitachi Chemical Co., Ltd.), (3) Circuit The order of the board, (4) epoxy prepreg GEA-679F with a thickness of 100/m, and (5) the thickness of 3/zm copper foil MT35S3 (made by Mitsui Metals, trade name) The copper foil is formed by the insulating resin substrate 3 1 3 on both sides of the laminated one-way board under the conditions of a temperature of 1 7 〇 ° C and a pressure hot pressing time of 60 minutes. The carrier copper foil is peeled off and the unnecessary substrate end is cut off. Figure (b)), the surface of the substrate is laminated with a dry film anti-uranium) etching: sodium oxide is water soluble. In the substrate type, the sodium carbonate aqueous solution of the sodium carbonate solution, the aluminum foil, and the anti-uranium layer, the circuit diagram of the micro-etching agent is roughened, and the carrier copper foil is made of glass epoxy, and the product is made of塡塡玻璃 m m m m 1 1 1 1 1 1 1 1 1 1 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( The product name) is exposed to a desired negative pattern and developed with an aqueous solution of sodium carbonate to form an etch-resistant uranium layer. Next, the unnecessary copper foil 3 1 4 is removed by etching with an aqueous solution of ferric chloride to form 0 0 at the desired portion. . 1 5 mm window hole. The ML 5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation is used for the output of the power of 2 6 m J and the pulse width at the window of the surface of the board. 1 0 0 // s, the number of strokes is 4 times, laser drilling 3 1 0 (refer to Figure 19 (c)). Ultrasonic cleaning and alkali permanganic acid solution remove carbonized resin residue and implement After washing, attaching to the catalyst, and promoting adhesion, electroless copper plating is performed. The inner wall of the perforation and the surface of the copper foil form a layer of electroless copper plating 3 1 5 of about 20 // m. The dry film resist H-903 0 is used for the necessary parts such as solder joints and circuit patterns on the surface of the board. (The product name, manufactured by Hitachi Chemical Co., Ltd.) forms an etching resist layer, removes unnecessary copper by etching, and forms an external layer circuit formed of copper foil 3 1 4 and electroplated copper 3 1 5 (refer to Fig. 19 (d) Apply a 30/m solder resist PSR-4000 AUS5 (trade name, manufactured by TAIYO INK MFG. CO., LTD.) to the surface of the board with a roller coater. After drying, expose and develop the image. The desired portion forms a solder resist layer 3 16 . Thereafter, an electroless nickel plating of 3 // m is formed on the surface layer of the exposed portion of the outer layer circuit pattern, and electroless gold plating (Ni/Au plating 3 17) is performed. A multilayer wiring board with a built-in capacitor is obtained (refer to Fig. 19 (e)). Experimental Example C-2 - 105- (101) 1251536 In addition to replacing the multilayer wiring board with built-in capacitors with material C-1 into a built-in capacitor In the same procedure as in Experimental Example C-1 except for the material c-2 of the multilayer wiring board, the number of built-in capacitors was obtained. Wiring plate. Experimental Example C-3 A multilayer wiring board with a built-in capacitor was obtained in the same manner as in Experimental Example C-1 except that the film etchant (1) was replaced with a film etchant (2). Experimental Example C-4 A multilayer wiring board with a built-in capacitor was obtained in the same manner as in Experimental Example C-1, except that the film etchant (1) was replaced with a film etchant (3) and 3 〇 °C. Experimental Example C - 5 A multilayer wiring board with a built-in capacitor was obtained in the same manner as in Experimental Example C-1 except that the film etchant (1) was replaced with a film etchant (4). The engraving agent (1) was replaced with a film etchant (5), and a multilayer wiring board with a built-in capacitor was obtained in the same manner as in Experimental Example C-1 - 106-(102) 1251536 Experimental Example C-7 The surface of the copper foil 303 of the material C-1 for the multilayer wiring board is subjected to roughening treatment using an organic acid-based microetching agent CZ-8 1 0 0 B (manufactured by Μ ECC Ο., LTD.) Pre-bonding treatment. A glass epoxy prepreg GEA -6 7 9F (available from Hitachi Chemical Co., Ltd.) having a thickness of 100 μm as the insulating resin substrate 3 〇 4 (insulating material) is used as the surface of the copper foil 300. ) A copper foil 5GTS-1 8 (manufactured by FURUKAWA CIRCUIT FOIL CO., LTD.) having a thickness of 1 8 // m is placed at a temperature of 1 70 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. The laminate is integrated under the stamping conditions to obtain a substrate (see Fig. 17 (a)). Further, on the surface of the P Z T film 3 01, a chromium film of 〇 5 // m is formed by DC sputtering. Then, a dry film resist layer H-903 0 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on the surface of the copper foil 305 of the substrate, and exposure to a desired negative pattern was carried out, and development was carried out with an aqueous solution of sodium carbonate. An etch resist layer is formed. Next, an unnecessary copper foil is removed by etching with an aqueous solution of ferric chloride, and a window hole of 0 0 · 1 mm is formed at a desired portion (see Fig. 17 (b)), and the resist is removed by an aqueous solution of sodium hydroxide. Floor. Then, a ML5 05 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used in the window hole 3, and the laser drilling was performed under the conditions of an output of 26 mJ, a pulse width of 1 〇〇# s, and a stroke number of 4 times. 0 8 (Refer to Figure 17 (c)). Thereafter, the carbonized resin residue was removed by ultrasonic cleaning and alkali permanganic acid solution, and the catalyst was adhered to promote adhesion. Electroless copper plating was performed to form a 0.5/m copper film on both surfaces of the substrate. Further, copper plating is performed on the surface of the substrate to form a metal layer composed of a copper conductor 309 for electrically connecting the circuit conductor of the inner layer of -107-(103) 1251536 and the conductor layer of the surface of the substrate (refer to FIG. (d)). Then, a dry film anti-uranium layer H-9030 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on the surface of the substrate, and exposure to a desired negative pattern was carried out, and development was carried out with a sodium carbonate aqueous solution to form an etch-resistant uranium layer. Further, after the unnecessary electroplating copper is removed by etching with an aqueous solution of ferric chloride, the resist layer is removed by an aqueous solution of sodium hydroxide, and the chromium film 306 is removed by etching with a potassium ferricyanide aqueous solution to form a pattern of the first capacitor electrode 310. (Refer to Figure 18 (a)). Next, an alkaline development type resist layer PER-20 (manufactured by TAIYO INK MFG. CO., LTD.), which is used as an etching resist layer 311, is applied to the first capacitor electrode 3 1 0 side of the substrate. Product name) (Refer to Fig. 18(b)), after pre-baking for 10 minutes and 15 minutes, exposure to a desired negative pattern, drying at 130 ° C for 30 minutes, and implementation with sodium carbonate aqueous solution For example, an uranium resist layer 3 1 1 is formed on the first capacitor electrode 3 10 (refer to Fig. 18 (c)). Then, the PZT thin film 301 is removed by etching at a temperature of 20 ° C by a thin film etchant (1), and the tantalum film 3 0 2 is removed by etching with a ruthenium etching solution REC-01 (manufactured by Kanto Chemical Co., Ltd.). (d)), the etching resist layer 3 1 1 is peeled off by an aqueous sodium hydroxide solution (refer to Fig. 18 (e)). A dry film resist layer H-9〇4〇 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the substrate, and exposure to a desired negative pattern was carried out, and development was carried out with an aqueous solution of sodium carbonate to form an etching resist layer. Next, the unnecessary copper foil 305 is removed by etching with an aqueous solution of ferric chloride, and the unnecessary copper foil 305 and the electroplated copper 309 thereon are removed by etching, and then the etching resist is peeled off by an aqueous solution of sodium hydroxide. A circuit board including a circuit pattern of -108-(104) 1251536 second capacitor electrode 312 formed of copper foil 303 is formed (see Fig. 19(a)). Using this circuit board, multilayering was carried out in the same manner as in Experimental Example C-1 to obtain a multilayer wiring board in which a capacitor was built. Experimental Example C-8 The organic acid-based microetching agent CZ-8100B (trade name, manufactured by MEC CO., LTD.) was used for the surface of the copper foil 300 of the material C-1 for the multilayer wiring board in which the capacitor was placed. Roughening treatment, as a multi-layer pre-bonding treatment. On the surface of the copper foil 303, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of ΙΟΟμπι, which is used as the insulating resin substrate 306, is provided with a copper fg having a thickness of 18/m. 5GTS-18 (manufactured by FURUKAWA CIRCUIT FOIL CO.? LTD., trade name), laminated at a temperature of 17 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to obtain a substrate (see page 17) Figure (a)). Further, on the surface of the PZT film 301, a chrome film of // 5 // m was formed by DC sputtering. Then, a dry film resist layer H-9030 (manufactured by Hitachi Chemical Co., Ltd., trade name) was placed on the surface of the copper foil 305 of the substrate to perform exposure of a desired negative pattern, and development was carried out with an aqueous solution of sodium carbonate to form an etching resistance. Eclipse layer. Next, an unnecessary copper foil was removed by etching with a ferric chloride aqueous solution, and a window hole of 0 0.1 mm was formed in a desired portion, and the resist layer was peeled off by an aqueous sodium hydroxide solution (refer to Fig. 7 (B)). Then, the ML5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used in the window hole 3 07 to produce a power of 26 mJ, -109- (105) 1251536, a pulse width of 100 s, and a stroke number of four times. Implement the laser hole 3 0 8 (refer to Figure 17 (c)). Thereafter, the carbonized resin slag was removed by ultrasonic cleaning and alkali permanganic acid solution, and the catalyst was added to promote adhesion. Electroless copper plating was performed to form a 0.5 " m copper film on both sides of the substrate.

此外，在該基板表面實施銅電鍍，形成由用以電性連結內層之電路導體及基板表面之導體層之電鍍銅3 0 9所構成之金屬層（參照第17圖（d))。接著，在該基板之表面層疊乾薄膜抗蝕層H-903 0 (日立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗蝕層。此外，利用氯化鐵水溶液鈾刻除去不必要之電鍍銅3 09後，利用氫氧化鈉水溶液剝離抗蝕層，利用鐵氰化鉀水溶液蝕刻除去鉻膜3 06，形成第1電容器電極3 1 0之圖案（參照第1 8圖（a ))。其次，在該基板之第1電容器電極3 1 0側塗布1 2 // m之當做蝕刻抗蝕層 3 1 1使用之溶劑顯像型抗蝕層 AZ 9245 ( CLAIANT JAPAN K · K ·製、商品名稱）（參照第1 8圖（b ))，實施η 〇 °c、1 〇分鐘之預烘焙後實施期望之負圖案之曝光並實施 120 °c 、10分鐘之乾燥，以 AZ400K DEVELOPER ( CLAIANT JAPAN K.K.製、商品名稱）進行顯像，形成蝕刻抗蝕層3 1 1 (參照第1 8圖（c )第1 8圖 (c ))。接著，利用20%氟化氫銨（NH4F · HF )水溶液在20°C鈾刻除去PZT薄膜301，利用釕鈾刻液REC-01 ( 關東化學株式會社製、商品名稱）蝕刻除去釕薄膜3 02 ( 參照第 3圖之（d ))，利用 AZ REMOVER-700 ( -110- 1251536 (106) CLAIANT JAPAN K. K.製、商品名稱）剝離蝕刻抗蝕層 3 1 1 (參照第1 8圖（e ))。在該基板層疊乾薄膜抗蝕層 Η - 9 0 4 0 (日立化成工業株式會社製、商品名稱），實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗蝕層。接著，利用氯化鐵水溶液蝕刻除去不必要之銅箔 3 03，蝕刻除去不必要之銅箔3 0 5及其上之電鍍銅3 09後，利用氫氧化鈉水溶液剝離抗蝕層，形成具有由銅箔303 形成之第2電容器電極312之電路圖案，製成電路板（參照第1 9圖（a ))。在該電路板之電路表面，實施利用有機酸系微蝕刻劑 CZ-8100B (MEC CO·，LTD.製、商品名稱）之粗化處理，當做多層化黏結前處理。依據（1 )附3 5 // m載體銅箔之厚度爲3//m之銅箔MT35S3(三井金屬鑛業株式會社製、商品名稱）、（2 )厚度爲1 00 // m之含塡料玻璃環氧半固化片 GEA-67 9F (日立化成工業株式會社製、商品名稱）、（3 )電路板、（4 )厚度爲1 0 0 // m之含塡料玻璃環氧半固化片GEA-6 79F、以及（5 )附35 // m載體銅箔之厚度爲3//m之銅箔MT35S3(三拝金屬鑛業株式會社製、商品名稱）之順序，在溫度17〇t：、壓力1 .5MPa、加熱加壓時間6 0分鐘之冲壓條件下實施積層一體化，在電路板之兩面上利用絶緣樹脂基材3 1 3實施銅箔3 1 4之積層。剥離載體銅箔並切除不必要之基板端部後（參照第19 圖（b ))，在該基板之表面層疊乾薄膜抗蝕層H-903 0 ( 日立化成工業株式會社製、商品名稱），實施期望之負圖 -111 - (107) 1251536 案之曝光並以碳酸鈉水溶液實施顯像，形成触刻抗蝕層。其次，利用氯化鐵水溶液蝕刻除去不必要之銅箔3 1 4，在期望部位形成0 〇 . 1 5 m m之窗孔。在配設於該電路板表面之窗孔之部位上，利用三菱電機株式會社製ML 5 0 5 GT型碳酸氣體雷射，以輸出功率 2 6 m J、脈衝寬度1 0 0 // s、冲程數4次之條件實施雷射鑽孔（參照第1 9圖（c ))。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並洗淨、附與觸媒、促進密合後，實施無電解銅電鍍，在雷射孔內壁及銅箔表面形成約20 // m之無電解銅電鍍層。在該電路板表面之焊接點及電路圖案等必要部位利用乾薄膜抗蝕層H-903 0 (日立化成工業株式會社製、商品名稱）形成蝕刻抗蝕層，蝕刻除去不必要之銅，形成由銅箔3 1 4及電鍍銅3 1 5形成之外層電路（參照第19圖（d))。在該電路板表面以滾筒塗布器塗布30 "m 防焊漆 PSR-4000 AUS5 ( TAIYO INK MFG. CO·， LTD.製、商品名稱），乾燥後，實施曝光、顯像，在期望之部位形成防焊漆層3 1 6。其後，在外層電路圖案露出部表面層形成3 // m之無電解鎳電鍍及0.1 // m之無電解金電鍍（Ni/Au電鎪17 )，得到內設電容器之多層配線板 (參照第1 9圖（e ))。實驗例C-9 在內設電容器之多層配線板用材料C-1之銅箔3 03表面，實施利用有機酸系微蝕刻劑CZ-8100B ( MEC CO., -112· (108) 1251536 LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理。在該銅箔3 0 3表面利用當做絶緣樹脂基材3 04使用之厚度爲1〇〇 V m之玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱）配設厚度爲1 8 // m之銅箔 5GTS- 1 8 ( FURUKAWA CIRCUIT FOIL C0.5 LTD.製、商品名稱），在溫度17〇°C、壓力1.5MPa、加熱加壓時間 60分鐘之冲壓條件下實施積層一體化，得到基板（參照第17圖（a))。此外，在其PZT薄膜301表面以DC濺鑛法形成〇 · 〇 5 // m之鉻膜3 0 6。其次，在該基板之銅箔 305表面層疊乾薄膜抗蝕層H-9030 (日立化成工業株式會社製、商品名稱）’實施期望之負圖案之曝光並以碳酸鈉水溶液實施顯像，形成蝕刻抗蝕層。其次，使用氯化鐵水溶液鈾刻除去不必要之銅箔，在期望之部位形成0 0.1mm 之窗孔3 07，利用氫氧化鈉水溶液剝離抗鈾層（第1 7圖 (B )參照）。接著，在窗孔3 07之部位利用三菱電機株式會社製ML 5 05 GT型碳酸氣體雷射，以輸出功率26m J、脈衝寬度1〇〇 // s、冲程數4次之條件實施雷射孔3 0 8 (第 1 7圖（c )參照）。其後，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並附與觸媒、促進密合後，實施無電解銅電鍍，在基板之兩面形成〇.5//m之銅薄膜。此外，在該基板表面實施銅電鍍，形成由用以電性連結內層之電路導體及基板表面之導體層連結電鍍銅3 09所構成之金屬層（參照第1 7圖（d ))。接著，在該基板之表面層疊乾薄膜抗蝕層H-903 0 (日立化成工業株式會社 -113- (109) 1251536 製、商品名稱），實施期望之負圖案之曝光並溶液實施顯像，形成鈾刻抗蝕層。此外，利用液蝕刻除去不必要之電鍍銅3 09後，利用氫氧剝離抗蝕層，利用鐵氰化鉀水溶液蝕刻除去鉻成第1電容器電極310之圖案（參照第18圖次，在該基板之第1電容器電極3 1 0側塗布做蝕刻抗蝕層3 11使用之溶劑顯像型抗蝕層 CLAIANT JAPAN K „ K .製、商品名稱）（參照 ))，實施1 1 〇 °C、1 0分鐘之預烘焙後實施期之曝光並實施 120 °c、10分鐘之乾燥， DEVELOPER ( CLAIANT JAPAN K.K.製、商品顯像，形成抗鈾層3 1 1 (參照第1 8圖（c )) 利用CF4氣體之RIE法，蝕刻除去PZT薄膜膜3 02後（參照第18圖（d ))，利用 AZ 700 ( CLAIANT JAPAN Κ·Κ·製、商品名稱）蝕層3 1 1 (參照第1 8圖（e ))。在該基板層蝕層H-9 (MO (日立化成工業株式會社製、商實施期望之負圖案之曝光並以碳酸鈉水溶液實成鈾刻抗蝕層。接著，利用氯化鐵水溶液蝕刻之銅箔3 03，蝕刻除去不必要之銅箔3 0 5及其 3 09後，利用氫氧化鈉水溶液剝離抗蝕層，形箔3 03形成之第2電容器電極312之電路圖案板（參照第1 9圖（a ))。採用該電路板，其後以和實驗例C-8相同以碳酸鈉水氯化鐵水溶化鈉水溶液膜306 ，形 (a))。其 1 2 // m 之當 -AZ9245 ( 第1 8圖（b 望之負圖案以 AZ400K 名稱）進行。接著，以 3 0 1及釕薄 REMOVER-剝離蝕刻抗疊乾薄膜抗品名稱），施顯像，形除去不必要上之電鍍銅成含有由銅 ’製成電路之步驟得到 -114- (110) 1251536 內設電容器之多層配線板（參照第1 9圖（e ))。實驗例c - 1〜C - 7時，任何基板在薄膜之鈾刻時皆未發現鈾刻殘渣或抗蝕層之剝離等，圖案化性十分良好。其次，檢測電容器容量。電容器容量係使用以5 0Ω同軸纜線 SUC0FLEX 1 04/ 1 00 ( SUHNER公司製、商品名稱）連結於阻抗分析儀 4291B (AGILENT TECHNOLOGIES 製、商品名稱）之高頻信號檢測探針 MICROPROBE ACP50 ( GSG25 0型、Cascade公司製、商品名稱）之檢測系統。電容器之電極尺寸爲1mm□，檢測1 GHz之電容。結果如表3所示。表3 抗蝕層類型蝕刻劑電容器容量（nF) 最小値最大値平均値 C-1 乾薄膜薄膜蝕刻液（1) 1.5 1.7 1.6 C-2 乾薄膜薄膜触刻液（1) 1.1 1.2 1.1 C-3 乾薄膜薄膜蝕刻液(2) 1.5 1.7 1.6 實 04 乾薄膜薄膜蝕刻液(3) 1.5 1.7 1.6 驗 C-5 乾薄膜薄膜蝕刻液(4) 1.5 1.7 1.6 例 C-6 乾薄膜薄膜蝕刻液(5) 1.5 1.7 1.6 C-7 液狀、鹼性顯像薄膜蝕刻液(1) 1.5 1.7 1.6 C-8 液狀、溶劑顯像 20%氟化氫銨 1.5 1.7 1.6 C-9 液狀、溶劑顯像 CF4氣體 1.5 1.7 1.6 -115- (111) !251536 如表3所示，實驗例C -1〜C - 7所製成之內設電之多層配線板之電容器容量誤差皆低於± 1 0%，可製一且良好之電容器。係和實驗例C - 8〜C - 9相當之誤可知，利用實驗例C - 1〜C - 7亦可得到和實驗例c - 8，相同精度之內設電容器之多層配線。然而，傳統之 CF4氣體之RIE法（實驗例C-9 )、及20%氟化氫 NH4F · HF )水溶液（實驗例C_8 )等則會不同，如所述，因係使用鹼性顯像型之抗蝕層之濕蝕刻法，而易應用於傳統之印刷配線板之步驟，具有良好作業性濟效益。 (實施例D ) 內設電容器之多層配線板用材料D-1 在厚度爲18//m之壓延銅箔M-BNH-18(三井金業株式會社製、商品名稱）之表面，以採用四異丙氧、四第三丁氧基銷、二-三甲基乙醯甲烷鉛錯合物、二氧化氮之微波電漿CVD，在基材溫度爲3 5 0 °C之條，形成厚度爲0.5 // m之PZT (锆鈦酸鉛）薄膜。如可得到在銅箔1 0 2 (金屬箔A )之單面配設著p z T 1 〇 1 (介電質薄膜）之內設電容器之多層配線板用材 1 (第 1 圖（a))。內設電容器之多層配線板用材料EK2 在厚度爲18//m之壓延銅箔M-BNH-18(ミ井^ 容器成均差， ^ C-9 採用銨（前面很容及經屬鑛基鈦以及件下此，薄膜屬鑛 -116- 1251536 (112) 業株式會社製、商品名稱）之表面以D C濺鍍法形成〇. 2 // m之釕薄膜。此外，在其基板表面上以使用四異丙氧基鈦、四第三丁氧基鉻、二-三甲基乙醯甲烷鉛錯合物、以及二氧化氮之微波電漿CV D，在基材溫度爲3 5 (TC之條件下’形成厚度爲0.5 // m之p Z T (銷駄酸錯）薄膜。如此，可得到在銅箔1 02 (金屬箔A )之單面利用釕薄膜1 〇3 配設PZT薄膜101 (介電質薄膜）之內設電容器之多層配線板用材料D - 2 (第1圖（b ))。內設電容器之多層配線板用材料D-3 在厚度爲18//m之壓延銅箔M-BNH-18(三井金屬鑛業株式會社製、商品名稱）之表面以D C濺鍍法形成〇 . 2 // m之釕薄膜。此外，在其表面塗布強介電質薄膜形成材料PZT (關東化學株式會製、商品名稱），實施溫度15〇 C、加熱時間3 0分鐘之預烘焙。再重複實施5次塗布及預烘焙，其後，實施溫度3 5 (TC、加熱時間1小時之熱處理，形成厚度爲〇·5 // m之PZT薄膜。如此，可得到在銅箔1〇2 (金屬箔A)之單面利用釕薄膜103配設PZT薄膜 1 〇 1 (介電質薄膜）之內設電容器之多層配線板用材料（3 )(第 1 圖（b))。實施例D-1 在內設電容器之多層配線板用材料D -1之銅箔4 0 2 ( 金屬箔 A )之表面，實施利用有機酸系微蝕刻劑 CZ- -117- (113) 1251536Further, copper plating is applied to the surface of the substrate to form a metal layer composed of a plated copper 309 for electrically connecting the circuit conductor of the inner layer and the conductor layer on the surface of the substrate (see Fig. 17 (d)). Then, a dry film resist layer H-903 0 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on the surface of the substrate, and exposure to a desired negative pattern was carried out, and development was carried out with an aqueous solution of sodium carbonate to form an etching resist layer. . Further, after the unnecessary electroplating copper is removed by uranium chloride aqueous solution, the resist layer is removed by an aqueous solution of sodium hydroxide, and the chromium film is removed by etching with a potassium ferricyanide aqueous solution to form a first capacitor electrode 3 1 0. The pattern (see Figure 18 (a)). Next, a solvent-developing resist layer AZ 9245 (available as CLAIANT JAPAN K K) manufactured by the etch resist layer 3 1 1 is applied to the first capacitor electrode 3 1 0 side of the substrate. Name) (Refer to Figure 18 (b)), perform pre-baking at η 〇 °c, 1 〇 minutes, perform exposure of the desired negative pattern, and perform drying at 120 ° C for 10 minutes to AZ400K DEVELOPER ( CLAIANT JAPAN The KK system and the product name are developed to form an etching resist layer 31 (refer to Fig. 18 (c), Fig. 18 (c)). Then, the PZT thin film 301 was removed by uranium engraving at 20 ° C in an aqueous solution of 20% ammonium hydrogen fluoride (NH 4 F · HF ), and the tantalum film 3 02 was removed by etching with uranium uranium engraving REC-01 (manufactured by Kanto Chemical Co., Ltd.). In (d) of Fig. 3, the etching resist layer 31 1 is peeled off by AZ REMOVER-700 (trade name: manufactured by -110- 1251536 (106) CLAIANT JAPAN KK) (refer to Fig. 18 (e)). A dry film resist layer 9-900 (manufactured by Hitachi Chemical Co., Ltd., trade name) was laminated on the substrate, and exposure to a negative pattern was carried out, and development was carried out with an aqueous solution of sodium carbonate to form an etching resist layer. Next, the unnecessary copper foil 303 is removed by etching with an aqueous solution of ferric chloride, and the unnecessary copper foil 305 and the electroplated copper 309 thereon are removed by etching, and then the resist layer is peeled off by an aqueous solution of sodium hydroxide to form The circuit pattern of the second capacitor electrode 312 formed by the copper foil 303 is formed into a circuit board (see Fig. 19 (a)). A roughening treatment using an organic acid-based microetching agent CZ-8100B (trade name, manufactured by MEC CO., LTD.) is carried out on the surface of the circuit board, and the multilayer pre-bonding treatment is performed. (1) Copper foil MT35S3 (manufactured by Mitsui Mining & Mining Co., Ltd., product name) having a thickness of 3/m, with a thickness of 3 / / m, and (2) a material containing 100 Å / m of thickness Glass epoxy prepreg GEA-67 9F (manufactured by Hitachi Chemical Co., Ltd., trade name), (3) circuit board, (4) glass epoxy epoxy prepreg GEA-6 79F with a thickness of 100 μm And (5) a copper foil MT35S3 (manufactured by Sanken Metal Mining Co., Ltd., product name) having a thickness of 3 / / m of 35 / m carrier copper foil, at a temperature of 17 〇 t:, a pressure of 1.5 MPa, Lamination integration was carried out under the press conditions of 60 minutes of heating and pressurization, and the laminate of the copper foils 314 was performed on both surfaces of the board by the insulating resin substrate 3 1 3 . After the carrier copper foil is peeled off and the unnecessary substrate end portion is cut out (see FIG. 19(b)), a dry film resist layer H-903 0 (manufactured by Hitachi Chemical Co., Ltd., trade name) is laminated on the surface of the substrate. The desired negative image - 111 - (107) 1251536 was exposed and developed with an aqueous solution of sodium carbonate to form a etched resist layer. Next, the unnecessary copper foil 3 1 4 was removed by etching with an aqueous solution of ferric chloride to form a window of 0 〇 . 15 m m at a desired portion. A ML 5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used at a portion of a window hole provided on the surface of the board to have an output of 2 6 m J and a pulse width of 1 0 0 // s. Laser drilling is carried out under conditions of four times (see Figure 19 (c)). After removing the carbonized resin residue by ultrasonic cleaning and alkali permanganic acid solution, washing, attaching the catalyst, and promoting adhesion, electroless copper plating is performed to form about 20 / 2 on the inner wall of the laser hole and the surface of the copper foil. / m of electroless copper plating. A dry resist layer H-903 0 (manufactured by Hitachi Chemical Co., Ltd., trade name) is used to form an etching resist layer on the surface of the board, such as solder joints and circuit patterns, and unnecessary copper is removed by etching. The copper foil 3 1 4 and the electroplated copper 3 1 5 form an outer layer circuit (refer to Fig. 19 (d)). Apply 30 "m solder resist PSR-4000 AUS5 (made by TAIYO INK MFG. CO., LTD., trade name) to the surface of the board with a roller coater, and then perform exposure and development on the desired part. A solder resist layer 3 16 is formed. Thereafter, an electroless nickel plating of 3 // m and an electroless gold plating (Ni/Au electric 17) of 0.1 // m were formed on the surface layer of the exposed portion of the outer layer pattern to obtain a multilayer wiring board with a built-in capacitor (refer to Figure 19 (e)). Experimental Example C-9 The surface of the copper foil 303 of the material C-1 for the multilayer wiring board in which the capacitor was provided was subjected to an organic acid-based microetching agent CZ-8100B (MEC CO., -112· (108) 1251536 LTD· The roughening of the system and the name of the product is treated as a multi-layer bonding pre-treatment. On the surface of the copper foil 303, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd., trade name) having a thickness of 1 〇〇V m used as the insulating resin substrate 304 is disposed to have a thickness of 18 // m copper foil 5GTS- 1 8 (manufactured by FURUKAWA CIRCUIT FOIL C0.5 LTD., product name), laminated at a temperature of 17 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. The substrate was obtained (see Fig. 17 (a)). Further, on the surface of the PZT thin film 301, a chromium film of 〇 · 〇 5 / m was formed by DC sputtering. Then, a dry film resist layer H-9030 (manufactured by Hitachi Chemical Co., Ltd., trade name) was placed on the surface of the copper foil 305 of the substrate to perform exposure of a desired negative pattern, and development was carried out with an aqueous solution of sodium carbonate to form an etching resistance. Eclipse layer. Next, an unnecessary copper foil was removed by uranium chloride aqueous solution, and a window hole of 0 0.1 mm was formed at a desired portion, and the anti-uranium layer was peeled off by an aqueous sodium hydroxide solution (refer to Fig. 17 (B)). Then, the ML 5 05 GT-type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used in the window hole 3 07, and the laser hole was applied under the conditions of an output of 26 mJ, a pulse width of 1 〇〇//s, and a stroke number of four times. 3 0 8 (Refer to Figure 7 (c)). Thereafter, the carbonized resin slag is removed by ultrasonic cleaning and alkali permanganic acid solution, and the catalyst is added to promote adhesion, and then electroless copper plating is performed to form a copper film of 〇.5//m on both sides of the substrate. . Further, copper plating is applied to the surface of the substrate to form a metal layer composed of a plating conductor for electrically connecting the inner conductor and the conductor layer of the substrate (see Fig. 17 (d)). Then, a dry film resist layer H-903 0 (manufactured by Hitachi Chemical Co., Ltd. - 113-(109) 1251536, trade name) is laminated on the surface of the substrate, and exposure to a desired negative pattern is carried out to develop a solution to form a solution. Uranium engraved resist. Further, after the unnecessary electroplating copper is removed by liquid etching, the resist layer is removed by hydrogen and oxygen, and the pattern of the first capacitor electrode 310 is removed by etching with a potassium ferricyanide aqueous solution (refer to Fig. 18, on the substrate). The first capacitor electrode 3 1 0 side is coated with the solvent-etching resist layer CLAIANT JAPAN K „ K., product name (see)) used to etch the resist layer 3 11 , and 1 1 〇 ° C, 1 Exposure after 0 minutes of pre-baking and drying at 120 °c for 10 minutes, DEVELOPER (made by CLAIANT JAPAN KK, commercial imaging, forming anti-uranium layer 3 1 1 (refer to Figure 18 (c)) RIE method of CF4 gas, after etching and removing PZT thin film 308 (refer to Fig. 18 (d)), etch layer 3 1 1 by AZ 700 (made by CLAIANT JAPAN Κ·Κ, product name) (refer to Fig. 18) (e)) The substrate etching layer H-9 (MO (manufactured by Hitachi Chemical Co., Ltd., the manufacturer performs a desired negative pattern exposure and forms an uranium engraved resist layer with an aqueous solution of sodium carbonate. Next, using chlorination Copper aqueous solution etched copper foil 03, etched to remove unnecessary copper foil 3 0 5 and its 3 09 The resist pattern is removed by a sodium hydroxide aqueous solution, and the circuit pattern plate of the second capacitor electrode 312 formed by the shaped foil 303 is formed (refer to Fig. 19 (a)). This circuit board is used, and the experimental example C-8 is used. The sodium hydride aqueous solution film 306 is dissolved in the same manner with sodium carbonate water, and the shape is (a)). The 1 2 // m is -AZ9245 (Fig. 18 (the negative pattern of the desired pattern is AZ400K name). Then, In the case of the 3 0 1 and thin REMOVER-peel etching anti-stack film resistance, the image is removed, and the unnecessary electroplating copper is removed to obtain the circuit made of copper '-114- (110) 1251536 A multilayer wiring board with a capacitor built therein (refer to Fig. 19 (e)). In the case of the experimental example c - 1 to C - 7, no uranium residue or peeling of the resist layer was observed in any of the substrates during uranium engraving of the film. The patterning property is very good. Secondly, the capacity of the capacitor is measured. The capacitor capacity is connected to the impedance analyzer 4291B (the product name of AGILENT TECHNOLOGIES, using the 50 Ω coaxial cable SUC0FLEX 1 04/ 1 00 (product name, manufactured by SUHNER). ) high frequency signal detection probe MICROPROBE Detection system for ACP50 (GSG25 0, manufactured by Cascade, trade name) The capacitor has an electrode size of 1 mm□ and detects a capacitance of 1 GHz. The results are shown in Table 3. Table 3: Resist layer type etchant capacitor capacity (nF) minimum 値 maximum 値 average 値 C-1 dry film film etchant (1) 1.5 1.7 1.6 C-2 dry film film etchant (1) 1.1 1.2 1.1 C- 3 dry film film etching solution (2) 1.5 1.7 1.6 real 04 dry film film etching solution (3) 1.5 1.7 1.6 test C-5 dry film film etching solution (4) 1.5 1.7 1.6 case C-6 dry film film etching solution ( 5) 1.5 1.7 1.6 C-7 liquid and alkaline imaging film etching solution (1) 1.5 1.7 1.6 C-8 liquid, solvent imaging 20% ammonium hydrogen fluoride 1.5 1.7 1.6 C-9 liquid, solvent imaging CF4 Gas 1.5 1.7 1.6 -115- (111) !251536 As shown in Table 3, the capacitor capacity error of the built-in electric multilayer wiring board made by the experimental examples C-1 to C-7 was less than ±10%, A good and good capacitor can be made. It is also known that the experimental examples C - 8 to C - 9 are equivalent to each other. It is also known that the multilayer wiring of the capacitor having the same precision as that of the experimental example c - 8 can be obtained by the experimental examples C - 1 to C - 7. However, the conventional CF4 gas RIE method (Experimental Example C-9) and 20% hydrogen fluoride NH4F·HF aqueous solution (Experimental Example C_8) are different, as described above, because the alkaline imaging type is used. The wet etching method of the etch layer is easy to apply to the steps of the conventional printed wiring board, and has good workability. (Example D) The material D-1 for a multilayer wiring board in which a capacitor is provided is a surface of a rolled copper foil M-BNH-18 (manufactured by Mitsui Jinsei Co., Ltd., trade name) having a thickness of 18/m. Microwave plasma CVD of isopropoxy oxygen, tetra-tertiary butoxyl, di-trimethylethylmethane-methane lead complex, and nitrogen dioxide at a substrate temperature of 350 ° C to form a thickness of PZT (lead zirconate titanate) film of 0.5 // m. For example, a multilayer wiring board material 1 in which a capacitor is provided on a single side of a copper foil 1 0 2 (metal foil A) with a p z T 1 〇 1 (dielectric film) can be obtained (Fig. 1 (a)). Material EK2 for multilayer wiring board with capacitors is rolled copper foil M-BNH-18 with a thickness of 18/m (the well is poor in the case of the well, ^ ammonium is used in the C-9 (the front is very suitable for the mineral base) Titanium and the following, the surface of the film genus -116- 1251536 (112), manufactured by Kosei Co., Ltd., is formed by DC sputtering to form a film of //. 2 // m. In addition, on the surface of the substrate Using titanium tetraisopropoxide, tetra-tert-butoxy chromium, di-trimethyl ethane oxime methane lead complex, and nitrogen dioxide microwave plasma CV D at a substrate temperature of 3 5 (TC Under the condition, a pZT (pin yttrium yttrium) film having a thickness of 0.5 // m is formed. Thus, a PZT film 101 can be obtained by using a ruthenium film 1 〇 3 on one side of the copper foil 012 (metal foil A) ( Material D-2 for multilayer wiring board in which a capacitor is provided (Fig. 1(b)). Material D-3 for multilayer wiring board with capacitor built in rolled copper foil having a thickness of 18/m The surface of M-BNH-18 (manufactured by Mitsui Mining and Mining Co., Ltd., trade name) is formed by DC sputtering to form a film of //. 2 // m. In addition, a strong dielectric is coated on the surface. The film forming material PZT (manufactured by Kanto Chemical Co., Ltd., trade name) was prebaked at a temperature of 15 ° C and a heating time of 30 minutes. The coating and prebaking were repeated five times, and thereafter, the temperature was 3 5 (TC). Heat treatment at a heating time of 1 hour to form a PZT film having a thickness of 〇·5 // m. Thus, a PZT film 1 〇1 can be obtained by using a tantalum film 103 on one side of the copper foil 1〇2 (metal foil A). The material (3) (Fig. 1(b)) of the multilayer wiring board of the capacitor is provided in the (dielectric film). Example D-1 Copper foil 4 of the material D-1 of the multilayer wiring board in which the capacitor is provided 0 2 (metal foil A) surface, using organic acid microetching agent CZ--117- (113) 1251536

8 100B ( MEC CO.，LTD.製、商品名稱）之粗化處理，當做多層化黏結前處理（第2 0圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材4 0 4 (絶緣層）使用之厚度爲1 〇〇 # m之玻璃環氧半固化片GEA-679F (日立化成工業株式會社製、商品名稱）配設厚度爲12 // m之銅箔405 (金屬箔B ) GTS-12 ( FURUKAWA CIRCUIT FOIL C0.9 LTD。製、商品名稱），在溫度18(TC、壓力1.5MPa、力f]熱力口壓時間60分鐘之冲壓條件下實施積層一體化，得到基板（第2 0圖（b ))。其次，在該基板之兩面形成期望之蝕刻抗鈾層，使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望之部位形成0 0.15 mm之窗孔 405’（第 20圖（c))。接著，在窗孔 4 0 5’之部位利用三菱電機株式會社製ML5 05 GT型碳酸氣體雷射，以輸出功率26mJ、脈衝寬度100 // s、冲程數4 次之條件實施雷射照射，形成雷射孔406，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣（第20圖（d ))。此外，在其PZT薄膜401 (介電質薄膜）表面以DC濺鍍法形成0.05 // m之鉻薄膜407。其後，在基板兩面實施利用觸媒附與齊jj ( Neoganth WA、ATOTECH JAPAN (株）製、商品名稱）之附與觸媒處理、及利用密合促進劑（ NeoganthWA，ATOTECH JAPAN (株）製、商品名稱）之促進密合處理後，實施無電解銅電鍍，形成〇. 5 // m之銅薄膜，此外，在基板兩面利用電性銅電鍍形成2 0 μ m之金屬層，形成由電鍍銅408所構成之金屬層（第20圖（e -118- 1251536 (114) ))。在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去不必要之電鍍銅408，利用鐵氰化鉀水溶液蝕刻除去露出之鉻薄膜407，形成第1電容器電極409 之圖案（第20圖（f))。接著，形成期望圖案之抗蝕層 ’以利用CF4氣體之RIE法，蝕刻除去PZT薄膜401，形成電容器介電質401(第20圖（g))。其次，在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去銅箔4 0 2、銅箔4 0 5、以及電鍍銅4 0 8之不必要部份，製成形成含有第2電容器電極410之電路圖案之電路板（第 20 圖（h))。在該電路板之電路表面，實施利用有機酸系微蝕刻劑 CZ-8 100B ( MEC CO·，LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理。依據（1 )附3 5 // m載體銅箔之厚度爲3//m之銅箔MT35S3(三井金屬鑛業株式會社製、商品名稱）、（2)絶緣樹脂基材412之厚度爲100/zm 之含塡料玻璃環氧半固化片GE A-67 9F (日立化成工業株式會社製、商品名稱）、（3 )電路板、（4 )絶緣樹脂基材412之厚度爲100//m之含塡料玻璃環氧半固化片 GEA-679F以及（5)附35//m載體銅箔之厚度爲3//m之銅箔MT35S3 (三井金屬鑛業株式會社製、商品名稱）之順序，在溫度180°C、壓力1.5MPa、加熱加壓時間60分鐘之冲壓條件下實施積層一體化。剥離載體銅箔並切除不必要之基板端部後，在該基板表面形成期望之蝕刻抗蝕層，使用氯化鐵水溶液蝕刻除去不必要之銅箔，在期望部位 -119- (115) 1251536 形成0 〇 . 1 5 m m之窗孔。在配設於該基板表面之窗孔部位上，利用三菱電機株式會社製ML5 0 5 GT型碳酸氣體雷射，以輸出功率26m J、脈衝寬度1 〇〇 // s、冲程數4次之條件實施雷射鑽孔。以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣並洗淨、附與觸媒、促進密合後，實施無電解銅電鍍，在雷射孔內壁及銅箔表面形成約2 0 // m之無電解銅電鍍層。在該基板表面之焊接點及電路圖案等必要部位形成蝕刻抗蝕層，蝕刻除去不必要之銅，形成外層電路。在該基板表面以滾筒塗布器塗布30//m防焊漆？8卜 4000 AUS5 ( TAIYO INK MFG. CO.，LTD.製、商品名稱），乾燥後，實施曝光、顯像，在期望之部位形成防焊漆層 411。其後，在外層電路圖案露出部表面層形成3//m之無電解鎳電鍍、及〇. 1 # Π1之無電解金電鍍（N i - A u電鍍 420 )，得到內設電容器之多層配線板（第20圖（i )) 實施例D-2 在內設電容器之多層配線板用材料D-3之銅箔402之表面，實施利用有機酸系微蝕刻劑CZ-8100B ( MEC C0·， LTD .製、商品名稱）之粗化處理，當做多層化黏結前處理（第2 1圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之厚度爲100/zm之玻璃環氧半固化片GEA-679F(日立化 -120- (116) 1251536 成工業株式會社製、商品名稱）配設厚度爲1 2 // m之銅 m 5GTS-12 ( FURUKAWA CIRCUIT FOIL CO·，LTD.製、商品名稱），在溫度180°C、壓力1.5MPa、加熱加壓時間 6 0分鐘之冲壓條件下實施積層一體化，得到基板（第2 1 圖（b ))。其次，在該基板之兩面形成期望之飩刻抗蝕層，使用氯化鐵水溶液鈾刻除去不必要之銅箔，在期望之部位形成0 〇.15mm之窗孔405’（第21圖（c))。接著，在窗孔405’之部位利用三菱電機株式會社製ML 5 0 5 GT 型碳酸氣體雷射，以輸出功率26mJ、脈衝寬度100 // s、冲程數4次之條件實施雷射照射，形成雷射孔406，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣（第2 1圖（d ) )。此外，在其PZT薄膜401之表面以DC濺鍍法形成 0 · 0 5 // m之鉻薄膜4 0 7。其後，在基板兩面附與觸媒、促進密合後，實施無電解銅電鍍，形成0.5 // m之銅薄膜，此外，在基板兩面利用電性銅電鍍形成2 0 // m之金屬層，形成由電鍍銅408所構成之金屬層（第21圖（e))。在該基板表面形成期望之鈾刻抗鈾層，利用氯化鐵水溶液蝕刻除去電鍍銅4 0 8之不必要部份，利用鐵氰化鉀水溶液蝕刻除去露出之鉻薄膜407，形成第1電容器電極409之圖案（第21圖（f))。接著，形成期望圖案之抗蝕層，以利用C F 4氣體之RIE法，蝕刻除去P Z T薄膜4 0 1及釕薄膜403之不必要部份，形成電容器介電質401，（第21 圖（g ))。其次，在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去銅箔4 0 2、銅箔4 0 5、以及 -121 - (117) 1251536 電鍍銅408之不必要部份，製成形成含有第2電容器電極 4 1 〇之電路圖案之電路板（第2 1圖（h ))。其後，以和貫施例D - 1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第2 1圖（i ))。實施例D - 3 在內設電容器之多層配線板用材料D-2之銅箔402之表面，實施利用有機酸系微蝕刻劑C Z - 8 1 0 0 B ( Μ E C C 0 .， L T D .製、商品名稱）之粗化處理，當做多層化黏結前處理（第22圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之厚度爲100//m之玻璃環氧半固化片GEA-679F(日立化成工業株式會社製、商品名稱）配設附3 5 // m載體銅箔之厚度爲3//m之銅箔5MT3 5M3(三井金屬鑛業株式會社製、商品名稱），在溫度180°C、壓力1.5MPa、加熱加壓時間60分鐘之冲壓條件下實施積層一體化，形成基板（第2 2圖（b ))。其次’以人工作業剝離載體銅箔後，利用三菱電機株式會社製ML 5 0 5 GT型碳酸氣體雷射，在基板之銅箔405之面以輸出功率30mj、脈衝寬度15 # s、冲程數6次之條件貫施雷射鑽孔，製成0 〇 · 1 5 m m之雷射孔 4 0 6。其後，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣（第22圖（c))。此外，在其PZT薄膜401之表面以DC濺鍍法形成〇·05从m之鉻薄膜407。其後，在基板兩面附與觸媒、促進密合後，實施無電解銅電鍍，形成 -122- 1251536 (118) Ο . 5 // m之銅薄膜，此外，在基板兩面利用電性銅電鎪形成20 // m之金屬層，形成由電鍍銅40 8所構成之金屬層 (第22圖（d ))。在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去由電鍍銅408所構成之金屬層之不必要部份，利用鐵氰化鉀水溶液蝕刻除去露出之鉻薄膜407，形成第1電容器電極409之圖案（第22圖（e ))。接著，形成期望圖案之抗蝕層，利用20%氟化氫銨 (NH4F · HF )水溶液鈾刻除去ρΖΤ薄膜401之不必要部份，實施PZT薄膜之圖案化，形成電容器介電質401’（第22圖（f))。接著，利用釕蝕刻液REC-01 (關東化學株式會製、商品名稱）蝕刻除去露出之釕薄膜403 (第 22圖（g ))。其次，在該基板表面形成期望之鈾刻抗蝕層，利用氯化鐵水溶液蝕刻除去銅箔402、銅箔405、以及電鍍銅40 8之不必要部份，製成形成含有第2電容器電極410之電路圖案之電路板（第22圖（h))。其後，以和實施例D-1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第22圖（i ))。實施例D-4 在內設電容器之多層配線板用材料C - 3之銅箔4 0 2之表面，實施利用有機酸系微蝕刻劑CZ-8100B ( MEC CO.， LTD.製、商品名稱）之粗化處理，當做多層化黏結前處理（第2 3圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之 -123- (119) 12515368 100B (MEC CO., LTD., product name) roughening treatment, as a multi-layer bonding pre-treatment (Fig. 20 (a)). On the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F having a thickness of 1 〇〇# m used as the insulating resin substrate 4 0 4 (insulating layer) is used (Hitachi Chemicals Co., Ltd., product name) Copper foil 405 (metal foil B) GTS-12 (manufactured by FURUKAWA CIRCUIT FOIL C0.9 LTD., product name) with a thickness of 12 // m, at a temperature of 18 (TC, The laminate was integrated under the stamping conditions of a pressure of 1.5 MPa and a force of f] for a thermal pressure of 60 minutes to obtain a substrate (Fig. 20(b)). Next, a desired etch-resistant uranium layer was formed on both sides of the substrate, and used. The iron chloride aqueous solution is etched to remove the unnecessary copper foil, and a window hole 405' of 0 0.15 mm is formed in a desired portion (Fig. 20 (c)). Next, Mitsubishi Electric Corporation is used in the window 4 0 5' portion. ML5 05 GT type carbon dioxide gas laser, with laser output of 26mJ, pulse width 100 // s, stroke number 4 times, forming laser hole 406, ultrasonic cleaning and alkali permanganic acid solution Removing the carbonized resin residue (Fig. 20(d)). On the surface of the PZT film 401 (dielectric film), a chromium film 407 of 0.05 // m was formed by DC sputtering. Thereafter, the catalyst was attached to both sides of the substrate by a catalyst (manufactured by Neoganth WA, ATOTECH JAPAN Co., Ltd.). , and the use of the adhesion promoter ( NeoganthWA, manufactured by ATOTECH JAPAN Co., Ltd., trade name) to facilitate the adhesion treatment, and then electroless copper plating is performed to form 〇. 5 // m The copper film is further formed by electroless copper plating on both sides of the substrate to form a metal layer of 20 μm to form a metal layer composed of the plated copper 408 (Fig. 20 (e-118-1215336 (114))). A desired etching resist layer is formed on the surface of the substrate, and unnecessary plating copper 408 is removed by etching with an aqueous solution of ferric chloride, and the exposed chromium film 407 is removed by etching with an aqueous solution of potassium ferricyanide to form a pattern of the first capacitor electrode 409 (20th) (f)) Next, a resist layer forming a desired pattern is etched to remove the PZT thin film 401 by an RIE method using CF4 gas to form a capacitor dielectric 401 (Fig. 20(g)). Second, on the substrate Forming a desired etch resist on the surface, A circuit board for forming a circuit pattern including the second capacitor electrode 410 is formed by etching an unnecessary portion of the copper foil 4 0 2 , the copper foil 405, and the electroplated copper 4 0 8 with an aqueous solution of ferric chloride (Fig. 20) (h)) The surface of the circuit board is subjected to a roughening treatment using an organic acid-based microetching agent CZ-8 100B (trade name, manufactured by MEC CO., LTD.), and is subjected to multi-layer bonding pretreatment. (1) Copper foil MT35S3 (manufactured by Mitsui Mining and Mining Co., Ltd., product name) having a thickness of 3 / / m of 3 / 5 m carrier copper foil, (2) The thickness of the insulating resin substrate 412 is 100 / zm The glass-containing epoxy prepreg GE A-67 9F (manufactured by Hitachi Chemical Co., Ltd., trade name), (3) circuit board, and (4) insulating resin substrate 412 having a thickness of 100/m Glass epoxy prepreg GEA-679F and (5) copper foil MT35S3 (manufactured by Mitsui Mining & Mining Co., Ltd., product name) having a thickness of 3/m with a 35//m carrier copper foil, at a temperature of 180 ° C, The lamination integration was carried out under a stamping condition of a pressure of 1.5 MPa and a heating and pressing time of 60 minutes. After the carrier copper foil is peeled off and the unnecessary substrate end portion is cut, a desired etching resist layer is formed on the surface of the substrate, and an unnecessary copper foil is removed by etching with an aqueous solution of ferric chloride to form a desired portion -119-(115) 1251536. 0 〇. 1 5 mm window hole. In the window hole portion of the surface of the substrate, a ML5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used, and the output was 26 m J, the pulse width was 1 〇〇//s, and the number of strokes was 4 times. Perform laser drilling. After removing the carbonized resin residue by ultrasonic cleaning and alkali permanganic acid solution, washing, attaching the catalyst, and promoting adhesion, electroless copper plating is performed to form about 20 on the inner wall of the laser hole and the surface of the copper foil. // m electroless copper plating. An etching resist layer is formed on a necessary portion such as a solder joint and a circuit pattern on the surface of the substrate, and unnecessary copper is removed by etching to form an outer layer circuit. Apply 30//m solder resist to the surface of the substrate with a roller coater? 8 Bu 4000 AUS5 (manufactured by TAIYO INK MFG. CO., LTD., trade name), after drying, exposure and development are carried out to form a solder resist layer 411 at a desired portion. Thereafter, an electroless nickel plating of 3//m and an electroless gold plating (N i - A u plating 420 ) of 1. 1 # Π1 were formed on the surface layer of the exposed portion of the outer layer pattern to obtain a multilayer wiring of the built-in capacitor. Plate (Fig. 20(i)) Example D-2 The surface of the copper foil 402 of the material D-3 for the multilayer wiring board in which the capacitor is provided is subjected to an organic acid-based microetching agent CZ-8100B (MEC C0·, The roughening treatment of LTD., product name) is treated as a multi-layer bonding pre-treatment (Fig. 21 (a)). On the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F having a thickness of 100/zm used as the insulating resin substrate 404 is used (Hitachi-120-(116) 1251536 Manufactured by the company, the company name is a copper m 5GTS-12 (manufactured by FURUKAWA CIRCUIT FOIL CO., LTD., product name) having a thickness of 1 2 // m, and is heated at a temperature of 180 ° C and a pressure of 1.5 MPa. The laminate was integrated under a press condition of a press time of 60 minutes to obtain a substrate (Fig. 21 (b)). Next, a desired engraved resist layer is formed on both sides of the substrate, and an unnecessary copper foil is removed by uranium chloride aqueous solution to form a window 405' of 0 〇.15 mm at a desired portion (Fig. 21 (c )). Then, a laser beam of ML 5 0 5 GT type carbon dioxide gas manufactured by Mitsubishi Electric Corporation was used in the window hole 405', and laser irradiation was performed under the conditions of an output of 26 mJ, a pulse width of 100 // s, and a stroke number of four times. The laser hole 406 is ultrasonically washed and the alkali permanganic acid solution removes the carbonized resin residue (Fig. 21 (d)). Further, a chromium film of 0·0 5 // m was formed on the surface of the PZT thin film 401 by DC sputtering. Thereafter, after the catalyst is adhered to both surfaces of the substrate and the adhesion is promoted, electroless copper plating is performed to form a copper film of 0.5 // m, and a metal layer of 20 // m is formed by electroplating on both sides of the substrate. A metal layer composed of electroplated copper 408 is formed (Fig. 21(e)). Forming a desired uranium enriched uranium layer on the surface of the substrate, etching an unnecessary portion of the electroplated copper by etching with an aqueous solution of ferric chloride, and etching the exposed chromium film 407 by using an aqueous solution of potassium ferricyanide to form a first capacitor electrode. Pattern of 409 (Fig. 21 (f)). Next, a resist layer of a desired pattern is formed, and an unnecessary portion of the PZT thin film 401 and the germanium thin film 403 is removed by etching using a CF 4 gas RIE method to form a capacitor dielectric 401, (FIG. 21 (g) ). Next, a desired etching resist layer is formed on the surface of the substrate, and an unnecessary portion of the copper foil 406, the copper foil 405, and the -121-(117) 1251536 electroplated copper 408 is removed by etching with an aqueous solution of ferric chloride. A circuit board (Fig. 21 (h)) for forming a circuit pattern including the second capacitor electrode 4 1 。 is formed. Thereafter, the multilayer wiring board was processed in the same manner as in the example D-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 21 (i)). [Example D - 3] The surface of the copper foil 402 of the material D-2 for the multilayer wiring board in which the capacitor was provided was made of an organic acid-based microetching agent CZ-8 1 0 0 B (manufactured by ECC 0., LTD. The roughening of the product name) is treated as a multi-layered pre-bonding process (Fig. 22(a)). In the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100/m as the insulating resin substrate 404 is used. Name) Copper foil 5MT3 5M3 (manufactured by Mitsui Mining & Mining Co., Ltd.) with a thickness of 3 / / m carrier copper foil of 3 / / m, at a temperature of 180 ° C, a pressure of 1.5 MPa, heating and pressurization The laminate was integrated under a stamping condition of 60 minutes to form a substrate (Fig. 22 (b)). Next, after the carrier copper foil was peeled off by a manual operation, a ML 5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used, and an output of 30 mj, a pulse width of 15 #s, and a stroke number of 6 were obtained on the surface of the copper foil 405 of the substrate. The second condition is to apply a laser drill hole to make a 0 0 · 1 5 mm laser hole 4 0 6 . Thereafter, the carbonized resin residue is removed by ultrasonic cleaning and an alkali permanganic acid solution (Fig. 22(c)). Further, a chromium film 407 of 〇·05 from m was formed by DC sputtering on the surface of the PZT thin film 401. Thereafter, after the catalyst is adhered to both sides of the substrate and the adhesion is promoted, electroless copper plating is performed to form a copper film of -122 to 1251536 (118) Ο 5 / m, and electric copper is used on both sides of the substrate. The crucible forms a metal layer of 20 // m to form a metal layer composed of electroplated copper 40 8 (Fig. 22(d)). A desired etching resist layer is formed on the surface of the substrate, an unnecessary portion of the metal layer composed of the electroplated copper 408 is removed by etching with an aqueous solution of ferric chloride, and the exposed chromium film 407 is removed by etching with a potassium ferricyanide aqueous solution to form a first 1 Pattern of capacitor electrode 409 (Fig. 22(e)). Next, a resist layer of a desired pattern is formed, and an unnecessary portion of the ruthenium film 401 is removed by uranium etching with a 20% ammonium hydrogen fluoride (NH 4 F · HF ) solution, and patterning of the PZT film is performed to form a capacitor dielectric 401 ′ (22nd) Figure (f)). Then, the exposed tantalum film 403 is removed by etching using a ruthenium etching solution REC-01 (manufactured by Kanto Chemical Co., Ltd., trade name) (Fig. 22(g)). Next, a desired uranium resist layer is formed on the surface of the substrate, and an unnecessary portion of the copper foil 402, the copper foil 405, and the plated copper 40 is removed by etching with an aqueous solution of ferric chloride to form a second capacitor electrode 410. Circuit board of circuit pattern (Fig. 22(h)). Thereafter, the multilayer wiring board was processed in the same manner as in the example D-1 to obtain a multilayer wiring board having a built-in capacitor (Fig. 22(i)). Example D-4 The organic acid-based microetching agent CZ-8100B (trade name, manufactured by MEC CO., LTD.) was used for the surface of the copper foil 420 of the material C-3 for the multilayer wiring board in which the capacitor was provided. The roughening treatment is performed as a multi-layered pre-bonding treatment (Fig. 2 (a)). The surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided is used as the insulating resin substrate 404 -123- (119) 1251536

厚度爲100// m之玻璃環氧半固化片GEA-679F(日立化成工業株式會社製、商品名稱）配設附3 5 // m載體銅箔之厚度爲3//m之銅箔5MT35S3(三井金屬鑛業株式會社製、商品名稱），在溫度180 °C、壓力1.5 MPa、加熱加壓時間6 0分鐘之冲壓條件下實施積層一體化，形成基板（第23圖（b ))。此半固化片係利用溫度l〇〇°C、壓力 1 . 5 MP a、力Q熱力日壓時間1 〇分鐘之條件之熱壓在兩面貼附厚度爲25//m之聚對苯二甲酸乙二酯（PET)之薄膜並在期望之部位實施鑽床鑽孔後，利用網板印染充塡熱硬化性樹脂內分散著銅粉之導電性糊13AE 1 65 0 ( TATSUTA SYSTEM ELECTRONICS公司製、商品名稱），然後再剝離表面之PET薄膜者。其次，在ρζτ薄膜401之表面以 D C濺鍍法形成〇 · 〇 5 # m之鉻薄膜4 〇 7後，在基板之兩面利用電性銅電鍍形成2 0 // m之由電鍍銅4 0 8所構成之金屬層（第2 3圖（c ))。在該基板表面形成期望之蝕刻抗倉虫層’利用氯化鐵水溶液蝕刻除去由電鍍銅4 〇 8所構成之金屬層之不必要部份，利用鐵氰化鉀水溶液蝕刻除去露出之絡薄膜7’形成第1電容器電極409之圖案（第23圖 (d ))。接著’形成期望圖案之抗鈾層，利用2 0 %氟化氮錢（NHj · HF )水溶液蝕刻除去ρζτ薄膜4〇1之不必 ’貫施pZT薄膜之圖案化，形成電容器介電質 4 〇 1 (第2 3圖（e ))。接著，利用釕蝕刻液RE C - 01 ( 關東化學株式會製、商品名稱）鈾刻除去露出之釕薄膜 4〇° (第23圖（f))。其次，在該基板表面形成期望之 -124- (120) 1251536 蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去銅箔402、銅箔 4 0 5、以及電鑛銅408之不必要部份’製成形成含有弟2 電容器電極410之電路圖案之電路板（第23圖（g))。其後，以和實施例D - 1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第2 3圖（h ))。實施例D-5 除了將充塡至內設電容器之多層配線板用材料及積層之半固化片之孔之導電性糊換成利用化學反應實施金屬化之導電性糊 NANO PASTE ( HARIMA CHEMICALS, INC·製、商品名稱）以外，以和實施例D-4相同之步驟得到內設電容器之多層配線板。實施例D - 6 在內設電容器之多層配線板用材D - 3之銅箔4 0 2之表面，實施利用有機酸系微蝕刻劑 CZ-8100B ( MEC CO.， LTD.製、商品名稱）之粗化處理，當做多層化黏結前處理（第24圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之厚度爲l〇〇//m之玻璃環氧半固化片GEA-679F(日立化成工業株式會社製、商品名稱）配設附3 5 // m載體銅箔之厚度爲之銅箔5MT35S3(三井金屬鑛業株式會社製、商品名稱），在溫度180 °C、壓力1.5 MPa、加熱加壓時間60分鐘之冲壓條件下實施積層一體化，形成基板（ -125· (121) 1251536 箔倉虫窗用出射之之對 j • 05 法板厚孔第兩鉻案電利膜電刻第24圖（b))。其次，在剝離載體銅箔之基板之銅 4 0 5之表面形成期望之蝕刻抗鈾層，利用氯化鐵水溶液刻除去不必要之銅箱，在期望之部位形成0 0 . 1 5 m m之孔405’（第24圖（c ))。接著，窗孔40 5’之部位利三菱電機株式會社製ML 5 0 5 GT型碳酸氣體雷射，以輸功率26mJ、脈衝寬度1〇〇 μ s、冲程數4次之條件雷照射雷射孔406，以超音波洗淨及鹼高錳酸液除去碳化樹脂渣（第2 4圖（d ))。此外，在其Ρ Ζ Τ薄膜4 01 表面以D C濺鑛法形成〇 · 〇 5 # m之鉻薄膜4 0 7。其後，該基板兩面附與觸媒、促進密合後，實施無電解銅電鍍形成0 · 5 // m之銅薄膜1 9。利用此方式，以形成之〇 //m之鉻薄膜407及0.5//m之銅薄膜419形成半加成之基底金屬層（厚度爲0.1〜5#m之金屬層）。在該基之兩面形成期望之電鍍抗蝕層4 1 4，實施銅電鍍，形成度爲20//m之由當做含有第1電容器電極409及雷射 406之部份電路使用之電鍍銅415所構成之導體圖案（ 24圖（e ))。剝離電鍍抗蝕層4 1 4後，蝕刻除去基板面之0.5//m之銅薄膜419之不必要部份及0.05//m之薄膜407之不必要部份，形成第1電容器電極409之圖。此時，亦會實施3 // m厚之銅箔40 5之圖案化來形成路（第24圖（f))。接著，形成期望圖案之抗蝕層，用20%氟化氫銨（NH4F · HF )水溶液蝕刻除去PZT薄 401之不必要部份，實施PZT薄膜401之圖案化，形成容器介電質401，（第24圖（g))。接著，利用釕鈾 -126- (122) 1251536 液R Ε Ο Ο 1 (關東化學株式會製、商品名稱）鈾刻除去露出之釕薄膜403(第24圖（h))。其次，在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液鈾刻除去銅箔 402之不必要部份，形成含有第2電容器電極410之電路圖案之電路板（第24圖（i ))。其後，以和實施例D-1 相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第24圖（j ))。實施例D-7 在內設電容器之多層配線板用材料C-3之銅箔402之表面，實施利用有機酸系微蝕刻劑CZ-8100B(MEC CO.， LTD.製、商品名稱）之粗化處理，當做多層化黏結前處理（第2 5圖（a ))。在該內設電容器之多層配線板用材料之銅筢4 0 2之表面，利用當做絶緣樹脂基材4 0 4使用之厚度爲100//m之玻璃環氧半固化片GEA-679F(日立化成工業株式會社製、商品名稱）配設附3 5 // m載體銅箔之厚度爲3//m之銅箔5MT35M3(三井金屬鑛業株式會社製、商品名稱），在溫度1 8 0 °C、壓力1 · 5 Μ P a、加熱加壓時間6 0分鐘之冲壓條件下實施積層一體化，形成基板（第2 5圖（b ))。以人工作業剝離載體銅箔後，利用三菱電機株式會社製ML 5 0 5 GT型碳酸氣體雷射，以輸出功率 3 0m J、脈衝寬度1 5 // s、冲程數6次之條件實施雷射鑽孔，製成0 0 · 1 5 m m之雷射孔4 0 6。其後，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣（第2 5圖（c ))。此外， -127- (123) 1251536 在PZT薄膜401之表面以DC濺鍍法形成〇〇5//m之鉻薄膜4 0 7。此外，對該基板之兩面附與觸媒、促進密合後，貫施無電銅電鑛’形成〇 ♦ 5 // πι之銅薄膜4 1 9。利用此方式，以形成之〇.〇5//m之鉻薄膜407及0.5//m之銅薄膜419形成半加成法之基底金屬層（厚度爲之金屬層）。在該基板之表面形成期望之電鍍抗鈾層414，實施銅電鍍，形成厚度爲20//m之由當做含有第1電容器電極409及雷射孔406之部份電路使用之電鍍銅415所構成之導體圖案（第2 5圖（d ))。剝離電鍍抗蝕層4 1 4 後，蝕刻除去露出基板表面之0 · 5 // m之銅薄膜4 1 9及 0· 05 // m之鉻薄膜407之露出部份，形成含有第1電容器電極4 〇 9及雷射孔4 0 6之部份電路之圖案。此時，亦會實施3//m厚之銅箔405之圖案化來形成電路（第25圖（e ))。接著，形成期望圖案之抗鈾層，利用2 0 %氟化氫錢 (NH4F · HF ) 7太溶液蝕刻除去PZT薄膜401，實施PZT 薄膜401之圖案化，形成電容器介電質401’（第25圖（f ))。其後，利用釕蝕刻液REC-01 (關東化學株式會製、商品名稱）蝕刻除去釕薄膜403之露出部份（第25圖 (g ))。其次，在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去銅箔402之不必要部份，形成含有第2電容器電極410之電路圖案，製成電路板（第 2 5圖（h ))。其後，以和實施例D -1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第25 圖（i ))。 -128- (124) 1251536 實施例D-8 在內設電容器之多層配線板用材料D-3之銅箔402之表面，實施利用有機酸系微蝕刻劑C Z - 8 1 0 0 B ( Μ E C C Ο .， L T D .製、商品名稱）之粗化處理，當做多層化黏結前處理（第2 6圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之厚度爲l〇〇//m之玻璃環氧半固化片GEA-679F(日立化成工業株式會社製、商品名稱）配設厚度爲1 8 # m之銅箱 5GTS-18 ( FURUKAWA CIRCUIT FOIL C0.5 LTD.製、商品名稱），在溫度1 8 0 °C、壓力1 . 5 Μ P a、加熱加壓時間 6 0分鐘之冲壓條件下實施積層一體化，形成基板（第2 6 圖（b ))。此半固化片係利用溫度1 0 0 °C、壓力1 · 5 Μ P a 、加熱加壓時間1 〇分鐘之條件之熱壓在兩面貼附厚度爲 25//m之聚對苯二甲酸乙二酯（PET)之薄膜並在期望之部位實施鑽床鑽孔後，利用網板印染，充塡熱硬化性樹脂內分散銅粉之導電性糊 13AE1650 (TATSUTA SYSTEM ELECTRONICS公司製、商品名稱），然後再剝離表面之 PET薄膜者。其次，在ΡΖΤ薄膜4〇1之表面以DC濺鍍法形成0.0 5 // m之鉻薄膜4 〇 7。其後，對該基板兩面附與觸媒’促進密合後’實施無電解銅電鍍，形成〇. 5 # m之銅薄膜419。利用此方式，以形成之0.05//m之鉻薄膜4〇7 及0.5// m之銅薄膜419形成半加成法之基底金屬層（厚度爲0.1〜5#m之金屬層）。其後，在基板兩面形成期望之電鍍抗蝕層414，實施銅電鍍，形成厚度爲20//m之當 -129- (125) 1251536 做第1電容器電極409使用之導體圖案（第26圖（c)) 。剝離電鑛抗融層4 1 4後，利用氯化鐵水溶液鈾刻除去露出基板表面之〇.5//m之銅薄膜419，以鐵氰化鉀水溶液蝕刻除去露出之〇. 〇 5 // m之鉻薄膜4 0 7，形成第1電容器電極409之圖案（第26圖（d))。接著，形成期望圖案之抗蝕層，利用20%氟化氫銨（NH4F · HF )水溶液蝕刻除去PZT薄膜401之不必要部份，實施PZT薄膜401之圖案化，形成電容器介電質401’（第26圖（e))。接著，利用釕蝕刻液REC-01 (關東化學株式會製、商品名稱 )鈾刻除去露出之釕薄膜403 (第26圖（f))。其次，在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液鈾刻除去銅箔402以及銅箔405之不必要部份，形成含有第2電容器電極410之電路圖案，製成電路板（第26圖 (g ))。其後，以和實施例D-1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第26圖（h 實施例D-9 除了將充塡至內設電容器之多層配線板用材料及積層之半固化片之孔之導電性糊換成利用化學反應實施金屬化之導電性糊 NANO PASTE ( HARIMA CHEMICALS, INC.製、商品名稱）以外，以和實施例D-8相同之步驟得到內設電容器之多層配線板。 -130- (126) 1251536 實施例D -1 ΟGEM-679F (manufactured by Hitachi Chemical Co., Ltd., manufactured by Hitachi Chemical Co., Ltd.) with a thickness of 100/m, and a copper foil 5MT35S3 (Mitsui Metal) with a thickness of 3//m carrier copper foil of 3/m The company, which is manufactured by Mining Co., Ltd., carries out lamination integration under the conditions of a temperature of 180 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes to form a substrate (Fig. 23 (b)). The prepreg is coated with polyethylene terephthalate having a thickness of 25/m on both sides by a hot pressing condition of a temperature of 10 ° C, a pressure of 1.5 MP a, and a force of Q heat of 1 〇 minutes. After the film of the ester (PET) is drilled in a desired position, the conductive paste 13AE 1 65 0 (trade name) manufactured by TATSUTA SYSTEM ELECTRONICS Co., Ltd. is used to print the conductive paste of the copper powder in the thermosetting resin. Then peel the surface of the PET film. Next, on the surface of the ρζτ film 401, a chrome film 4 〇7 of 〇· 〇5 # m is formed by DC sputtering, and then electroplated on both sides of the substrate is formed by electroplating copper to form 20 0 / m of electroplated copper 4 0 8 The metal layer formed (Fig. 2 (c)). Forming a desired etch-resistant burd layer on the surface of the substrate. The unnecessary portion of the metal layer composed of the electroplated copper 4 〇 8 is removed by etching with an aqueous solution of ferric chloride, and the exposed film 7 is removed by etching with an aqueous solution of potassium ferricyanide. 'The pattern of the first capacitor electrode 409 is formed (Fig. 23(d)). Then, 'the uranium layer of the desired pattern is formed, and the ρζτ film 4 〇1 is removed by etching with a 20% aqueous solution of fluorinated nitrogen (NHj · HF ), and the pattern of the pZT film is not required to form a capacitor dielectric 4 〇1. (Fig. 2 (e)). Then, the exposed ruthenium film was removed by uranium etching solution RE C - 01 (manufactured by Kanto Chemical Co., Ltd., trade name) 4 〇 ° (Fig. 23 (f)). Next, a desired -124-(120) 1251536 etching resist layer is formed on the surface of the substrate, and an unnecessary portion of the copper foil 402, the copper foil 405, and the electric copper 408 is removed by etching with an aqueous solution of ferric chloride. A circuit board including a circuit pattern of the capacitor electrode 410 of the second embodiment is formed (Fig. 23(g)). Thereafter, the multilayer wiring board was processed in the same manner as in Example D-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 2 (3)). Example D-5: A conductive paste filled with a material for a multilayer wiring board filled with a built-in capacitor and a via of a prepreg, and a conductive paste NANO PASTE (manufactured by HARIMA CHEMICALS, INC.) A multilayer wiring board with a built-in capacitor was obtained in the same manner as in Example D-4 except for the product name. Example D - 6 The organic acid-based microetching agent CZ-8100B (manufactured by MEC CO., LTD., trade name) was used for the surface of the copper foil 420 of the multilayer wiring board D-3. The roughening treatment is performed as a multi-layered pre-bonding treatment (Fig. 24(a)). In the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 10 Å/m is used as the insulating resin substrate 404. (product name) is provided with copper foil 5MT35S3 (manufactured by Mitsui Mining & Mining Co., Ltd., product name) with a thickness of 3 5 // m carrier copper foil, at a temperature of 180 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. Under the stamping conditions, the integration of the layers is carried out to form the substrate (-125· (121) 1251536. The foil worm window is used to emit the pair of j • 05. The thick hole of the second chrome film is electrically engraved. Figure 24 (b) ). Next, a desired etch-resistant uranium layer is formed on the surface of the copper 405 of the substrate on which the carrier copper foil is peeled off, and an unnecessary copper box is removed by using an aqueous solution of ferric chloride to form a hole of 0.15 mm at a desired portion. 405' (Fig. 24(c)). Next, the window hole 40 5' is a ML 5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation, and the laser beam is irradiated with a lightning power of 26 mJ, a pulse width of 1 〇〇 μ s, and a stroke number of four times. 406, removing the carbonized resin residue by ultrasonic cleaning and alkali permanganic acid solution (Fig. 24 (d)). Further, a chrome film of 〇 · 〇 5 # m is formed on the surface of the Ρ Τ film 4 01 by DC sputtering. Thereafter, the substrate was bonded to the catalyst on both sides to promote adhesion, and then electroless copper plating was performed to form a copper film 19 of 0 · 5 // m. In this manner, a semi-additive base metal layer (a metal layer having a thickness of 0.1 to 5 #m) is formed by forming a chrome film 407 of 〇m and a copper film 419 of 0.5/m. A desired plating resist layer 4 1 4 is formed on both sides of the substrate, and copper plating is performed to form a plating copper 415 which is used as a part of the circuit including the first capacitor electrode 409 and the laser 406 with a degree of 20/m. The conductor pattern formed (24 (e)). After the plating resist layer 4 1 4 is peeled off, an unnecessary portion of the copper film 419 of 0.5//m on the substrate surface and an unnecessary portion of the film 407 of 0.05//m are removed by etching to form a pattern of the first capacitor electrode 409. . At this time, patterning of the copper foil 40 5 of 3 // m thick is also performed to form a road (Fig. 24(f)). Next, a resist layer of a desired pattern is formed, and an unnecessary portion of the PZT thin 401 is removed by etching with a 20% aqueous solution of ammonium hydrogen fluoride (NH 4 F · HF ), and patterning of the PZT thin film 401 is performed to form a dielectric 401 of the container, (24th) Figure (g)). Next, the exposed ruthenium film 403 (Fig. 24(h)) is removed by uranium engraving with uranium uranium-126-(122) 1251536 liquid R Ε Ο Ο 1 (manufactured by Kanto Chemical Co., Ltd., trade name). Next, a desired etching resist layer is formed on the surface of the substrate, and an unnecessary portion of the copper foil 402 is removed by uranium chloride aqueous solution to form a circuit board including the circuit pattern of the second capacitor electrode 410 (Fig. 24 (i )). Thereafter, the multilayer wiring board was processed in the same manner as in the example D-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 24(j)). In the case of the surface of the copper foil 402 of the material C-3 for the multilayer wiring board in which the capacitor is provided, the organic acid-based microetching agent CZ-8100B (trade name, manufactured by MEC CO., LTD.) is used. Treatment, as a multi-layer pre-bonding treatment (Fig. 25 (a)). On the surface of the copper crucible 40 2 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F having a thickness of 100/m as the insulating resin substrate 104 is used (Hitachi Chemical Industrial Co., Ltd.) Co., Ltd., the product name) is equipped with a copper foil 5MT35M3 (manufactured by Mitsui Mining & Mining Co., Ltd., product name) with a thickness of 3 / / m of copper foil of 3 / / m, at a temperature of 180 ° C, pressure 1 · 5 Μ P a, heating and pressurizing time for 60 minutes under the stamping conditions, stacking is carried out to form a substrate (Fig. 25 (b)). After the carrier copper foil was peeled off by a manual operation, a laser was applied using a ML 5 0 5 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation at a power output of 30 m J, a pulse width of 1 5 // s, and a stroke number of six times. Drill holes to make a 0 0 · 15 mm laser hole 4 0 6 . Thereafter, the carbonized resin residue is removed by ultrasonic cleaning and an alkali permanganic acid solution (Fig. 25 (c)). Further, -127-(123) 1251536 forms a ruthenium film of 〇〇5//m 407 on the surface of the PZT film 401 by DC sputtering. Further, after the catalyst is adhered to both sides of the substrate and the adhesion is promoted, the electroless copper ore is formed to form a copper film 4 1 9 of 〇 5 // πι. In this manner, a ferritic film 407 of 〇. 5//m and a copper film 419 of 0.5//m are formed to form a semi-additive base metal layer (thickness of the metal layer). A desired electroplating anti-uranium layer 414 is formed on the surface of the substrate, and copper electroplating is performed to form a copper plating layer 415 having a thickness of 20/m which is used as a part of the circuit including the first capacitor electrode 409 and the laser hole 406. Conductor pattern (Fig. 25 (d)). After the plating resist layer 4 1 4 is peeled off, the exposed portion of the chromium film 407 of the 0·5 // m copper film 4 1 9 and the 0·05 // m exposed on the surface of the substrate is removed by etching to form the first capacitor electrode. 4 〇9 and the pattern of part of the circuit of the laser hole 4 0 6 . At this time, patterning of a 3/m thick copper foil 405 is also performed to form a circuit (Fig. 25(e)). Next, an anti-uranium layer of a desired pattern is formed, and the PZT film 401 is removed by etching with a 20% hydrogen fluoride (NH4F · HF ) 7 too solution, and the PZT film 401 is patterned to form a capacitor dielectric 401' (Fig. 25 (Fig. 25) f)). Then, the exposed portion of the tantalum film 403 is removed by etching using a ruthenium etching solution REC-01 (manufactured by Kanto Chemical Co., Ltd., trade name) (Fig. 25(g)). Next, a desired etching resist layer is formed on the surface of the substrate, and an unnecessary portion of the copper foil 402 is removed by etching with an aqueous solution of ferric chloride to form a circuit pattern including the second capacitor electrode 410, thereby forming a circuit board (Fig. 25) (h)). Thereafter, the processing of the multilayer wiring board was carried out in the same manner as in the embodiment D-1 to obtain a multilayer wiring board in which a capacitor was built (Fig. 25(i)). -128- (124) 1251536 Example D-8 Using the organic acid-based microetching agent CZ-8 1 0 0 B (Μ ECC) on the surface of the copper foil 402 of the material D-3 for the multilayer wiring board in which the capacitor is provided粗., LTD., product name) roughening treatment, as a multi-layer bonding pre-treatment (Fig. 26 (a)). In the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 10 Å/m is used as the insulating resin substrate 404. , the product name) is equipped with a copper box 5GTS-18 (manufactured by FURUKAWA CIRCUIT FOIL C0.5 LTD., product name) with a thickness of 1 8 # m, at a temperature of 180 ° C, a pressure of 1.5 Μ P a, heating The laminate was integrated under a press condition of a press time of 60 minutes to form a substrate (Fig. 26 (b)). The prepreg is coated with polyethylene terephthalate having a thickness of 25/m on both sides by hot pressing at a temperature of 1 0 0 ° C, a pressure of 1 · 5 Μ P a , and a heating and pressing time of 1 〇 minute. After the film of the (PET) is drilled in a desired position, the conductive paste 13AE1650 (trade name, manufactured by TATSUTA SYSTEM ELECTRONICS Co., Ltd.) is dispersed in the thermosetting resin by a screen printing, and then peeled off. The surface of the PET film. Next, a chromium film 4 〇 7 of 0.0 5 // m was formed by DC sputtering on the surface of the tantalum film 4〇1. Thereafter, electroless copper plating was performed on both sides of the substrate with the contact of the catalyst to promote electroless copper plating to form a copper film 419 of 〇. 5 # m. In this manner, a half-additive base metal layer (metal layer having a thickness of 0.1 to 5 #m) was formed by forming a 0.05//m chromium film 4〇7 and a 0.5//m copper film 419. Thereafter, a desired plating resist layer 414 is formed on both surfaces of the substrate, and copper plating is performed to form a thickness of 20/m. When -129-(125) 1251536 is used as the conductor pattern for the first capacitor electrode 409 (Fig. 26 ( c)). After stripping the anti-melting layer 4 4 of the electric ore, the copper film 419 of the surface of the substrate exposed to the surface of the substrate is removed by uranium chloride aqueous solution, and is removed by etching with an aqueous solution of potassium ferricyanide. 〇5 // The chromium film of m 507 forms a pattern of the first capacitor electrode 409 (Fig. 26(d)). Next, a resist layer of a desired pattern is formed, and an unnecessary portion of the PZT thin film 401 is removed by etching with a 20% ammonium hydrogen fluoride (NH 4 F · HF ) aqueous solution, and patterning of the PZT thin film 401 is performed to form a capacitor dielectric 401 ′ (26th) Figure (e)). Then, the exposed ruthenium film 403 is removed by uranium etching solution REC-01 (manufactured by Kanto Chemical Co., Ltd., trade name) (Fig. 26(f)). Next, a desired etching resist layer is formed on the surface of the substrate, and unnecessary portions of the copper foil 402 and the copper foil 405 are removed by uranium chloride aqueous solution to form a circuit pattern including the second capacitor electrode 410, thereby forming a circuit board. (Fig. 26(g)). Thereafter, the multilayer wiring board was processed in the same manner as in the example D-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 26 (h Example D-9 except for charging the multilayer wiring to the built-in capacitor) The same procedure as in Example D-8 except that the conductive paste of the material for the plate and the layer of the prepreg was replaced with a conductive paste NANO PASTE (manufactured by HARIMA CHEMICALS, INC., trade name) which was metallized by a chemical reaction. A multilayer wiring board with a built-in capacitor is obtained. -130- (126) 1251536 Embodiment D -1 Ο

在內設電容器之多層配線板用材料D-3之銅箔402之表面，實施利用有機酸系微飩刻劑CZ-8100B ( MEC C0·， L T D.製、商品名稱）之粗化處理’當做多層化黏結前處理（第2 7圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之厚度爲 100//m之玻璃環氧半固化片 GEA-679F(日立化成工業株式會社製、商品名稱）配設厚度爲1 8 // m之銀箔 5GTS-1 8 ( FURUKAWA CIRCUIT FOIL CO.? LTD.製、商品名稱），在溫度180 °C、壓力1.5 MPa、加熱加壓時間 60分鐘之冲壓條件下實施積層一體化，形成基板（第27 圖（b ))。該半固化片係利用溫度lOOt：、壓力1 .5MPa 、加熱加壓時間1 〇分鐘之條件之熱壓在兩面貼附厚度爲 25//m之聚對苯二甲酸乙二酯（PET)之薄膜並在期望之部位實施鑽床鑽孔後，利用網板印染充塡在熱硬化性樹脂內分散著銅粉之導電性糊 AE 1 65 0 ( TATSUTA S YSTEM ELECTRONICS公司製 '商品名稱），然後再剝離表面之 PET薄膜者。其次，在PZT薄膜401表面之期望之部位，利用網板印染，印刷4 0 // m之厚度之利用化學反應實施金屬化之導電性糊 NANO PASTE ( HARIMA CHEMICALS，IN C ·製、商品名稱）後，以溫度2 0 0 °C、加熱時間1小時之條件進行烘焙，實施導電性糊之金屬化，形成第1電容器電極416之圖案（第27圖（c))。接著，形成期望圖案之抗蝕層，並利用20%氟化氫銨（NH4F -131 - (127) 1251536 • H F )水溶液蝕刻除去P Z T薄膜4 Ο 1之不必要部份實施 ΡΖΤ薄膜之圖案化而形成電容器介電質401 ’後，利用釕蝕刻液REC-01 (關東化學株式會製、商品名稱）鈾刻除去釕薄膜4 0 3之露出部份（第2 7圖（d ))。其次，在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液飩刻除去銅箔402及銀箔4 0 5之不必要部份，形成第2電容器電極4 1 0之電路圖案，製成電路板（第2 7圖（e ))。其後，以和實施例D-1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第27圖（f))。實施例D -1 1The surface of the copper foil 402 of the material D-3 for the multilayer wiring board in which the capacitor is provided is subjected to roughening treatment using an organic acid-based micro-etching agent CZ-8100B (manufactured by MEC C0·, LT D., trade name). As a multi-layer pre-bonding treatment (Fig. 27 (a)). In the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100/m as the insulating resin substrate 404 is used. Name) It is equipped with a silver foil 5GTS-1 8 (manufactured by FURUKAWA CIRCUIT FOIL CO.? LTD.) having a thickness of 1 8 // m, and is stamped at a temperature of 180 ° C, a pressure of 1.5 MPa, and a heating and pressing time of 60 minutes. The laminate is integrated under the conditions to form a substrate (Fig. 27(b)). The prepreg is attached to a film of polyethylene terephthalate (PET) having a thickness of 25/m on both sides by heat pressing at a temperature of 100 t:, a pressure of 1.5 MPa, and a heating and pressing time of 1 〇. After performing the drilling of the drill hole in the desired portion, the conductive paste AE 1 65 0 (trade name, manufactured by TATSUTA S YSTEM ELECTRONICS Co., Ltd.) in which the copper powder is dispersed in the thermosetting resin is filled with the screen printing, and then the surface is peeled off. PET film. Next, in the desired portion of the surface of the PZT film 401, a conductive paste NANO PASTE (manufactured by HARIMA CHEMICALS, INC., trade name) which is metallized by a chemical reaction using a screen printing and printing thickness of 40 Å. Thereafter, baking was carried out under the conditions of a temperature of 200 ° C and a heating time of 1 hour, and metallization of the conductive paste was carried out to form a pattern of the first capacitor electrode 416 (Fig. 27 (c)). Next, a resist layer of a desired pattern is formed, and an unnecessary portion of the PZT thin film 4 Ο 1 is removed by etching with an aqueous solution of 20% ammonium hydrogen fluoride (NH 4 F -131 - (127) 1251536 • HF ) to form a capacitor of the tantalum film to form a capacitor. After the dielectric material 401', the exposed portion of the tantalum film 404 was removed by uranium etching solution REC-01 (manufactured by Kanto Chemical Co., Ltd., trade name) (Fig. 27 (d)). Next, a desired etching resist layer is formed on the surface of the substrate, and unnecessary portions of the copper foil 402 and the silver foil 405 are removed by etching with an aqueous solution of ferric chloride to form a circuit pattern of the second capacitor electrode 4 10 . Circuit board (Fig. 27 (e)). Thereafter, the multilayer wiring board was processed in the same manner as in the example D-1 to obtain a multilayer wiring board in which a capacitor was provided (Fig. 27(f)). Example D -1 1

除了將充塡至內設電容器之多層配線板用材料及積層之半固化片之孔之導電性糊換成利用化學反應實施金屬化之導電性糊 NANO PASTE ( HARIMA CHEMICALS，INC·製、商品名稱）以外，以和實施例D-1 0相同之步驟得到內設電容器之多層配線板。實施例D -1 2 在內設電容器之多層配線板用材料D-3之銅箔402之表面，實施利用有機酸系微蝕刻劑CZ-8100B ( MEC CO.， LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理（第2 8圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之厚度爲100/zm之玻璃環氧半固化片GEA-679F(曰立化 -132· (128) 1251536 成工業株式會社製、商品名稱）配設厚度爲12//m之銅范 5GTS-12 ( FURUKAWA CIRCUIT FOIL CO。，LTD.製' 商品名稱），在溫度180°C、壓力l.5MPa、力□熱加壓時間 6 0分鐘之冲壓條件下實施積層一體化，形成基板（第2 8 圖（b ))。其次’形成期望圖案之抗蝕層並利用20%氟化氫銨（NH4F · HF )水溶液蝕刻除去ρζτ薄膜401實施 PZT薄膜之圖案化而形成電容器介電質40 Γ後，利用釕鈾刻液REC-0 1 (關東化學株式會製、商品名稱）蝕刻除去釕薄膜4 03 (第28圖（c ))。在該基板之兩面形成期望之蝕刻抗鈾層，利用氯化鐵水溶液蝕刻除去銅箔4 0 5之不必要部份，在期望之部位形成0 0.1 5 mm之窗孔4 0 5 ’（第 2 8圖（d ))。接著，在窗孔4 0 5 ’之部位利用三菱電機株式會社製ML505GT型碳酸氣體雷射，以輸出功率26mJ、脈衝寬度1 〇〇 // s、冲程數4次之條件實施雷射照射，形成雷射孔4 0 6，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣（第2 8圖（e ))。此外，在基板之電容器介電質 4 0 1 ’側之面，以D C濺鍍法形成0 · 〇 5 // m之鉻薄膜4 0 7。其後，對基板兩面附與觸媒、促進密合後，實施無電解銅電鍍，形成〇 · 5 // m之銅薄膜，此外，在其上利用電性銅電鍍形成20/zm之金屬層，而形成由電鍍銅408所構成之金屬層（第28圖（f))。在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去電鍍銅408及銅箔 4 0 5之不必要部份，利用鐵氰化鉀水溶液蝕刻除去露出之鉻薄膜4 0 7，此外，利用氯化鐵水溶液蝕刻除去露出之銅 -133- (129) 1251536 箔402，形成含有第1電容器電極409及第2電容器電極 4 1 0之電路圖案（第2 8圖（g ))。其後，以和實施例D -1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第2 8圖（h ))。實施例D - 1 3 在內設電容器之多層配線板用材料D-3之銅箔402之表面，實施利用有機酸系微蝕刻劑CZ-8100B ( MEC CO.， LTD·製、商品名稱）之粗化處理，當做多層化黏結前處理（第29圖（a ))。在該內設電容器之多層配線板用材料之銅箔4 0 2之表面，利用當做絶緣樹脂基材4 0 4使用之厚度爲l〇〇//m之玻璃環氧半固化片 GEA-679F(日立化成工業株式會社製、商品名稱）配設附3 5 // m載體銅箔之厚度爲3/zm之銅箔5MT35M3(三井金屬鑛業株式會社製、商品名稱）’在溫度180C、壓力1.5MPa、加熱加壓時間60分鐘之冲壓條件下實施積層一體化，得到基板（第2 9圖（b ))。其次，形成期望圖案之抗蝕層並利用 20%氟化氫銨（NH4F · HF )水溶液蝕刻除去PZT薄膜401 實施PZT薄膜之圖案化而形成電容器介電質401’後，利用釕蝕刻液RE C - 0 1 (關東化學株式會製、商品名稱）蝕刻除去釕薄膜403之露出部份（第29圖（c))。以人工作秦剝離載體銅泊後’在銅泊4 0 5之特定表面利用二菱電機株式會社製ML 5 05 GT型碳酸氣體雷射，以輸出功率 3 0m J、脈衝寬度1 5 // s、冲程數6次之條件實施雷射照射 -134^ (130) 1251536 ，製成0 0.15mm之雷射孔406。其後，以超音波洗淨及鹼高錳酸液除去碳化之樹脂渣（第29圖（d ))。此外，在該基板之形成電容器介電質401’之面上，以DC濺鍍法形成0.0 5 // m之鉻薄膜4 0 7。其後，對基板兩面附與觸媒、促進密合後，實施無電解銅電鍍，形成〇. 5 // m之銅薄膜，此外，在其上利用電性銅電鍍形成2 0 // m之金屬層，形成由電鍍銅408所構成之金屬層（第29圖（e))。在該基板表面形成期望之蝕刻抗蝕層，利用氯化鐵水溶液蝕刻除去電鍍銅408及銅箔405之不必要部份，利用鐵氰化鉀水溶液蝕刻除去露出之鉻薄膜4 0 7，此外，利用氯化鐵水溶液蝕刻除去露出之銅箔402，形成含有第1電容器電極409及第2電容器電極410之電路圖案（第29圖（f ))。其後，以和實施例D - 1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第29圖（g )) 實施例D -1 4 在內設電容器之多層配線板用材料D-3之銅箔402之表面’實施利用有機酸系微蝕刻劑C Z - 8 1 0 0 B ( Μ E C C Ο .， LTD.製、商品名稱）之粗化處理，當做多層化黏結前處 3 (第3 0圖（a ))。在該內設電容器之多層配線板用材料之銅箔402之表面，利用當做絶緣樹脂基材404使用之厚度爲100/im之玻璃環氧半固化片GEA-679F(日立化成工業株式會社製、商品名稱）配設附3 5 # m載體銅箔 -135- (131) 1251536 之厚度爲3//m之銅箔5MT3553 (三井鑛山株式會製、商品名稱），在溫度180°C、壓力1.5MPa、力□熱加壓時間 6 0分鐘之冲壓條件下實施積層一體化，形成基板（第30 圖（b ))。該半固化片係利用溫度l〇〇°C、壓力1 .5MPa 、加熱加壓時間1 〇分鐘之條件之熱壓在兩面貼附厚度爲 2 5 # m之聚對苯二甲酸乙二酯（PET )之薄膜並在期望之部位實施鑽床鑽孔後，利用網板印染，充塡熱硬化性樹脂內分散銅粉之導電性糊 AE 1 650 ( TATSUTA SYSTEM ELECTRONICS公司製、商品名稱），然後再剝離表面之 PET薄膜者。其次，形成期望圖案之抗蝕層並利用20%氟化氫銨（ NH4F · HF )水溶液蝕刻除去PZT薄膜401實施PZT薄膜之圖案化而形成電容器介電質40 1 ’後，利用釕蝕刻液 REC-01 (關東化學株式會製、商品名稱）鈾刻除去釕薄膜403之露出部份（第30圖（c))。此外，在基板之電容器介電質401 ’面側以DC濺鍍法形成0.05 // m之鉻薄膜 407並附與觸媒、促進密合後，實施無電解銅電鍍，形成 0.5 // m之銅薄膜。此外，在基板兩面利用電性銅電鍍形成20//m之由電鍍銅408所構成之金屬層（第30圖（d ))。在該基板表面形成期望之蝕刻抗鈾層，利用氯化鐵水溶液鈾刻除去電鍍銅408及銅箔40 5之不必要部份，利用鐵氰化鉀水溶液蝕刻除去露出之鉻薄膜7，此外，利用氯化鐵水溶液蝕刻除去露出之銅箔402，形成含有第1電容器電極409及第2電容器電極410之電路圖案（第30 -136- (132) 1251536 圖（e ))。其後，以和實施例D -1相同之步驟實施多層配線板之加工，得到內設電容器之多層配線板（第3 0圖實施例D-15 除了將充塡至內設電容器之多層配線板用材料及積層之半固化片之孔之導電性糊換成利用化學反應實施金屬化之導電性糊 NANO PASTE ( HARIMA CHEMICALS，INC·製、商品名稱）以外，以和實施例D-1 4相同之步驟得到內設電容器之多層配線板。比較例D - 1 準備具有用以連結兩面之電路圖案之導體孔（孔內充塡著孔充塡樹脂418)之板厚爲〇.2mm之兩面電路基板（第31圖（a))。在該基板之單面以DC濺鍍法形成0.2 // m之釕薄膜403。形成期望圖案之抗蝕層，以RIE法蝕刻除去電路以外之釕薄膜403，形成含有第2電容器電極 421之電路圖案（第31圖（b))。此外，在其基板表面塗布強介電質薄膜形成材料PZT (關東化學株式會製、商品名稱），實施溫度1 5 (TC、加熱時間3 0分鐘之預烘焙。再重複實施5次塗布及預烘焙，其後，實施溫度2 5 (TC 、加熱時間1小時之熱處理，形成厚度爲〇 · 5 // m之P Z T 薄膜401(第31圖（c))。此外，在其PZT薄膜401之表面，以DC濺鍍法形成〇.05 # m之鉻薄膜407。此外， -137- (133) 1251536 在其構成之蝕不必 4 07 3 1 | 層配圖（容器容器結果表面利用電性銅電鍍形成2 0 // m之由電鍍銅4 0 8所之金屬層（第31圖（d))。在該基板表面形成期望刻抗蝕層’利用氯化鐵水溶液蝕刻除去電鍍銅4〇8之要部份，利用鐵氰化鉀水溶液蝕刻除去露出之鉻薄膜製成形成第1電容器電極422之圖案之電路板（第 1(e))。其後’以和實施例D -1相同之步驟實施多線板之加工’得到內設電容器之多層配線板（第3 i f))。針對實施例D — 1〜D-15及比較例D-1所得到之內設電之多層配線板，檢測介電質之膜厚、電容率、以及電谷重。各檢測方法和前述相同。以下之表4係其檢測 -138- (134) 1251536 表4 電容率膜厚（//m) 電容器容量（Nf) 最小値最大値平均値最小値最大値平均値 D-1 70 0.45 0.52 0.48 1.1 1.3 1.2 D-2 100 0.48 0.51 0.50 1.5 1.7 1.6 D-3 70 0.45 0.52 0.48 1.1 1.3 1.2 D-4 100 0.48 0.51 0.50 1.5 1.7 1.6 D-5 100 0.48 0.51 0.50 1.5 1.7 1.6 D-6 100 0.48 0.51 0.50 1.5 1.7 1.6 β1 D-7 100 0.48 0.51 0.50 1.5 1.7 1.6 施 D-8 100 0.48 0.51 0.50 1.5 1.7 1.6 例 D-9 100 0.48 0.51 0.50 1.5 1.7 1.6 D-10 100 0.48 0.51 0.50 1.5 1.7 1.6 D-11 100 0.48 0.51 0.50 1.5 1.7 1.6 D-12 100 0.48 0.51 0.50 1.5 1.7 1.6 D-13 100 0.48 0.51 0.50 1.5 1.7 1.6 D-14 100 0.48 0.51 0.50 1.5 1.7 1.6 D-15 100 0.48 0.51 0.50 1.5 1.7 1.6 比較例D-1 80 0.33 0.67 0.50 1.0 2.0 1.3 實施例D-1〜D-1 5皆採用金屬箔表面配設著電容率爲 10〜2000且膜厚爲0.05〜2// m之介電質薄膜之內設電容器之多層配線板用材料所製成之內設電容器之基板。製成之電容器容量之誤差皆低於± 1 〇 %，可製成均一且良好之 -139- (135) 1251536 電容器。又，比較例因係在實施金屬層圖案化之基板表面形成介電質薄膜之內設電容器之基板，膜厚誤差較大，結果，電容器容量之誤差亦爲最大之54%。前述係本發明之良好實施形態，相關業者應可了解在不違背本發明之精神及範圍內實施各種變更及修正。In addition to the conductive paste of the material for the multilayer wiring board and the layer of the prepreg, which is filled with the built-in capacitor, is replaced by a conductive paste NANO PASTE (manufactured by HARIMA CHEMICALS, INC., trade name) which is metallized by a chemical reaction. A multilayer wiring board with a built-in capacitor was obtained in the same manner as in the example D-1 0. In the case of the surface of the copper foil 402 of the material D-3 for the multilayer wiring board in which the capacitor is provided, the organic acid-based microetching agent CZ-8100B (manufactured by MEC CO., LTD., trade name) is used. The roughening treatment is treated as a multi-layered pre-bonding treatment (Fig. 28(a)). On the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F having a thickness of 100/zm used as the insulating resin substrate 404 is used (曰立化-132· (128) 1251536, manufactured by Seiko Co., Ltd., and the product name) is a copper vane 5GTS-12 (product name) manufactured by FURUKAWA CIRCUIT FOIL CO., LTD., having a thickness of 12/m, at a temperature of 180 ° C and a pressure of 1.5 MPa. The laminate is integrated under the stamping conditions of the hot pressurization time of 60 minutes to form a substrate (Fig. 28 (b)). Next, 'the resist layer of the desired pattern is formed and the pζ film 401 is removed by etching with a 20% ammonium hydrogen fluoride (NH4F·HF) aqueous solution to form a PZT film to form a capacitor dielectric 40 Γ, and then the uranium engraving REC-0 is used. 1 (Kanto Chemical Co., Ltd., product name) Etching and removing the tantalum film 4 03 (Fig. 28 (c)). A desired etch-resistant uranium layer is formed on both sides of the substrate, and an unnecessary portion of the copper foil 405 is removed by etching with an aqueous solution of ferric chloride to form a window of 0 0.1 5 mm at a desired portion. 8 (d)). Then, the ML505GT-type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used in the window hole 4 0 5 ', and laser irradiation was performed under the conditions of an output of 26 mJ, a pulse width of 1 〇〇//s, and a stroke number of four times. The laser hole of the laser hole is removed by ultrasonic cleaning and alkali permanganic acid solution (Fig. 28 (e)). Further, on the surface of the capacitor dielectric 4 0 1 ' side of the substrate, a chromium film 407 of 0 · 〇 5 // m was formed by DC sputtering. Thereafter, after the catalyst is adhered to both surfaces of the substrate and the adhesion is promoted, electroless copper plating is performed to form a copper film of 〇·5 // m, and a metal layer of 20/zm is formed thereon by electroplating with copper. And a metal layer composed of the electroplated copper 408 is formed (Fig. 28(f)). A desired etching resist layer is formed on the surface of the substrate, and an unnecessary portion of the copper plating 408 and the copper foil 405 is removed by etching with an aqueous solution of ferric chloride, and the exposed chromium film is removed by etching with an aqueous solution of potassium ferricyanide. Further, the exposed copper-133-(129) 1251536 foil 402 was removed by etching with an aqueous solution of ferric chloride to form a circuit pattern including the first capacitor electrode 409 and the second capacitor electrode 4 10 (Fig. 28 (g)). Thereafter, the multilayer wiring board was processed in the same manner as in Example D-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 28 (h)). In the case of the surface of the copper foil 402 of the material D-3 for the multilayer wiring board in which the capacitor is provided, the organic acid-based microetching agent CZ-8100B (manufactured by MEC CO., LTD., trade name) is used. The roughening treatment is treated as a multi-layered pre-bonding treatment (Fig. 29(a)). On the surface of the copper foil 420 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F having a thickness of 10 Å/m is used as the insulating resin substrate 407 (Hitachi Chemical Co., Ltd.) Industrial Co., Ltd., product name) is equipped with a copper foil 5MT35M3 (manufactured by Mitsui Mining & Mining Co., Ltd., product name) with a thickness of 3/zm, which is 3/4 m, and is heated at a temperature of 180 C and a pressure of 1.5 MPa. The laminate was integrated under a press condition of a press time of 60 minutes to obtain a substrate (Fig. 2(b)). Next, a resist layer of a desired pattern is formed and the PZT thin film 401 is removed by etching with a 20% aqueous solution of ammonium hydrogen fluoride (NH 4 F · HF ). After the patterning of the PZT thin film is performed to form a capacitor dielectric 401 ′, the etchant RE C - 0 is used. 1 (manufactured by Kanto Chemical Co., Ltd., trade name) The exposed portion of the tantalum film 403 is removed by etching (Fig. 29(c)). After working on the copper stripping carrier copper, the ML 5 05 GT type carbon dioxide gas laser manufactured by Mitsubishi Electric Corporation was used on the specific surface of the copper berth 400 to output power of 30 m J and pulse width of 1 5 // s. The laser irradiation -134^ (130) 1251536 was carried out under the condition of 6 strokes to make a 0 0.15 mm laser hole 406. Thereafter, the carbonized resin residue is removed by ultrasonic cleaning and an alkali permanganic acid solution (Fig. 29 (d)). Further, on the surface of the substrate on which the capacitor dielectric 401' is formed, a chromium film of 70 /5 m is formed by DC sputtering. Thereafter, after the catalyst is adhered to both surfaces of the substrate and the adhesion is promoted, electroless copper plating is performed to form a copper film of //.5 // m, and further, electro-optical plating is used to form 20 0 m. The metal layer forms a metal layer composed of electroplated copper 408 (Fig. 29(e)). A desired etching resist layer is formed on the surface of the substrate, and an unnecessary portion of the copper plating 408 and the copper foil 405 is removed by etching with an aqueous solution of ferric chloride, and the exposed chromium film is removed by etching with an aqueous solution of potassium ferricyanide. The exposed copper foil 402 is removed by etching with an aqueous solution of ferric chloride to form a circuit pattern including the first capacitor electrode 409 and the second capacitor electrode 410 (Fig. 29(f)). Thereafter, the multilayer wiring board was processed in the same manner as in Example D-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 29(g)). Example D -1 4 Multilayer wiring board with a capacitor built therein The surface of the copper foil 402 of the material D-3 is subjected to roughening treatment using an organic acid-based microetching agent CZ-8 1 0 0 B (manufactured by ECC Ο., LTD., as a product name). Section 3 (Fig. 3 (a)). In the surface of the copper foil 402 of the material for the multilayer wiring board in which the capacitor is provided, a glass epoxy prepreg GEA-679F (manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 100/im used as the insulating resin substrate 404 is used. ) It is equipped with a copper foil 5MT3553 (made by Mitsui Mining Co., Ltd., trade name) with a thickness of 3//m with a copper foil-135- (131) 1251536, at a temperature of 180 ° C and a pressure of 1.5 MPa. The laminate is integrated under the stamping conditions of 60 minutes of hot pressurization time to form a substrate (Fig. 30(b)). The prepreg is coated with polyethylene terephthalate (PET) having a thickness of 2 5 # m on both sides by hot pressing under the conditions of temperature l〇〇°C, pressure of 1.5 MPa, and heating and pressing time of 1 〇 minutes. After the film is drilled in a desired portion, the conductive paste AE 1 650 (trade name) manufactured by TATSUTA SYSTEM ELECTRONICS Co., Ltd., which is dispersed in a thermosetting resin, is stenciled by a screen, and then the surface is peeled off. PET film. Next, a resist layer of a desired pattern is formed and the PZT thin film 401 is removed by etching with a 20% ammonium hydrogen fluoride (NH 4 F · HF ) aqueous solution to form a PZT thin film to form a capacitor dielectric 40 1 ', and then a ruthenium etching solution REC-01 is used. (The Kanto Chemical Co., Ltd. product name) The uranium engraving removes the exposed portion of the tantalum film 403 (Fig. 30(c)). In addition, a chromium film 407 of 0.05 // m is formed by DC sputtering on the surface of the capacitor dielectric 401 ' of the substrate, and the catalyst is bonded to the catalyst to promote adhesion. Electroless copper plating is performed to form 0.5 // m. Copper film. Further, a metal layer composed of electroplated copper 408 of 20/m was formed by electroplating on both sides of the substrate (Fig. 30(d)). Forming a desired etch-resistant uranium layer on the surface of the substrate, removing unnecessary portions of the electroplated copper 408 and the copper foil 40 5 by uranium chloride aqueous solution, and etching the exposed chromium film 7 by using a potassium ferricyanide aqueous solution, and further, The exposed copper foil 402 is removed by etching with an aqueous solution of ferric chloride to form a circuit pattern including the first capacitor electrode 409 and the second capacitor electrode 410 (No. 30-136-(132) 1251536 (e)). Thereafter, the multilayer wiring board was processed in the same manner as in Example D-1 to obtain a multilayer wiring board with a built-in capacitor (Fig. 30, Embodiment D-15 except for a multilayer wiring board which is charged to a built-in capacitor) The same procedure as in Example D-1 4 except that the conductive paste of the material and the laminated prepreg was replaced with a conductive paste NANO PASTE (manufactured by HARIMA CHEMICALS, INC., trade name) which was metallized by a chemical reaction. A multilayer wiring board having a built-in capacitor was obtained. Comparative Example D - 1 A two-sided circuit board having a thickness of 〇. 2 mm having a conductor hole (the hole filled with the resin 418 filled in the hole) for connecting the circuit patterns on both sides was prepared ( Fig. 31(a)): A 0.2*m thin film 403 is formed on one side of the substrate by DC sputtering. A resist layer of a desired pattern is formed, and a thin film 403 other than the circuit is etched by RIE to form The circuit pattern of the second capacitor electrode 421 (Fig. 31(b)) is applied. The surface of the substrate is coated with a ferroelectric thin film forming material PZT (manufactured by Kanto Chemical Co., Ltd., trade name), and the temperature is 15 (TC). Heating time 30 minutes Pre-baking of the bell. Repeat the coating and pre-baking five times, and then heat-treating at a temperature of 2 5 (TC, heating time for 1 hour to form a PZT film 401 having a thickness of 〇·5 // m (Fig. 31 ( c)). Further, on the surface of the PZT film 401, a chrome film 407 of 〇.05 #m is formed by DC sputtering. In addition, -137-(133) 1251536 does not have to be etched in its composition 4 07 3 1 | The layered pattern (the surface of the container container is formed by electroplating with copper to form a metal layer of 20 0 / 8 m of electroplated copper (Fig. 31 (d)). A desired resist layer is formed on the surface of the substrate. The portion of the electroplated copper 4〇8 is removed by etching with an aqueous solution of ferric chloride, and the exposed chromium film is removed by etching with an aqueous solution of potassium ferricyanide to form a circuit board in which the pattern of the first capacitor electrode 422 is formed (first (e)). Thereafter, 'the same process as in Example D-1 was carried out to carry out the processing of the multi-wire board' to obtain a multilayer wiring board (3rd if) having a built-in capacitor. For Examples D-1 to D-15 and Comparative Example D- The obtained multilayer wiring board with electric power is used to detect the film thickness, permittivity, and electric weight of the dielectric. The method is the same as the above. Table 4 below is the test -138- (134) 1251536 Table 4 Capacitance film thickness (//m) Capacitor capacity (Nf) Minimum 値 Maximum 値 Average 値 Minimum 値 Maximum 値 Average 値 D-1 70 0.45 0.52 0.48 1.1 1.3 1.2 D-2 100 0.48 0.51 0.50 1.5 1.7 1.6 D-3 70 0.45 0.52 0.48 1.1 1.3 1.2 D-4 100 0.48 0.51 0.50 1.5 1.7 1.6 D-5 100 0.48 0.51 0.50 1.5 1.7 1.6 D-6 100 0.48 0.51 0.50 1.5 1.7 1.6 β1 D-7 100 0.48 0.51 0.50 1.5 1.7 1.6 Application D-8 100 0.48 0.51 0.50 1.5 1.7 1.6 Example D-9 100 0.48 0.51 0.50 1.5 1.7 1.6 D-10 100 0.48 0.51 0.50 1.5 1.7 1.6 D-11 100 0.48 0.51 0.50 1.5 1.7 1.6 D-12 100 0.48 0.51 0.50 1.5 1.7 1.6 D-13 100 0.48 0.51 0.50 1.5 1.7 1.6 D-14 100 0.48 0.51 0.50 1.5 1.7 1.6 D-15 100 0.48 0.51 0.50 1.5 1.7 1.6 Comparative Example D-1 80 0.33 0.67 0.50 1.0 2.0 1.3 Each of the examples D-1 to D-1 5 was provided with a dielectric material having a permittivity of 10 to 2,000 and a film thickness of 0.05 to 2/m. A substrate in which a capacitor is formed of a material for a multilayer wiring board of a capacitor. The capacitance of the fabricated capacitor is less than ± 1 〇 %, making it a uniform and good -139- (135) 1251536 capacitor. Further, in the comparative example, since the substrate in which the capacitor was formed on the surface of the substrate on which the metal layer was patterned was formed, the film thickness error was large, and as a result, the error in the capacitor capacity was also 54% at the maximum. The foregoing is a preferred embodiment of the present invention, and it should be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.

【圖式簡單說明】第1圖係本發明實施例之內設電容器之多層配線板用材料之剖面圖。第2圖係實施例A-1、實施例A-2、以及實施例A-5 之處理之剖面圖。第3圖係實施例A-3之處理之剖面圖。第4圖係實施例A-4之處理之剖面圖。第5圖係實施例A - 6之處理之剖面圖。BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a material for a multilayer wiring board in which a capacitor is provided in an embodiment of the present invention. Fig. 2 is a cross-sectional view showing the treatment of Example A-1, Example A-2, and Example A-5. Figure 3 is a cross-sectional view showing the treatment of Example A-3. Figure 4 is a cross-sectional view showing the treatment of Example A-4. Figure 5 is a cross-sectional view showing the treatment of Examples A - 6.

第6圖係實施例A- 7之處理之剖面圖。第7圖係實施例A- 8之處理之剖面圖。第8圖係比較例A- 1之處理之剖面圖。第9圖至第1 1圖係本發明實施例B所使用之內層基板之剖面圖。第12圖係實施例B-1之處理、以及實施例B-4及B-5之處理之部份剖面圖。第1 3圖係實施例B - 6之處理之剖面圖。第1 4圖係實施例B - 7之處理之剖面圖。 -140- (136) 1251536 第1 5圖係實施例B - 8之處理之剖面圖。第1 6圖係比較例B -1之處理之剖面圖。第17〜19圖係實驗例C-1〜C-9之製造步驟之剖面圖〇第2 0圖係實施例D - 1之處理之剖面圖。第2 1圖係實施例D · 2之處理之剖面圖。第2 2圖係貫施例D - 3之處理之剖面圖。第23圖係實施例D-4及實施例D-5之處理之剖面圖〇第2 4圖係貫施例D - 6之處理之剖面圖。第2 5圖係實施例D - 7之處理之剖面圖。第2 6圖係實施例D - 8及實施例D - 9之處理之剖面圖〇第2 7圖係實施例D - 1 0及實施例D - 1 1之處理之剖面圖。第2 8圖係實施例D - 1 2之處理之剖面圖。第2 9圖係實施例D -1 3之處理之剖面圖。第30圖係實施例D-14及實施例D-15之處理之剖面圖。第3 1圖係比較例D-1之處理之剖面圖。〔元件符號之說明〕 101 PZT (锆鈦酸鉛）薄膜 102 銅箔 -141 - (137) 1251536 103 釕薄膜 104 兩面基板 105 電鍍銅 106 孔充塡樹脂 107 絶緣樹脂基材 108 鉻薄膜 1 09 金屬層Figure 6 is a cross-sectional view showing the treatment of Examples A-7. Figure 7 is a cross-sectional view showing the treatment of Examples A-8. Figure 8 is a cross-sectional view showing the treatment of Comparative Example A-1. Fig. 9 through Fig. 1 1 are cross-sectional views of the inner layer substrate used in the embodiment B of the present invention. Figure 12 is a partial cross-sectional view showing the treatment of Example B-1 and the treatment of Examples B-4 and B-5. Figure 13 is a cross-sectional view of the treatment of Example B-6. Figure 14 is a cross-sectional view of the treatment of Example B-7. -140- (136) 1251536 Figure 15 is a cross-sectional view of the treatment of Example B-8. Fig. 16 is a cross-sectional view showing the treatment of Comparative Example B-1. 17 to 19 are sectional views of the manufacturing steps of Experimental Examples C-1 to C-9. Fig. 20 is a cross-sectional view showing the treatment of Example D-1. Figure 21 is a cross-sectional view showing the treatment of Example D. Figure 2 is a cross-sectional view of the treatment of Example D-3. Figure 23 is a cross-sectional view showing the treatment of Example D-4 and Example D-5. Figure 24 is a cross-sectional view of the treatment of Example D-6. Figure 25 is a cross-sectional view of the treatment of Example D-7. Fig. 26 is a cross-sectional view showing the treatment of the embodiment D-8 and the embodiment D-9. Fig. 27 is a cross-sectional view showing the treatment of the embodiment D-10 and the embodiment D-1. Figure 28 is a cross-sectional view of the treatment of Example D-2. Figure 29 is a cross-sectional view showing the treatment of Example D-1. Figure 30 is a cross-sectional view showing the treatment of Examples D-14 and D-15. Fig. 3 is a cross-sectional view showing the treatment of Comparative Example D-1. [Description of component symbols] 101 PZT (lead zirconate titanate) film 102 Copper foil-141 - (137) 1251536 103 钌 film 104 double-sided substrate 105 electroplated copper 106 hole filled resin 107 insulating resin substrate 108 chrome film 1 09 metal Floor

110 雷射鑽孔 111 電鍍抗蝕層 112 絶緣樹脂基材 113 防焊漆 117 導電性糊 20 1 銅箔 202 絶緣樹脂基材 203 孔充塡樹脂110 Laser drilling 111 Plating resist 112 Insulating resin substrate 113 Solder resist 117 Conductive paste 20 1 Copper foil 202 Insulating resin substrate 203 Hole filling resin

204 無電解銅電鍍層 205 充塡銅糊NF2000 206 導電性糊 207 釕薄膜 208 PZT (锆鈦酸鉛）薄膜 209 鉻薄膜 210 金屬層 2 11 絶緣樹脂基材 212 防焊漆 -142- (138)1251536 2 13 外層電路 2 14 金屬層 2 1 5 電鍍抗蝕層 2 16 導電性糊 2 17 第 1 電容器電極 2 18 第 2 電容器電極 2 19 內層板 220 多層配線板 3 0 1 PZT 薄膜 302 釕薄膜 303 銅箔 304 絶緣樹脂基材 305 銅箔 5GTS- 18 306 鉻膜 3 07 窗孔 308 雷射鑽孔 309 電鍍銅 3 10 第 1 電容器電極 3 11 蝕刻抗倉虫層 3 12 第 2 電容器電極 3 13 絶緣樹脂基材 3 14 銅箔 3 15 電解電鑛銅 3 16 防焊漆204 Electroless copper plating 205 Copper paste NF2000 206 Conductive paste 207 钌 Film 208 PZT (lead zirconate titanate) film 209 Chrome film 210 Metal layer 2 11 Insulating resin substrate 212 Solder resist paint -142- (138) 1251536 2 13 Outer layer circuit 2 14 Metal layer 2 1 5 Plating resist 2 16 Conductive paste 2 17 1st capacitor electrode 2 18 2nd capacitor electrode 2 19 Inner layer 220 Multilayer wiring board 3 0 1 PZT film 302 钌 film 303 Copper foil 304 Insulating resin substrate 305 Copper foil 5GTS- 18 306 Chrome film 3 07 Window hole 308 Laser drilling 309 Electroplating copper 3 10 1st capacitor electrode 3 11 Etching anti-burst layer 3 12 2nd capacitor electrode 3 13 Insulating resin substrate 3 14 Copper foil 3 15 Electrolytic copper oxide 3 16 Anti-corrosion paint

-143- (139)1251536 3 17 Μ j \ w 電解金電鍍 40 1 ΡΖΤ 薄膜 40 1 5 電容器介電質 402 銅箔 403 釕薄膜 404 絶緣樹脂基材 405 銅箔 405 ’ 窗孔 406 雷射孔 407 鉻薄膜 408 電鍍銅 409 第 1 電容器電極 4 10 第 2 電容器電極 4 11 防焊漆 4 12 絶緣樹脂基材 4 14 電鍍抗蝕層 4 15 電鍍銅 4 16 第 1 電容器電極 4 18 孔充塡樹脂 4 19 銅薄膜 420 Au電鍍 42 1 第 2 電容器電極 422 第 1 電容器電極-143- (139)1251536 3 17 Μ j \ w Electrolytic gold plating 40 1 薄膜 Film 40 1 5 Capacitor dielectric 402 Copper foil 403 钌 Film 404 Insulating resin substrate 405 Copper foil 405 'Window hole 406 Laser hole 407 Chrome film 408 Electroplated copper 409 1st capacitor electrode 4 10 2nd capacitor electrode 4 11 Solder resist 4 4 Insulating resin substrate 4 14 Plating resist 4 15 Electroplating copper 4 16 1st capacitor electrode 4 18 hole filling resin 4 19 copper film 420 Au plating 42 1 second capacitor electrode 422 first capacitor electrode

-144--144-

Claims

1251536 (1) Pickup, Patent Application No. 1 · A material for a multilayer wiring board with a built-in capacitor, characterized in that: the surface of the metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 0.05 to 2//m. Electrochemical film. 2 · For the material of the multilayer wiring board with capacitors in the first item of the patent application,

The dielectric film is made of barium titanate, barium titanate, calcium titanate, magnesium titanate, lead titanate, barium titanate, titanium dioxide, barium zirconate, calcium zirconate, lead chromate, barium titanate, Any one of lead chromite titanate, lead magnesium ruthenate-lead titanate, or a solid solution containing two or more of them, or a laminate comprising two or more of them. 3. A material for a multi-layer wiring board having a capacitor as set forth in claim 1 or 2, wherein

The metal foil is made of copper, and a metal film is disposed on the surface of the dielectric film, and the metal film is an oxidized protective film of copper. The metal forming the oxidized protective film of copper is from platinum. One or more selected from the group consisting of gold, silver, palladium, rhodium, and ruthenium. 4. A material for a multilayer wiring board in which a capacitor is provided in the first or second aspect of the patent application, wherein the metal foil is made of copper, and the surface thereof is provided with a metal film 'the above-mentioned metal film is stabilized by auto-oxidation coating The film is one or more selected from the group consisting of chromium, molybdenum, titanium, and nickel in which the above-mentioned stable auto-oxidation film is formed. 5 · If the capacitor is multi-layered in the first or second part of the patent application -145- (2) 1251536 wire plate material, wherein the surface roughness of the metal foil is 0. 01~0. 5// m. 6) A method for manufacturing a material for a multilayer wiring board with a built-in capacitor, characterized in that: a capacitance ratio of 10 to 2000 is formed on the surface of the metal foil by a vacuum evaporation method, and the film thickness is 0. 05~2//m dielectric film. 7 - A method for manufacturing a material for a multilayer wiring board with a built-in capacitor, characterized in that: a permittivity of 10 to 2000 is formed on the surface of the metal foil by ion plating, and the film thickness is 0. 05~2// m dielectric film. 8. A method for manufacturing a material for a multilayer wiring board in which a capacitor is provided, characterized in that: a CVD (Chemical Vapor Deposition) method is used to form a permittivity of 10 to 2000 on a surface of a metal case and a film thickness of 0. 05~2//m dielectric film. 9. A method for manufacturing a material for a multilayer wiring board with a built-in capacitor, characterized in that: a sputtering method is used to form a permittivity of 10 to 2000 on the surface of the metal foil and a film thickness of 0. 05~2//m dielectric film. 1 〇 — — — — 电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器电容器 05~2//m dielectric film. 1 1 . A manufacturing method of a multilayer wiring board material of -146-(3) 1251536 capacitor, which is a method of manufacturing a multi-layer wiring board of a capacitor, which is in a heating furnace of a constant temperature management, as in any one of claims 6 to 10 The metal case is continuously moved to form a dielectric film. A manufacturing method of a material for a multilayer wiring board in which a capacitor is provided in any one of claims 6 to 10, wherein the dielectric film is made of barium titanate, barium titanate, or titanic acid. Any of calcium, magnesium titanate, lead titanate, barium titanate, titanium dioxide, barium chromate, calcium chromate, lead zirconate, barium titanate, lead chromite titanate, lead magnesium citrate-lead titanate Or a film comprising any two or more of solid solutions or a laminate of two or more of them. The manufacturing method of a material for a multilayer wiring board in which a capacitor is provided in any one of claims 6 to 10, wherein the metal foil is made of copper and forms a surface of a dielectric film. A metal film is disposed, and the metal film is an oxidized protective film of copper, and the metal forming the oxidized protective film of copper is selected from the group consisting of platinum, gold, silver, palladium, rhodium, and iridium. More than one species. A method for producing a material for a multilayer wiring board in which a capacitor is provided in any one of claims 6 to 10, wherein the metal foil is made of copper and a metal film is provided on the surface thereof. The metal film is a self-oxidizing film which is stable in stability, and the metal which forms the stable self-oxidizing film is one or more selected from the group consisting of chromium, molybdenum, titanium, and nickel. 1 5 . A method for producing a material for a multilayer wiring board in which a capacitor is provided in any one of claims 6 to 10, wherein -147- (4) 1251536 has a surface roughness of 0. 01~1 6 . a method for manufacturing a multilayer wiring board with a built-in capacitor, wherein a capacitor having a dielectric constant of 10 to 2000 and a film thickness of 〇·〇5 to 2 //m is disposed on the surface of the metal foil. The material for a multilayer wiring board is characterized by: 1) a step of laminating a substrate having a conductor circuit with a prepreg for a metal foil surface of a material for a multilayer wiring board on which a capacitor is provided; 2) for dielectric properties a step of forming a metal layer of 10 to 50 / / m on the surface of the film; 3) etching to remove any portion of the metal layer to form a desired first capacitor electrode; 4) retaining at least dielectric And removing any portion of the first capacitor electrode of the thin film to form a desired capacitor dielectric; and 5) removing at least any portion of the capacitor dielectric exposed by removing the dielectric film The etching is removed to form a conductor pattern containing a desired second capacitor electrode. 1 7 . The method of manufacturing a multilayer wiring board having a capacitor as set forth in claim 16 wherein the metal layer formed on the surface of the dielectric film contains at least a group consisting of chromium, molybdenum, titanium, and nickel. A method for manufacturing a multilayer wiring board in which a plurality of metal layers selected from the group are selected from the group consisting of a metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 〇. 〇5~2 -148· (5) 1251536 // m dielectric film is a material for a multilayer wiring board in which a capacitor is provided, which is characterized by: 1) a material for a multilayer wiring board for a built-in capacitor On the metal foil surface, a step of laminating a substrate having a conductor circuit using a prepreg; 2) forming a surface on the surface of the dielectric film. a step of forming a metal layer of 1 to 5//m; 3) a step of forming a metal plating resist layer in such a manner as to retain any portion of the first capacitor electrode; 4) forming a metal oxide ore to form 1〇~50/ /m brother 1 capacitor electrode step; 5) to remove the metal plating anti-crack layer step; 6) to remove the surface formed on the dielectric film 0. a step of a metal layer of 1 to 5 Å/m; 7) a step of etching to remove any portion of the first capacitor electrode containing at least a dielectric film to form a desired capacitor dielectric; and 8) The step of etching to remove at least a portion of the capacitor dielectric of the metal layer exposed by removing the dielectric film to form a conductor pattern containing the desired second capacitor electrode is performed. A manufacturing method of a multilayer wiring board having a capacitor as set forth in claim 18, wherein the metal layer formed on the surface of the dielectric film contains at least chromium chrome-titanium and nickel. One or more metal layers selected by the group. -149- (6) 1251536 20. A method of manufacturing a multilayer wiring board having a capacitor provided in the 18th or 19th aspect of the patent application, wherein the metal plating includes at least one selected from the group consisting of copper, silver, tin, nickel, and zinc. metal. 2 1 · A method for manufacturing a multilayer wiring board with a built-in capacitor, the surface of the metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 〇. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2, which is characterized by: 1) a layer of a prepreg for use on a metal foil surface of a material for a multilayer wiring board in which a capacitor is provided a step of forming a substrate of a conductor circuit; 2) forming a desired metal layer by forming a metal layer of a conductive paste by a chemical reaction in any part of the surface of the dielectric film to form a metal layer of 1 〇 to 5 0 // m a step of a capacitor electrode; 3) a step of etching to remove a portion of the first capacitor electrode containing at least a dielectric film to form a desired capacitor dielectric; and 4) removing the dielectric by retention The step of etching the film to expose at least any portion of the capacitor dielectric to form a conductor pattern containing the desired second capacitor electrode. twenty two. A method for producing a multilayer wiring board in which a capacitor is provided in claim 21, wherein the metal particles of the conductive paste which are metallized by a chemical reaction contain at least gold, platinum, silver, copper, palladium, and rhodium One or more metals selected from the group consisting of, and the average particle diameter is 〇. 1~l〇nm. -150- (7) 1251536 23 . - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the surface of the metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2, which is characterized by: 1) a layer of a prepreg used on a metal foil surface of a material for a multilayer wiring board in which a capacitor is provided. a step of a substrate having a conductor circuit; 2) a step of etching away any portion of the dielectric film to form a desired dielectric of the capacitor; 3) forming a surface of the substrate on which the capacitor dielectric is formed a step of a metal layer of 10 to 50 //m; and 4) etching and removing away any part of the metal layer to form a desired first capacitor electrode, a second capacitor electrode, and a capacitor electrode electrically insulated The step of any conductor pattern. twenty four. A method of manufacturing a multilayer wiring board having a capacitor built in any one of the claims 16 to 19 and 21 to 23, wherein a surface area of the metal foil is 10 to 2000 and a film thickness is 0. . a through-hole of an insulating material is disposed on any portion of the metal foil surface of the material for the multilayer wiring board in which the capacitor is provided in the dielectric film of the 05~ and the prepreg in which the substrate having the conductor circuit is laminated, and the through hole is The conductive paste containing a thermosetting resin and a metal tantalum is filled. 2 5. A method of manufacturing a multilayer wiring board having a capacitor built in any one of the claims 16 to 19 and 21 to 23, wherein a surface area of the metal foil is 10 to 2000 and a film thickness is 0. . Multilayer wiring board with capacitors in the dielectric film of 05~2//m -151 - (8) 1251536 Arranged on any part of the prepreg that is laminated with the metal foil surface of the material and the substrate with the conductor circuit A through hole of the insulating material, and the through hole is filled with a conductive paste which is metallized by a chemical reaction. 2 6. - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the surface of the metal crucible is provided with a permittivity of 10 to 2000 and a film thickness of 〇. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 〇5 to 2/m, which is characterized by: 1) a prepreg for using a metal foil surface of a material for a multilayer wiring board of a built-in capacitor; a step of laminating a substrate having a conductor circuit; 2) a step of forming a metal layer of 10 to 50/m on the surface of the dielectric film; 3) etching and removing any portion of the metal layer to form a desired a step of the first capacitor electrode; 4) a step of etching to remove any portion of the first capacitor electrode containing at least the dielectric film to form a desired capacitor dielectric; 5) for removing by etching a step of exposing the dielectric layer to an exposed portion of the prepreg; 6) removing the exposed insulating layer by laser irradiation to form a hole to expose the inner conductor circuit; 7) To form a 0. on the surface of the substrate. a step of forming a metal layer of 1 to 5//m; 8) a step of forming a plating resist layer on a portion other than any portion containing the hole; -152- 1251536 Ο) 9) at a portion where the plating resist layer is formed a step of forming a metal layer of 10 to 5 0 // m on the surface of the substrate for electrically connecting the circuit patterns between the layers, and 10) performing etching removal on the 0·1 to metal layer formed on the surface of the substrate And 1 1) etching is performed to retain at least any portion including the capacitor dielectric and the via hole to form a conductor pattern including the desired second capacitor electrode. 2 7 . A method of manufacturing a multilayer wiring board having a capacitor built in the sixth aspect of the patent application, wherein the metal layer formed on the surface of the dielectric film contains at least a group selected from the group consisting of chromium, molybdenum, titanium, and nickel. One or more metal layers 〇 2 8. - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the surface of the metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2, which is characterized by: 1) a layer of a prepreg used on a metal foil surface of a material for a multilayer wiring board in which a capacitor is provided. have. The step of the substrate of the conductor circuit; 2) for forming a surface on the surface of the dielectric film. a step of a metal layer of 1 to 5//m; 3) a step of forming a metal plating resist layer in such a manner as to retain any portion of the first capacitor electrode; 4) for forming 10 to 50// by metal plating The first capacitor of m is -153- (10) 1251536 electrode step; 5) the step of removing the metal plating resist layer; 6) etching to remove the 01~5//m formed on the surface of the dielectric film a step of a metal layer; 7) a step of etching to remove a portion of the first capacitor electrode containing at least a dielectric film to form a desired capacitor dielectric; 8) for removing the dielectric by etching a step of exposing any portion of the thin film to expose the insulating layer of the cured prepreg; 9) removing the exposed insulating layer by laser irradiation to form a hole, exposing the inner layer of the conductor circuit, and exposing the inner layer Step 10) of the conductor circuit is used to form a surface on the surface of the substrate. a step of forming a metal layer of 1 to 5/m; 1) a step of forming a plating resist layer on a portion other than the portion containing the hole; 1 2) a surface of the substrate other than the portion where the plating resist layer is formed Forming a metal layer of 10 to 5 0 // m for electrically connecting the circuit patterns between the layers; 13) for forming a surface formed on the surface of the substrate. a step of etching away the metal layer of 1 to 5//m; and 14) etching and removing at least any portion including the capacitor dielectric and the via hole to form a desired second The step of the conductor pattern of the capacitor electrode. -154- (11) 1251536 29. A method of manufacturing a multilayer wiring board having a capacitor provided in claim 28, wherein the metal layer formed on the surface of the dielectric film contains at least a group selected from the group consisting of chromium, molybdenum, titanium, and nickel. More than one metal layer. 3 0. A method of manufacturing a multilayer wiring board having a capacitor built in the 28th or 29th aspect of the patent application, wherein the metal plating includes at least one selected from the group consisting of copper, silver, tin, nickel, and zinc. metal. 3 1 . - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the surface of the metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2, which is characterized by: 1) a layer of a prepreg used on a metal foil surface of a material for a multilayer wiring board in which a capacitor is provided. a step of forming a substrate of a conductor circuit; 2) forming a desired metal layer by forming a metal layer of 10 to 50/m in a conductive paste by chemical reaction on any portion of the surface of the dielectric film. a step of a capacitor electrode; 3) a step of etching to remove a portion of the first capacitor electrode containing at least a dielectric film to form a desired capacitor dielectric; 4) for removing the dielectric by etching a step of exposing any portion of the film to the exposed portion, and exposing the insulating layer of the cured prepreg, 5) removing the exposed insulating layer by laser irradiation to form a hole 'to expose the conductor circuit of the inner layer; -155 (12) 1251536 6) used to form 0 on the surface of the substrate. a step of forming a metal layer of 1 to 5//m; 7) a step of forming a plating resist layer on a portion other than the portion containing the hole; 8) forming a surface of the substrate other than the portion where the plating resist layer is formed Oh. 〜5 0 / / m metal layer, used to electrically connect the circuit pattern between the layers of the step 9) used to etch away the surface formed on the substrate 0. a step of a metal layer of 1 to 5//m; and 10) etching and removing at least any portion including a capacitor dielectric and a via hole to form a desired second capacitor electrode The step of the conductor pattern. 3 2 . A method for producing a multilayer wiring board in which a capacitor is provided in a 31st patent application, wherein the metal particles of the conductive paste which are metallized by a chemical reaction contain at least gold, platinum, silver, copper, palladium, and rhodium At least one metal selected from the group consisting of, and having an average particle diameter of 〇·1~1 Onm 〇3 3 . - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the surface of the metal foil is provided with a permittivity of 10 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2, which is characterized by: 1) a layer of a prepreg used on a metal foil surface of a material for a multilayer wiring board in which a capacitor is provided. a step of a substrate having a conductor circuit; - 156-(13) 1251536 2) a step of removing uranium engraving by retaining any portion of the dielectric film to form a desired capacitor dielectric; 3) etching to remove the cause a step of removing the dielectric layer and exposing the insulating layer of the hardened prepreg; 4) removing the exposed insulating layer by laser irradiation to form a hole to expose the conductor circuit of the inner layer; 5) a step of forming a metal layer of 10 to 50 #m on the surface of the substrate on which the capacitor dielectric is formed and the surface in the hole; and 6) retaining at least any portion including the dielectric of the capacitor and the hole of the conductor The way to enter. The step of etching is removed to form a conductor pattern containing the desired second capacitor electrode. 34. For example, the patent scope is 16~19, 21~23, 26~29, and. A manufacturing method of a multilayer wiring board in which a capacitor is provided in any one of the items 1 to 3, wherein a prepreg is laminated on the surface of the metal foil with a permittivity of 10 to 2000 and a film thickness of 0_05 to 2//m. In the dielectric film, a substrate having a conductor circuit on a metal foil surface of a material for a multilayer wiring board is provided, and the conductor layer of the substrate is two or more layers, and the circuit pattern of the adjacent conductor layer is used in any part. The substrate is connected to the hole. 35. A method of manufacturing a multilayer wiring board having a capacitor provided in any one of claims 16 to 19, 21 to 23, 26 to 29, and 3 to 3, wherein the etching removes the dielectric film The method is an ion beam etching method, a RIE (Reactive Ion Etching) method, or a solution etching method, which is a method of -157-(14) 1251536. 3 6. A method of manufacturing a multilayer wiring board in which a capacitor is provided in any one of claims 16 to 19, 21 to 23, 26 to 29, and 3 to 3, wherein the second capacitor electrode is a multilayer wiring board Ground plane or power plane. 3 7. A method of manufacturing a multilayer wiring board with a capacitor built in any one of claims 16 to 19, 21 to 23, 26 to 29, and 3 to 3, wherein the insulating material of the substrate is made of a resin, And glass woven fabric or glass non-woven fabric. 38. A method of manufacturing a multilayer wiring board with a capacitor built in any one of claims 16 to 19, 21 to 23, 26 to 29, and 3 to 3, wherein the resin used for the insulating material of the substrate A thermosetting resin having a glass transition point temperature of 170 ° C or higher. The substrate for a multilayer wiring board in which a capacitor is provided is characterized in that a substrate having a through hole between the conductor layers and a metal layer having a smooth surface has a permittivity of 10 to 2000. The film thickness is 0. 05~2#m dielectric film. 40. The substrate for a multilayer wiring board in which a capacitor is provided in the 39th aspect of the patent application, wherein the through hole is electrically connected by metal plating. 4 1 . A multi-layer wiring of a capacitor of the ninth aspect of the patent application-158- (15) 1251536, wherein the through-hole is electrically connected by a conductive paste composed of a metal tantalum and a resin. 4-2. The substrate for a multi-layer wiring board in which a capacitor is provided in the third or fourth aspect of the patent application, wherein the through-hole is electrically connected by a conductive paste which is metallized by a chemical reaction. 4 3 . A substrate for a multilayer wiring board having a capacitor, wherein the dielectric film is made of barium titanate or barium titanate, as claimed in any one of claims ninth to fourteenth. Any one of calcium titanate, magnesium titanate, lead titanate, barium titanate, titanium dioxide, barium zirconate, calcium chromate, lead chromate, or a solid solution containing two or more of them, or containing A film composed of two or more kinds of laminates. 44. A substrate for a multilayer wiring board in which a capacitor is provided in any one of claims 39 to 41, wherein 'the method of forming the dielectric thin film is vacuum evaporation, ion plating, CVD, CVD (Chemical Vapor Deposition) method, beach plating method, and sol-gel method. 4 5. The substrate for a multilayer wiring board in which a capacitor is provided in any one of claims 39 to 41, wherein the dielectric film is formed at a substrate temperature of 25 ° C to 350 t. 46. The substrate for a multilayer wiring board having a capacitor according to any one of claims 39 to 41, wherein the insulating material of the substrate is made of a resin, and a glass woven fabric or g $-159- (16) 1251536 Woven fabric. 4 7 . The substrate for a multilayer wiring board in which a capacitor is provided in any one of the above-mentioned claims, wherein the insulating material of the substrate is a resin-based thermosetting resin having a glass transition point temperature of Above 170 °C. 4 8 . The substrate for a multilayer wiring board in which a capacitor is provided in any one of the above-mentioned claims, wherein the metal layer is made of copper, and an oxidized protective film of copper is disposed on the surface thereof. The metal is one or more selected from the group consisting of platinum, gold, silver, palladium, rhodium, and iridium. 4 9. The substrate for a multilayer wiring board in which a capacitor is provided in any one of claims 39 to 41, wherein the metal layer is made of copper, and a metal film is disposed on a surface thereof. The self-oxidation coating film forms at least one selected from the group consisting of chromium, molybdenum, titanium, and nickel. 50. A substrate for a multilayer wiring board having a capacitor, wherein the surface roughness of the metal layer is 0. 01~0. 5// m. 5 1 . A method for manufacturing a multilayer wiring board in which a capacitor is built is used as an inner layer board using a substrate for a multilayer wiring board in which a capacitor is provided in any one of claims 30 to 50, and is characterized in that The method has the following steps: 1) forming a 10~ metal layer-160-(17) 1251536 on the surface of the dielectric film; 2) etching and removing any part of the metal layer to form a desired first capacitor a step of an electrode; 3) etching to remove a portion of the first capacitor electrode containing at least the dielectric film to form a desired capacitor dielectric; and 4) retaining at least a dielectric removal The step of etching and removing any portion of the capacitor dielectric of the metal layer exposed by the thin film to form a conductor pattern containing the desired second capacitor electrode. 52. The method of manufacturing a multilayer wiring board having a capacitor as set forth in claim 51, wherein the metal layer formed on the surface of the dielectric film contains at least a group consisting of chromium, molybdenum, titanium, and nickel. One or more metal layers selected. 5 3 - a method for manufacturing a multilayer wiring board in which a capacitor is built, which is used as an inner layer board using a substrate for a multilayer wiring board in which a capacitor is provided in any one of claims 30 to 50 The method has the following features: 1) forming a surface on the surface of the dielectric film. a step of forming a metal layer of 1 to 5/zm; 2) a step of forming a metal plating resist layer in such a manner as to retain any portion of the electrode of the first capacitor; 3) forming 1 to 50//m by metal plating a step of the first capacitor electrode; 4) a step of removing the metal plating resist layer; -161 - (18) 1251536 5) for etching away the surface formed on the surface of the dielectric film 〜 5// a step of the metal layer of m; 6) etching to remove any portion of the first capacitor electrode containing at least the dielectric film to form a desired capacitor dielectric; and 7) retaining at least The step of etching to remove a conductor pattern containing a desired second capacitor electrode is performed by removing any portion of the capacitor dielectric of the metal layer exposed by the dielectric film. 5 4 . The method for manufacturing a multilayer wiring board having a capacitor in the fifth aspect of the patent application, wherein the metal layer formed on the surface of the dielectric film contains at least a group consisting of complex, molybdenum, titanium, and nickel. One or more metal layers selected from the group. 55. A method of manufacturing a layer wiring board, wherein the metal plating includes at least one selected from the group consisting of copper, silver, tin, nickel, and zinc, as in the case of the patent application No. 53 or 54; The above metal. 5 6 - a method for manufacturing a multilayer wiring board with a built-in capacitor, which is used as an inner layer board using a substrate for a multilayer wiring board in which a capacitor is provided in any one of claims 30 to 50 The method has the following steps: 1) forming a desired first capacitor electrode by forming a metal layer of 10 to 50 #m by using a conductive paste formed by chemical reaction in any part of the surface of the dielectric film; 2) performing etching removal in such a manner as to retain any portion of the first capacitor electrode containing at least the dielectric thin film to form a desired capacitor dielectric-162-(19) 1251536; and 3) retaining at least The step of etching to remove a conductor pattern containing a desired second capacitor electrode is performed by removing any portion of the capacitor dielectric of the metal layer exposed by the dielectric film. 5 7 . The method for manufacturing a multilayer wiring board having a capacitor in the 56th aspect of the patent application, wherein the metal particles of the conductive paste which are subjected to metallization by chemical reaction contain at least gold, platinum, silver, copper, palladium, And one or more metals selected from the group formed by the crucible, and the average particle diameter thereof is 0. 1 to 10 nm. 58. A method of manufacturing a multilayer wiring board in which a capacitor is provided, which is used as an inner layer board using a substrate for a multilayer wiring board in which a capacitor is provided in any one of claims 39 to 50, which is characterized in that 1) a step of etching to remove any portion of the dielectric film to form a desired capacitor dielectric; 2) forming a thickness of 1 〇 50 50 m on the surface of the substrate on which the capacitor dielectric is formed And a step of etching to remove any desired portion of the metal layer to form a desired first capacitor electrode, a second capacitor electrode, and a capacitor conductor that is electrically insulated from any conductor pattern. 5 9. A method of manufacturing a multilayer wiring board with a capacitor built in any one of claims 5 to 5 and 5 to 5, wherein the method of etching and removing the dielectric film is ion beam etching. Method, RIE (-163- (20) 1251536 1 Q t! E tching ) method, or solution etching method. 6〇. For example, the manufacturing method of the multilayer wiring board in which the capacitor is included in any of the patent scopes 5 to 54 and the patent range 5-6 to 5 R, wherein the second extraction container electrode system Ground plane or power plane of a multilayer wiring board. 61 ~ The multilayer wiring board of the capacitor with a built-in capacitor has a plurality of insulation layers, a stomach layer, and an electrical connection for performing the electrical connection of the conductor layer, and the dielectric film is a permittivity of at least one layer of the insulating layer. The electrode is 20 to 2000 and has a film thickness of 〇1 to 1 #m and has an electrode opposite to the insulating layer. The conductor layer pattern forming the first capacitor electrode forms an electrode of all the capacitors, and 2) the dielectric material The projection surface of the film includes a projection surface of the first capacitor electrode, and 3) the conductor layer forming the second capacitor electrode has a second capacitor electrode 'and at least one pattern electrically insulated from the electrode. 62. A multilayer wiring board having a capacitor, comprising a plurality of insulating layers, a plurality of conductor layers, and a via hole for electrically connecting the conductor layers, wherein the dielectric film is at least one layer The electric layer ratio of the insulating layer is 20 to 2000 and the film thickness is 0. 1 to Ivm, and having an electrode opposite to the insulating layer, characterized by: 1) a first capacitor electrode having a dielectric film projection of a dielectric forming a capacitor, -164-(21) 1251536 2 All of the conductor layers forming the first capacitor electrode at the ends of the dielectric film are electrically connected to the second capacitor electrode. 63. A multi-layer wiring board having a capacitor provided in the scope of claim 6 or 62, wherein the second capacitor electrode is a ground layer or a power supply layer of the multilayer wiring board. 64. For example, a multi-layer wiring board with a capacitor built in the 61st or 62th patent application, wherein the dielectric film is made of barium titanate, total titanate, calcium titanate, magnesium titanate, lead titanate, barium titanate, titanium dioxide. A film comprising any one of strontium chromate, calcium zirconate, and lead chromate, or a solid solution containing two or more of them, or a laminate comprising two or more of them. 6 5. For example, a multi-layer wiring board of a capacitor is provided in the 61st or 62nd patent application, wherein the insulating material of the substrate is composed of a resin, a glass woven fabric or a glass non-woven fabric. 66. For example, a multi-layer wiring board in which a capacitor is provided in the 61st or 62nd patent application, wherein the resin-based thermosetting resin used for the insulating material of the substrate has a glass transition point temperature of 17 〇 ° C or more. 6 7. For example, a multilayer wiring board having a capacitor built in the 61st or 62th patent application, wherein the second capacitor electrode is made of copper, and the surface thereof contains platinum, gold, silver, palladium, rhodium, iridium, chromium, molybdenum, titanium, And at least one metal layer selected from the group consisting of nickel. -165- (22) 1251536 6 8. For example, the multi-layer wiring board of the capacitor is provided in the 61st or 62th patent application, wherein the surface roughness of the second capacitor electrode is 0. 01~0. 5em. 6 9. A multi-layer wiring board having a capacitor built in the 61st or 62th patent application, wherein the first capacitor electrode is selected from the group consisting of copper, silver, tin, nickel, zinc, chromium, molybdenum, titanium, and nickel. At least one or more metal layers. 70. For example, a multi-layer wiring board with a capacitor built in Article 61 or 62 of the patent application area, wherein . The first capacitor electrode is made of a conductive paste which is metallized by a chemical reaction, and the metal contains at least one metal selected from the group consisting of platinum, gold, silver, copper, tin, palladium, and rhodium. . 71. A semiconductor device characterized in that a semiconductor wafer is placed on a multilayer wiring board in which a capacitor is provided as in any one of claims 61 to 70. 72. - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the metal foil is provided with a single-sided capacitance ratio of 1 〇 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2/m is disposed on at least one side of the insulating material in a manner that the metal foil is in contact with the insulating material, and is characterized by: 1) The step of forming a metal layer as a capacitor electrode at a specific position on the dielectric film on the surface of the substrate; 2) forming an etching resist layer-166-(23) 1251536 on at least the aforementioned metal layer on the surface of the substrate 3) performing a wet etching step of the dielectric film using an etchant containing a chelating agent and hydrogen peroxide; and 4) removing the etching resist layer after the wet etching. 73. A method of manufacturing a multilayer wiring board having a capacitor as set forth in claim 72, wherein the concentration of the etchant is 0. 001~〇. 5 mol/l, and the hydrogen peroxide concentration is 1 to 50% by weight, and the pH of the etchant is in the range of 2 to 7. 74. A method of manufacturing a multilayer wiring board having a capacitor as set forth in claim 72 or 73, wherein the chelating agent is derived from ethylenediaminetetraacetic acid (EDTA), hydroxy ethylimino diacetic acid (HID A ), and imino diacetic acid ( At least one selected from the group consisting of IDA), dihydroxyethyl glycine (DHEG), and these alkali salts. 75 . A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein a capacitor having a capacitance of 1 〇 to 2000 and a film thickness of (K05 〜2//m dielectric film) is disposed on one side of the metal foil The material for the multi-layer wiring board is disposed on the substrate on at least one side of the insulating material in such a manner that the metal foil contacts the insulating material, and is characterized in that: 1) is formed at a specific position on the dielectric film on the surface of the substrate. The step of using a metal layer for the capacitor electrode; 2) the step of forming an etch resist layer on at least the aforementioned metal layer on the surface of the substrate; 3) utilizing from the sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid, and acetic acid -167- (24 1251536 a step of performing wet etching of a dielectric film by at least one acid selected from the group consisting of hydrogen and an etchant layer of hydrogen peroxide; and 4) a step of removing the etching resist after wet etching. 7 6 · A method for manufacturing a multilayer wiring board having a capacitor as set forth in claim 75, wherein the acid concentration of the feeding agent is 1 to 3 Owt%, and the hydrogen peroxide concentration is 1 to 5 0 wt % 〇 77. A method of manufacturing a multilayer wiring board in which a capacitor is provided in any one of claims 72, 73, 75, and 76, wherein a photosensitive dry film is used for etching the resist layer. 7 8 . The method for producing a multilayer wiring board having a capacitor in the seventh aspect of the patent application, wherein the film thickness of the photosensitive dry film is not performed by using an etching resist formed of a photosensitive dry film Wet etching is used as 1 to 3 times the thickness of the metal layer used for the capacitor electrode. 79. A method for manufacturing a multilayer wiring board of the electric grid Yi 1 according to any one of the claims 72, 73, 75, and 76, wherein the wet etching of the dielectric film is performed at a liquid temperature of 2 0~ 4 5 °C hungry agent implementation. 80. A method of manufacturing a multilayer wiring board with a capacitor built in any one of the claims 72, 73, 75, and 76, wherein the dielectric film is made of barium titanate, barium titanate, calcium titanate, Any one of phthalate, lead acid, barium titanate, titanium dioxide, barium acid, chromic acid, and lead acid, or a solid solution containing two or more of them, or 168- (25) 1251536 A film composed of two or more layers of a laminate. 8 1 . - A method for manufacturing a multilayer wiring board with a built-in capacitor is adopted. The metal foil A is provided with a single-sided capacitance ratio of 1 〇 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2, which is characterized by: 1) a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided, and a metal foil is formed of an insulating material a step of forming a substrate by laminating B; 2) performing a step of removing an arbitrary portion of the metal foil B to expose the insulating layer formed of the insulating material; 3) removing the exposed insulating layer by laser irradiation to form a hole a step of exposing the metal foil A; 4) a step of forming a metal layer on both sides of the surface of the substrate including the holes; 5) forming a metal layer on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed a step of arbitrarily forming a first capacitor electrode pattern; 6) a step of etching a dielectric film having an arbitrary shape of a first capacitor electrode pattern by etching the exposed dielectric film; and 7) removing the dielectric film The exposed metal foil A is etched to form a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern. 8 2 . A method for manufacturing a multilayer wiring board with a built-in capacitor, which is a method for manufacturing a multilayer wiring board having a capacitor built in the scope of claim No. 81, characterized in that: -169- (26) 1251536 5 ) or 7 ) In the etching step, a circuit of an arbitrary shape is formed on the surface of the substrate on which the metal foil B is laminated. 8 3 . A method for manufacturing a multilayer wiring board with a built-in capacitor is to use a metal foil A with a single-sided configuration with a permittivity of 10 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2/m, which is characterized in that: 1) a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided is made of an insulating material. Step of forming a substrate by laminating B; 2) performing a laser irradiation on any portion of the metal foil B, removing the metal foil B and the insulating layer formed by the insulating material to form a hole, and exposing the metal foil A 3) a step of forming a metal layer on both sides of the surface of the substrate including the hole; 4) etching the metal layer on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed to form the first capacitor electrode of an arbitrary shape a step of patterning; 5) a step of etching to form a capacitor dielectric having an arbitrary shape of the first capacitor electrode pattern on the exposed dielectric film; and 6) etching the metal foil A exposed to remove the dielectric film A step of forming a second capacitor electrode having an arbitrary shape of a capacitor dielectric pattern is formed. 84. A method of manufacturing a multilayer wiring board with a built-in capacitor, such as a method for manufacturing a multilayer wiring board having a capacitor built in Article 83 of the patent scope, characterized by: -170- (27) (27) 1251536 4 Or in the etching step of 6) 'forming a circuit of any shape on the surface of the substrate on which the metal foil B is laminated. - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the metal foil A is provided with a single-sided capacitance ratio of 10 to 2000 and a film thickness of 〇. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 〇5 to 2 //2, and is characterized in that: 1) an arbitrary portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided a step of forming a substrate by inserting a through-hole with a conductive paste containing a thermosetting resin and a metal tantalum, and laminating the metal foil B with an insulating material; 2) at least a dielectric on the surface of the substrate a step of forming a metal layer on the film side; 3) a step of etching a metal layer on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed to form a first capacitor electrode pattern of an arbitrary shape; 4) exposing the exposed dielectric a step of etching to form a capacitor dielectric having an arbitrary shape of the first capacitor electrode pattern; and 5) etching the metal foil A exposed to remove the dielectric film to form an arbitrary shape including a capacitor dielectric pattern The step of the second capacitor electrode. 8 6 . - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the metal foil A is provided with a single-sided capacitance ratio of 1 〇 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 〇5 to 2/2, which is characterized by having: -171 - (28) 1251536 1) a metal foil of a material for a multilayer wiring board in which a capacitor is provided a step of arranging a through hole at any portion of the A surface, filling the through hole with a conductive paste which is metallized by a chemical reaction, and forming a substrate by laminating the metal foil B with an insulating material; 2) at the surface of the substrate a step of forming a metal layer on at least the dielectric film side; 3) a step of etching a metal layer on the dielectric film of the material for the multilayer wiring board in which the capacitor is formed to form a first capacitor electrode pattern of an arbitrary shape; 4) a step of etching the dielectric film to form a capacitor dielectric having an arbitrary shape of the first capacitor electrode pattern; and 5) forming a capacitor-containing dielectric pattern by etching the metal foil A exposed by removing the dielectric film The step of the second capacitor electrode of any shape. 8 7. A method for manufacturing a multilayer wiring board with a built-in capacitor, which is a method for manufacturing a multilayer wiring board having a capacitor built in claim 85 or 86, which is characterized in that: in the etching step of 3) or 5), in the substrate A circuit of any shape is formed on the surface of the metal foil B. 8 8 . The method for manufacturing a multilayer wiring board with a capacitor built in any one of claims 8 to 8 in which a chromium, molybdenum, titanium is formed between the dielectric film and the metal layer And the step of at least one other metal layer selected by the group consisting of nickel. -172- (29) (29)1251536 8 9 · A method for manufacturing a multilayer wiring board with a built-in capacitor is to use a metal foil A with a single-sided capacitance ratio of 10 to 2000 and a film thickness of 〇. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 〇5 to 2/m, which is characterized in that: 1) a metal surface of a material for a multilayer wiring board in which a capacitor is provided is made of an insulating material. a step of forming a substrate by laminating the foil B; 2) performing an etching removal of any portion of the metal foil B to expose the insulating layer formed of the insulating material; 3) removing the exposed insulating layer by laser irradiation to form a hole, And the step of exposing the metal foil A; 4) forming a zero on both sides of the substrate including the hole. a step of forming a metal layer of 1 to 5/m; 5) a step of forming a metal plating resist on the surface of the substrate by retaining the portion used as the first capacitor electrode and any portion of the portion; a step of forming a conductor pattern by using metal plating as a part of the first capacitor electrode and a portion containing the hole; 7) a step of removing the metal plating resist; 8) etching removing the surface from the substrate 0. a step of a metal layer of 1 to 5 // m; 9) a step of etching a dielectric film having an arbitrary shape of the first capacitor electrode pattern by etching the exposed dielectric film; 1 〇) removing the dielectric film And the exposed metal foil A is etched to form a second capacitor electrode having a shape of a capacitor dielectric pattern of -173- (30) 1251536; and 1 1) etching the exposed metal foil B to form a circuit . 9 0. - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the metal foil A is provided with a single-sided capacitance ratio of 10 to 2000 and a film thickness of 〇. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 〇5 to 2/m, which is characterized in that: ^ a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided is made of a metal material using a rim material a step of forming a substrate by laminating the foil B; 2) performing laser irradiation on any portion of the metal foil B, removing the metal foil B, and an insulating layer formed of the insulating material to form a hole, thereby exposing the metal foil A Steps; 3) Forming 0 on both sides of the substrate including the holes. a step of a metal layer of 1 to 5/m; 4) a step of forming a metal plating resist on the surface of the substrate by retaining the portion used as the first capacitor electrode and containing any portion of the ?L portion 5) a step of forming a conductor pattern by using metal plating as a part of the first capacitor electrode and a portion containing the hole; 6) a step of removing the metal plating resist; 7) for starving Remove the exposed substrate surface. a step of a metal layer of 1 to 5 #m; 8) a step of etching a dielectric film having an arbitrary shape of the first capacitor electrode pattern by etching the exposed dielectric film; 9) exposing the dielectric film The metal foil A forms a second capacitor electrode having an arbitrary shape of a dielectric-174-(31) 1251536 container dielectric pattern; and 1) a step of etching the exposed metal foil B to form a circuit. 9 1 · A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the metal foil A is provided with a single-sided capacitance of 10 〜 200 00 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 〇5 to 2//m, and is characterized in that: 1) an arbitrary portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided a step of forming a substrate by inserting a through-hole with a conductive paste containing a thermosetting resin and a metal tantalum, and forming a substrate by laminating the metal foil B with a prepreg; 2) at least a dielectric film side of the substrate The surface forms 0. a step of a metal layer of 1 to 5 //m; 3) a step of forming a metal plating resist on the surface of the substrate in such a manner as to retain any portion of the portion used as the first capacitor electrode; 4) using metal plating a step of forming a conductor pattern in a portion containing the portion used as the first capacitor electrode; 5) a step of removing the metal plating resist layer; 6) etching to remove the exposed substrate surface. a step of a metal layer of 1 to 5 #m; 7) a step of etching a dielectric film having an arbitrary shape of the first capacitor electrode pattern by etching the exposed dielectric film; and 8) removing the dielectric film The exposed metal foil A is etched to form a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern, and -175-(32) 1251536 is a step of etching the exposed metal foil B to form a circuit. 92. A method for manufacturing a multilayer wiring board with a built-in capacitor is to use a metal foil A with a single capacitance of 10 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2 μm, which is characterized in that: 1) a through hole is provided in any portion of the metal foil A surface of the material for the multilayer wiring board in which the capacitor is provided. And a step of forming a substrate by laminating the conductive paste with a metallization by a chemical reaction, and forming a substrate by laminating the metal foil B with a prepreg; 2) forming a surface on the surface of at least the dielectric film side of the substrate. a step of a metal layer of 1 to 5 // m; _ 3) a step of forming a metal plating resist on the surface of the substrate in such a manner as to retain any portion of the portion used as the first capacitor electrode; 4) using metal The step of forming a conductor pattern on the portion containing the portion used as the first capacitor electrode; 5) the step of removing the metal plating resist layer; 6) etching to remove the exposed substrate surface. a step of a metal layer of 1 to 5//m; 7) a step of etching a dielectric film having an arbitrary shape of the first capacitor electrode pattern by etching the exposed dielectric film; and 8) removing the dielectric film The exposed metal foil A is formed by etching a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern, and etching the exposed metal foil B to form a circuit. 9 3 · A method for manufacturing a multilayer wiring board of -176- (33) 1251536 capacitor, as described in any one of claims 8 9 to 9 2, wherein at least 0 is formed on the surface of the dielectric film. The gold of 1~5/im is: (1) one less metal layer selected from the group consisting of chromium, molybdenum, titanium, and nickel, or (2) from copper, silver, tin, nickel, and At least one metal layer selected from the group, or (3) at least one metal selected from the group consisting of titanium, and nickel, and composed of copper, silver, tin, nickel, and zinc The metal layer of the species selected by the group. 94. The method for manufacturing a multilayer wiring board of any one of the capacitors of the invention, wherein the conductor pattern formed by metal plating contains at least a group consisting of copper, silver, and zinc. More than one type of gold 9 5. A method for manufacturing a multilayer wiring board in which a capacitor is provided is a multilayer wiring board in which a capacitor having a dielectric constant of 10 to 2000 and a film thickness of 1/2/m is provided on one surface of the metal foil A. It is characterized in that: 1) a through hole is formed in any portion of the metal fi of the material for the multilayer wiring board in which the capacitor is provided, and the through hole is filled with a conductive paste containing a thermosetting resin and a material, and the insulating material is used. a step of forming a layer of B to form a substrate; 2) forming a metal layer on a portion of the surface of the dielectric film with a chemically metallized conductive paste to form a desired container electrode; 3) retaining The first capacitor layer containing at least a dielectric film contains a chromium or molybdenum layer formed of zinc; and at least one of tin and mirror is provided. , the profit is 0. 0 5 Materials! A-side metal ruthenium metal foil reaction 1st electric electrode -177- (34) 1251536 Any part of the way to remove the etching to form the desired capacitor dielectric; and 4) The metal foil A exposed by the electric thin film is etched to form a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern, and the exposed metal foil B is etched to form a circuit. 96. A method for manufacturing a multilayer wiring board with a built-in capacitor is to use a metal foil A with a single-sided configuration with a permittivity of 10 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2/m, which is characterized in that: 1) an arbitrary portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided is disposed. a step of forming a substrate by filling a through hole with a conductive paste which is metallized by a chemical reaction, and forming a substrate by laminating a metal foil B with an insulating material; 2) at any part of the surface of the dielectric film, a step of forming a metal layer by a metallization conductive paste by a chemical reaction to form a desired first capacitor electrode; 3) etching and removing any portion of the first capacitor electrode containing at least a dielectric film; a step of forming a desired capacitor dielectric; and 4) removing the metal foil A exposed by removing the dielectric film to form a second capacitor electrode having an arbitrary shape including a capacitor dielectric pattern, and exposing the exposed metal foil B The step of performing etching to form a circuit. 9 7. - A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the surface of the metal foil A is provided with a permittivity of 10 to 2000 and a film thickness of 0. 05 - 178 - (35) (35) 1251536 ~ 2 / / m dielectric film with capacitors for the multilayer wiring board material 'characterized by: 1) The material for the multilayer wiring board of the built-in capacitor a step of forming a substrate by laminating a metal foil B with an insulating material; 2) performing etching to remove a portion of the dielectric film to form a desired capacitor dielectric; 3) a step of removing any portion of the metal foil B to expose the insulating layer formed of the insulating material; 4) removing the exposed insulating layer by laser irradiation to form a hole to expose the metal foil A; 5) a step of forming a metal layer on both sides of the substrate surface in the hole; 6) removing the portion of the metal layer and the metal foil a to remove the desired first capacitor electrode and the second capacitor electrode . 9 8 · A method for manufacturing a multilayer wiring board with a built-in capacitor, the surface of which is provided with a metal foil A having a permittivity of 1 〇 to 2000 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2/m, which is characterized in that: 1) a metal case A surface of a material for a multilayer wiring board in which a capacitor is provided is made of an insulating material. a step of laminating the foil B to form a substrate; 2) etching to remove any portion of the dielectric film to remove the step of forming a desired capacitor dielectric; 3) performing laser irradiation on any portion of the metal foil B Irradiation, simultaneously removing -179- (36) 1251536 metal foil B, and the insulating layer formed by the above insulating material to form a hole to expose the metal foil A; 4) forming on both sides of the substrate surface including the hole And a step of forming a desired first capacitor electrode and a second capacitor electrode by etching and removing any of the metal layer and the metal foil A. 9 9 · A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein the metal foil A is provided with a single-sided capacitance ratio of 10 〜 200 00 and a film thickness of 0. A material for a multilayer wiring board in which a capacitor is provided in a dielectric film of 05 to 2/m, which is characterized by: 1) an arbitrary portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided a step of filling a through hole with a conductive paste containing a thermosetting resin and a metal tantalum, and forming a substrate by laminating a metal foil B with an insulating material; 2) retaining any portion of the dielectric film Etching to remove the step of forming a desired capacitor dielectric; 3) forming a metal layer on the surface of the substrate having at least a capacitor dielectric; 4) retaining the metal layer and any part of the metal foil A The step of etching is performed to form a desired first capacitor electrode and second capacitor electrode. 10 0. A method for manufacturing a multilayer wiring board with a built-in capacitor, wherein a metal foil A is provided with a single-sided capacitance of 10 to 2000 and a film thickness of 0·05 -180- (37) 1251536 〜2 // m A material for a multilayer wiring board in which a capacitor is provided in an electric film is characterized in that: 1) a through hole is formed in any portion of a metal foil A surface of a material for a multilayer wiring board in which a capacitor is provided, and is implemented by a chemical reaction a metalized conductive paste is filled in the through hole, and a step of forming a substrate by laminating the metal foil B $ with an insulating material; 2) etching and removing the portion of the dielectric film to form a desired capacitor a step of dielectric; 3) a step of forming a metal layer on a surface of the substrate having at least a capacitor dielectric; 4) etching and removing the metal layer and any portion of the metal foil A to form a desired 1 step of a capacitor electrode and a second capacitor electrode. 101. A method for producing a multilayer wiring board in which a capacitor is provided in any one of claims 86, 92, 95, 96, and 1 wherein a conductive paste which is metallized by a chemical reaction contains gold or platinum. And at least one metal particle selected from the group consisting of silver, copper, palladium, and rhodium, and the average particle diameter of the metal particles is 0. 1~l〇nm. 102. A method of manufacturing a multilayer wiring board having a capacitor provided in any one of claims 81 to 86, 89 to 92, and 95 to 100, wherein the method of removing the dielectric film by the worm Any one of the ion beam etching method, the RIE (Reactive I〇n Etching) method, or the solution etching method-181 - (38) 1251536 method. 103. A method of manufacturing a multilayer wiring board having a capacitor provided in any one of claims 81 to 86, 89 to 92, and 95 to 100, wherein the second capacitor electrode is a ground layer or a power source of the multilayer wiring board Floor. 1 〇 4 . A method of manufacturing a multilayer wiring board with a capacitor built in any one of claims 8 to 8 6 , 8 9 to 9 2 , and 9 5 to 1 , wherein the insulating layer of the substrate is formed The insulating material used is a prepreg composed of a resin, and a glass woven fabric or a glass non-woven fabric. 105. A method of manufacturing a multilayer wiring board having a capacitor provided in any one of claims 81 to 86, 89 to 92, and 95 to 100, wherein an insulating material used for forming an insulating layer of the substrate The resin contained in the resin is a prepreg of a thermosetting resin, and the glass transition point temperature of the thermosetting resin is 170 ° C or higher. 106. A method of manufacturing a multilayer wiring board having a capacitor provided in any one of claims 81 to 86, 89 to 92, and 100, wherein a dielectric film is made of barium titanate or titanic acid. Barium, calcium titanate, magnesium titanate, lead titanate, barium titanate, titanium dioxide, barium strontium silicate, calcium zirconate, lead chromate, barium titanate, lead chromite titanate, and lead magnesium titanate A material for a multilayer wiring board - 182 - 1251536 (39) which is provided with a capacitor or a solid solution of any two or more of them, or a capacitor comprising a laminate of two or more of them. 107. A method of manufacturing a multilayer wiring board having a capacitor provided in any one of claims 81 to 86, 89 to 92, and 95 to 100, wherein the metal foil A is made of copper and The surface of the dielectric film is provided with an oxidized protective coating metal of copper. The metal forming the oxidized protective film of copper is selected from the group consisting of platinum, gold, silver 'palladium, rhodium, and ruthenium. A material for a multilayer wiring board in which one or more capacitors are provided. 108. A method of manufacturing a multilayer wiring board in which a capacitor is provided in any one of claims 81 to 86, 89 to 92, and 95 to 100, wherein a metal foil A is made of copper and a dielectric is formed. On the surface of the film, a stable self-oxidizing film is formed, and one type of the metal selected from the group consisting of chrome 'molybdenum' titanium and nickel is formed. A material for a multilayer wiring board of a capacitor. 109. A method of manufacturing a multilayer wiring board in which a capacitor is provided in any one of claims 81 to 86, 89 to 92, and 95 to 1 in the patent application, wherein a dielectric film is formed using the metal foil A The surface roughness of the surface is 0. 0 1~0. The material for the multilayer wiring board of the capacitor is set within 5 // m. -183-