JP2005064316A - Method for manufacturing printed wiring board equipped with passive element and wiring board to be obtained and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board equipped with passive element with the less number of processes than that in a conventional manner. <P>SOLUTION: A high dielectric constant resin layer(second insulating layer) 9, metal layers(second conductor layers) 11 and 12 where a window hole for laser 10 is formed, an insulating resin layer(first insulating layer) 14 and a surface metal layer(first conductor layer) are integrally laminated in this order at the surface side of a flattened internal layer circuit board G with a circuit pattern(third conductor layer) on the surface. Afterwards, a laser beam is irradiated from the upper part of the first conductor layer to a part corresponding to the window hole for laser 10, and a laser hole reaching the third conductor layer is formed, and a metal layer is formed on the internal wall of the laser hole and the overall surface of the third conductor layer, and an external layer circuit pattern is formed around the hole of the substrate surface and in a necessary place. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a printed wiring board with a built-in passive element, an obtained wiring board, and a semiconductor device using the wiring board.

  2. Description of the Related Art A passive element built-in printed wiring board in which passive elements such as a capacitor (also referred to as a capacitor), an inductor, and a resistor are built in a substrate has been known for the purpose of downsizing the device (see Non-Patent Document 1).

In addition, a method of making a filter circuit by incorporating a capacitor or an inductor filter in a printed wiring board has been conventionally known (see Patent Document 1 and Patent Document 2).
Japanese Patent Laid-Open No. 10-233562 JP 2002-164630 A "Current status of circuit board technology with built-in components attracting attention", Journal of Japan Institute of Electronics Packaging, Vol. 5, no. 7, Nov. 2002, p621-645

However, in the method disclosed in Japanese Patent Application Laid-Open No. 10-233562, a plurality of through-holes are formed, and a space between these through-holes is built in the substrate as a capacitor. There is a limit to increasing the density of circuit patterns.
Further, in the method disclosed in Japanese Patent Application Laid-Open No. 2002-164630, since a terminal is formed on the side surface of the substrate, if a terminal is to be formed at a predetermined position on the desired substrate surface, it is necessary to route wiring from the substrate side surface to the substrate surface. And the process becomes complicated.

  An object of the present invention is to provide a method for manufacturing a printed wiring board capable of high-density wiring that incorporates passive elements such as capacitors and inductors, and to provide a manufacturing method having a smaller number of work steps than in the past. It is to provide a printed wiring board with a built-in passive element obtained by the manufacturing method, and further to provide a semiconductor device using the printed wiring board with a built-in passive element.

In order to achieve the above object, the present invention has the following configuration. That is, the present invention basically includes a high dielectric constant resin layer (second insulating layer) 9 and a laser on the surface side of the flattened inner circuit board G having a circuit pattern (third conductor layer) on the surface. After laminating and integrating the metal layer (second conductor layer) 11 + 12 in which the window hole 10 is formed, the insulating resin layer (first insulating layer) 14, and the surface metal layer (first conductor layer), the laser Over the first conductor layer (without removing the first conductor layer or after removing the first conductor layer corresponding to the laser window hole 10) From which the laser beam is applied to form a laser hole reaching the third conductor layer, a metal layer is formed on the inner surface of the laser hole and the entire surface of the third conductor layer, and
An outer layer circuit pattern is formed around a hole on a surface of a substrate and at a necessary place, and a method for manufacturing a printed wiring board with a built-in passive element is provided.

Here, in the said manufacturing method, Preferably, following process (6)-(12) is performed in order.
Step (6): The flattening resin 7 is disposed on at least the surface side of the inner circuit board F having the circuit (conductor) pattern on the surface until the circuit (conductor) pattern is hidden, and the resin is cured by heat treatment or the like. After that, the inner circuit board F is flattened by polishing until a circuit pattern appears.
Step (7): A high dielectric constant resin layer (second insulating layer) 9 and a metal foil 8 are sequentially stacked on the surface side of the flattened inner layer circuit board G, and laminated and integrated under heating and pressure.
Step (8): The metal foil on the surface side of the obtained substrate is etched to form a laser window hole 10 and another electrode 11 of the two capacitor electrodes (if necessary, an inductor 12 ) Is formed (circuit board I).
Step (9): The prepreg 14 and the metal foil 13a are sequentially stacked on the surface (both surfaces as necessary) of the obtained circuit board I, and laminated and integrated under heating and pressure.
Step (10): The metal foil 13a / 13 corresponding to the window hole 10 may be removed from the position corresponding to the laser window hole 10 without removing the metal foil 13a / 13 or from above the first conductor layer. Laser holes are applied to form laser holes 15a that reach the circuit pattern 6 on the surface of the inner circuit board. If necessary, the laser hole 15b is also formed at a desired position on the back surface (lower surface) side.
Step (11): The metal plating layer 16 is formed on the entire inner surface of the laser hole and the surface of the metal foil.
Step (12): The outer layer circuit pattern 17 is formed around the holes on the surface (both sides if necessary) of the obtained substrate and in necessary places.

In the step (6), the high dielectric constant resin layer (second insulating layer) 9 and the metal foil in the next step (7) are filled by flattening by filling a resin between the conductor patterns on the surface of the inner layer circuit board. 8 or when the high dielectric constant resin sheet with metal foil is laminated, a high dielectric constant resin layer with little thickness variation can be obtained, and a capacitor with small capacitance variation can be formed.
In the step (8), the circuit pattern layer (second conductor layer) including the other capacitor electrode 11 of the two capacitor electrodes and the other of the two capacitor electrodes. Controlling the diameter of the via hole 20a connecting the second conductor layer and the third conductor layer by providing a clearance (hole) in the land portion with the circuit pattern (third conductor layer) including the capacitor electrode. Is possible.
Further, in the step (10), since the laser drilling is performed without removing the metal foil on the substrate surface, the step of forming the laser window hole can be omitted.
The diameter of the via hole 20a in the circuit pattern (first conductor layer) on the surface is preferably 50 to 300 μm. If the thickness is less than 50 μm, the aspect ratio (hole depth H / hole diameter D) increases and the plating property decreases, and if it exceeds 300 μm, it is difficult to increase the density of the wiring board.

In the said manufacturing method, it can replace with a process (10) and a process (10 ') can also be performed.
Step (10 ′): The metal foil 13 on the surface is etched away at a desired location to form the laser window hole 21a, and then the laser hole from the window hole 21a to the circuit pattern 6 on the surface of the inner layer circuit board. 15a is formed. If necessary, the laser hole 15b is also formed at a desired position on the back surface (lower surface) side.

  In this case, since the laser window hole is formed in advance on the metal foil on the surface of the substrate by etching, the circuit pattern (first conductor layer), the second on the surface even when the metal foil thickness is relatively thick, such as 20 μm or more. A via hole 20a connecting the conductor layer and the third conductor layer can be formed. The diameter of the via hole 20a can be easily controlled by the window hole diameter.

Here, following the step (12), preferably, the next step (13) is performed.
Step (13): A layer of a solder resist solution is formed on the surface (both sides if necessary) of the obtained substrate, and dried, exposed and developed to form a solder resist 19 at a desired location.
When the metal of the outer circuit pattern 17 is copper, it is preferable to perform the next step (14).
Step (14): An electroless nickel plating layer and then an electroless gold plating layer are formed on the exposed portion of the outer circuit pattern 17.

Moreover, the inner layer circuit board used at the said process (6) can be produced by performing the following process (1), (2), (3), (4), (5) in order.
Process (1): The hole 3 is provided with a drill etc. in the desired location of a double-sided metal foil tension laminated board (1 + 2).
Step (2): After this is washed, the metal plating layer 4 is formed on the inner wall of the hole 3 and the metal foil surface.
Step (3): After roughening the substrate surface, the hole filling resin 5 is filled in the holes 3, and the resin is cured by heat treatment.
Step (4): The metal plating layer 6 is formed on the front surface and the back surface of the obtained substrate.
Step (5): The metal plating layer 6 is etched, and a desired circuit pattern including one of the two capacitor electrodes is formed on the front surface side, and a desired circuit pattern is formed on the back surface side. The inner layer circuit board is formed with a circuit pattern.

The present invention also relates to a printed wiring board with a built-in passive element obtained by the above manufacturing method. That is, the passive element built-in printed wiring board of the present invention, in order from the surface side, the layer of the circuit pattern 17 including the pad 17a (first conductor layer), the insulating resin layer 14 derived from the prepreg (first insulating layer), A circuit pattern layer (second conductor layer) including the other one of the two capacitor electrodes 11 (and the inductor 12 as necessary), a high dielectric constant resin layer 9, and two A circuit pattern (third conductor layer) including one of the capacitor electrodes, a resin (flattening resin) 7 filled around the circuit pattern, and the metal-clad laminate used A passive element built-in printed wiring board including a base material layer (second insulating layer) 1, a circuit pattern (fourth conductor layer) and a planarizing resin 7 filled around the circuit pattern, That pudding On the surface side (upper surface side) of the wiring board, a via hole 20a that electrically connects the first conductor layer, the second conductor layer, and the third conductor layer is formed, and the third conductor layer and the fourth conductor layer are formed. A via hole is also formed between the two.
Here, the via hole formed between the third conductor layer and the fourth conductor layer is usually filled with a hole filling resin in order to enable high density wiring.

  The passive element built-in printed wiring board has a circuit pattern layer including an insulating resin layer (third insulating layer) 14 derived from a prepreg and a pad 18a on the lower surface side of the fourth conductor layer. A fifth conductor layer) and a via hole 20b that electrically connects the fourth conductor layer and the fifth conductor layer.

  The present invention also relates to a semiconductor device in which a semiconductor chip is mounted on the passive element built-in printed wiring board.

According to the manufacturing method of the present invention, a passive element built-in printed wiring board capable of high-density wiring can be economically manufactured with a smaller number of processes than in the past.
The passive element built-in printed wiring board of the present invention is novel and enables high-density wiring. In addition, a semiconductor device can be provided by mounting a semiconductor chip.

Hereinafter, the present invention will be described in more detail.
The conductor (metal) used in the circuit of the printed circuit board with a built-in passive element in the present invention is selected in consideration of electrical characteristics and economy. You can choose from metals such as copper, silver, gold, tin, nickel, and zinc. Two or more metals may be used.

  As the high dielectric constant material in the high dielectric constant resin layer, a varnish obtained by mixing an insulating resin and a high dielectric constant filler with an organic solvent such as methyl ethyl ketone can be used.

What is preferable as said insulating resin is an epoxy resin which can be used in a semi-cured state and has high dielectric constant characteristics with excellent insulating properties after curing.
Here, the epoxy resin is preferably cured and exhibits an adhesive action, and is preferably an epoxy resin that is bifunctional or higher and has a molecular weight of less than 5000 (more preferably less than 3000).
Examples of the bifunctional epoxy resin include bisphenol A type or bisphenol F type resin. The bisphenol A type or bisphenol F type liquid resin is commercially available from Yuka Shell Epoxy Co., Ltd. under the trade names of Epicoat 807, Epicoat 827, and Epicoat 828. In addition, from Dow Chemical Japan, D.C. E. R. 330, D.E. E. R. 331, D.D. E. R. It is marketed under the trade name 361. Further, they are commercially available from Toto Kasei Co., Ltd. under the trade names YD8125 and YD8170.

  Further, for the purpose of increasing the Tg, a polyfunctional epoxy resin (for example, a phenol novolac type epoxy resin or a cresol novolac type epoxy resin) may be added thereto. A phenol novolac type epoxy resin is commercially available from Nippon Kayaku Co., Ltd. under the trade name EPPN-201. Cresol novolac type epoxy resins are commercially available from Sumitomo Chemical Co., Ltd. under the trade names ESCN-190 and ESCN-195. Further, they are commercially available from Nippon Kayaku Co., Ltd. under the trade names EOCN1012, EOCN1025, and EOCN1027. Further, they are commercially available from Toto Kasei Co., Ltd. under the trade names YDCN701, YDCN703, and YDCN704.

  In addition, as a curing agent for curing the epoxy resin, a commonly used curing agent can be used, for example, one molecule of amine, polyamide, acid anhydride, polysulfide, boron trifluoride, and phenolic hydroxyl group. Examples thereof include bisphenol A, bisphenol F, and bisphenol S, which are compounds having two or more compounds. In particular, a phenol novolac resin, a bisphenol novolak resin, a cresol novolak resin, or the like, which is a phenol resin, is preferable because of its excellent electric corrosion resistance when absorbing moisture. Plyofen LF2882, available from Dainippon Ink and Chemicals, Phenolite TD-2090, Phonolite TD-2149, Phenolite VH4150, Phenolite VH4170 (all trade names) are particularly preferred.

  Along with the curing agent, curing accelerators such as various imidazoles can be used. Examples of imidazole include 2-methylimidazole, 2-ethyl-4methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-phenylimidazolium trimellitate, and the like. Such imidazoles are commercially available from Shikoku Kasei Kogyo Co., Ltd. under the trade names 2E4MZ, 2PZ-CN, and 2PZ-CNS.

As the high dielectric constant filler, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, lead titanate, titanium dioxide, barium zirconate, calcium zirconate, lead zirconate, etc. are used. Can do. These may be used alone or in combination of two or more. In particular, it is preferable to use a material having a relative dielectric constant of 50 or more.
The blending amount of the high dielectric constant filler is preferably 300 to 3000 parts by weight with respect to 100 parts by weight of the insulating resin.

  In addition, in order to improve the handling of high dielectric constant materials (varnish including insulating resin and high dielectric constant filler), at least one functional group such as epoxy group, amide group, carboxyl group, cyanate group, hydroxy group, etc. It is preferable to blend a high molecular weight resin having a weight average molecular weight of 10,000 to 800,000. If the weight average molecular weight is 10,000 or more, the tackiness of the high dielectric constant material in the B stage can be reduced and the flexibility during curing can be improved, and the high dielectric constant filler can be easily dispersed uniformly. is there.

  Examples of such a high molecular weight resin include phenoxy resin, high molecular weight epoxy resin, ultrahigh molecular weight epoxy resin, polyamideimide resin, and functional group-containing reactive rubber. The phenoxy resin is commercially available from Toto Kasei Co., Ltd. under the trade names of Phenototo YP-40 and Phenototo YP-50. Also, commercially available from Phenoxy Associates under the trade names PKHC, PKHH and PKHJ. The above-mentioned high molecular weight epoxy resins, and also ultra high molecular weight epoxy resins having a weight average molecular weight exceeding 80,000 (Japanese Patent Publication No. 7-59617, Japanese Patent Publication No. 7-59618, Japanese Patent Publication No. 7-59619, Japanese Patent Publication No. 7-59620) No. 7-64911 and No. 7-68327), both of which are manufactured by Hitachi Chemical Co., Ltd. The polyamideimide resin is commercially available from Hitachi Chemical Co., Ltd. under the trade name KS9000 series. As the functional group-containing reactive rubber, a carboxyl group-containing acrylic rubber is commercially available from Teito Chemical Industry Co., Ltd. under the trade name HTR-860P, and an epoxy group-containing acrylic rubber is marketed under the trade name HTR-860P-3. .

  Further, a dispersant may be added to the high dielectric constant material. As the dispersant, commercially available non-silicone dispersants and the like can be used. Moreover, what is necessary is just to determine the compounding quantity suitably by experiment.

  The melt viscosity at 120 ° C. of the high dielectric constant material is preferably 100 to 200 Pa · s. When the minimum melt viscosity is less than 100 Pa · s, the flow becomes large and the thickness variation tends to increase. On the other hand, if it exceeds 200 Pa · s, the adhesiveness tends to decrease.

  The metal (foil) used for the second conductor layer includes copper (foil), aluminum (foil), etc., preferably copper foil, and the thickness is preferably 1 to 35 μm, and 1 to 12 μm. More preferably it is.

  A high dielectric constant resin sheet with a metal foil can also be used as the high dielectric constant resin layer (second insulating layer) and the upper metal layer (second conductor layer). A high dielectric constant material including an insulating resin and a high dielectric constant filler is mixed with an organic solvent such as methyl ethyl ketone to form a varnish, which is applied to a metal foil, dried, and formed into a sheet.

As the planarizing resin used in the present invention, a paste-type epoxy thermosetting resin that is easy to apply is used. For example, CCF-300AS (manufactured by Taiyo Ink Manufacture Co., Ltd.), CCF-500AS (manufactured by Taiyo Ink Manufacture Co., Ltd.), AE-2500 (manufactured by Ajinomoto Fine-Techno Manufacture Co., Ltd.), etc., are available. .
Further, as the hole-filling resin to be used, a paste type epoxy thermosetting resin that easily enters the hole is used. For example, there are HDI-200DB4 (manufactured by Taiyo Ink Manufacturing Co., Ltd.), AE-83CL (manufactured by Ajinomoto Fine Techno Manufacturing Co., Ltd.), CB-800 (manufactured by DuPont Manufacturing Co., Ltd.), etc., all of which are commercially available.

  The pattern when the inductor is built in the substrate is preferably a spiral. This is because when the inductor is formed by etching, the spiral pattern has better inductor characteristics than the meander pattern.

  As the insulating material for the substrate other than the capacitor material, a material made of resin and glass woven fabric and / or glass nonwoven fabric is preferable. In order to heat-treat the substrate, it is necessary to be able to maintain the rigidity of the substrate even at a high temperature. It is preferable to use an insulating material made of a resin and a glass woven fabric and / or a glass nonwoven fabric rather than using it. It is also possible to use a sheet of a thermoplastic resin such as a highly heat-resistant fluororesin or polyetheretherketone, or a thermosetting resin such as polyimide or polyamideimide, but these are difficult in terms of economy. . The glass woven fabric and the glass nonwoven fabric are not limited as long as they have high rigidity at high temperature, that is, high elastic modulus, and D glass, E glass, S glass, and the like can be used.

Of the three conductor layers (first conductor layer, second conductor layer, and third conductor layer) in order from the surface side of the printed wiring board with built-in passive elements, the layer that forms the capacitor of the passive elements is the second conductor. Capacitor electrodes are formed on the layer and the third conductor layer.
In addition, the layer forming the inductor of the passive element is preferably formed on either the second conductor layer or the third conductor layer, or on both layers. Thereby, the wiring possible area | region of a board | substrate surface layer increases, and density increase can be achieved.

  One of the capacitor electrodes is connected to a via hole 20a connecting the surface layer (first conductor layer), the second conductor layer, and the third conductor layer, and the other capacitor electrode is a surface layer (first conductor layer). If the inductor is formed in the second conductor layer and / or the third conductor layer, the filter circuit function is provided inside the wiring board. Can be granted.

Two insulating layers (first insulating layer and second insulating layer) sandwiched between three conductive layers (first conductive layer, second conductive layer and third conductive layer) in order from the surface side of the printed wiring board with built-in passive element ), The second insulating layer far from the wiring board surface is a capacitor dielectric. Here, the thickness ratio between the first insulating layer and the second insulating layer is preferably 2 to 10: 1.
There is a relationship between the thickness of the insulating layer and the size of the via hole diameter, and the thinner the insulating layer, the easier the formation of a small diameter via hole. Further, the capacitance of the capacitor increases as the thickness of the second insulating layer serving as a dielectric decreases, and the capacitor can be made smaller. Nonetheless, the thinner the second insulating layer, the harder it becomes to handle, so it is preferably 0.1 to 30 μm, more preferably 10 to 20 μm. The thickness of the first insulating layer is preferably 10 to 300 μm (more preferably 100 to 200 μm). As a result, the diameter of the via hole 15a connecting the three conductor layers (the first conductor layer, the second conductor layer, and the third conductor layer) can be easily reduced to 0.3 mm or less, and the wiring density can be increased. .

In the via hole 20a, the aspect ratio (H ₁ / D ₁ ) of the hole diameter (D ₁ ) and the hole depth (H ₁ ) at the portion connecting the second conductor layer and the third conductor layer is preferably 0.5 or less. And When the aspect ratio exceeds 0.5, the plating property is lowered and the connection reliability is lowered. The aspect ratio may be smaller than the aspect ratio (H ₂ / D ₂ ) of the hole diameter (D ₂ ) and the hole depth (H ₂ ) at the location where the first conductor layer and the second conductor layer are connected. preferable. On the contrary, the diameter of the via hole 20a in the first conductor layer is increased, which hinders high density wiring.

  A semiconductor device can be obtained by mounting a semiconductor chip on the printed wiring board with a built-in passive element described so far. By having a capacitor with a small capacitance variation and an inductor with a high inductance density in the substrate, a semiconductor device that achieves both miniaturization and weight reduction can be manufactured.

In the manufacturing method according to the present invention, the metal foil 13a / 13 corresponding to the laser window hole 10 may or may not be removed before the laser beam is applied from above the first conductor layer. By adjusting the thickness of the metal foil 13a / 13 and the output of the laser beam, the laser hole 15a reaching the circuit pattern (metal plating layer) 6 on the surface of the inner circuit board can be formed in any case.
In the printed wiring board with a built-in passive element of the present invention, the three conductor layers (first conductor layer, second conductor layer, and third conductor layer) in order from the surface side are connected by one via hole 20a. Can be made dense.
Further, since the via holes 20a and 20b are respectively provided on the front surface side and the back surface side of the passive element built-in printed wiring board, the filling of the holes is unnecessary. Therefore, part of the hole filling operation can be omitted, and the whole contributes to process shortening.
Furthermore, a via hole connecting the first conductor layer (surface layer), the second conductor layer and the third conductor layer, and a via hole connecting the first conductor layer (surface layer) and the second conductor layer (not shown) Z)) drills with a laser and performs plating at the same time. Therefore, the number of manufacturing steps is smaller than that of a conventional two-stage stacked via hole, and the cost is excellent.

Hereinafter, the present invention will be described more specifically with reference to examples. In addition, the names, manufacturers, product names, and the like of materials used in Examples and Comparative Examples are summarized below.
Bisphenol A type epoxy resin: YD-8125 manufactured by Tohto Kasei Co., Ltd.
Cresol novolac type epoxy resin: YDCN-703 manufactured by Toto Kasei Co., Ltd.
Phenol novolac resin as an epoxy resin curing agent: BRAIOFEN LF2882 manufactured by Dainippon Ink & Chemicals, Inc.
Phenoxy resin as a high molecular weight resin (weight average molecular weight 50,000): Phenotote YP-50 manufactured by Tohto Kasei Co., Ltd.
Average particle diameter 1.5 μm barium titanate filler: BT-100PR manufactured by Fuji Titanium Industry Co., Ltd.
Barium titanate filler with an average particle size of 0.6 μm: HPBT-1 manufactured by Fuji Titanium Industry Co., Ltd.
Non-silicone dispersant as dispersant: BYK-W9010 manufactured by BYK Japan
Electrolytic copper foil having a thickness of 12 μm: GTS-12 manufactured by Furukawa Circuit Foil Co., Ltd.
Copper foil-clad glass epoxy laminate: MCL-E-679F manufactured by Hitachi Chemical Co., Ltd.
Cavity filling resin: HDI-200DB4 manufactured by Taiyo Ink Manufacturing Co., Ltd.
Flattening resin: CCF-300AS manufactured by Taiyo Ink Manufacturing Co., Ltd.
80 μm thick glass epoxy prepreg with filler: GEA-679F manufactured by Hitachi Chemical Co., Ltd.
3 μm thick copper foil with 35 μm carrier copper foil: MT35S3 manufactured by Mitsui Metal Mining Co., Ltd.
Electroless copper plating solution: CUST-3000 manufactured by Hitachi Chemical Co., Ltd.
Solder resist solution: PSR-4000AUS5 manufactured by Taiyo Ink Manufacturing Co., Ltd.
Electroless nickel plating solution: NIPS100 manufactured by Hitachi Chemical Co., Ltd.
Electroless gold plating solution: HGS2000 manufactured by Hitachi Chemical Co., Ltd.

Example 1
(I) Production of high-dielectric-constant resin sheet with copper foil A high-dielectric-constant resin sheet with copper foil used for the production of a passive element built-in printed wiring board was produced in advance.
66 parts by weight of bisphenol A type epoxy resin (hereinafter simply referred to as “parts”), 34 parts of cresol novolac type epoxy resin, 63 parts of phenol novolac resin as an epoxy resin curing agent, phenoxy resin (weight average molecular weight 50,000) as a high molecular weight resin ) 24 parts, 0.6 part of 1-cyanoethyl-2-phenylimidazole (Curazole 2PZ-CN) as a curing accelerator, 1300 parts of barium titanate filler with an average particle size of 1.5 μm as a high dielectric constant filler, Using a bead mill, methyl ethyl ketone is added to a resin composition comprising 400 parts of a barium titanate filler having an average particle size of 0.6 μm as a high dielectric constant filler and 11.2 parts of a non-silicone dispersant as a dispersant. The mixture was stirred and mixed at 1000 rpm for 1 hour. After passing the mixture through a 200-mesh nylon cloth, a resin varnish obtained by vacuum degassing is applied onto an electrolytic copper foil having a thickness of 12 μm, heated at 140 ° C. for 5 minutes, and applied in a B-stage state. A film (film thickness: 10 μm) was formed (high dielectric constant resin sheet with copper foil).

  When the melt viscosity at 120 ° C. of the obtained resin sheet was measured using a Shimadzu flow tester CFT-100 type with a jig having a nozzle diameter of 2 mm, it was 150 Pa · s. Moreover, about the hardened | cured material heated and hardened at 170 degreeC for 1 hour, the dielectric constant computed from the impedance characteristic (25 degreeC, 1 MHz) calculated | required using LCR meter YHP4275A (Yokogawa Hewlett-Packard Co., Ltd. brand name) is 45.

(Ii) Production of Passive Element Built-In Printed Wiring Board FIG. 1 shows a method (procedure) for producing a passive element built-in printed wiring board of the present invention. Hereinafter, it demonstrates in order of a process.
Step (1): Desired of copper foil-clad glass epoxy laminate (plate thickness 0.2 mm, copper foil thickness 9 μm) (1 + 2) in which copper foils 2 a and 2 b are pasted on both surfaces of a substrate (glass epoxy laminate) 1 The drill hole 3 was provided in the location (FIG.1 (b)).
Step (2): The carbonized resin residue is removed by ultrasonic cleaning and an alkaline permanganate solution, and after performing adhesion promoting treatment using a catalyst for this, an electroless copper plating solution is used to form a drill hole. A copper plating layer 4 of about 15 μm was formed on the inner wall and the copper foil surface (FIG. 1C).

Step (3): After performing roughening treatment on both sides of the obtained substrate, which is a combination of blackening treatment mainly composed of sodium hypochlorite and reduction treatment mainly composed of dimethylaminoborane, The paste-type hole-filling resin 5 is filled by screen printing and cured by heat treatment at 170 ° C. for 60 minutes, and then both surfaces of the substrate are polished with a buff brush to remove excess cured resin (FIG. 1D )).
Step (4): After an adhesion promoting treatment using a catalyst, an electroless copper plating layer 6 of about 15 μm was formed on both surfaces of the substrate (FIG. 1 (e)).

Step (5): A desired etching resist is formed on both surfaces of the substrate, unnecessary copper is removed by etching using a ferric chloride aqueous solution, and one of two capacitor electrodes is formed on the surface side. A desired circuit (conductor) pattern including the inner circuit board F on which the desired circuit pattern was formed was formed on the back side (FIG. 1 (f)).
Step (6): Paste type flattening resin 7 is applied to both surfaces of the obtained inner layer circuit board F using a roll coater to such an extent that the surface circuit pattern is hidden, and this is heat-treated at 170 ° C. for 60 minutes. After curing with, polishing was performed with a buff brush until a circuit pattern appeared to remove excess resin. The irregularities on the inner circuit board surface at this time were 3 μm or less. Thereafter, the surface of the circuit was subjected to a roughening process combining the blackening process and the reduction process (described above) to obtain a flattened inner circuit board G (FIG. 1 (g)).

Step (7): On the surface (upper surface) of the inner layer circuit board G, a high-permittivity resin sheet with copper foil (8 + 9) prepared in advance is overlapped so that the high dielectric constant resin layer 9 side is in contact with the inner layer circuit board G. Lamination was integrated under the press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a time of 60 minutes (FIG. 1 (h)).
Step (8): A desired etching resist is formed on the copper foil on the surface side of the obtained substrate, unnecessary copper foil is removed by etching (as described above), and the laser window hole 10, among the two capacitor electrodes A desired circuit pattern including the other electrode 11 and the inductor 12 was formed. Subsequently, the surface was subjected to a roughening process (described above) in which a blackening process and a reduction process were combined to obtain a circuit board I (FIG. 1 (i)).

  Step (9): On the front side of the obtained circuit board I, two 80 μm thick filler-filled glass epoxy prepregs 14 and a 35 μm carrier copper foil-attached 3 μm thick copper foil 13 a / b are sequentially stacked, and the back surface Similarly, two prepregs 14 and a copper foil 13a / b with carrier copper foil are sequentially laminated on the side, and laminated and integrated under press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a time of 60 minutes, and then the carrier copper foil 13b and 13b were peeled off. Thereafter, the surfaces of the copper foils (3 μm) 13a and 13a were roughened using MEC etch bond CZ-8101 (trade name, manufactured by MEC Co., Ltd.) (FIG. 1 (j)).

  Step (10): On the substrate surface (upper surface) side, a carbon dioxide laser (NLC-1B21 type: manufactured by Hitachi Via Mechanics Co., Ltd.) is provided at a position corresponding to the window hole 10 on the copper foil of the high dielectric constant resin sheet with copper foil. Name), a copper plating layer on the surface of the inner circuit board is processed under the conditions of a pulse width of 35 μs, a shot number of 1 time, a pulse width of 20 μs, a shot number of 2 times, a pulse width of 10 μs, and a shot number of 3 times. A laser hole 15a reaching 6 was formed, and a laser hole 15b was similarly formed at a desired position on the back surface (lower surface) side of the substrate (FIG. 1 (k)).

Step (11): After removal of carbonized resin residue and cleaning (described above), after catalyst adhesion promoting treatment (described above), copper plating is performed using an electroless copper plating solution on the laser hole inner wall and the copper foil surface. A copper plating layer 16 of about 20 μm was formed (FIG. 1 (l)).
Step (12): After forming an etching resist around the holes on both sides of the obtained substrate and at necessary places, unnecessary copper is removed by etching, and outer layers including conductor patterns (pads) 17a and 18a around the holes Circuit patterns 17 and 18 were formed (FIG. 1 (m)).

Step (13): Using a roll coater, a solder resist solution was applied to the substrate surface to a thickness of 30 μm, dried, exposed and developed to form a solder resist 19 at a desired location.
Step (14): Using an electroless nickel plating solution, a 3 μm nickel plating layer is formed on the exposed surface of the outer circuit pattern, and then a 0.1 μm gold plating layer is formed using an electroless gold plating solution. An element built-in printed wiring board was obtained (FIG. 1 (n)).

  In addition, the number of processes in Example 1 is 9 processes, 2 processes for drilling, 3 processes for plating, 3 processes for circuit processing, and 1 process for filling holes.

  A cross-sectional view (enlarged view) of the obtained passive element built-in printed wiring board is shown in FIG. In order from the front surface (upper surface) side, the circuit pattern layer (first conductor layer) including the pad 17a, the prepreg-derived insulating resin layer 14 (first insulating layer), and the other one of the two capacitor electrodes A circuit pattern including a capacitor electrode 11 and an inductor 12 (second conductor layer), a high dielectric constant resin layer 9, and the other capacitor electrode of the two capacitor electrodes. (Third conductor layer) and resin (flattening resin) 7 filled around the circuit pattern, base material layer 1 derived from the copper-clad laminate used, circuit pattern (fourth conductor layer) and the same A passive element comprising a planarizing resin 7 filled around a circuit pattern, an insulating resin layer (third insulating layer) 14 derived from a prepreg, and a circuit pattern layer (fifth conductor layer) including a pad 18a. Built-in pudding A via hole 20a that electrically connects the first conductor layer, the second conductor layer, and the third conductor layer is formed on one surface (surface side; upper surface side) of the printed wiring board. Between the third conductor layer and the fourth conductor layer, a via hole filled with a hole filling resin is formed in the hole. A via hole 20b that electrically connects the fourth conductor layer and the fifth conductor layer is also formed on the other surface (back surface side; lower surface side) of the printed wiring board.

Example 2
FIG. 3 shows another manufacturing method (procedure) for the printed wiring board with a built-in passive element according to the present invention. Here, steps (1) to (8) are the same as steps (1) to (8) in Example 1 (that is, FIGS. 1 (a) to (i)), and are therefore omitted.
Step (9 ′): After the roughening treatment (described above) combining blackening treatment and reduction treatment is performed on the circuit surface of the circuit board I in FIG. Two sheets of 80 μm filler-filled glass epoxy prepreg 14 and 12 μm thick copper foil 13 are stacked in order, and two sheets of 80 μm thick prepreg 14 and 12 μm thick copper foil 13 are stacked in order on the back side as well. The laminate was integrated under the press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a time of 60 minutes. Thereafter, an etching resist was formed at desired locations on both sides of the substrate, and unnecessary copper foil was removed by etching to form laser window holes 21a and 21b having a diameter of 0.15 mm (FIG. 3 (j ′)).
Step (10 '): Using a carbon dioxide laser (NLC-1B21 type: Hitachi Via Mechanics Co., Ltd. product name) at the locations where the laser window holes 21a and 21b are formed, under the conditions of a pulse width of 20 μs and a shot count of 8 times. Laser drilling was performed to make a laser hole reaching the copper plating layer on the surface of the inner circuit board (FIG. 2 (k)).
Steps (11) to (14) are also the same as those in the first embodiment, and will be omitted.

  The number of steps in Example 2 is 2 steps for drilling, 3 steps for plating, 4 steps for circuit processing, and 1 step for hole filling, for a total of 10 steps.

Comparative Example In the same manner as in steps (1) to (7) in Example 1 (see FIGS. 1 (a) to (h)), a high dielectric constant resin sheet is laminated and integrated on one side of a circuit board. A desired etching resist was formed on the copper foil of the sheet, and unnecessary copper foil was removed by etching to form a laser window hole 10 having a diameter of 0.15 mm at a desired location (FIG. 4 (i)).
Using a carbon dioxide laser (ML505GT type: trade name, manufactured by Mitsubishi Electric Corporation) at the location of the window hole provided on the substrate surface, a laser hole 15 was provided under the conditions of a pulse width of 100 μs and a shot count of 6 (FIG. 3). (J)).
After removing and washing the carbonized resin residue and performing adhesion promoting treatment with a catalyst, copper plating was performed using an electroless copper plating solution, and a copper plating layer 4 of about 20 μm was formed on the inner wall of the laser hole and the copper foil surface. (FIG. 3 (k)).

The via hole of this substrate was filled with paste-type hole filling resin 5 by screen printing and cured by heat treatment at 170 ° C. for 60 minutes (FIG. 3 (l)).
The surface of the substrate was polished with a buff brush, excess resin was removed, and adhesion promoting treatment with a catalyst was performed. Then, an electroless copper plating layer 4 of about 15 μm was formed on the substrate surface (FIG. 3 (m)).
After forming a desired etching resist on the surface of the obtained substrate, unnecessary copper was removed by etching to form a circuit pattern including the capacitor electrode 11 and the inductor 12 (FIG. 3 (n)).

The surface of this circuit pattern is subjected to a roughening process (described above) that combines a blackening process and a reduction process, and two glass epoxy prepregs 14 each having a thickness of 80 μm and a 35 μm carrier copper foil are provided on each of the front and back surfaces. Copper foils 13a / b having a thickness of 3 μm were sequentially stacked and laminated and integrated under press conditions of a temperature of 170 ° C., a pressure of 1.5 MPa, and a time of 60 minutes. Thereafter, the carrier copper foil was peeled off (FIG. 3 (o)).
Unnecessary substrate ends were cut, and a desired etching resist was formed on the substrate surface. Then, unnecessary copper foil was removed by etching to form a laser window hole with a diameter of 0.15 mm at a desired location. Thereafter, a laser hole 15 was provided at the location of the laser window hole using a carbon dioxide laser (ML505GT type: trade name, manufactured by Mitsubishi Electric Corporation) under the conditions of an output power of 26 mJ, a pulse width of 100 μs, and a shot number of 6 times ( FIG. 3 (p)).

After removing and washing the carbonized resin residue, the catalyst was subjected to adhesion promotion treatment and copper plating was performed using an electroless copper plating solution to form a copper plating layer 4 of about 20 μm on the laser hole inner wall and the copper foil surface. (FIG. 3 (q)).
Etching resist was formed on necessary portions such as pads and circuit patterns on the surface of the substrate, and unnecessary copper was removed by etching to form outer layer circuit patterns 17 (FIG. 3 (r)).

  The number of steps in the comparative example is 3 steps for drilling, 5 steps for plating, 5 steps for circuit processing, and 2 steps for hole filling, for a total of 15 steps.

Sectional drawing (Example 1) which shows the manufacturing method (procedure) of the printed wiring board with a built-in passive element. Sectional drawing (enlarged view) of the obtained passive element built-in printed wiring board. Sectional drawing which shows another manufacturing method (procedure) of the printed wiring board with a built-in passive element (Example 2). Sectional drawing which shows the manufacturing method (procedure) of a comparative example.

Explanation of symbols

1: Base material (inner layer base material, glass epoxy laminate)
2, 2a, 2b: Metal foil (copper foil)
1 + 2: Copper-clad glass epoxy laminate 3: Hole 4, 6: Metal plating layer (electroless copper plating layer)
5, 7: Filling resin or flattening resin (paste-type thermosetting insulating material)
8: Metal foil (copper foil)
8 + 9: High dielectric constant resin sheet with copper foil 9: High dielectric constant resin layer (second insulating layer) 10: Laser window hole 11: The other electrode 12 of the capacitor electrodes 12: Inductor 13: Metal foil (copper) Foil)
13a / b: Copper foil with carrier copper foil 13a: Copper foil (3 μm) 13b: Carrier copper foil 14: Base material (prepreg) or insulating resin layer derived from prepreg (first insulating layer)
15: Laser hole 16: Electroless copper plating layer 17, 18: Outer layer circuit pattern 17a, 18a: Pad 19: Solder resist 20a, 20b: Via hole 21a, 21b: Laser window hole F: Inner layer circuit board G: Planarization Inner layer circuit board I: circuit board

Claims (8)

On the surface side of the flattened inner layer circuit board having a circuit pattern (third conductor layer) on the surface, a high dielectric constant resin layer (second insulating layer) and a metal layer having a laser window hole (in order) A second conductor layer), an insulating resin layer (first insulating layer), and a surface metal layer (first conductor layer) are laminated and integrated;
Laser light is applied from above the first conductor layer to a position corresponding to the laser window hole to form a laser hole reaching the third conductor layer, and then the laser hole inner wall and the entire surface of the third conductor layer are formed. A method of manufacturing a printed wiring board with a built-in passive element, in which a metal layer is formed, and an outer layer circuit pattern is formed around a hole on the surface of the substrate and at a necessary position. The manufacturing method of the printed wiring board with a built-in passive element of Claim 1 which performs the following process (6)-(12) in order.
Step (6): At least the surface side of the inner layer circuit board having the circuit pattern (third conductor layer) on the surface is arranged with a planarizing resin until the circuit pattern is hidden, and after the resin is cured, the circuit pattern Is polished until the inner circuit board is flattened.
Step (7): A high dielectric constant resin layer (second insulating layer) and a metal foil are sequentially stacked on the surface side of the flattened inner layer circuit board, and laminated and integrated under heating and pressure.
Step (8): Etching the surface-side metal foil to form a desired circuit pattern (second conductor layer) including a laser window hole and the other of the two capacitor electrodes. .
Step (9): A prepreg and a metal foil are sequentially laminated on the surface of the obtained circuit board, and laminated and integrated under heating and pressure.
Step (10): A laser hole reaching the circuit pattern on the surface of the inner layer circuit board is formed by applying a laser beam from above the first conductor layer to a position corresponding to the laser window hole. If necessary, a laser hole is also formed at a desired position on the back surface (lower surface) side.
Step (11): A metal plating layer is formed on the inner wall of the laser hole and the surface metal foil.
Step (12): An outer layer circuit pattern is formed around the hole on the surface of the obtained substrate and at a necessary place. The method for manufacturing a printed wiring board with a built-in passive element according to claim 2, wherein the following process (10 ') is performed instead of the process (10).
Step (10 ′): The metal foil on the surface is etched away at a desired location to form a laser window hole, and then a laser hole reaching the circuit pattern on the surface of the inner layer circuit board is formed from the window hole. If necessary, a laser hole is formed at a desired position also on the back surface side. 4. The method for manufacturing a printed wiring board with a built-in passive element according to claim 2, wherein the next step (13) is performed following the step (12).
Step (13): A layer of a solder resist solution is formed on the surface of the obtained substrate, and dried, exposed and developed to form a solder resist at a desired location. 5. The method of manufacturing a printed wiring board with a built-in passive element according to claim 1, wherein the inner layer circuit board performs the following steps (1), (2), (3), (4), (5) in order. A method of manufacturing a printed wiring board with a built-in passive element using an inner-layer circuit board fabricated in this way.
Process (1): A hole is provided in the desired location of a double-sided metal foil-clad laminate.
Step (2): A metal plating layer is formed on the inner wall of the hole and the surface of the metal foil.
Step (3): The hole filling resin is filled in the hole.
Step (4): A metal plating layer is formed on the front surface and the back surface of the obtained substrate.
Step (5): Etching the metal plating layer to form a desired circuit pattern including one of the two capacitor electrodes on the front surface side and a desired circuit on the back surface side. The inner circuit board is formed with a pattern. A circuit including a circuit pattern layer (first conductor layer) including pads, an insulating resin layer (first insulating layer), and the other one of the two capacitor electrodes in order from the surface side A circuit pattern (third conductor layer) including a pattern layer (second conductor layer), a high dielectric constant resin layer (second insulating layer), and one of the two capacitor electrodes; The flattening resin filled around the circuit pattern, the base layer (second insulating layer) derived from the metal-clad laminate used, the circuit pattern (fourth conductor layer) and the circuit pattern are filled Passive element built-in printed wiring board composed of a flattening resin,
On the surface side of the printed wiring board, a via hole for electrically connecting the first conductor layer, the second conductor layer, and the third conductor layer is formed, and between the third conductor layer and the fourth conductor layer. The printed wiring board with a built-in passive element in which via holes are formed. The printed wiring board with a built-in passive element according to claim 6, further comprising an insulating resin layer (third insulating layer) and a circuit pattern layer (fifth conductive layer) including pads on the lower surface side of the fourth conductive layer. And a passive element built-in printed wiring board in which via holes for electrically connecting the fourth conductor layer and the fifth conductor layer are formed. A semiconductor device comprising a semiconductor chip mounted on the printed wiring board with built-in passive elements according to claim 6.

Images