CN106328600B - Encapsulating structure and preparation method thereof - Google Patents
Encapsulating structure and preparation method thereof Download PDFInfo
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- CN106328600B CN106328600B CN201510381443.4A CN201510381443A CN106328600B CN 106328600 B CN106328600 B CN 106328600B CN 201510381443 A CN201510381443 A CN 201510381443A CN 106328600 B CN106328600 B CN 106328600B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73259—Bump and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
The present invention provides a kind of encapsulating structure and preparation method thereof, and encapsulating structure includes circuit base plate, at least an electronic component and connected slot.Circuit base plate includes an at least core layer, at least three pattern layers line layers, at least two layers of dielectric layer, multiple conductive through holes and multiple route connection pads.It is embedded in one at least within layer of dielectric layer and is located in the configuring area of core layer in electronic component.Wherein one layer of electric connection that electronic component passes through partially electronically conductive through-hole and patterned line layer.Connected slot has bottom, the sidewall portion of multiple connection bottoms and multiple connection connection pads in sidewall portion.Circuit base plate is assembled to bottom, and relative to configuring area bending route connection pad is electrically connected with connection pad is connect by the bent area of core layer.Encapsulating structure provided by the invention and preparation method thereof has lesser volume, may conform to the demand of slimming.
Description
Technical field
The invention relates to a kind of encapsulating structures and preparation method thereof, and have smaller size smaller in particular to one kind
Encapsulating structure and preparation method thereof.
Background technique
In general, the purpose of encapsulation is to protect exposed electronic component, reduces the density of electronic component contact and mention
The good heat dissipation of electronic component.Common encapsulation step is: electronic component being first configured at lead frame by adhesion layer
(Leadframe) on chip seat；Then, the contact on electronic component is electrically connected to conducting wire in such a way that routing engages
On the interior pin of frame；Later, chip, chip seat and interior pin are packaged by packing colloid, and expose lead frame
Outer pin portion.Finally, the element after encapsulation is plugged in female plug slot via its outer pin again and completes encapsulating structure
Production.
Element since existing encapsulating structure need to be packaged electronic component by packing colloid, after encapsulation
Its thickness and volume will increase.And female plug slot certainly will have certain volume to be electrically connected with the element after encapsulation
Space come accommodate encapsulation after element.That is, the volume of existing encapsulating structure and thickness and can not effectively be thinned,
Therefore it is unable to satisfy consumer's demand light and short for electronic product.
Summary of the invention
The present invention provides a kind of encapsulating structure, with lesser volume, may conform to the demand of slimming.
The present invention also provides a kind of production methods of encapsulating structure, to make above-mentioned encapsulating structure.
Encapsulating structure of the invention comprising circuit base plate, at least an electronic component and connected slot.Circuit base plate packet
An at least core layer, at least three pattern layers line layers, at least two layers of dielectric layer, multiple conductive through holes and multiple routes is included to connect
Pad.Core layer has configuring area, bent area and upper surface and lower surface relative to each other around configuring area.Patterned lines
Road floor is configured in core layer and is located in configuring area.Dielectric layer is configured in core layer and is located in configuring area, dielectric
Layer is between patterned line layer, and patterned line layer is in be alternately stacked with dielectric layer.Conductive through hole is electrically connected wantonly two
Adjacent patterned line layer.Route connection pad is configured on the lower surface of core layer and is located at bent area.It is embedded in electronic component
In one at least within layer of dielectric layer, and it is located in configuring area, wherein electronic component passes through partially electronically conductive through-hole and patterning
Wherein one layer of electric connection of line layer.Connected slot have bottom, it is multiple connection bottom sidewall portion and it is multiple be located at side
Connection connection pad in wall portion, wherein circuit base plate is assembled to bottom, and is bent by the bent area of core layer relative to configuring area
And route connection pad is electrically connected with connection pad is connect.
In one embodiment of this invention, the profile of the configuring area of above-mentioned core layer is rectangle, and the bending of core layer
The profile in area is multiple rectangles being separated from each other.
In one embodiment of this invention, above-mentioned circuit base plate further include: two soldermask layers are respectively arranged at core layer
Upper surface and lower surface on and be located at configuring area.Soldermask layer is covered farthest away from the upper surface of core layer and two patterns of lower surface
Change line layer.
In one embodiment of this invention, above-mentioned circuit base plate further include: multiple surface treatment patterns are respectively arranged at
On route connection pad, wherein surface treatment pattern directly connects connection pad.
In one embodiment of this invention, above-mentioned circuit base plate further include: multiple auxiliary patterns are configured at core layer
On upper surface and it is located at bent area, wherein auxiliary patterns respectively correspond the setting of route connection pad.
In one embodiment of this invention, an above-mentioned at least core layer is two core layers, and core layer, patterned circuit
Layer and the perpendicular stacking of dielectric layer.
In one embodiment of this invention, each sidewall portion of above-mentioned connected slot and bottom have an angle, and angle
Greater than 90 degree and it is less than 180 degree, and connects connection pad and be located in different level heights.
The production method of encapsulating structure of the invention comprising following fabrication steps.It provides in and is embedded with an at least electronics
The circuit base plate of element, circuit base plate include: an at least core layer, at least three pattern layers line layers, at least two layers of dielectric layer,
Multiple conductive through holes and multiple route connection pads.Core layer have configuring area, around configuring area bent area and opposite to each other
Upper surface and lower surface.Patterned line layer and dielectric layer are configured in core layer and are located in configuring area, and dielectric layer is located at
Between patterned line layer, and patterned line layer is in be alternately stacked with dielectric layer.It is adjacent that conductive through hole is electrically connected wantonly two
Patterned line layer, and route connection pad is configured on the lower surface of core layer and is located at bent area.Dielectric is embedded in electronic component
In one at least within layer of layer and it is located in configuring area.Electronic component passes through its of partially electronically conductive through-hole and patterned line layer
In one layer electric connection.Connected slot is provided, wherein connected slot has bottom, multiple connection sidewall portions of bottom and multiple
Connection connection pad in sidewall portion.The interior circuit base plate for being embedded with electronic component is assembled in connected slot, wherein route base
Plate is located at the bottom of connected slot, and by the bent area of core layer relative to configuring area bending make route connection pad with connect
Connection pad is electrically connected.
In one embodiment of this invention, above-mentioned at least three pattern layers line layers include more internal patterned circuit
Layer and two layers of external print line layer.At least two layers of dielectric layer include more internal dielectric layer and two layers of outer dielectric
Layer.Conductive through hole includes multiple inner conductive through-holes and multiple external conductive through-holes.Circuit base plate will be embedded in electronic component
Step includes: to form at least a groove, further groove in internal patterned line layer and internal dielectric layer to expose interior view
One layer therein of case line layer, and internal patterned line layer is electrically connected to each other by inner conductive through-hole.By electronics member
Part is configured in groove, and wherein electronic component is located in the inside patterned line layer that groove is exposed.Pressing is external respectively
Line layer on dielectric layer and each external dielectric layers is on the upper surface and lower surface of core layer, and wherein external dielectric layers are at least
In one of them filling groove.A patterning process and a through-hole processing procedure are carried out, and line level pattern is made to turn to external print
Line layer simultaneously forms external conductive through-hole, wherein external print line layer by external conductive through-hole respectively with electronic component with
And internal patterned line layer is electrically connected.
In one embodiment of this invention, above-mentioned that the interior circuit base plate for being embedded with electronic component is assembled in connected slot
It before, further include forming two soldermask layers on the upper surface and lower surface of core layer and being located at configuring area, wherein soldermask layer divides
It Fu Gai not external print line layer.
In one embodiment of this invention, above-mentioned that the interior circuit base plate for being embedded with electronic component is assembled in connected slot
Before, multiple surface treatment patterns are formed on route connection pad.
Based on above-mentioned, due to the electronic component of encapsulating structure of the invention be it is interior be embedded in circuit base plate, and circuit base plate
It is to be assembled to the bottom of connected slot, and bend relative to configuring area by the bent area of core layer, so that on circuit base plate
Route connection pad and connected slot connection connection pad be electrically connected.Therefore, encapsulating structure of the invention relative to it is existing will be via
Element after packing colloid encapsulation is assembled to for the formed encapsulating structure of female plug slot, can have lesser encapsulation volume.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Figure 1A is a kind of diagrammatic cross-section of encapsulating structure of one embodiment of the invention；
Figure 1B is the schematic top plan view for the circuit base plate of Figure 1A not bent；
Fig. 2 is a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 3 is a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 4 is a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 5 A to Fig. 5 G is a kind of diagrammatic cross-section of the production method of encapsulating structure of one embodiment of the invention.
Description of symbols:
100a, 100b, 100c, 100d: encapsulating structure；
110,110a, 110b, 110c, 110d: circuit base plate；
111,111 ': core layer；
111a: configuring area；
111b, 111b ': bent area；
111c: upper surface；
111d: lower surface；
112: line layer；
112a, 112b, 112c, 112d, 112e, 112f, 112g, 112h: patterned line layer；
113a, 113b, 113c, 113d, 113e, 113f: dielectric layer；
114: conductive through hole；
114a: inner conductive through-hole；
114b: external conductive through-hole；
115: route connection pad；
116: soldermask layer；
117: surface-treated layer；
118: auxiliary patterns；
120a, 120b: electronic component；
130a, 130d: connected slot；
132a, 132d: bottom；
134a, 134d: sidewall portion；
136a, 136d: connection connection pad；
A: angle；
C1, C2: groove.
Specific embodiment
Figure 1A is a kind of diagrammatic cross-section of encapsulating structure of one embodiment of the invention.Figure 1B is not bending for Figure 1A
The schematic top plan view of circuit base plate.It please refer to Figure 1A, in the present embodiment, encapsulating structure 100a includes a circuit base plate
110a, at least an electronic component (two electronic components 120a, 120b are schematically illustrated in Figure 1A) and a connected slot 130a.
Circuit base plate 110a includes an at least core layer 111 (one is schematically illustrated in Figure 1A), at least three pattern layers line layers (figure
Three patterned line layers 112a, 112b, 112c are schematically illustrated in 1A), at least two layers of dielectric layer (schematically illustrate in Figure 1A
Two dielectric layers 113a, 113b), multiple conductive through holes 114 and multiple route connection pads 115.
Specifically, core layer 111 have a configuring area 111a, one around configuring area 111a bent area 111b and that
This opposite upper surface 111c and a lower surface 111d.Patterned line layer 112a, 112b, 112c are configured at core layer 111
Above and it is located in the 111a of configuring area.Dielectric layer 113a, 113b are configured in core layer 111 and are located in the 111a of configuring area, wherein
Dielectric layer 113a, 113b between patterned line layer 112a, 112b, 112c, and patterned line layer 112a, 112b,
112c is in be alternately stacked with dielectric layer 113a, 113b.Conductive through hole 114 is electrically connected wantonly two adjacent patterned line layer
112a,112b,112c.Route connection pad 115 is configured on the lower surface 111d of core layer 111 and is located at bent area 111b.Electronics
It is embedded in dielectric layer 113a, and is located in the 111a of configuring area in element 120a, 120b, wherein electronic component 120a, 120b passes through
Partially electronically conductive through-hole 114 and patterned line layer 112b is electrically connected.Connected slot 130a has a bottom 132a, multiple connections
The sidewall portion 134a of bottom 132a and multiple connection connection pad 136a on the sidewall portion 134a, wherein circuit base plate 110a group
It is filled to bottom 132a, and route connection pad 115 is made relative to configuring area 111a bending by the bent area 111b of core layer 111
It is electrically connected with connection pad 136a is connect.
More specifically, circuit base plate 110a is embodied as three layer line base boards, and wherein the material of core layer 111 is, for example,
It is constituted with flexible polyimides or other flexible materials appropriate, such as polyethylene terephthalate
(polyethylene terephthalate, PET), polyethers (polyethersulfone, PES) or poly- M-phthalic acid second two
Ester (polyethylene naphthalate, PEN) etc., but be not limited thereto.Please refer to Figure 1B, the configuration of core layer 111
The profile of area 111a is, for example, a rectangle, and the profile of the bent area 111b of core layer 111 is, for example, multiple is separated from each other
Rectangle.Electronic component 120a, 120b are, for example, active member, such as transistor；Either, e.g. passive device, such as resistance
Device (resistor), capacitor (capacitor), inductor (inductor), filter (filter), but not as
Limit.Furthermore the circuit base plate 110a of the present embodiment can further include two soldermask layers 116, and wherein soldermask layer 116 is respectively arranged at core
On the upper surface 111c and lower surface 111d of central layer 111 and it is located at configuring area 111a, and soldermask layer 116 is covered farthest away from core layer
Two patterned line layers 112b, 112c of 111 upper surface 111c and lower surface 111d, to protect patterned line layer
112b,112c.In addition, the circuit base plate 110a of the present embodiment can further include multiple surface treatment patterns 117, wherein being surface-treated
Layer 117 can be respectively arranged on route connection pad 115, and be surface-treated pattern 117 and directly connected connection pad 136a.
Due to electronic component 120a, 120b of this example be it is interior be embedded in circuit base plate 110a, it is existing there is no need to use
Packing colloid carry out the encapsulation of element, can effectively reduce after electronic component 120a, 120b be assembled on circuit base plate 110a
The volume and thickness of integral member.Furthermore due to can effectively simplify whole envelope without being packaged via packing colloid
The production process of assembling structure, and can effectively reduce production cost.Further, since the circuit base plate 110a of the present embodiment is to be assembled to
The bottom 132a of connected slot 130a, and bent by the bent area 111b of core layer 111 relative to configuring area 111a, so that
The connection connection pad 136a of route connection pad 115 and connected slot 130a on circuit base plate 110a is electrically connected.Therefore, the present embodiment
Encapsulating structure compared with the existing technology in by the element after being encapsulated via packing colloid be assembled to female plug slot formed encapsulation knot
For structure, there can be lesser encapsulation volume.
It should be noted that, following embodiments continue to use the appended drawing reference and partial content of previous embodiment, wherein adopting herein
Identical or approximate element is denoted by the same reference numerals, and the explanation of same technique content is omitted.About omission
Partial explanation can refer to previous embodiment, and following embodiment will not be repeated herein.
Fig. 2 is a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.It please also refer to Figure 1A and figure
2, the encapsulating structure 100b of the present embodiment is similar to the encapsulating structure 100a in Figure 1A, is in place of the two main difference: this reality
The circuit base plate 110b for applying example is embodied as eight layer line base boards, i.e. circuit base plate 110b has eight pattern layers line layers
112a, 112b, 112c, 112d, 112e, 112f, 112g, 112h, and in circuit base plate 110b in buried three electronic components
120a,120b,120c.As shown in Fig. 2, the circuit base plate 110b of the present embodiment has two groove C1, C2 to expose figure respectively
Case line layer 112a, 112d, wherein electronic component 120a, 120b is located in groove C1 and directly contact groove C1 is exposed
Patterned line layer 112a, and electronic component 120c is located at the patterning that in groove C2 and directly contact groove C1 is exposed
Line layer 112d.
Since electronic component 120a, 120b, 120c of the encapsulating structure 100b of the present embodiment are interior to be embedded in circuit base plate
In 110b, and circuit base plate 110b is the bottom 132a for being assembled to connected slot 130a, and passes through the bent area of core layer 111
111b is bent relative to configuring area 111a, so that the company of route connection pad 115 and connected slot 130a on circuit base plate 110b
Connection pad 136a is electrically connected.Therefore, the encapsulating structure 100b of the present embodiment compared with the existing technology in will be via packing colloid
Element after encapsulation is assembled to for the formed encapsulating structure of female plug slot, can have lesser encapsulation volume.
Fig. 3 is a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.It please also refer to Fig. 2 and Fig. 3,
The encapsulating structure 100c of the present embodiment is similar to the encapsulating structure 100b in Fig. 2, is in place of the two main difference: the present embodiment
Circuit base plate 110c further include multiple auxiliary patterns 118, wherein auxiliary patterns 118 are configured at the upper surface of core layer 111
111c is upper and is located at bent area 111b, and wherein auxiliary patterns 118 respectively correspond route connection pad 136a setting.Herein, setting auxiliary
The purpose of pattern 118 is to enable the bent area 111b after bending and allows really because of the factor of gravity route connection pad 115 and company
Connection pad 136a is electrically connected.
Fig. 4 is a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.It please also refer to Fig. 2 and Fig. 4,
The encapsulating structure 100d of the present embodiment is similar to the encapsulating structure 100b in Fig. 2, is in place of the two main difference: the present embodiment
Circuit base plate 110d embody there are two core layers 111,111 ', wherein core layer 111,111 ', patterned line layer 112a,
112b, 112c, 112d, 112e, 112f, 112g, 112h and the perpendicular heap of dielectric layer 113a, 113b, 113c, 113d, 113e
It is folded.As shown in figure 4, bent area 111b, 111b of core layer 111,111 ' ' there is an air spacing between the two, that is to say, that
Core layer 111,111 ', which is separated from each other, to be not attached to.In addition, each sidewall portion 134d of the connected slot 130d of the present embodiment and bottom
Portion 132d has an included angle A, and included angle A is greater than 90 degree and is less than 180 degree, and connects connection pad 136d and be located at different level heights
On.When circuit base plate 110d is assembled to the bottom 132d of connected slot 130d, the bent area 111b of core layer 111,111 ',
111b ' can make route connection pad 115 be electrically connected respectively with the connection connection pad 136d on differentiated levels because of bending.This
When, bent area 111b, 111b of core layer 111,111 ' ' the sidewall portion 134d of connected slot 130d can be parallel to and be not orthogonal to
The bottom 132d of connected slot 130d.
The structure for only introducing encapsulating structure 100a, 100b, 100c, 100d of the invention above, is not introduced of the invention
The production method of encapsulating structure.In this regard, below as an example, and 5A will be respectively cooperating with the encapsulating structure 100b in Fig. 2
It is described in detail to production method of Fig. 5 G to encapsulating structure of the invention.
Fig. 5 A to Fig. 5 G is a kind of diagrammatic cross-section of the production method of encapsulating structure of one embodiment of the invention.It please be first
With reference to Fig. 5 F, according to the production method of the encapsulating structure of the present embodiment, firstly, provide in be embedded with electronic component 120a, 120b,
The circuit base plate 110b of 120c.Specifically, Fig. 5 A is please referred to, circuit base plate 110 is first provided, wherein circuit base plate 110 includes
Core layer 111, internal patterned line layer (i.e. patterned line layer 112a, 112d, 112e, 112f, 112g, 112h), inside
Dielectric layer (i.e. dielectric layer 113a, 113b, 113d, 113e), inner conductive through-hole 114a and route connection pad 115.Core layer 111
With configuring area 111a, bent area 111b and upper surface 111c relative to each other around configuring area 111a and lower surface
111d.Patterned line layer 112a, 112d, 112e, 112f, 112g, 112h and dielectric layer 113a, 113b, 113c, 113d are configured
In in core layer 111 and in the 111a of configuring area, dielectric layer 113a, 113b, 113d, 113e are located at patterned line layer
Between 112a, 112d, 112e, 112f, 112g, 112h, and patterned line layer 112a, 112d, 112e, 112f, 112g, 112h
It is in be alternately stacked with dielectric layer 113a, 113b, 113d, 113e.Inner conductive through-hole 114a is electrically connected wantonly two adjacent pattern
Change line layer 112a, 112d, 112e, 112f, 112g, 112h, and route connection pad 115 is configured at the lower surface of core layer 111
111d is upper and is located at bent area 111b.
Then, Fig. 5 B is please referred to, in patterned line layer 112a, 112d, 112e, 112f, 112g, 112h and dielectric layer
In 113a, 113b, 113c, 113d formed groove C1, C2, further groove C1, C2 expose respectively pattern lines layer 112a,
112d。
Then, Fig. 5 C is please referred to, electronic component 120a, 120b, 120c are configured at groove C1, C2, wherein electronic component
120a, 120b, 120c are located in patterned line layer 112a, 112d that groove C1, C2 are exposed.
Then, Fig. 5 D is please referred to, presses external dielectric layers (i.e. dielectric layer 113c, 113f) and its upper wiring layer 112 respectively
On the upper surface 111c and lower surface 111d of core layer 111, dielectric layer 113c, 113f are respectively filled in groove C1, C2.
At this point, being embedded in dielectric layer 113c and being located in the 111a of configuring area in electronic component 120a, 120b, and buried in electronic component 120c
In dielectric layer 113f and it is located in the 111a of configuring area.
Then, Fig. 5 E is please referred to, a patterning process and a through-hole processing procedure are carried out, and keeps line layer 112 patterned outer
Portion's pattern lines layer (i.e. patterned line layer 112b, 112c) simultaneously forms external conductive through-hole 114b, wherein patterned line layer
112b, 112c by external conductive through-hole 114b respectively with electronic component 120a, 120b, 120c and patterned line layer
112g, 112h are electrically connected.That is, electronic component 120a, 120b, 120c pass through conductive through hole 114b and patterned circuit
Layer 112b, 112c are electrically connected.
Then, Fig. 5 F is please referred to, forms two soldermask layers 116 in the upper surface 111c and lower surface 111d of core layer 111
Above and it is located at configuring area 111a, wherein soldermask layer 116 is covered each by patterned line layer 112b, 112c.For effective protection line
Road connection pad 115 can also form surface treatment pattern 117 on route connection pad 115.So far, it is completed with built-in type electronics member
The production of the circuit base plate 110b of part.
Later, Fig. 5 G is please referred to, connected slot 130a is provided, wherein connected slot 130a has bottom 132a, connection bottom
The sidewall portion 134a of the portion 132a and connection connection pad 136a on sidewall portion 134a.Later, it refer again to Fig. 5 G, buried interior
There are the circuit base plate 110b of electronic component 120a, 120b, 120c to be assembled in connected slot 130a, wherein circuit base plate 110b
Make in the bottom 132a of connected slot 130a, and by the bent area 111b of core layer 111 relative to configuring area 111a bending
It obtains route connection pad 115 and is electrically connected with connection pad 136a is connect.So far, the production of encapsulating structure 100b is completed.
In conclusion due to the electronic component of encapsulating structure of the invention be it is interior be embedded in circuit base plate, and circuit base plate
It is to be assembled to the bottom of connected slot, and bend relative to configuring area by the bent area of core layer, so that on circuit base plate
Route connection pad and connected slot connection connection pad be electrically connected.Therefore, encapsulating structure of the invention compared with the existing technology in
For element after encapsulating via packing colloid is assembled to the formed encapsulating structure of female plug slot, there can be lesser packaging body
Product.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (11)
1. a kind of encapsulating structure characterized by comprising
Circuit base plate, comprising:
An at least core layer, with configuring area, the bent area around the configuring area and upper surface relative to each other and following table
Face；
At least three pattern layers line layers, be configured on the upper surface of the core layer on the lower surface and be located at institute
It states in configuring area；
At least two layers of dielectric layer are configured in the core layer and are located in the configuring area, and wherein those dielectric layers, which are located at, is somebody's turn to do
Between a little patterned line layers, and those patterned line layers are in be alternately stacked with those dielectric layers；
Multiple conductive through holes are electrically connected wantonly two those adjacent patterned line layers；And
Multiple route connection pads, are configured on the lower surface of the core layer, and are located at the bent area；
An at least electronic component is inside embedded in one at least within layer of those dielectric layers, and is located in configuring area, wherein described
Wherein one layer of electric connection that electronic component passes through those conductive through holes of part and those patterned line layers；And
Connected slot, sidewall portion and multiple connections in those sidewall portions with bottom, multiple connection bottoms
Connection pad wherein the circuit base plate is assembled to the bottom, and is matched by the bent area of the core layer relative to described
It sets area's bending and those route connection pads is made to connect connection pad electric connection with those.
2. encapsulating structure according to claim 1, which is characterized in that the profile of the configuring area of the core layer is square
Shape, and the profile of the bent area of the core layer is multiple rectangles being separated from each other.
3. encapsulating structure according to claim 1, which is characterized in that the circuit base plate further include: two soldermask layers, point
The configuring area is not configured on the upper surface and the lower surface of the core layer and is located at, and wherein those soldermask layers cover
Cover two patterned line layers of the upper surface and the lower surface farthest away from the core layer.
4. encapsulating structure according to claim 1, which is characterized in that the circuit base plate further include: multiple surface treatments
Pattern is respectively arranged on those route connection pads, and wherein those surface treatment patterns directly contact those connection connection pads.
5. encapsulating structure according to claim 1, which is characterized in that the circuit base plate further include: multiple auxiliary patterns,
It is configured on the upper surface of the core layer, and is located at the bent area, wherein those auxiliary patterns respectively correspond those
The setting of route connection pad.
6. encapsulating structure according to claim 1, which is characterized in that an at least core layer is two core layers, and should
A little core layers, those patterned line layers and the perpendicular stacking of those dielectric layers.
7. encapsulating structure according to claim 6, which is characterized in that each sidewall portion of the connected slot with it is described
Bottom has angle, and the angle is greater than 90 degree and is less than 180 degree, and those connection connection pads are located at different level heights
On.
8. a kind of production method of encapsulating structure characterized by comprising
The circuit base plate that an at least electronic component is embedded in is provided, the circuit base plate includes: an at least core layer, at least three
Pattern layers line layer, at least two layers of dielectric layer, multiple conductive through holes and multiple route connection pads, wherein the core layer has
Configuring area, around the configuring area bent area and upper surface and lower surface relative to each other, those patterned line layers with
Those dielectric layers are configured in the core layer and are located in the configuring area, those dielectric layers are located at those patterned line layers
Between, and those patterned line layers are in be alternately stacked, and those conductive through holes electric connection wantonly two is adjacent with those dielectric layers
Those patterned line layers, and those route connection pads be configured on the lower surface of the core layer and be located at the bending
Area, and be embedded in one at least within layer of those dielectric layers and be located in the configuring area in the electronic component, the electricity
Wherein one layer of electric connection that subcomponent passes through those conductive through holes of part and those patterned line layers；
Connected slot is provided, wherein the connected slot has bottom, the sidewall portion of multiple connection bottoms and multiple positions
In the connection connection pad in those sidewall portions；And
The interior circuit base plate for being embedded with the electronic component is assembled in the connected slot, wherein the circuit base plate position
Make in the bottom of the connected slot, and by the bent area of the core layer relative to configuring area bending
It obtains those route connection pads and connect connection pad electric connection with those.
9. the production method of encapsulating structure according to claim 8, which is characterized in that at least three pattern layers routes
Layer includes more internal patterned line layer and two layers of external print line layer, and at least two layers of dielectric layer include more
Layer internal dielectric layer and two layers of external dielectric layers, and those conductive through holes include that multiple inner conductive through-holes are led with multiple outsides
The step of being embedded in the circuit base plate in the electronic component include: by electric through-hole
An at least groove is formed in those internal patterned line layers and those internal dielectric layers, wherein the groove exposes
One layer therein of those internal pattern line layers, and those internal patterned line layers pass through those inner conductive through-holes each other
It is electrically connected；
The electronic component is configured in the groove, wherein the electronic component be located at the groove exposed it is described
In internal patterned line layer；
The line layer on those external dielectric layers and each external dielectric layers is pressed respectively in the upper table of the core layer
On face and the lower surface, wherein at least one described groove of filling of those external dielectric layers；And
Patterning process and through-hole processing procedure are carried out, and so that those line level patterns is turned to those external print line layers and is formed and is somebody's turn to do
A little external conductive through-holes, wherein those external print line layers by those external conductive through-holes respectively with the electronic component
And those internal patterned line layers are electrically connected.
10. the production method of encapsulating structure according to claim 9, which is characterized in that further include:
Before the interior circuit base plate for being embedded with the electronic component is assembled in the connected slot, two soldermask layers are formed
On the upper surface and the lower surface of the core layer and it is located at the configuring area, wherein those soldermask layers are covered each by
Those external print line layers.
11. the production method of encapsulating structure according to claim 8, which is characterized in that further include:
Before the interior circuit base plate for being embedded with the electronic component is assembled in the connected slot, formed at multiple surfaces
Pattern is managed on those route connection pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510381443.4A CN106328600B (en) | 2015-07-02 | 2015-07-02 | Encapsulating structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510381443.4A CN106328600B (en) | 2015-07-02 | 2015-07-02 | Encapsulating structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN106328600A CN106328600A (en) | 2017-01-11 |
| CN106328600B true CN106328600B (en) | 2019-04-30 |
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|---|---|---|---|---|
| JP2005064316A (en) * | 2003-08-18 | 2005-03-10 | Hitachi Chem Co Ltd | Method for manufacturing printed wiring board equipped with passive element and wiring board to be obtained and semiconductor device |
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| CN103681458A (en) * | 2012-09-03 | 2014-03-26 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional flexible stacked encapsulating structure of embedded ultrathin chip |
| CN103904048A (en) * | 2012-12-27 | 2014-07-02 | 欣兴电子股份有限公司 | Built-in chip packaging structure |
| CN104137256A (en) * | 2011-12-29 | 2014-11-05 | 英维萨斯公司 | Embedded heat spreader for microelectronic package |
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|---|---|---|---|---|
| TWI278268B (en) * | 2006-02-23 | 2007-04-01 | Via Tech Inc | Arrangement of non-signal through vias and wiring board applying the same |
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|---|---|---|---|---|
| JP2005064316A (en) * | 2003-08-18 | 2005-03-10 | Hitachi Chem Co Ltd | Method for manufacturing printed wiring board equipped with passive element and wiring board to be obtained and semiconductor device |
| TW200603355A (en) * | 2004-07-14 | 2006-01-16 | Chipmos Technologies Inc | Chip-under-tape package and process for manufacturing the same |
| CN104137256A (en) * | 2011-12-29 | 2014-11-05 | 英维萨斯公司 | Embedded heat spreader for microelectronic package |
| CN103681458A (en) * | 2012-09-03 | 2014-03-26 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional flexible stacked encapsulating structure of embedded ultrathin chip |
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| Publication number | Publication date |
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| CN106328600A (en) | 2017-01-11 |
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