JPS6488748A - Apparatus and method for generating data induction state signal - Google Patents
Apparatus and method for generating data induction state signalInfo
- Publication number
- JPS6488748A JPS6488748A JP63164822A JP16482288A JPS6488748A JP S6488748 A JPS6488748 A JP S6488748A JP 63164822 A JP63164822 A JP 63164822A JP 16482288 A JP16482288 A JP 16482288A JP S6488748 A JPS6488748 A JP S6488748A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- flbc
- prescribed
- arithmetic operation
- pool value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US6928587A | 1987-07-01 | 1987-07-01 | |
US69285 | 1987-07-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6488748A true JPS6488748A (en) | 1989-04-03 |
JP2626675B2 JP2626675B2 (ja) | 1997-07-02 |
Family
ID=22087945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63164822A Expired - Fee Related JP2626675B2 (ja) | 1987-07-01 | 1988-07-01 | データ誘起状態信号発生装置及び方法 |
Country Status (9)
Country | Link |
---|---|
EP (1) | EP0297890B1 (ja) |
JP (1) | JP2626675B2 (ja) |
KR (1) | KR970004510B1 (ja) |
CN (1) | CN1013903B (ja) |
AU (1) | AU626264B2 (ja) |
BR (1) | BR8803379A (ja) |
CA (1) | CA1303745C (ja) |
DE (1) | DE3856049T2 (ja) |
IN (1) | IN169637B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7079775B2 (en) | 2001-02-05 | 2006-07-18 | Finisar Corporation | Integrated memory mapped controller circuit for fiber optics transceiver |
US7346809B2 (en) * | 2004-08-05 | 2008-03-18 | International Business Machines Corporation | Bootable post crash analysis environment |
US10248488B2 (en) | 2015-12-29 | 2019-04-02 | Intel Corporation | Fault tolerance and detection by replication of input data and evaluating a packed data execution result |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4334268A (en) * | 1979-05-01 | 1982-06-08 | Motorola, Inc. | Microcomputer with branch on bit set/clear instructions |
JPS6014338A (ja) * | 1983-06-30 | 1985-01-24 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 計算機システムにおける分岐機構 |
-
1988
- 1988-06-28 IN IN529/CAL/88A patent/IN169637B/en unknown
- 1988-06-30 DE DE3856049T patent/DE3856049T2/de not_active Expired - Lifetime
- 1988-06-30 CA CA000570920A patent/CA1303745C/en not_active Expired - Fee Related
- 1988-06-30 EP EP88305988A patent/EP0297890B1/en not_active Expired - Lifetime
- 1988-07-01 KR KR88008151A patent/KR970004510B1/ko not_active IP Right Cessation
- 1988-07-01 AU AU18639/88A patent/AU626264B2/en not_active Ceased
- 1988-07-01 JP JP63164822A patent/JP2626675B2/ja not_active Expired - Fee Related
- 1988-07-01 BR BR8803379A patent/BR8803379A/pt not_active Application Discontinuation
- 1988-07-01 CN CN88104662A patent/CN1013903B/zh not_active Expired
Also Published As
Publication number | Publication date |
---|---|
CN1031286A (zh) | 1989-02-22 |
DE3856049D1 (de) | 1997-11-27 |
AU1863988A (en) | 1989-01-05 |
EP0297890A2 (en) | 1989-01-04 |
BR8803379A (pt) | 1989-01-24 |
KR970004510B1 (en) | 1997-03-28 |
CA1303745C (en) | 1992-06-16 |
DE3856049T2 (de) | 1998-05-07 |
EP0297890A3 (en) | 1990-07-11 |
CN1013903B (zh) | 1991-09-11 |
JP2626675B2 (ja) | 1997-07-02 |
AU626264B2 (en) | 1992-07-30 |
IN169637B (ja) | 1991-11-23 |
EP0297890B1 (en) | 1997-10-22 |
KR890002758A (ko) | 1989-04-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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R250 | Receipt of annual fees |
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|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |